a

FEATURES
128-Position, 2-Channel
Potentiometer Replacement
10 k, 50 k, 100 k, 1 M
Very Low Power: 40 A Max
2.7 V Dual Supply Operation or
2.7 V to 5.5 V Single Supply Operation
Increment/Decrement Count Control
APPLICATIONS
Stereo Channel Audio Level Control
Mechanical Potentiometer Replacement
Remote Incremental Adjustment Applications
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Line Impedance Matching

GENERAL DESCRIPTION

The AD5222 provides a dual channel, 128-position, digitally

controlled variable-resistor (VR) device. This device performs
the same electronic adjustment function as a potentiometer or
variable resistor. These products were optimized for instrument
and test equipment push-button applications. Choices between
bandwidth or power dissipation are available as a result of the
wide selection of end-to-end terminal resistance values.
The AD5222 contains two fixed resistors with wiper contacts that
tap the fixed resistor value at a point determined by a digitally
controlled up/down counter. The resistance between the wiper
and either end point of the fixed resistor provides a constant
resistance step size that is equal to the end-to-end resistance
divided by the number of positions (e.g., R STEP = 10 k/128 =
78 ). The variable resistor offers a true adjustable value of
resistance, between Terminal A and the wiper, or Terminal B
and the wiper. The fixed A-to-B terminal resistance of 10 k,
50 k, 100 k, or 1 M has a nominal temperature coefficient
of 35 ppm/C.
The chip select CS, count CLK and U/D direction control inputs
set the variable resistor position. The MODE determines whether
both VRs are incremented together or independently. With
MODE at logic zero, both wipers are incremented UP or DOWN
without changing the relative settings between the wipers. Also,
the relative ratio between the wipers is preserved if either wiper
reaches the end of the resistor array. In the independent MODE
(Logic 1) only the VR determined by the DACSEL pin is changed.
DACSEL (Logic 0) changes RDAC 1. These inputs, which control the internal up/down counter, can be easily generated with

Increment/Decrement
Dual Digital Potentiometer
AD5222
FUNCTIONAL BLOCK DIAGRAM

VDD

AD5222

A1
UP/DOWN
COUNTER

U/D

DECODE

W1
B1

POR
CS
MODE
DACSEL
CLK

DAC
SELECT
AND
ENABLE

A2
UP/DOWN
COUNTER

DECODE

W2
B2

GND

VSS

mechanical or push-button switches (or other contact closure

devices). This simple digital interface eliminates the need for
microcontrollers in front panel interface designs.
The AD5222 is available in the surface-mount (SO-14) package.
For ultracompact solutions, selected models are available in the
thin TSSOP-14 package. All parts are guaranteed to operate
over the extended industrial temperature range of 40C to
+85C. For 3-wire, SPI-compatible interface applications, see
the AD5203/AD5204/AD5206, AD7376, and AD8400/AD8402/
AD8403 products.
5V
VDD
CS
U/D
U/D
CLK

A1
W1
B1

INCREMENT

A2
DACSEL

W2

MODE

B2

GND

VSS

Figure 1. Typical Push-Button Control Application

REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999

V 10% or 5 V 10%, V
AD5222SPECIFICATIONS (Vunless= 3otherwise
noted.)
DD

Parameter

Symbol

SS

= 0 V, VA = +VDD, VB = 0 V, 40C < TA < +85C,

Condition

DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)

R-DNL
RWB, VA = NC
Resistor Differential NL2
Resistor Nonlinearity2
R-INL
RWB, VA = NC
Nominal Resistor Tolerance
R
VAB = VDD, Wiper = No Connect, T A = 25C
Resistance Temperature Coefficient
RAB/T
VAB = VDD, Wiper = No Connect
Wiper Resistance3
RW
IW = VDD /R, VDD = 3 V or 5 V
Nominal Resistance Match
R/RO
CH 1 to 2, V AB = VDD, TA = 25C
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Resolution
N
INL
RAB = 10 k, 50 k, or 100 k
Integral Nonlinearity4
INL
RAB = 1 M
Differential Nonlinearity4
DNL
Voltage Divider Temperature Coefficient VW /T
Code = 40H
Full-Scale Error
VWFSE
Code = 7F H
Zero-Scale Error
VWZSE
Code = 00H
RESISTOR TERMINALS
Voltage Range 5
Capacitance6 A, B
Capacitance6 W
Common-Mode Leakage

VA, B, W
CA, B
CW
ICM

DIGITAL INPUTS AND OUTPUTS

Input Logic High
Input Logic Low
Input Current
Input Capacitance6

VIH
VIL
IIL
CIL

VDD = 5 V/3 V
VDD = 5 V/3 V
VIN = 0 V or 5 V

POWER SUPPLIES
Power Single-Supply Range
Power Dual-Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation 7
Power Supply Sensitivity

VDD RANGE
VDD/SS RANGE
IDD
ISS
PDISS
PSS

VSS = 0 V

BW_10K
BW_50K
BW_100K
BW_1M
THDW
tS
eN_WB

RAB = 10 k, Code = 40 H
RAB = 50 k, Code = 40 H
RAB = 100 k, Code = 40H
RAB = 500 k, Code = 40H
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
RAB = 10 k, 1 LSB Error Band
RWB = 5 k, f = 1 kHz

DYNAMIC CHARACTERISTICS6, 8, 9
Bandwidth 3 dB

Total Harmonic Distortion

VW Settling Time
Resistor Noise Voltage

Min

Typ1 Max

Unit

1
1
30

1/4 +1
0.4 +1
+30
35
45
100
0.2 1

LSB
LSB
%
ppm/C

1/4
1/2
1/4
20
0.5
0.5

Bits
LSB
LSB
LSB
ppm/C
LSB
LSB

7
1
2
1
1
0
VSS

f = 1 MHz, Measured to GND, Code = 40 H

f = 1 MHz, Measured to GND, Code = 40 H
VA = V B = V W

+0
1
VDD

45
60
1
2.4/2.1
5
2.7
2.3

VIH = 5 V or VIL = 0 V
VSS = 2.5 V, VDD = +2.7 V
VIH = 5 V or VIL = 0 V, VDD = 5 V

INTERFACE TIMING CHARACTERISTICS (Applies to All Parts) 6, 10

Input Clock Pulsewidth
tCH, t CL
Clock Level High or Low
CS to CLK Setup Time
tCSS
CS Rise to CLK Hold Time
tCSH
U/D to Clock Fall Setup Time
tUDS
U/D to Clock Fall Hold Time
tUDH
DACSEL to Clock Fall Setup Time
tDSS
DACSEL to Clock Fall Hold Time
tDSH
MODE to Clock Fall Setup Time
tMDS
MODE to Clock Fall Hold Time
tMDH

+1
+2
+1

30
20
20
10
30
20
30
20
40

V
pF
pF
nA

V
0.8/0.6 V
1
A
pF

5.5
2.7
15
40
15
40
150 400
0.002 0.05

V
V
A
A
W
%/%

1000
180
78
7
0.005
2
14

kHz
kHz
kHz
kHz
%
s
nVHz
ns
ns
ns
ns
ns
ns
ns
ns
ns

NOTES
1Typicals represent average readings at 25C, V
DD = 5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 22 test circuit.
3Wiper resistance is not measured on the R
AB = 1 M models.
4INL and DNL are measured at V with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V = V
W
A
DD and VB = 0 V. DNL
specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 21 test circuit.
5Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6Guaranteed by design and not subject to production test.
7P
DISS is calculated from (I DD V DD). CMOS logic level inputs result in minimum power dissipation.
8Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.
The highest R value results in the minimum overall power consumption.
9All dynamic characteristics use V
DD = 5 V.
10See timing diagram for location of measured values. All input control voltages are specified with t = t = 2.5 ns (10% to 90% of +3 V) and timed from a voltage level
R
F
of 1.5 V. Switching characteristics are measured using both V DD = 5 V or V DD = 3 V.
Specifications subject to change without notice.

REV. 0

AD5222
ABSOLUTE MAXIMUM RATINGS

ORDERING GUIDE

(TA = 25C, unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +7 V

VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 5 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VA, VB, V W to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
AX BX , AX WX , BX WX . . . . . . . . . . . . . . . . . . . 20 mA
Digital Input Voltage to GND . . . . . . . . . . . . 0 V, VDD + 0.3 V
Operating Temperature Range . . . . . . . . . . . 40C to +85C
Maximum Junction Temperature (TJ max) . . . . . . . . . . 150C
Storage Temperature . . . . . . . . . . . . . . . . . . 65C to +150C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300C
Package Power Dissipation . . . . . . . . . . . . . (TJ max TA)/JA
Thermal Resistance JA,
SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158C/W
TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206C/W

Model

Kilo
Package
Package
Ohms Temperature Description Option

AD5222BR10
AD5222BRU10
AD5222BR50
AD5222BRU50
AD5222BR100
AD5222BRU100
AD5222BR1M
AD5222BRU1M

10
10
50
50
100
100
1,000
1,000

40C/+85C
40C/+85C
40C/+85C
40C/+85C
40C/+85C
40C/+85C
40C/+85C
40C/+85C

SO-14
TSSOP-14
SO-14
TSSOP-14
SO-14
TSSOP-14
SO-14
TSSOP-14

R-14
RU-14
R-14
RU-14
R-14
RU-14
R-14
RU-14

The AD5222 die size is 56 mil 60 mil, 3360 sq. mil; 1.4224 mm 1.524 mm,
2.1677 sq. mm. Contains 1503 transistors. Patent Number 5495245 applies.

PIN FUNCTION DESCRIPTIONS

Pin Name

CS

tCSS

tCH
tCL

tCSH

CLK

tUDS
tUDH

U/D

1
2
3
4

tDSS
tDSH

DACSEL

tMDS
tMDH

MODE

Figure 2. Detail Timing Diagram

5
6
7
8
9
10

Truth Table

CS

CLK

U/D

Operation

L
L
H

t
t
X

H
L
X

Wiper Increment Toward Terminal A

Wiper Decrement Toward Terminal B
Wiper Position Fixed

Common Mode (MODE = 0) moves both wipers together either

UP or DOWN the resistor array without changing the relative
distance between the wipers. Also, the distance between both
wipers is preserved if either reaches the end of the array. Independent Mode (MODE = 1) allows user to control each RDAC
individually: DACSEL = 0 sets RDAC1; DACSEL = 1: sets
RDAC2.

11
12
13
14

Description

B1
A1
W1
VSS

B Terminal RDAC #1.

A Terminal RDAC #1.
Wiper RDAC #1, DACSEL = 0.
Negative Power Supply. Specified for operation
at both 0 V or 2.7 V (Sum of |VDD | + |VSS |
< 5.5 V).
W2
Wiper RDAC #2, DACSEL = 1.
A2
A Terminal RDAC #2.
B2
B Terminal RDAC #2.
GND
Ground.
MODE
Common MODE = 0, Independent MODE = 1.
DACSEL DAC Select determines which wiper is incremented in the Independent MODE = 1.
DACSEL = 0 sets RDAC1, DACSEL = 1 sets
RDAC2.
U/D
UP/DOWN Direction Control.
CLK
Serial Clock Input, Negative Edge Triggered.
CS
Chip Select Input, Active Low. When CS is
high, the UP/DOWN counter is disabled.
VDD
Positive Power Supply. Specified for operation
at both +3 V or +5 V. (Sum of |VDD | + |VSS |
< 5.5 V).
PIN CONFIGURATION
B1 1

14 VDD

A1 2

13 CS

12 CLK
TOP VIEW
11 U/D
(Not to Scale)
W2 5
10 DACSEL
W1 3

AD5222

VSS 4

A2 6

9 MODE

B2 7

8 GND

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5222 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. 0

WARNING!
ESD SENSITIVE DEVICE

AD5222Typical Performance Characteristics

100

0.25

0.15

50

TA = +258C

0.10
0.05
0
0.05

TA = +858C

0.10

25
0.15
RWB
0

32

64
CODE Decimal

96

0.25

128

Figure 3. Wiper-To-End Terminal Resistance vs. Code

20H

50kV VERSION

05H

2.5
2

02H

1.5
RAB = 10kV
VDD = 5V
TA = 258C

1
0.5

112

128

3
4
IWA CURRENT mA

10kV VERSION

0.4
0.2
0
0.2
100kV VERSION

1MV VERSION

0.4
0.6
0.8
1.0

Figure 4. Resistance Linearity vs. Conduction Current

16

32

48
64
80
CODE Decimal

96

112

128

Figure 7. R-INL Resistance Nonlinearity Error vs. Code

0.6

180

150

96

0.6
08H

3.5

48
64
80
CODE Decimal

VDD/VSS = 2.7V/0V
TA = 258C

0.8
10H

32

1.0

3FH

4.5

16

Figure 6. R-DNL Relative Resistance Step Position

Change vs. Code

R-INL ERROR LSB

VDD = +15V
VSS = 15V
RAB = 50kV

0.20

RWA

VWB VOLTAGE V

TA = 558C

75
R-DNL ERROR LSB

PERCENT OF NOMINAL
END-TO-END RESISTANCE % RAB

0.20

SS = 600 UNITS
VDD = 2.7V
TA = 258C

VDD/VSS = 2.7V/0V
TA = 258C

0.4

10kV VERSION

0.2

50kV VERSION

INL LSB

FREQUENCY

120

90

0
0.2
0.4

60

100kV VERSION

0.6
30

1MV VERSION
0.8

40 41 42 44 45 47 48 50 51 53 54 56 57 59 60
WIPER RESISTANCE V

1.0
0

16

32

48
64
80
CODE Decimal

96

112

128

Figure 8. Potentiometer Divider INL Error vs. Code

Figure 5. Wiper Contact Resistance

REV. 0

AD5222
9
VDD/VSS = 2.7V/0V
TA = 258C

1MV VERSION

60

10kV VERSION

50
40

50kV VERSION

20
10

A
OP42

50kV

1MV
9

12

10

15

20

18

B
100kV

16

32

48
64
80
CODE Decimal

96

112

BW 10kV
50kV
100kV
1MV

21
100

30
128

Figure 9. VWB /T Potentiometer Mode Tempco

1k

764kHz
132kHz
64kHz
6.6kHz

10k
FREQUENCY Hz

1M

100k

Figure 12. Gain vs. Frequency vs. RAB

10

120

FILTER = 22kHz
VDD = 62.7V
VIN = 1V rms
TA = 258C

VDD/VSS = 2.7V/0V
TA = 258C

100
RHEOSTAT MODE TEMPCO ppm/8C

10kV

100kV VERSION

30

VDD = +2.7V
VSS = 2.7V
DATA = 40H
VA = 50mV rms
VB = 0V

GAIN dB

POTENTIOMETER MODE TEMPCO ppm/8C

70

100kV VERSION

80

1.0
THD + NOISE %

60
50kV VERSION
40
20
0
20

60

SEE TEST CIRCUIT FIGURE 25

0.01

10kV VERSION

40

0.1

SEE TEST CIRCUIT FIGURE 26

1MV VERSION
0.001

80
0

16

32

48
64
80
CODE Decimal

96

112

10

128

Figure 10. RWB /T Rheostat Mode Tempco

100

1k
FREQUENCY Hz

10k

100k

Figure 13. Total Harmonic Distortion Plus Noise vs.

Frequency

0
NORMALIZED GAIN FLATNESS 0.1dB/DIV

CODE = 3FH
20H

10

GAIN - dB

10H
20

08H
04H

30

02H
01H

40
TA = 258C
SEE TEST CIRCUIT FIGURE 32
50
10

100

1k

10k
100k
FREQUENCY Hz

1M

10M

10kV

100kV

SEE TEST CIRUIT 27

VDD = 2.7V
VSS = 2.7V
VA = 50mV rms
VB = 0V
DATA = 40H

50kV

A
W

OP42

B
10

Figure 11. 10 k Gain vs. Frequency vs. Code

REV. 0

1MV

100

1k
10k
FREQUENCY Hz

100k

1M

Figure 14. Normalized Gain Flatness vs. Frequency

AD5222
1200

10

800

SUPPLY CURRENT mA

1000
IDD SUPPLY CURRENT mA

TA = 258C

A VDD = 5.5V
CODE = 15H
B VDD = 3.3V
CODE = 15H
C VDD = 5.5V
CODE = 3FH
D VDD = 3.3V
CODE = 3FH

600
A

400

VDD = 5.5V
VA = 5.5V

VDD/VSS = 62.5V
VA = 2.5V

0.1

0.01

200
C
D

0
10k

100k
FREQUENCY Hz

0.001

10M

1M

VDD = 2.7V
VA = 2.7V
0

Figure 15. IDD , ISS Supply Current vs. Clock Frequency

2
3
4
INPUT LOGIC VOLTAGE V

Figure 18. Supply Current vs. Input Logic Voltage

100
TA = 258C

SWITCH RESISTANCE V

90

VDD = 2.7V
VA = 2.7V
VB = 0V

VDD/VSS = 2.7V/0V

80
70

VW

20mV/DIV

60
50
VDD/VSS = 62.7V
40

2V/DIV
30

CLK

VDD/VSS = 5.5V/0V
20
10
3

0
1
2
3
COMMON MODE Volts

Figure 16. Incremental Wiper Contact Resistance vs.

VDD / V SS

Figure 19. Midscale Transition 3FH to 40H

SUPPLY CURRENT mA

LOGIC = 0V OR VDD
VDD = 2.7V
VA = 2.7V
VB = 0V

0.1

VWA

VWB

20mV/DIV
VDD = 5.5V OR VDD/VSS = 62.7V
0.01

VDD = 2.7V
CLK

2V/DIV

0.001
40

15

10
35
TEMPERATURE 8C

60

85

Figure 17. Supply Current vs. Temperature

Figure 20. Stereo Step Transition, Mode = 0

REV. 0

Parametric Test CircuitsAD5222

A
V+ = VDD
1LSB = V+/128

DUT
A
W

V+

DUT B
+5V

VIN

OP279

VOUT

VMS

5V

Figure 25. Inverting Programmable Gain Test Circuit

Figure 21. Potentiometer Divider Nonlinearity Error Test

Circuit (INL, DNL)

+5V
NO CONNECT
DUT
A
W

OP279

VIN

IW

VOUT

5V

DUT

VMS

Figure 22. Resistor Position Nonlinearity Error (Rheostat

Operation; R-INL, R-DNL)

DUT
A
W

VMS2

Figure 26. Noninverting Programmable Gain Test Circuit

+15V

IW = VDD /R NOMINAL

W
VIN

VW

DUT
B

OP42

VOUT

B
VMS1

RW = [VMS1 V MS2]/IW
15V

Figure 27. Gain vs. Frequency Test Circuit

Figure 23. Wiper Resistance Test Circuit

VA
V+ = VDD 10%
V+

VDD

A
B

PSRR (dB) = 20 LOG

W
VMS

DVMS%
PSS (%/%) =
DVDD%

DV

CODE = 00H

MS
(
)

DVDD

ISW

0.1V

0 TO VDD

Figure 28. Incremental ON Resistance Test Circuit

Figure 24. Power Supply Sensitivity Test Circuit (PSS,

PSRR)

REV. 0

RSW = 0.1V
ISW

DUT

AD5222
OPERATION

U/D

The AD5222 provides a 128-position, digitally-controlled, variable

resistor (VR) device. Changing the VR settings is accomplished
by pulsing the CLK pin while CS is active low. The U/D (UP/
DOWN) control input pin controls the direction of the increment.
When the wiper hits the end of the resistor (Terminal A or B)
additional CLK pulses no longer change the wiper setting. The
wiper position is immediately decoded by the wiper decode logic
changing the wiper resistance. Appropriate debounce circuitry is
required when push-button switches are used to control the
count sequence and direction of count. The exact timing requirements are shown in Figure 2. The AD5222 powers ON in a
centered wiper position, exhibiting nearly equal resistances of
RWA and R WB.

RDAC 1
U/D
COUNTER

DACSEL

MODE

RDAC 2
U/D
COUNTER

CS

CLK
VDD

AD5222

A1
UP/DOWN
COUNTER

U/D

DECODE

Figure 30. Detailed Digital Logic Interface Circuit

W1

All digital inputs (CS, U/D, CLK, MODE, DACSEL) are

protected with a series input resistor and parallel Zener ESD
structure shown in Figure 31. All potentiometer terminal pins
(A, B, W) are protected from ESD as shown in Figure 32.

B1
POR
CS
MODE
DACSEL
CLK

DAC
SELECT
AND
ENABLE

A2
UP/DOWN
COUNTER

DECODE

GND

W2

1kV
LOGIC

B2

VSS

VSS

Figure 31. Equivalent ESD Protection Digital Pins

Figure 29. Block Diagram
20V
A, B, W

DIGITAL INTERFACING OPERATION

VSS

The AD5222 contains a push-button controllable interface. The

active inputs are clock (CLK), CS and up/down (U/D). While
the MODE, and DACSEL pins control common updates or
individual updates. The negative-edge sensitive CLK input
requires clean transitions to avoid clocking multiple pulses into
the internal UP/DOWN counter register, Figure 30. Standard
logic families work well. If mechanical switches are used for
product evaluation a flip-flop or other suitable means should
debounce them. When CS is taken active low, the clock begins
to increment or decrement the internal up/down counter, dependent upon the state of the U/D control pin. The UP/DOWN
counter value (D) starts at 40H at system power ON. Each new
CLK pulse will increment the value of the internal counter by
1 LSB until the full-scale value of 7FH is reached, as long as the
U/D pin is logic high. If the U/D pin is taken to logic low, the
counter will count down, stopping at code 00H (zero-scale).
Additional clock pulses on the CLK pin are ignored when the
wiper is at either the 00H position or the 7F H position. The
detailed digital logic interface circuitry is shown in Figure 30.

Figure 32. Equivalent ESD Protection Analog Pins

RS

D0
D1
D2
D3
D4
D5
D6

RS

RS

W
RDAC
UP/DOWN
CNTR
&
DECODE

RS

RS = RNOMINAL/128

Figure 33. AD5222 Equivalent RDAC Circuit

REV. 0

AD5222
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation

The nominal resistance of the RDAC between Terminals A and

B are available with values of 10 k, 50 k, 100 k, and 1 M
The final three characters of the part number determine the
nominal resistance value, e.g., 10 k = 10; 50 k = 50; 100 k
= 100; 1 M = 1M. The nominal resistance (RAB ) of the VR
has 128 contact points accessed by the wiper terminal, plus the
B terminal contact. At power ON, the resistance from the wiper
to either end Terminal A or B is approximately equal. Pulsing
the CLK pin will increase the resistance from the wiper W to
Terminal B by one unit of RS resistance, see Figure 33. The
resistance RWB is determined by the number of pulses applied to
the clock pin. Each segment of the internal resistor string has a
nominal resistance value of RS = RAB/128, which becomes 78
in the case of the 10 k AD5222BR10 product. Care should be
taken to limit the current flow between W and B in the direct
contact state (RWB code = 0) to a maximum value of 20 mA to
avoid degradation or possible destruction of the internal switch
contact.
Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical (see Figure 3). The resistance between the
wiper W and Terminal A also produces a digitally controlled
resistance RWA. When these terminals are used the B-terminal
should be tied to the wiper.

The RBA temperature coefficient increases as the wiper is programmed near the B-terminal due to the larger percentage
contribution of the wiper contact switch resistance, which has a
0.5%/C temperature coefficient. Figures 9 and 10 show the
effect of the wiper contact resistance as a function of code setting.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation

The digital potentiometer easily generates an output voltage

proportional to the input voltage applied to a given terminal.
For example connecting A-terminal to 5 V and B-terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than 5 V. Each
LSB of voltage is equal to the voltage applied across Terminals
AB divided by the 128-position resolution of the potentiometer
divider. The general equation defining the output voltage with
respect to ground for any given input voltage applied to Terminals AB is:
VW(D) = D/128 VAB + VB

D represents the current contents of the internal up/down counter.

Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors
not the absolute value, therefore, the drift improves to 20 ppm/C.

The typical part-to-part distribution of R BA is process-lotdependent having a 30% variation. The change in RBA with
temperature has a 35 ppm/C temperature coefficient.

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AD5222
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

14-Lead Narrow Body SOIC

(R-14)
0.201 (5.10)
0.193 (4.90)

0.3444 (8.75)
0.3367 (8.55)
0.1574 (4.00)
0.1497 (3.80)

PIN 1

C3715810/99

14-Lead TSSOP
(RU-14)

14

0.050 (1.27)
BSC

0.0688 (1.75)
0.0532 (1.35)

0.2440 (6.20)
0.2284 (5.80)

14

0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)

0.0196 (0.50)
3 458
0.0099 (0.25)

PIN 1
88
0.0192 (0.49) SEATING
08 0.0500 (1.27)
0.0099 (0.25)
0.0138 (0.35) PLANE
0.0160 (0.41)
0.0075 (0.19)

0.006 (0.15)
0.002 (0.05)

SEATING
PLANE

0.0256
(0.65)
BSC

0.0433 (1.10)
MAX

0.0118 (0.30)
0.0075 (0.19)

0.0079 (0.20)
0.0035 (0.090)

88
08

0.028 (0.70)
0.020 (0.50)

PRINTED IN U.S.A.

0.0098 (0.25)
0.0040 (0.10)

10

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