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Lecture 02
The 8086 Microprocessor Architecture
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Daniel D. DECE
In this Lecture:
AAiT
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AAiT
Data Reg.
AAiT
Address
decoder
To
Memory
Stack Pointer
ALU
Program counter
Flags
-Carry
- Zero
- Overflow
- Interrupt
Accumulator
Counting Reg.
Input Reg.
Instruction Reg.
Instruction
decoder &
execution unit
Output Reg.
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AAiT
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AAiT
Instruction
Instruction opcode
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AAiT
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Internal Architecture
AAiT
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AAiT
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AAiT
Flag Register
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10
Flag Register
AAiT
11
Flag Register
cntd
AAiT
12
Flag Register
cntd
AAiT
13
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Instruction Queue
oWhile the EU is decoding or executing an instruction, which does
not require use of the buses, the BIU fetches up to six instruction
bytes for the following instructions.
oThe BIU stores these pre-fetched bytes in a first-in-first-out register
set called a queue. When the EU is ready for its next instruction, it
simply reads the instruction byte(s) for the instruction from the
queue in the BIU.
oFetching the next instruction while the current instruction
is being executed is called pipelining.
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Segment Registers
oThe four segment registers are the code segment (CS)
register, the data segment (DS) register, the stack segment
(SS) register, and the extra segment (ES) register.
o A segment register is used to hold the upper 16 bits of the
starting address for each of the segments.
oThe four segments can be separated or for small programs,
which do not need all 64 Kbytes in each segment, they can
overlap.
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AAiT
17
AAiT
h
19
Instruction Pointer
The IP contains the distance or offset from the base address in Code
Segment (CS) to the next instruction byte to be fetched.
The 16-bit offset in IP is added to the 16-bit segment base address in
CS to produce the 20-bit physical address.
Location of the next instruction in memory is, therefore
address of next instruction. = (CS << 4) + IP;
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Instruction Pointer
Example: Let CS holds 348Ah,
and IP holds 4214h
Now the actual address in the
physical memory space is
given by CS:IP and calculated
as:
CS is first shifted left four times
16*CS = 348A0h
Then the offset in IP is added
348A0h
+ 4214h
Actual address 38AB4h
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Stack Pointer
A stack is a section of memory set aside to store addresses and data
while a subprogram is executing.
The 8086 allow you to set aside an entire 64KB segment as a stack.
The upper 16 bits of the starting address for this segment are kept in
the stack segment register (SS).
The stack pointer (SP) register holds the 16-bit offset from the start
of the segment to the memory location where a word was most
recently stored on the stack (Top of stack).
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23
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AX [Accumulator]
AH:AL
BX [Base Register]
BH:BL
DH:DL
CS [Code Segment]
DS [Data Segment]
SS [Stack Segment]
ES [Extra Segment]
IP [Instruction pointer]
SP [Stack pointer]
BP [Base pointer]
SI [Source Index]
DI [Destination Index]
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General Purpose
Registers
Segment Registers
Base address of segments
Pointer Registers
Offset within a segment
Index Registers
x x x x O D I
Flags
T S Z x A x P x C
25
AAiT
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Segment
AAiT
Offset
<< 4
Segment
0000
Adder
Physical Address
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AAiT
Rule of thumb
The P has a set of rules that apply whenever memory is addressed,
which defines the segment-offset register combinations used by
certain addressing modes
Segment
offset
Special Purpose
CS
IP
Instruction Address
DS
BX, BP, DI or SI
Data Address
SS
SP or BP
Stack Address
ES
SI/DI
String source/destination
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8086 Datasheet
Pin layout and signal descriptions
Physical memory organization
General bus operations
I/O addressing capabilities
Special processor activities