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Features
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Ordering Information
RT8152
Package Type
QW : WQFN-32L 5x5 (W-Type)
Operating Temperature Range
G : Green (Halogen Free with Commercial Standard)
VRON Power
C : 1.05V
D : 3.3V
Applications
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Note :
Richtek Green products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
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1
RT8152C/D
Pin Configurations
VID4
VID5
VID6
VRTT
VID0
VID1
VID2
VID3
(TOP VIEW)
32 31 30 29 28 27 26 25
NTC
OCSET
DPRSLPVR
VRON
PGOOD
24
23
CLKEN
VCC
SOFT
BOOT
UGATE
PHASE
PGND
LGATE
PVDD
GND
TON
22
21
GND
20
19
18
33
17
COMP
ISEN_N
ISEN
10 11 12 13 14 15 16
RGND
CM
CMSET
VSEN
FB
WQFN-32L 5x5
RT8152C/D
R1
+5V
VCC
TON
17
R2
R3
19
C2
C5
C3
C1
PVDD
VID0
BOOT 24
UGATE 23
30 VID1
PHASE 22
LGATE 20
VID4
29 VID2
28
VID3
27 VID4
VID5
26
31
VID0
VID1
VID2
VID3
VID5
25 VID6
3 DPRSLPVR
4 VRON
VID6
DPRSLPVR
VRON
PGND
R4
C4
Q1
L1
R5
R8
V OUT
Q2
R6
21
D1
R7
C7
C OUT
C6
16
ISEN
ISEN_N 15
CMSET
R13
11
C9
VSEN 12
FB 13
PWRGD
6 CLKEN
32
VRTT
CLKEN
VRTT
R9
R10
V CC
NTC2
C13
CPU V CC_SNS
COMP
14
R18
R21
R20
R19
V OUT
NTC1
R11
RGND 9
V CCP
+3.3V
R14
C12
PGOOD
1
R15
R16
NTC
OCSET
SOFT 8
CPU V SS_SNS
C10
R22
CM 10
CM
R12
R17
GND
C11
CPU V SS_SNS
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2
RT8152C/D
V IN
5V to 25V
RT8152C/D
R1
+5V
VCC
TON
17
R2
R3
19
C2
PVDD
VID0
BOOT 24
UGATE 23
30 VID1
PHASE 22
LGATE 20
VID4
29 VID2
28
VID3
27 VID4
VID5
26
31
VID0
VID1
VID2
VID3
VID5
25 VID6
3 DPRSLPVR
4 VRON
VID6
DPRSLPVR
VRON
6 CLKEN
5
PWRGD
32
VRTT
R9
V CC
PGND
Q1
R8
V OUT
Q2
R6
D1
CMSET
C7
R13
11
C OUT
C9
VSEN 12
FB 13
C12
C13
GPU V CC_SNS
PGOOD
VRTT
R7
C6
COMP
14
R18
R21
R20
R19
V OUT
NTC1
R11
SOFT 8
1
R16
L1
R5
ISEN
ISEN_N 15
RGND 9
NTC
OCSET
GPU V SS_SNS
C10
R22
CM 10
CM
R12
R17
NTC2
C4
16
V CCP
R15
R4
21
+3.3V
R14
C5
C3
C1
GND
C11
GPU V SS_SNS
Pin Name
Pin Function
Thermal Detection Input for VRTT Circuit. Connect this pin with a resistor divider
NTC
from VCC using NTC on the top to set the thermal management threshold level.
Over Current Protection Setting. Connect a resistor voltage divider from VCC to
OCSET
ground, the joint of the resistor divider is connected to OCSET pin, with a voltage
VOCSET, to set the over current threshold ILIM.
DPRSLPVR Deeper Sleep Mode Signal.
VRON
Voltage Regulator Enabler.
PGOOD
Power Good Indicator.
Inverted Clock Enable. Pull high by a resistor for CPU core application. This
CLKEN
open-drain pin is an output indicating the start of the PLL locking of the clock chip.
Connect to GND for Render application.
VCC
Chip Power.
Soft-Start. This pin provides soft-start function and slew rate controller.
The feedback voltage of the converter follows the ramping voltage on the SOFT pin
SOFT
during soft-start and other voltage transitions according to different mode of
operation and VID change.
Return Ground. This pin is the negative node of the differential remote voltage
RGND
sensing.
To be continued
DS8152C/D-00 July 2009
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3
RT8152C/D
Pin No.
10
Pin Name
CM
Pin Function
Current Monitor Output. This pin outputs a voltage proportional to the output
current.
Current Monitor Output Gain Externally Setting. Connect this pin with one
11
CMSET
12
VSEN
13
FB
14
COMP
15
ISEN_N
16
ISEN
17
TON
18,
33 (Exposed Pad)
GND
Ground. The exposed pad must be soldered to a large PCB and connected
to GND for maximum power dissipation.
19
PVDD
Driver Power.
20
LGATE
Lower Gate Drive. This pin drives the gate of the low-side MOSFETs.
21
PGND
Driver Ground.
PHASE
This pin is return node of the high-side MOSFET driver. Connect this pin to
the high-side MOSFET sources together with the low-side MOSFET drains
22
voltage sensing.
UGATE
24
BOOT
Upper Gate Drive. This pin drives the gate of the high-side MOSFETs.
Bootstrap Power Input. This pin powers the high-side MOSFET drivers.
Connect this pin to bootstrap capacitor.
Voltage ID. DAC voltage identification inputs for IMVP6.5.
25 to 31
32
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4
VID6 to VID0
VRTT
The logic threshold is 30% of the VCCP as the maximum value for low state
and 70% of the VCCP as the minimum value for the high state.
Voltage Regulator Thermal Throttling. This open-drain output pin will be
pulled low when the preset temperature level is exceeded.
RT8152C/D
Table 1. IMVP6.5 VID Code Table
VID6 VID5 VID4 VID3 VID2 VID1 VID0
Output
Output
1.5000V
1.0875V
1.4875V
1.0750V
1.4750V
1.0625V
1.4625V
1.0500V
1.4500V
1.0375V
1.4375V
1.0250V
1.4250V
1.0125V
1.4125V
1.0000V
1.4000V
0.9875V
1.3875V
0.9750V
1.3750V
0.9625V
1.3625V
0.9500V
1.3500V
0.9375V
1.3375V
0.9250V
1.3250V
0.9125V
1.3125V
0.9000V
1.3000V
0.8875V
1.2875V
0.8750V
1.2750V
0.8625V
1.2625V
0.8500V
1.2500V
0.8375V
1.2375V
0.8250V
1.2250V
0.8125V
1.2125V
0.8000V
1.2000V
0.7875V
1.1875V
0.7750V
1.1750V
0.7625V
1.1625V
0.7500V
1.1500V
0.7375V
1.1375V
0.7250V
1.1250V
0.7125V
1.1125V
0.7000V
1.1000V
0.6875V
To be continued
DS8152C/D-00 July 2009
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5
RT8152C/D
VID6 VID5 VID4 VID3 VID2 VID1 VID0
Output
Output
0.6750V
0.2875V
0.6625V
0.2750V
0.6500V
0.2625V
0.6375V
0.2500V
0.6250V
0.2375V
0.6125V
0.2250V
0.6000V
0.2125V
0.5875V
0.2000V
0.5750V
0.1875V
0.5625V
0.1750V
0.5500V
0.1625V
0.5375V
0.1500V
0.5250V
0.1375V
0.5125V
0.1250V
0.5000V
0.1125V
0.4875V
0.1000V
0.4750V
0.0875V
0.4625V
0.0750V
0.4500V
0.0625V
0.4375V
0.0500V
0.4250V
0.0375V
0.4125V
0.0250V
0.4000V
0.0125V
0.3875V
0.0000V
0.3750V
0.0000V
0.3625V
0.0000V
0.3500V
0.0000V
0.3375V
0.0000V
0.3250V
0.0000V
0.3125V
0.0000V
0.3000V
0.0000V
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6
VSEN
COMP
FB
SOFT
RGND
VID0
VID1
VID2
VID3
VID4
VID5
VID6
GND
DAC
V BOOT
VCC
Soft
Start
MUX
VDAC
NTC
ERROR
AMP
UVP Trip
Point
OVP Trip
Point
NVP Trip
Point
Mode
Selection
VRTT CLKEN
PGOOD
VCC
Offset Cancellation
OTP
Power On Reset
&
Central Logic
VRON
Mode
Selection
DPRSLPVR
TON
CM
Driver
Logic
Control
CCRCOT
On-Time
Generator
FB
PWMCP
OCP
Setting
OCSET
10
+
CM
CMSET
ISEN
ISEN_N
PGND
LGATE
PVDD
PHASE
UGATE
BOOT
RT8152C/D
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7
RT8152C/D
Absolute Maximum Ratings
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(Note 1)
VCC to GND --------------------------------------------------------------------------------------------------RGND, PGND to GND --------------------------------------------------------------------------------------VIDx to GND --------------------------------------------------------------------------------------------------DPRSLPVR, VRON to GND ------------------------------------------------------------------------------PGOOD, CLKEN, VRTT to GND -------------------------------------------------------------------------VSEN, FB, COMP, SOFT, OCSET, CM, CMSET, NTC to GND ----------------------------------ISEN, ISEN_N to GND -------------------------------------------------------------------------------------PVDD to PGND ----------------------------------------------------------------------------------------------LGATE to PGND
DC ---------------------------------------------------------------------------------------------------------------<20ns ----------------------------------------------------------------------------------------------------------PHASE to PGND
DC ---------------------------------------------------------------------------------------------------------------<20ns ----------------------------------------------------------------------------------------------------------BOOT to PHASE --------------------------------------------------------------------------------------------UGATE to PHASE
DC ---------------------------------------------------------------------------------------------------------------<20ns ----------------------------------------------------------------------------------------------------------TON to GND --------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25C
0.3V to 6.5V
0.3V to 0.3V
0.3V to VCC+
0.3V to VCC+
0.3V to VCC+
0.3V to VCC+
0.3V to VCC+
0.3V to 6.5V
2.778W
0.3V
0.3V
0.3V
0.3V
0.3V
36C/W
7C/W
150C
65C to 150C
260C
2kV
200V
(Note 3)
Supply Voltage, VCC ----------------------------------------------------------------------------------------Battery Voltage, VIN ----------------------------------------------------------------------------------------Junction Temperature Range ------------------------------------------------------------------------------Ambient Temperature Range -------------------------------------------------------------------------------
4.5V to 5.5V
5V to 25V
40C to 125C
40C to 85C
Electrical Characteristics
(VCC = 5V, TA = 25C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
--
10
mA
Supply Input
Supply Current
IVCC +
IPVDD
To be continued
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8
RT8152C/D
Parameter
Shutdown Current
Symbol
Test Conditions
Min
Typ
Max
Unit
--
--
--
20
--
40
50
60
80
100
120
ISS3
V FB
0.8
0.8
%VID
7.5
7.5
mV
RT8152C
1.089
1.1
1.111
RT8152D
1.188
1.2
1.212
70
80
--
dB
--
10
--
MHz
--
--
V/s
RL = 47k
0.5
--
3.6
V COMP = 2V
200
250
--
V COMP = 2V
--
20
--
mA
--
mV
ISEN_N = 1.5V
--
--
ISEN = 1.5V
--
--
--
10
--
V/V
DC Accuracy
Boot Voltage
V BOOT
Error Amplifier
DC Gain
RL = 47k
Gain-Bandwidth Product
GBW
Slew Rate
SRCOMP
V COMP
IOUTEA_COMP
(Note 5)
CLOAD = 5pF
(Note 5)
CLOAD = 10pF (Gain = 4,
Rf = 47k, V OUT = 0.5V 3V)
V OSCS
RISEN
DC Gain
V ISEN_IN
50
--
80
mV
V TON
ON-Time Setting
TON
--
350
--
ns
IRTON
25
--
280
TOff
250
--
500
ns
V UVLO
3.9
4.1
4.3
V OVABS
1.45
1.5
1.55
V OV
250
300
350
mV
Input Range
TON Setting
Protection
Under Voltage Lock-out
Threshold
Absolute Over Voltage
Protection Threshold
Relative Over Voltage
Protection Threshold
To be continued
DS8152C/D-00 July 2009
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9
RT8152C/D
Parameter
Under Voltage Protection
Threshold
Negative Voltage
Protection Threshold
Current Limit Threshold
Voltage
Thermal Shutdown
Threshold
Symbol
Test Conditions
Min
Typ
Max
Unit
400
350
mV
V UV
V NV
100
--
--
mV
V ILIM
46.5
50
53.5
mV
TSD
--
160
--
0.735
--
--
2.31
--
--
--
--
0.315
--
--
0.99
--
Logic Inputs
V IH
VRON Threshold
V IL
Leakage Current of VRON
DAC (VID0 VID6) and
DPRSLPVR
V IH
0.77
--
--
V IL
--
--
0.33
--
--
100
--
--
100
--
IPGOOD = 4mA
--
--
0.4
--
20
ms
TPG OOD
--
20
ms
V CLK EN
--
--
0.4
V OT
--
80
--
%VDD
V OT_HY
At VCC = 5V
--
230
--
mV
V VRTT
IVRTT = 40mA
--
--
0.4
770
800
830
mV
--
1.15
V TH_PGOOD
V PGOOD
PGOOD Delay
mV
Clock Enable
CLKEN Low Voltage
Thermal Throttling
Thermal Throttling
Threshold
Thermal Throttling
Threshold -Hysteresis
VRT T Output Voltage
Current Monitor
Current Monitor Output
Voltage in Operating
Range
Current Monitor Maximum
Output Voltage
--
To be continued
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10
RT8152C/D
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Gate Driver
Upper Driver Source
RUGATEsr
V BOOT V PHASE = 5V
V BOOT VUGATE = 1V
--
0.7
--
RUGATEsk
V UGATE = 1V
--
0.6
--
RLGATEsr
--
0.75
--
RLGATEsk
V LGATE = 1V
--
0.5
--
V BOOT VPHASE = 5V
V UGATE = 2.5V
--
--
V LGATE = 2.5V
--
--
V LGATE = 2.5V
--
--
PVDD to BOOT
--
30
--
R BOOT
Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution is recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. JA is measured in the natural convection at TA = 25C on a high effective four layers thermal conductivity test board of
JEDEC 51-7 thermal measurement standard. The case point of JC is on the expose pad for the WQFN package.
Note 5. Guaranteed by design.
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11
RT8152C/D
Typical Operating Characteristics
, L = 0.36
H, COUT = 330
F, No Load, TA = 25C, unless otherwise specified.
VIN = 12.6V, RTON = 150
100
90
70
VCC_SENSE (V)
Efficiency (%)
1.14
VIN = 8V
VIN = 12V
VIN = 19V
80
60
50
40
30
20
1.12
VIN = 8V
VIN = 12V
VIN = 19V
1.10
1.08
1.06
10
0
0
12
15
18
21
24
27
30
90
0.94
VCC_SENSE (V)
Efficiency (%)
60
50
40
30
20
21
24
27
30
0.92
0.91
0.90
VIN = 8V
VIN = 12V
VIN = 19V
0.89
0.88
0.87
0.86
10
0.85
0.84
0
0
12
15
18
21
24
27
30
12
15
18
21
24
27
30
1.1
95
1.0
90
0.9
0.8
85
0.7
VIN = 8V
VIN = 12V
VIN = 19V
80
75
V CM (V)
Efficiency (%)
18
0.93
VIN = 8V
VIN = 12V
VIN = 19V
70
15
100
80
12
70
VIN = 8V
VIN = 12V
VIN = 19V
0.6
0.5
0.4
65
0.3
60
0.2
55
0.1
0.0
50
0.3
0.6
0.9
1.2
1.5
1.8
2.1
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12
2.4
2.7
10
15
20
25
30
RT8152C/D
CPU Mode Power On
VCC_SENSE
(1V/Div)
VCC_SENSE
(1V/Div)
PGOOD
(5V/Div)
PGOOD
(5V/Div)
VRON
(5V/Div)
CLKEN
(5V/Div)
VRON
(5V/Div)
VID = 0.9375V, CLKEN Pull High to 3.3V
CLKEN
(5V/Div)
Time (1ms/Div)
Time (1ms/Div)
VCC_SENSE
(1V/Div)
PGOOD
(5V/Div)
UGATE
(20V/Div)
VRON
(5V/Div)
LGATE
(5V/Div)
CLKEN
(5V/Div)
VID0
(5V/Div)
VID = 0.9375V, CLKEN Pull High to 3.3V
Time (100s/Div)
Time (20s/Div)
VCC_SENSE
(100mV/Div)
VCC_SENSE
(100mV/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
LGATE
(5V/Div)
VID0
(5V/Div)
Time (20s/Div)
VID0
(5V/Div)
VID change from 0.9375V to 0.85V
Time (20s/Div)
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13
RT8152C/D
CCM Load Transient Response
VID = 0.9375V, ILOAD = 5A to 28A
CLKEN Pull High to 3.3V (CPU)
DPSLPVR = Low
VCC_SENSE
(50mV/Div)
VCC_SENSE
(50mV/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
LGATE
(5V/Div)
CLKEN Pull High to 3.3V (CPU)
Time (10s/Div)
Time (10s/Div)
VCC_SENSE
(100mV/Div)
I LOAD
(40A/Div)
VCC_SENSE
(1V/Div)
I LOAD
(20A/Div)
VID0
(5V/Div)
DPRSLPVR
(5V/Div)
PHASE
(10V/Div)
PWRGD
(2V/Div)
Time (40s/Div)
Time (10s/Div)
VCC_SENSE
(1V/Div)
VCC_SENSE
(1V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
LGATE
(10V/Div)
PWRGD
(2V/Div)
PWRGD
(2V/Div)
Time (10s/Div)
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14
Time (10s/Div)
RT8152C/D
Application Information
The RT8152C/D is a single-phase PWM controller with
embedded gate driver. It is compliant with Intel IMVP6.5
Voltage Regulator Specification to fulfill its mobile CPU
and Render voltage regulator power supply requirement.
Inductor current are continuously sensed for loop control,
droop tuning, and over-current protection. The 7-bit VID
DAC and a low offset differential amplifier allow the controller
to maintain high regulating accuracy to meet Intels
IMVP6.5 specification.
Design Tool
To help users to reduce the efforts and errors caused by
manual calculations using the design concept below, a
user-friendly design tool is now available on request.
This design tool calculates all necessary design
parameters by entering user's requirements. Please
contact Richtek's representatives for details.
Operation Modes
Table 2 shows the RT8152C/D operation modes. When
VRON is enable (=1), and within 10s the RT8152C/D will
detect the CLKEN to determine which operation mode is
applied. If the CLKEN is low, the RT8152C/D will operate
in Render core voltage regulator mode. If the CLKEN is
high, the IC will operate in CPU core voltage regulator
mode.
DPRSLPVR determines the operation mode of the
controller operation in CCM or RFM. The controller enters
RFM (Ring Free Mode) when DPRSLPVR = 1 and enters
CCM when DPRSLPVR = 0.
0.36uH
= 3.6k
1m 100nF
(2)
V OUT
L
PHASE
CLKEN
DPRSLPVR
Render CCM
(GND)
Render RFM
CPU CCM
(Pull High)
CPU RFM
Operation Mode
RX
ISEN
DCR
CX
+ VX -
ISEN_N
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15
RT8152C/D
Considering the inductance tolerance, the resistor RX has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load line requirement with a slow recovery, RX
is chosen too small. Vice versa, with a resistance too
large, the output voltage transient has only a small initial
dip and the recovery is too fast causing a ring-back.
Using current-sense resistor in series with the inductor
can have better accuracy, but the efficiency is a trade-off.
Considering the equivalent inductance (LESL) of the currentsense resistor, a RC filter is recommended. The RC filter
calculation method is similar to the above-mentioned
inductor DCR sensing method.
Loop Control
The RT8152C/D adopts Richtek's proprietary G-NAVPTM
topology. G-NAVPTM is based on the finite-gain current
mode with CCRCOT (Constant Current Ripple Constant
On Time) topology. The output voltage, VOUT, will decrease
with increasing output load current. The control loop
consists of PWM modulator with power stage, current
sense amplifier and error amplifier as shown in Figure 4.
V IN
RT8152C/D
UGATE
CCRCOT
PWM
Logic
RX
LGATE
V OUT
L
CX
LS_FET
CMP
+
COMP2
HS_FET
V CS
Ai
+
-
ISEN
ISEN_N
C2
COMP
EA
+
R2
R1
V CC_SENSE
(3)
A V = R2 =
R1
AI RSENSE
RDROOP
(4)
FB
+
-
Offset
Cancellation
C1
VDAC
V OUT
SOFT
RGND
A V2 > A V1
C SOFT
V SS_SENSE
A V2
A V1
0
Load Current
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16
RT8152C/D
Since the DCR of inductor is highly temperature dependent,
it affects the output accuracy at hot conditions.
Temperature compensation is recommended for the
lossless inductor DCR current-sense method. Figure 6
shows a simple but effective way of compensating the
temperature variations of the sense resistor using an NTC
thermistor placed in the feedback path.
C2
RT8152C/D
COMP
+
-
EA
+
VDAC
R2
R1b
FB
SOFT
R1a
(5)
) ( )}
1
298
T+273
(7)
(8)
Loop Compensation
V SS_SENSE
R2
R1a // RNTC, T + R1b
(9)
V CC_SENSE
NTC
{(
RSENSE, HOT
1 R
SENSE, COLD
C SOFT
RNTC, T = RNTC, 25 e
25
C1
RGND
A V, T =
R2 = AV,
1
2 C RC
(11)
C2 =
C RC
R2
(12)
RT8152C/D
shows the On-Time setting circuit. Connect a resistor
(RTON) between VIN and TON to set the on-time of UGATE:
12
14.5 10 RTON 2
TON =
(VIN VDAC)
(14)
TON THS-Delay
VDAC(MAX) + ILOAD(MAX) RON _ LS-FET + DCRL RDROOP
VIN(MAX) + ILOAD(MAX) RON _ LS-FET RON _ HS-FET
Where
CSOFT =
CCRCOT
On-Time
Generator
TON
VDAC
R TON
R1
V IN
C1
On-Time
ISS
SLEWRATE
(16)
Power-up Sequence
With the controller's VCC voltage rises above the POR
threshold (typ. 4.3V), the power-up sequence begins when
VRON goes high. If CLKEN = 1 (Pull High), the
RT8152C/D will enter CPU mode power-up sequence. If
the CLKEN = 0 (Connect to GND), the controller will enter
Render mode power-up sequence.
After the RT8152C/D enters CPU mode, VSEN starts
ramping up to VBOOT within 1ms. The slew rate during
power-up is 20A/CSOFT. The RT8152C/D pulls CLKEN low
after VSEN gets across VBOOT 0.1V for 73s. Right after
CLKEN goes low, VSEN starts ramping to first VDAC value.
After CLKEN goes low for approximately 4.7ms, PGOOD
is asserted HIGH. DPRSLPVR are valid right after PGOOD
is asserted. UVP is masked as long as VSEN is less than
VBOOT 0.1V.
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18
RT8152C/D
VCC 4.3V
4.1V
POR
VRON
VID
XX
Valid
V BOOT - 0.1V
xx
V BOOT
VSEN
PWM
0.2V
Hi-Z
DPRSLPVR
CCM
DPRSLPVR Defined
CCM
Pull Down
Valid
XX
XX
CLKEN
PGOOD
73us typ.
4.7ms typ.
VCC
4.3V
4.1V
POR
VRON
VID
XX
xx
Valid
VDAC-100mV
VDAC
VSEN
PWM
0.2V
Hi-Z
DPRSLPVR
CCM
XX
DPRSLPVR Defined
CCM
Pull Down
Valid
XX
PGOOD
4.77ms typ.
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19
RT8152C/D
Power-Down
When VRON goes low, the RT8152C/D enters low-power
shutdown mode. PGOOD is pulled low immediately and
the VSOFT ramps down with slew rate of 20A/CSOFT. VSEN
also ramps down following VSOFT. After VVSEN is lower than
200mV, the RT8152C/D turns off high-side FETs and lowside FETs. An internal discharge resistor at VSEN will be
enabled and the analog part will be turned off.
Deeper Sleep Mode Transitions
V CC
R OC1a
NTC
R OC1b
OCSET
R OC2
(17)
ROC1 = ROC2
1
VOCSET
(18)
V CC
ROC2 =
REQU, HOT REQU, COLD + (1 ) REQU, 25
VCC
(1 )
VOCSET, 25
R OC1
ROC1b =
R OC2
OCSET
(19)
(20)
(21)
Where
Figure 10. OCP Setting Without Temperature
Compensation
RT8152C/D provides current limit function and over current
protection. The current limit function is trggered when
inductor current exceeds the current limit threshold ILIM
defined by VOCSET. When current limit function is tripped,
high-side MOSFET will be forced off until the over current
condition is cleared.
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20
=
RSENSE, HOT
DCR25 [1 + 0.00393 (THOT 25)]
=
RSENSE, COLD DCR25 [1 + 0.00393 (TCOLD 25)]
(22)
REQU, T = R1a // RNTC, T
(23)
RT8152C/D
For example, the following design parameters are given :
V CC
VRTT
CMP
NTC
NTC
+
-
R TT
+
0.8 x V CC
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21
RT8152C/D
Users can use the same NTC thermistor for both thermalthrottling and current limit setting as shown in Figure 13.
Just divide the ROC1b into RTTa and RTTb, and write the
VNTC equation at thermal-throttling temperature TTC :
RTTa + RTTb = ROC1b
ROC2
(24)
ROC2 + RTTb
VCC = 0.8 VCC
+ ROC1b + ROC1a // RNTC, TT
(25)
(27)
V CC
VRTT
CMP
R OC1a
RCM = 55.6k
Current
Monitor
Generator
NTC
V CC_SENSE
R CMSET
CMSET
CM
V CM
R CM
R TTa
C1
RGND
NTC
VSEN
R TTb
+
0.8 x V CC
OCSET
R OC2
Inductor Selection
Figure 13. Using Single NTC Thermistor for ThermalThrottling and Current Limit Setting
Current Monitor
Figure 14 shows the current monitor setting principle.
Current monitor needs to meet IMVP6.5 specification, the
RT8152C/D is based on the relation between RDROOP and
load current to provide an easily setting and high accuracy
current monitor indicator.
The current monitor indication voltage VCM equation is
shown as :
VCM =
(28)
VIN VOUT
TON
IRipple MAX
(30)
VCM(MAX)
2 I(MAX) RDROOP
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22
(29)
RT8152C/D
Maximum Power Dissipation (W)
close proximity to the load. Latter ones are for midfrequency decoupling with especially small ESR and ESL
values while the bulk capacitors have to provide enough
stored energy to overcome the low-frequency bandwidth
gap between the regulator and the CPU.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
WQFN-32L 5x5
25
50
75
100
125
Layout Considerations
Careful PC board layout is critical to achieve low switching
losses and clean, stable operation. The switching power
stage requires particular attention. If possible, mount all
of the power components on the top side of the board
with their ground terminals flush against one another.
Follow these guidelines for optimum PC board layout :
`
RT8152C/D
Outline Dimension
D2
SEE DETAIL A
L
1
E2
1
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A
A1
1
2
A3
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
0.180
0.300
0.007
0.012
4.950
5.050
0.195
0.199
D2
3.400
3.750
0.134
0.148
4.950
5.050
0.195
0.199
E2
3.400
3.750
0.134
0.148
e
L
0.500
0.350
0.020
0.450
0.014
0.018
Headquarter
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
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24