QUESTIONS

1. what s difference b/w blocking and non blocking assignments?

where will u use it?
ans: 1.blocking stmt
these stmt blocks the other stmt from being executed.ie first these stmt gets executed before it lets other stmt execute.
2.Non blocking stmt
these stmt executes all parallely.withe designated delayes.
also see the link
http://asic-world.com/verilog/vbehave1.html#Procedural_Assignment_Statements
2. what s racing condition?
when s=1 and r=1, then both the signals fight against each other to determine the output.if this occurs output of the FF is not determined.
how to overcome?
1. we can reduce the noise.
2. (i think we can put master-slave FF)
3. if u replace latch enable signal by clock wat will be the difference?
(i think if we put clock ,then power consumption will be more)
4. how latch takes less power and ff takes more power?
(clock routing may take power)
5. what's diffrence b/w mealy and moore ckt?
mealy
it has less number of states.
it more prone to noise.
moore
it has more number of states.
it is less prone to noise.
6. how to overcome metastability?
by adding another FF
see our ASIC-by smith
7. if u have "case" stmt and "if" stmt, and if "case" s good for synthesis then wat s advantage of "if" stmt?
inside case stmt expression cannot be used like
case (x=x*5+y-10)
(x): z=5;
(y): f=10;
end case;

8. how will u write d ff using variables alone?(VHDL question)

(i don't know)
but i think using variable and signals we can write D FF
9. design a some gates using mux
refer any digital book
10. draw a state diagram for sequence detector.
refer any digital book
11. how to overcome racing condition?
(see the previous answer)
12. for a small example draw simlation time for non blocking assignment, blocking assignment.
(refer the previous link)
13. some questions on interfacing.

14. draw a simple circuit of D FF using pass gate transistor

refer any CMOS book
15. which universal gate do u prefer(NAND or NOR)?
ans: NAND gate
16. why?
ans: it takes less power,....(i think less arear)
17. draw the schematic of NAND gate.
see the book.
18. what determines drive strangth of a gate?
width of the gate determines drive strength of the gate.
19. what s clock skew?
when clock s routed through the chip it is subjected to parasitic capacitance,so the current is absorbed by the circuit, so clock is delayed by some
amount.which is called clock skew.
skew-- means delay
eqn:- r1+r1*c1+r1(c1+c2)+... like that (see any CMOS book)
20. how to reduce the frequency by half?(very very important question!!!)
ans i know:
just put a T FF.
if u put a T FF u reduce the freq by half.
if u put 2 power n FF, u reduce the frequency by n times.
they may ask u to code it in Verilog or VHDL.
21. how to double the frequency by two times.

see the link

http://www.hitequest.com/Hardware/El_hardware.htm