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by
Instructors Guide
Digital Communications 2
Edition 1 34935-10
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3034935100206
FIRST EDITION
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system,
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otherwise, without prior written permission from Lab-Volt Systems, Inc.
Information in this document is subject to change without notice and does not represent a
commitment on the part of Lab-Volt Systems, Inc. The Lab-Volt Information Technology
software and other materials described in this document are furnished under a license agreement
or a nondisclosure agreement. The software may be used or copied only in accordance with the
terms of the agreement.
FOREWORD
This instructor's guide provides a unit-by-unit outline of the principal points made
in the FACET curriculum. For each unit, instructors are given a unit objective, a
brief description of the material covered in each unit and a list of important points
to emphasize. Review question answers, unit test answers, faults and circuit
modifications (CM) are provided in the appendices.
SAFETY
INSTALLATION INSTRUCTIONS
Installing Courseware
Courseware is to be installed using the Configurator of Tech-Lab. For more
detailed information on installing Courseware refer to the Tech-Lab and
GradePoint 2020 Installation Guide Courseware installation section. The manual
number is 34288-E0.
Installing Resources
Resources are to be installed using the Configurator of Tech-Lab. For more
detailed information on installing and linking Resources to the courseware refer
to the Tech-Lab and GradePoint 2020 Installation Guide Resource installation
section. The manual number is 34288-E0.
Installing Applications
Install all applications per the manufacturers recommended settings. Refer to the
manufacturer documentation for assistance.
Applications are to be linked to the courseware using the Configurator of
Tech-Lab. For more detailed information on installing Applications refer to the
Tech-Lab and GradePoint 2020 Installation Guide Application installation section.
The manual number is 34288-E0.
ii
TABLE OF CONTENTS
UNIT 1: Circuit Board Familiarization
Exercise 1-1: Introduction to the Circuit Board
Exercise 1-2: Communications System Model
1-1
1-6
1-9
2-1
2-4
2-9
3-1
3-5
3-7
3-9
4-1
4-2
4-5
5-1
5-3
5-6
6-1
6-6
6-9
6-12
UNIT 7: Modem
Exercise 7-1: FSK Modem
Exercise 7-2: DPSK Modem
7-1
7-7
7-11
APPENDIX A
APPENDIX B
APPENDIX C
APPENDIX D
APPENDIX E
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EQUIPMENT REQUIRED
F.A.C.E.T. base unit
DIGITAL COMMUNICATIONS 2 circuit board
Power supply, 15 Vdc (2 required)*
Oscilloscope, dual trace
*Only required if the F.A.C.E.T. base unit does not contain a power supply.
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FAULTS AVAILABLE
None required
1-7
EXERCISE 1-2
EXERCISE OBJECTIVE
Demonstrate the operation of a communication system stage by stage.
DISCUSSION
The DIGITAL COMMUNICATIONS 2 circuit board has circuit blocks that perform the functions of all the elements of the comunications model.
The ENCODER block genetates signals that are encoded with digital data.
In the MODULATORS circuit block, the encoded signals modulate a carrier
signal.
The CHANNEL SIMULATOR circuit block simulates the transmission medium
over which the modulated signal is carried.
Demodulation is accomplished using the detectors.
The MAN SYNC DECODER block recovers the NRZ and clock signals.
CMs AVAILABLE
None required
FAULTS AVAILABLE
None required
PROCEDURE
The 30 procedure steps in this exercise include the following:
produce ASK by using the MAN output to the ENCODER block to
amplitude-modulate a carrier
transmit the ASK signal through the CHANNEL SIMULATOR and
introduce noise
1-9
recover the Manchester signal from the ASK using the SYNC DETECTOR
circuit block
decode the recovered Manchester signal into NRZ and clock signals using the
MAN SYNC DECODER circuit block
1-10
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recovery when long strings of 0's are transmitted.
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CMs AVAILABLE
CM2 - Data pattern = 10101010; sent at 300 bps
CM1 & CM2 - Data pattern = 01000100; sent at 1200 bps
FAULTS AVAILABLE
None required.
PROCEDURE
The 62 procedure steps in this exercise include the following:
NRZ LINE CODING
measuring the time period of the CLK
determining the length of the data word
determining the value of the bits contained in the data word
measuring the baud rate
determining the transmission speed
RZ LINE CODING
determining the value of the bits contained in the data word
determining the baud rate
determining the transmission speed
MANCHESTER LINE CODING
determining the value of the bits contained in the data word
observe the clocking information on the MANCHESTER coded signal
determining the baud rate
determining the transmission speed
relate baud rate to signal bandwidth
LINE LEVEL CODING
compare polar and unipolar NRZ signals
measure the dc content of a polar NRZ signal
measure the dc content of a polar Manchester signal
compare the dc content of Manchester and NRZ polar signals
2-5
EXERCISE 2-2
Decoding
EXERCISE OBJECTIVE
Describe three common methods used to decode RZ and Manchester signals
into NRZ signals.
DISCUSSION
Sometimes data and clock signals are sent over separate lines.
RZ and Manchester coded data can be decoded using a D-type flip-flop.
An XOR gate can be used to decode Manchester coded data.
CMs AVAILABLE
CM2 - Data pattern = 10101010; sent at 300 bps
FAULTS AVAILABLE
None required.
PROCEDURE
The 51 procedure steps in this exercise include the following:
DECODING RZ
decode RZ using a D-type flip-flop
compare RZ to decoded NRZ
observe the limited clock information available from an RZ signal
compare the decoded NRZ with the NRZ before it was coded as RZ
DECODE MANCHESTER.
decode Manchester using an XOR gate.
observe decoding spikes (glitches) that can occur.
compare the decoded NRZ with the NRZ before it was Manchester
coded.
lock the PLL
recover the CLK from the Manchester.
decode Manchester to NRZ.
2-9
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If the channel's passband is wide enough, two carrier signals can be used to
provide full-duplex operation. The BELL 103 standard defines a full-duplex 300
baud FSK modem using two audio carrier signals. The station originating the call
transmits 1070 Hz for a logic low and 1270 Hz for a logic high. The station
answering the phone transmits a 2025 Hz for a logic low and 2225 Hz for a logic
high. Each change in the baseband signal generates one change in the 300 baud
BELL 103 FSK carrier frequency.
FSK demodulators fall into two basic categories, synchronous and asynchronous. Asynchronous demodulators filter the carrier signal before using an
envelope detector to recover the baseband signal. Synchronous demodula-tors
synchronize a reference signal with the carrier signal to detect changes in carrier
frequency and recover the baseband signal.
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EXERCISE 3-1
EXERCISE OBJECTIVE
Describe the relationship between FSK and the baseband digital modulating
signal. Describe how an analog multiplexer can be used as an FSK modulator.
Describe the frequency spectrum of an FSK signal.
DISCUSSION
FSK is a simple low-cost modulation technique.
The FSK modulator can be acoustically coupled or direct coupled.
A VCO can be used as an FSK modulator.
The circuit board uses an analog MUX as an FSK modulator.
CMs AVAILABLE
CM6 - Changes the phase of the HI TONE carrier signal.
CM12 - Removes the HI TONE carrier from thr FSK MODULATOR.
FAULTS AVAILABLE
None Required.
PROCEDURE
The 39 procedure steps in this exercise include the following:
determine the baud rate of the NRZ modulating signal
determine the baud rate of the FSK MODULATOR output
compare the amplitude of the FSK when the modulating signal is high
and low
compare the FSK phase before and after the frequency changes
compare the FSK frequency for an NRZ high and low
observe the details of how a MUX is used to generate FSK
describe the frequency spectrum of an FSK signal as the spectrum of
two OOK signals
observe FSK switching discontinuities and note their effect on signal
bandwidth
3-5
EXERCISE 3-2
EXERCISE OBJECTIVE
Recover the baseband NRZ signal from the FSK signal, demonstrate how a filter
can convert an FSK signal into changes that represent the baseband signal, and
demonstrate the operation of an asynchronous envelope detector.
DISCUSSION
The FSK demodulator recovers the baseband digital signal by detecting the
frequency changes in the FSK carrier signal.
An FSK signal consists of two on-off keying (OOK) signals.
A bandpass filter can be used to pass one of the OOK carrier signals while
attenuating the other.
The filter output will change in amplitude as the FSK changes frequency.
The amplitude changes are detected by an asynchronous detector.
CMs AVAILABLE
CM7 - Changes the CHANNEL bandwidth to 1600 Hz
CM16 - Changes the center frequency of the ASYNC DETECTOR BANDPASS
filter from 3000 Hz to 1500 Hz.
3-7
FAULTS AVAILABLE
None required.
PROCEDURE
The 29 procedure steps in this exercise include the following:
review the relationship between the modulating NRZ and modulated FSK
signals
observe the amplitude changes in the bandpass filter output
determine that the FWR block output is a full wave rectified ASK signal
observe the data present in the low-pass filter output
adjust the voltage comparator reference voltage to restore the logic levels
of the recovered coded data
reduce the bandwidth of the channel simulator and observe that the NRZ is
more difficult to recover
3-8
EXERCISE 3-3
EXERCISE OBJECTIVE
Recover a digitial signal from an FSK signal using a syncronous detector,
demonstrate how a phase-locked loop can be used to detect the baseband digital
signal, and describe the operation of a phase-locked loop configured as a
frequency to voltage converter.
3-9
DISCUSSION
The FSK demodulator recovers the baseband digital signal by detecting the
frequency changes in the FSK carrier signal.
CMs AVAILABLE
CM6 - Changes the phase of the HI TONE carrier signal.
CM7 - Changes the CHANNEL bandwidth to 1600 Hz
CM10 - Selects the FSK phase comparator filter in the SYNC DETECTOR PLL
circuit.
FAULTS AVAILABLE
None Required.
PROCEDURE
The 40 procedure steps in this exercise include the following:
observe that the PLL output is not synchronous with the FSK signal when
the phase comparator has no input
observe that the phase comparator output keeps the VCO output
synchronous with the FSK signal
observe the XOR function used by the phase comparator
determine that the level of the VCO input (phase comparator output)
represents the frequency of the FSK signal
measure the frequency of the VCO when the NRZ is high and low
observe that the VCO input represents the state of the NRZ signal
determine that the VCO input is low-pass filtered before the NRZ logic
levels are restored using a voltage comparator
determine that a synchronous detection is less sensitive to amplitude
variations than asynchronous detection
determine that synchronous detection is sensitive to phase noise
3-10
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The regenerated carrier signal is then combined with the PSK signal in a product
detector. The product detector output is low-pass filtered, and the resulting
pulses are shaped by a voltage comparator to recover the original digital
intelligence signal from the received signal.
NEW TERMS AND WORDS
There are no new terms and words in this unit.
SCHEMATIC, CMs AND FAULTS
SCHEMATIC
CM
FAULT
SWITCH
NUMBER NUMBER
NUMBER
S6
CM6
CIRCUIT CHANGE
WHEN ACTIVE
EXERCISE OBJECTIVE
Explain and demonstrate how PSK signal generation is accomplished on the
circuit board.
DISCUSSION
The original signal is shifted from 0 and +5V logic levels to -5V and +5V polar
logic levels.
The polar digital signal is then multiplied with a carrier signal in a balanced
modulator.
Multiplying by a positive voltage produces a 0 phase shift.
Multiplying by a negative voltage produces a 180 phase shift.
PSK can be used with any type of encoding.
4-2
CMs AVAILABLE
CM6 - Changes the phase of the HI TONE carrier signal.
FAULTS AVAILABLE
None required.
PROCEDURE
The 20 procedure steps in this exercise include the following:
configure the MODULATORS block to produce a PSK modulated signal
use the BAL pot to control polar signal dc offset
determine that the modulator output is a PSK signal that represents the
digital input
measure the phase of the PSK signal when a logic high is input to the
modulator
observe a discontinuous PSK output when the phase between the carrier
and the baseband data signal is changed
4-3
EXERCISE 4-2
Synchronous Detection
EXERCISE OBJECTIVE
Explain and demonstrate synchronous detection of a PSK signal.
DISCUSSION
The carrier synchronizer regenerates a carrier from the received PSK signal.
The PLL VCO OUT frequency will also be twice the PSK signal frequency.
The doubler is a full wave rectifier and bandpass filter which removes the
intelligence from the PSK and doubles its frequency.
The final stage divides the VCO OUT frequency by 2 and shifts it by 90 to
produce the regenerated carrier.
The regenerated carrier is mixed with the PSK to demodulate the signal.
The low-pass filter and voltage comparator perform the final shaping of the
pulses.
CMs AVAILABLE
CM11 - Selectes the ASK/PSK phase comparator filter in the SYNC DETECTOR PLL circuit.
FAULTS AVAILABLE
None required.
PROCEDURE
The 29 procedure steps in this exercise include the following:
configure the circuit board to produce a PSK-modulated signal
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The carrier is disconnected (switch open) from the output for a binary 0. This
special technique of amplitude modulation is called on-off keying (OOK). The
abrupt on and off changes between signaling elements requires an increased
channel bandwidth over standard ASK.
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Manchester.
CMs AVAILABLE
CM1 & CM2 - Data pattern = 01000100; sent at 1200 bps.
FAULTS AVAILABLE
None required.
PROCEDURE
The 24 procedure steps in this exercise include the following:
generate an ASK modulated signal from an NRZ encoded signal
observe inputs and outputs with an oscilloscope
adjust offsets
5-4
EXERCISE 5-2
EXERCISE OBJECTIVE
Explain and demonstrate how ASK detection is accomplished on your circuit
board.
DISCUSSION
Detection, or demodulation, is the process of recovering the transmitted digital
intelligence from a modulated signal.
The amplitude changes in the ASK input signal are detected to recover the
original NRZ signal.
ASK signals can be demodulated asynchronously or synchronously.
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Noise can affect either the amplitude or phase of a signal. Phase noise is due to
inherent delays in circuits and components. Amplitude noise can be meas-ured
by determining the bit error rate (BER).
There are several ways to measure the BER. This block diagram shows the
method used by the BER COUNTER block on your circuit board.
The transmitted and received data are compared bit by bit. If the bits do not
match, an error pulse is generated. The errors are totalized in a counter over a
fixed time period generated by a one-shot. A display indicates how many err-ors
occurred within the time interval.
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An XOR gate is used because an error can be defined as a condition where the
received data is not the same as the transmitted data.
Each time you press and release the RESET pushbutton, the control circuit
simultaneously resets the counter and triggers a 106 ms one-shot. In your
circuit, 106 ms is the time required for 128 data bits.
Error pulses from the XOR gate are totalized by the counter only during the 106
ms window.
If you press and release RESET a second time, only the number of error pulses
in the second interval is displayed.
CMs AVAILABLE
CM7 - Changes the channel bandwidth to 1600 Hz.
CM15 - Changes the channel noise frequency.
FAULTS AVAILABLE
None required.
PROCEDURE
The 22 procedure steps in this exercise include the following:
apply a sine wave signal to the channel
observe the effects of channel band-limiting on the recovered signal
observe inputs and outputs with an oscilloscope
add noise to the signal and observe the effects on the recovered signal
observe the effects of changes in the noise bandwidth
convert your peak-to-peak measurements to rms values
calculate the signal-to-noise ratio (SNR) in decibels
determine the bit error count of an NRZ signal applied to the channel
calculate the bit error rate (BER) from the bit error count
6-7
EXERCISE 6-2
EXERCISE OBJECTIVE
Explain and demonstrate the effects of noise on ASK- and PSK-modulated
signals.
DISCUSSION
Noise can cause errors in digital transmission by causing logic levels to be read
incorrectly.
Zero volts is much smaller than the amplitude of a normal ASK signal, so noise
is often not sufficient to affect the recovered digital signal.
A low zero-state amplitude condition results in better noise immunity.
Because the PSK signal has a constant amplitude, it is not as sensitive to
amplitude noise.
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EXERCISE OBJECTIVE
Explain and demonstrate the effects of noise on FSK-modulated signals.
6-12
DISCUSSION
Noise can change the amplitude of an FSK signal, which also affects the
amplitude at the output of the bandpass filter.
Amplitude changes are passed on to the envelope detector which results in
errors in the recovered digital signal.
FSK signals can be detected either synchronously or asynchronously.
Synchronous detection provides better amplitude noise response because the
phase comparator senses phase changes independent of the signal amplitude.
In the case of asynchronous detection, noise response is improved by the
bandpass filter. Any noise frequencies outside the passband are attenuated by
the filter.
Noise frequencies above the high cutoff frequency and below the low cutoff
frequency will be rejected by the channel.
Telephone circuits are designed to pass a bandwidth limited to about 300 to
3000 Hz, which includes the high and low FSK carrier frequencies. Any noise
frequencies outside the passband are attenuated.
CMs AVAILABLE
CM10 - Selects the FSK phase comparator filter in the sync detector PLL circuit.
FAULTS AVAILABLE
None required.
PROCEDURE
The 44 procedure steps in this exercise include the following:
observe the effects of noise on an FSK-modulated, synchronously-detected
signal
observe the effects of noise on an asynchronously-detected FSK signal
observe inputs and outputs with an oscilloscope
compare the noise response of the sync and async detectors with an FSK
signal applied
demonstrate that the sync detector has better noise immunity than the
async detector
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EXERCISE 7-1
FSK Modem
EXERCISE OBJECTIVE
Describe and demonstrate the operation of an FSK modem.
DISCUSSION
For the transmit section of the modem IC configured for FSK operation:
The TXD input accepts digital information from the DTE.
The data is modulated and filtered for transmission and then output from ATO.
The control and mode selection circuitry has several external inputs used to
configure the modem.
Four inputs are connected to CM switches for external control. These inputs are
pulled high by external resistors, but they can be grounded by the CMs. CM4 is
a normally closed switch, while the others are normally open.
CM17 allows you to select answer or originate mode (A#/O).
With CM19, you can select the CCITT or Bell operating mode (C#/B).
The TL# (test loop) input allows you to select one of several test loop modes for
checking modem operation.
The test loop selected also depends on the modulation type (FSK or DPSK),
the standard (CCITT or Bell), and the BRS and A#/O input states.
BRS (binary rate selection) sets the modem for a high speed of 1200 bps (BRS
= 1) or a low speed of either 300 or 600 bps (BRS = 0).
A bit clock signal from the DTE is applied to a PLL via the TCLK input; this
synchronizes the chip's internal transmit clock.
An internal clock circuit, in conjunction with an external crystal, provides all the
required synchronization of both internal and external circuitry.
For the receive section of the modem IC when it is configured for FSK operation:
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(300 x 16 = 4800)
observe the DCD# output while making and breaking the connection
between RAI and ATO to confirm that the DCD# level indicates the
presence or absence of a signal at RAI
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ORRS
use the oscilloscope to measure the phase of the ATO at each bit time
calculate the phase change between adjacent bit times
use a table to confirm that the phase changes indicate dibit values of 00
open TXD to input a continuous string of zeroes
use the oscilloscope to measure the phase of the ATO at each bit time
calculate the phase change between adjacent bit times
use a table to confirm that the phase changes indicate dibit values of 11
connect NRZ as the input signal to TXD
compare the TXD and TEST signals and observe that the TEST output
signal is a reproduction of the NRZ input signal, but with an offset
use the oscilloscope to determine the number of dibits by which TEST
lags TXD
use the oscilloscope to measure the phase of the output signal at each
bit time
calculate the phase changes between adjacent dibits
use the phase changes to determine the data pattern of the output signal
activate a CM to enable the scrambler circuit
use the oscilloscope to confirm that the scrambler changes the
transmitted data pattern, and that the descrambler changes it back to the
original pattern
connect the modem output through the CHANNEL and back to the
modem input
activate a CM to attenuate the CHANNEL output, and turn the NOISE
pot to add noise to the signal
view the ATO signal and observe that the noise and attenuation do not
significantly affect the modem output
configure the modem for CCITT V.22, 600 bps, two-phase DPSK
operation
ground the TXD input to simulate transmission of a string of zeroes
measure the ATO signal phase at each bit time
calculate the phase change between adjacent bit times to determine that
the data bits are all zeroes
open the TXD input to simulate transmission of a string of ones
measure the ATO signal phase at each bit time
calculate the phase change between adjacent bit times to determine that
the data bits are all ones
7-13
APPENDIX A
Question Number
3
1-1
1-2
2-1
2-2
3-1
3-2
3-3
4-1
4-2
5-1
5-2
A-1
1
B
2
A
Question Number
3
C
4
D
5
A
6-2
6-3
7-1
7-2
A-2
Unit Number
Question Number *
5
6
* question numbers apply only when the question order is NOT randomized.
10
A-3
A-4
APPENDIX B
CIRCUIT MODIFICATIONS
NOTE: Only one circuit modification (CM) switch should be
activated at any one time. Fault and CM switches should not be
used together. Turning on multiple switches will cause
unpredictable results.
CIRCUIT
BLOCK
SWITCH
NUMBER
Default
Data
Pattern
S1
S2
S1 & S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
SWITCH EFFECT
(WHEN ON)
Data pattern = 10110100; sent at 1200
bps
Data pattern = 10110100; sent at 600 bps
Data pattern = 10101010; sent at 300 bps
Data pattern = 01000100; sent at 1200
bps
Changes the ASYNC DECTOR low-pass
filter cutoff frequency from 700 to 1500
Hz.
Changes the MODEM from test loop 3 to
normal operation mode.
Increases the gain of the D input to the
second stage of the ASYNC DETECTOR
full wave rectifier.
Changes the phase of the HIGH_TONE
carrier signal.
Changes the CHANNEL bandwidth to
1600 Hz.
Severely attenuates the CHANNEL
output.
Changes the CHANNEL bandwidth to
3200 Hz.
Selects the FSK phase comparator filter in
the SYNC DETECTOR PLL circuit.
Selects the ASK/PSK phase comparator
filter in the SYNC DETECTOR PLL circuit.
Removes the HIGH_TONE from the FSK
MODULATOR.
Removes the CARRIER signal from the
ASK/PSK MODULATOR circuit.
Opens the polar NRZ input to the PSK
MODULATOR circuit.
Changes the CHANNEL noise frequency.
Changes the center frequency of the
ASYNC DETECTOR BANDPASS filter
from 3000 Hz to 1500 Hz.
B-1
CIRCUIT
BLOCK
SWITCH
NUMBER
S17
S18
S19
S20
SWITCH EFFECT
(WHEN ON)
Configures the MODEM for answer mode.
Configures the MODEM for 1200 bps.
Configures the MODEM for CTITT.
Turns the MODEM input scrambler.
B-2
APPENDIX C
FAULTS
NOTE: Only one circuit modification (CM) switch should be
activated at any one time. Fault and CM switches should not be
used together. Turning on multiple switches will cause
unpredictable results.
CIRCUIT
BLOCK
SWITCH
NUMBER
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
SWITCH EFFECT
(WHEN ON)
Prevents POLAR INV from going high in
the FSK MODULATOR circuit.
Opens the output of the buffer amplifier
in the ASK/PSK MODULATOR circuit.
Loads down the output of the ASYNC
DETECTOR low-pass filter.
Opens the PLL-VCO frequency range
resistor in the SYNC DETECTOR circuit.
Opens the output of the mixer buffer amp
in the SYNC DETECTOR circuit.
Opens the output of the phase shifter
XOR gate in the SYNC DETECTOR
cirucit.
Shorts one of the DOUBLER diodes in
the SYNC DETECTOR circuit.
Removes the clock from the low-pass
filter in the SYNC DETECTOR circuit.
Opens the output of the CHANNEL.
Opens the PLL signal input to the phase
comparator in the MAN SYNC
DECODER.
Opens the LOCK frequency adjust on
the PLL in the MAN SYNC DECODER.
Opens the receive analog input (RAI) to
the MODEM.
C-1
C-2
APPENDIX D
D-1
D-2
Which of the following will have the least effect on the output of
an FSK synchronous detector?
a. changes in the FSK carrier signals amplitude
b. changes in the FSK carrier signals phase
c. changes in the FSK carrier signals frequency
d. changes in the FSK carrier signals digital data
D-3
Why are voice grade telephone lines limited to about 1200 baud
when using an FSK modulated carrier signal?
a. The phone system provides a limited passband.
b. The data is NRZ encoded.
c. It is the maximum baud rate for any FSK signal.
d. The phone system cannot pass dc signals.
D-4
D-5
D-6
D-7
D-8
D-9
D-10
D-11
Which of the following will have the least effect on the output of
an FSK synchronous detector?
a. changes in the FSK carrier signals amplitude
b. changes in the FSK carrier signals phase
c. changes in the FSK carrier signals frequency
d. changes in the FSK carrier signals digital data
D-12
Why are voice grade telephone lines limited to about 1200 baud
when using an FSK modulated carrier signal?
a. The phone system provides a limited passband.
b. The data is NRZ encoded.
c. It is the maximum baud rate for any FSK signal.
d. The phone system cannot pass dc signals.
D-13
D-14
D-15
D-16
D-17
D-18
APPENDIX E
Courseware Problems
The F.A.C.E.T. courseware has been written to meet carefully
selected objectives. All exercises have been tested for
accuracy, and information presented in discussions has been
reviewed for technical content. Tolerances have been computed
for all procedure and review question answers to assure that
responses are not invalidated by component or instrument
errors.
Nevertheless, you or your students may discover mistakes or
experience difficulty in using our publications. We appreciate
your comments and assure you that we will weigh them
carefully in our ongoing product improvement efforts.
As we address courseware problems, we will post corrections
for download from our web site, www.labvolt.com. Select the
customer support tab, and then choose product line: FACET.
Select a course, select from a list of symptoms that have been
addressed, and follow the instructions.
E-1
We will do our best to help you resolve problems if you call the
number below. However, for best results, and to avoid
confusion, we prefer that you write with a description of the
problem.
If you write, please include the following information:
E-2
THIS
THIS