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The design of portable devices requires consideration for peak power consumption to
ensure reliability and proper operation. However, the time averaged power is often more critical
as it is linearly related to the battery life. There are four sources of power dissipation in digital
CMOS circuits: switching power, short-circuit power, leakage power and static power. The
following equation describes these four components of power:
Pswitching is the switching power. For a properly designed CMOS circuit, this power
component usually dominates, and may account for more than 90% of the total power. denotes
the transition activity factor, which is defined as the average number of power consuming
transitions that is made at a node in one clock period. Vs is the voltage swing, where in most
cases it is the same as the supply voltage, Vdd. CL is the node capacitance. It can be broken into
three components, the gate capacitance, the diffusion capacitance, and the interconnect
capacitance. The interconnect capacitance is in general a function of the placement and routing.
fck is the frequency of clock. The switching power for static CMOS is derived as follows.
During the low to high output transition, the path from Vdd to the output node is con-
ducting to charge CL. Hence, the energy provided by the supply source is
where is the current drawn from the supply. Here, R is the resistance of the
path between the Vdd and the output node. Therefore, the energy can be rewritten as
During the high to low transition, no energy is supplied by the source. Hence, the average power
consumed during one clock cycle is
Eq. (2.4) and Eq. (2.5) estimate the energy and the power of a single gate only. From a system
point of view, is used to account for the actual number of gates switching at a point in time.
Pshortcircuit is the short-circuit power. It is a type of dynamic power and is typically
much smaller than Pswitching. Isc is known as the direct-path short circuit current. It refers to
the conducting current from power supply directly to ground when both the NMOS and PMOS
transistors are simultaneously active during switching.
Pleakage is the leakage power. Ileakage refers to the leakage current. It is primarily
determined by fabrication technology considerations and originates from two sources. The first is
the reverse leakage current of the parasitic drain-/source-substrate diodes. This current is in the
order of a few femtoamperes per diode, which translates into a few microwatts of power for a
million transistors. The second source is the sub threshold current of MOSFETs, which is in the
order of a few nanoamperes. For a million transistors, the total subthreshold leakage current
results in a few milliwatts of power.
Pstatic is the static power and Istatic is static current. This current arises from circuits that
have a constant source of current between the power supplies such as bias circuitries, pseudo-
NMOS logic families. For CMOS logic family, power is dissipated only when the circuits
switch, with no static power consumption.
Energy is independent of the clock frequency. Reducing the frequency will lower the
power consumption but will not change the energy required to perform a given operation, as
depicted by Eq. (2.4) and Eq. (2.5). It is important to note that the battery life is determined by
energy consumption, whereas the heat dissipation considerations are related to the power
consumption.
There are four factors that influence the power dissipation of CMOS circuits. They are
technology, circuit design style, architecture, and algorithm. The challenge of meeting the
contradicting goals of high performance and low power system operation has motivated the
development of low power process technologies and the scaling of device feature sizes.
Design considerations for low power should be carried out in all steps in the design hierarchy,
namely 1) Fundamental, 2) material, 3) device, 4) circuit, and 5) system.
2.1 LOW VOLTAGE
Power consumption is linearly proportional to voltage swing (Vs) and supply voltage
(Vdd) as indicated in Eq. (2.5). For most CMOS logic families, the swing is typically rail-to-rail.
Hence, power consumption is also said to be proportional to the square of the supply voltage,
Vdd. Therefore, lowering the Vdd is an efficient approach to reduce both energy and power,
presuming that the signal voltage swing can be freely chosen. This is, however, at the expense of
the delay of circuits. The delay, td, can be shown to be proportional to .The
exponent is between 1 and 2. It tends to be closer to 1 for MOS transistors that are in deep
sub-micrometer region, where carrier velocity saturation may occur. increases toward 2 for
longer channel transistors.
The current technology trends are to reduce feature size and lower supply voltage.
Lowering Vdd leads to increased circuit delays and therefore lower functional throughput.
Smaller feature size, however, reduces gate delay, as it is inversely proportional to the square of
the effective channel length of the devices. In addition, thinner gate oxides impose voltage
limitation for reliability reasons. Hence, the supply voltage must be lowered for smaller
geometries. The net effect is that circuit performance improves as CMOS technologies scale
down, despite of the Vdd reduction. Therefore, the new technology has made it possible to fulfill
the contradicting requirements of low-power and high throughput.
The various techniques that are currently used to scale the supply voltage include
optimizing the technology and device reliability, trading off area for low power in architecture
driven approach, and exploiting the concurrency possibility in algorithmic transformations.
Hence, the voltage scaling is limited by the threshold voltage Vth.
In applications such as digital processing, where the throughput is of more concern than
the speed, architecture can be designed to reduce the supply voltage at the expense of speed
without throughput degradation. Hence, the performance of the system can be maintained.
2.2 SWITCHING ACTIVITY REDUCTION
CMOS circuits dissipate power only when switching, therefore it is important to minimize
the switching activity for low power applications. Switching is decreased when the data rate is
low. Switching activity can be reduced by algorithmic optimization, architecture optimization,
logic topology, and circuit optimization, which are discussed as follows.
Algorithmic optimization depends heavily on the application and on the characteristics of
the data. Furthermore, the data representation may have a significant impact on the switching
activity. Recent researches show that the use of a gray code in address bits, where data changes
sequentially, results in less transition than the use of binary code.
Architecture optimization can be achieved through delay balancing, precomputation logic,
and power management scheme. Balanced tree topologies are often used to balance path delay,
hence reduce glitching. Precomputation logic predicts the output signal one clock cycle ahead
while using minimum circuit overhead. It generally limits a small subset of inputs to pass over to
the combinational blocks, and hence minimizes the switching activity of the system as a whole.
As shown in Figure 2.4 is a latch with clock gating.
The XOR gate compares the values of D and Q. If D and Q are the same, the output of
the XOR gate is 0. The AND gate then prevents the clock from triggering the latch. On the other
hand, if D and Q are different, then the XOR-AND logic allows for the passing of the clock
signal. This scheme eliminates any unnecessary clock switching internal to the latch. Power
management technique is one of the most effective approaches in switching activity reduction.
This power-down method puts the circuits in a sleep mode when they are idle. It can be applied
at different levels of hierarchy, from module to chip level, even at the printed circuit board.
Circuit optimization may come down to the choice of logic families as well as gate topologies.
The selection is also application oriented.
Moreover, for low power design, the rule is to size up only the transistors that are on
critical paths to meet the speed requirement and keep the rest of transistors minimum size as
much as possible. Layout optimization is also crucial. The appropriate layout styles not only
minimize the diffusion capacitances, but also the interconnect length, and hence leads to
significant power saving.
Since sequential optimizations change the state of the design, Combinational Equivalence
Checking Tools cannot be used for verification. This is not the case for Sequential Equivalence
Checking (SEC). SEC tools can comprehensively verify sequential changes to RTL like clock-
gating. System-level clock-gating is designed into the original hardware architecture and coded
as part of the RTL functionality. For example, sleep modes in a cell phone may strategically
disable the display, keyboard or radio depending on the phones current operational mode.
System-level clock-gating shuts off entire RTL blocks. Because large sections of logic are not
switching for many cycles it has the most potential to save power. On the other hand these
modifications invasive to the design function. The enable logic is part of an overall power
management strategy and sometime includes consideration for software control.
Verification of system-level power optimizations must be thought through in the system-
level test plan. Most hardware engineers understand how to write RTL in such a way that
synthesis tools can recognize and automate combinational clock-gating. Likewise hardware
architects recognize and build in system-level clock-gating opportunities. Even with these
optimizations place, there is substantial dynamic power saving opportunities remaining in the
RTL if designers understand the cost / reward tradeoffs of sequential clock-gating.
Probably the most significant problem is clock skew, which is the difference in arrival
time of the clock signal to different parts of a circuit. When a circuit is large and slow, the clock
skew is insignificant. But as circuits shrink and their speeds grow, this difference becomes very
significant and extra design time and often extra circuitry needs to be used to solve the problem.
It is becoming difficult to distribute clock as network spreads over die and may have irregular
layout. With all of the problems caused by the clock, it is very tempting to simply remove it from
the system. This is the fundamental idea behind asynchronous design. However, it is not as
simple as just removing the clock, since the operation of the circuit must still be controlled
somehow. Asynchronous circuits essentially govern themselves, and are therefore called self-
timed circuits.
The 90 nm process refers to the level of CMOS process technology that was
reached in the 20022003 timeframe, by most leading semiconductor companies, like Intel,
AMD, Infineon, Texas Instruments, IBM, and TSMC.
The 193 nm wavelength was introduced by many (but not all) companies for
lithography of critical layers mainly during the 90 nm node. Yield issues associated with this
transition (due to the use of new photoresists) were reflected in the high costs associated with
this transition.Even more significantly, the 300 mm wafer size became mainstream at the 90 nm
node. The previous wafer size was 200 mm diameter.
Advanced silicon integration technology for 3D packaging now offers post-processing of CMOS
such as wafer thinning to 50m and through-wafer vias of <10m. These technologies might be
applied to create new tracking detectors which can handle vertexing under the difficult rate
conditions. The sensor layers can be only ~50m thick with low noise performance and better
radiation hardness by using small volume pixels. Multi-layer sensors with integrated coincidence
signal processing could discriminate real tracks from various sources of background
p and n wells
Shallow trench isolation
Threshold shift and anti-punch through implants
Thin oxide and gate polysilicon
Lightly doped drains and sources
Sidewall spacer
Heavily doped drains and sources
Siliciding (Salicide and Polycide)
Bottom metal, tungsten plugs, and oxide
Higher level metals, tungsten plugs/vias, and oxide
Top level metal, vias and protective oxide
Starting Material
These are the areas where the transistors will be fabricated - NMOS in the p-well and PMOS in
the n-well. Done by implantation followed by a deep diffusion.
The natural thresholds of the NMOS is about 0V and of the PMOS is about 1.2V. An pimplant
is used to make the NMOS harder to invert and the PMOS easier resulting in threshold voltages
balanced around zero volts. Also an implant can be applied to create a higher-doped region
beneath the channels to prevent punch-through from the drain depletion region extending to
source depletion region.
A thin oxide is deposited followed by polysilicon. These layers are removed where they are not
wanted.
A lightly-doped implant is used to create a lightly-doped source and drain next to the channel of
the MOSFETs.
A layer of dielectric is deposited on the surface and removed in such a way as to leave
sidewall spacers next to the thin-oxide-polysilicon-polycide sandwich. These sidewall spacers
will prevent the part of the source and drain next to the channel from becoming heavily doped.
Note that not only does this step provide the completed sources and drains but allows for ohmic
contact into the wells and substrate.
An oxide layer is used to cover the transistors and to planarize the surface.
Tungsten plugs are built through the lower intermediate oxide layer to provide contact between
the devices, wells and substrate to the first-level metal.
Completed Fabrication
After multiple levels of metal are applied, the fabrication is completed with a thicker toplevel
metal and a protective layer to hermetically seal the circuit from the environment.Note that metal
is used for the upper level metal vias. The chip is electrically connected by removing the
protective layer over large bonding pads.
DSM technology typically has a minimum channel length between 0.35mand 0.1m
DSM technology addresses the problem of excessive depletion region widths injunction
isolation techniques by using shallow trench isolation
Lightly doped drains and sources are a key aspect of DSM technology.
EXISTING SYSTEM
Pulse-triggered Flip Flop (P-FF) has been considered a popular alternative to the
conventional masterslave-based FF in the applications of high-speed operations. Besides the
speed advantage, its circuit simplicity is also beneficial to lowering the power consumption of
the clock tree system. A P-FF consists of a pulse generator for generating strobe signals and a
latch for data storage. Since triggering pulses generated on the transition edges of the clock
signal are very narrow in pulse width, the latch acts like an edge-triggered FF. The circuit
complexity of a P-FF is simplified since only one latch, as opposed to two used in conventional
masterslave configuration, is needed. P-FFs also allow time borrowing across clock cycle
boundaries and feature a zero or even negative setup time. P-FFs are thus less sensitive to clock
jitter. Despite these advantages, pulse generation circuitry requires delicate pulse width control in
the face of process variation and the configuration of pulse clock distribution network.
Depending on the method of pulse generation. Pulse-triggered flip-flops can be classified
into two types, implicit and explicit, and this classification is due to the pulse generators they
use. In implicit-pulse triggered flip-flops (ip-FF), the pulse is generated inside the flip-flop, for
example, hybrid latch flip-flip (HLFF), semi-dynamic flip-flop(SDFF) , and implicit-pulsed data-
close-to-output flip-flop (ip-DCO). Whereas, in explicit-pulse triggered flip-flops (ep-FF), the
pulse is generated externally, for example, ex-plicit-pulsed data-close-to-output flip-flop (ep-
DCO).
One effective technique to obtain power savings inside a flip-flop can be devised by realizing the
fact that a common property among various high-speed flip-flops is the utilization of dynamic
structure. This dynamic behavior causes a lot of power to be wasted as a result of unnecessary
internal switching activity, especially in moderate or lower data activity environments. Reducing
these activities can effectively result in reducing the overall power dissipation. In this regard,
several existing approaches to reduce the internal switching activity are surveyed and classified
into conditional precharge and conditional capture techniques.
In Implicit-type P-FF designs, which are used as the reference design in later performance
comparisons, are first reviewed. A state-of-the-art P-FF design is given in Fig. It contains an
AND logic-based pulse generator. Inverters I5 and I6 are used to latch data and Inverters I7 and
I8 are used to hold the internal node X. The pulse generator takes complementary and delay
skewed clock signals to generate a transparent window equal in size to the delay by inverters I1-
I3.
Two practical problems exist in this design. First, during the rising edge, nMOS transistors
N2 and N3 are turned on. If data remains high, node X will be discharged on every rising edge of
the clock. This leads to a large switching power. The other problem is that node X controls two
larger MOS transistors (P2 and N5). The large capacitive load to node X causes speed and power
performance degradation.
SCCER DESIGN
low power P-FF design named SCCER using a conditional discharged technique . In this design,
the keeper logic (back-to-back inverters I7 and I8 in Fig. 1(a)) is replaced by a weak pull up
transistor P1 in conjunction with an inverter I2 to reduce the load capacitance of node X. The
discharge path contains nMOS transistors N2 and N1 connected in series. In order to eliminate
superfluous switching at node X, an extra nMOS transistor N3 is employed. Since N3 is
controlled by Q_fdbk, no discharge occurs if input data remains high. The worst case timing of
this design occurs when input data is 1 and node X is discharged through four transistors in
series, i.e., N1 through N4, while combating with the pull up transistor P1. A powerful pull-down
circuitry is thus needed to ensure node X can be properly discharged. This implies wider N1 and
N2 transistors and a longer delay from the delay inverter I1 to widen the discharge pulse width.
PROPOSED SYSTEM
The proposed design, as shown in Fig. 2, adopts two measures to overcome the
problems associated with existing P-FF designs. The first one is reducing the number of nMOS
transistors stacked in the discharging path. The second one is supporting a mechanism to
conditionally enhance the pull down strength when input data is 1. Refer to Fig. 2, the upper
part latch design is similar to the one employed in SCCER design [12]. As opposed to the
transistor stacking design in Fig. 1(a) and (c), transistor N2 is removed from the discharging
path. Transistor N2, in conjunction with an additional transistor N3, forms a two-input pass
transistor logic (PTL)-based AND gate [13], [14] to control the discharge of transistor N1. Since
the two inputs to the AND logic are mostly complementary (except during the transition edges of
the clock), the output node _ is kept at zero most of the time. When both input signals equal to
0 (during the falling edges of the clock), temporary floating at node _ is basically harmless. At
the rising edges of the clock, both transistors N2 and N3 are turned on and collaborate to pass a
weak logic high to node _, which then turns on transistor N1by a time span defined by the delay
inverter I1. The switching power at node _ can be reduced due to a diminished voltage swing.
Unlikethe MHLLF design [11], where the discharge control signal is drivenby a single transistor,
parallel conduction of two nMOS transistors (N2 and N3) speeds up the operations of pulse
generation.With this design measure, the number of stacked transistors along the discharging
path is reduced and the sizes of transistors N1-N5 can be reduced also.
In this design, the longest discharging path is formed when input data is
1 while the Qbar output is 1. To enhance the discharging under this
condition, transistor P3 is added. Transistor P3 is normally turned off because
node is pulled high most of the time. It steps in when node is discharged
to _ below the __. This provides additional boost to node _ (from
____ to __). The generated pulse is taller, which enhances the pull-down
strength of transistor N1. After the rising edge of the clock, the delay inverter
I1 drives node _ back to zero through transistor N3 to shut down the
discharging path. The voltage level of Node rises and turns off transistor P3
eventually. With the intervention of P3, the width of the generated
discharging
pulse is stretched out. This means to create a pulse with sufficient width for
correct data capturing, a bulky delay inverter design, which constitutes most
of the power consumption in pulse generation logic, is no longer needed. It
should be noted that this conditional pulse enhancement technique takes
effects only when the FF output _ is subject to a data change from 0 to 1. The
leads to a better power performance than those schemes using an
indiscriminate pulsewidth enhancement approach. Another benefit of this
conditional pulse enhancement scheme is the reduction in leakage power
due to shrunken transistors in the critical discharging path and in the delay
inverter.
Microwind is a tool for designing and simulating circuits at layout level. The tool features
full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics, 2D
cross section, 3D process viewer), and an analog simulator. DSCH is software for logic design.
Based on primitives, a hierarchical circuit can be built and simulated. It also includes delay and
power consumption evaluation. Silicon is for 3D display of the atomic structure of silicon, with
emphasis on the silicon lattice, the dopants, and the silicon dioxide.
Change the model parameters and see their effects on Id/Vd, Id/Vg, Id(log)/Vg, threshold
vs Length.
You can also fit the simulations with measurements we made in test chips fabricated in
0.35, 0.25 and 0.18 m.
Full length tutorial on MOS models is provided in manual, with details on all parameters.
Documentation includes several aspects of MOS modeling
EDA tools like MICROWIND & DSCH, which offers a complete IC design flow, which
starts with schematic building of digital circuits and then converting into verilog file for
compilation in CMOS layout using MICROWIND layout compiler. Every engineer needs to
verify circuit before going for Fabrication. FPGAs are best available platform for ASIC
prototyping.
A prototype is A system model to test and develop the product before its final
implementation.Field Programmable Gate Arrays (FPGA) are build around using Look-Up
Tables (LUTs) and switch matrix, and are rich in resources. Advantages like high gate density,
flexibility, moderate speed, etc. gives ideal platform to ASIC designers for prototyping their
designs before going for fabrication of ASIC.
DSCH can convert the digital circuits into Verilog file which can be further synthesized
for FPGA/CPLD devices of any vendor. The same Verilog file can be compiled for layout
conversion in MICROWIND.
The back-end design of circuits is supported by MICROWIND. User can design digital
circuits and compile here using Verilog file. MICROWIND automatically generates a error free
CMOS layout. Although this place-route is not optimized enough as we do not indulge in
complex place & route algorithms.
User can also create CMOS layout of their own using compile one line Verilog syntax or
custom build the layouts by manual drawing.
The CMOS layouts can be verified using inbuilt mix-signal simulator and analyzed further
for DRC, cross talks, delays, 2D cross section, 3D view, etc.
Here are some global design guideline for successful implementation of digital circuits for ASIC
and FPGA platforms.
2. Use a single master set or reset. Preferably, use asynchronous resets because they work
independently from the clock. When an asynchronous reset establishes the initial state, it puts the
entire circuit into a known state and helps make logic simulation and manufacturing test easier.
Keep in mind that CMOS ASIC technology prefers active-low asynchronous set or reset, but
often FPGAs use active high.
3. Avoid race conditions on de-asserting concurrent set and preset signals. You cannot predict in
simulation how the flip-flop will behave when both set and reset are de-asserted close in time.
4. Do not use delayed logic or monostable pulse generators, which relies on delays for its
operation (they are unpredictable in ASIC & FPGA). Instead use synchronous pulse generators
which have known timings and does not generates glitches.
5. Use clock-enabled flip-flops for clock division. In many FPGA implementations, ripple clock
dividers are popular. Not only can ripple clock dividers cause problems with EDAtools, the
generated clock will experience a phase delay.
6. Use clock-enabled flip-flops to avoid glitching state decoders. FPGAs are sometimes tolerant
when a state decoder goes through 11 while changing from 01 to 10. To ASICs, this causes
implementation-dependent glitches. Using clock-enabled flip-flops not only avoids glitches but
also adds no additional clock delays.
7. Have resets and transition states for Finite State Machines. Although FSMs are usually
synchronous, they still can have issues during the conversion process. Make sure there are no
dead states because during power-up the FSM can enter an unused state. Make sure reset is also
available on your FSM to make life easier during simulation and test vector generation.
8 Avoid latches; use flip-flops instead. Latches cause complications with static timing and
timing-driven layout tools. Latches are difficult to analyze, and the gate savings between a latch
and a flop are less important with submicron technology.
The n-channel MOS device requires a logic value 1 (or a supply VDD) to be on. In
contrary, the p-channel MOS device requires a logic value 0 to be on. When the MOS device is
on, the link between the source and drain is equivalent to a resistance. The order of range of this
on resistance is 100-5K. The off resistance is considered infinite at first order, as its value
is several M.
The specifications we are going to see may be different for different foundry and technology.
Design Example (3 Levels): NOR Gate
Logic Design
Circuit Design
Layout Design
Open the layout editor window in Microwind. Click File -> Select Foundry and select
X.rul.This sets your layout designs in X technology.
Click on Compile -> Compile Verilog File. An Open Window appears Select the .txt
verilog file saved before and open it.
After selecting the .txt file, a new window appears called Verilog file.Click on Size on the
right top menus. This shows up the NMOS and PMOS sizes. Set the sizes according to choice.
Click Compile and then Back to editor in the Verilog File Window. This creates a layout in
layout editor window using automatic layout generation procedure.
Add a capacitance to the output of the design. The value of the capacitance depends on your
choice.
Click on OK. The capacitance is shown on the left bottom corner with a value of 0.015fF.
Click Simulate -> Run simulation. A simulation window appears with inputs and output,
shows the tphl, tplh and tp of the circuit. The power consumption is also shown on the
right bottom portion of the window.
If you are unable to meet the specifications of the circuit change the transistor sizes.
Generate the layout again and run the simulations till you achieve your target delays.
Microwind / DSCH NOR Example: Layout Design
Design the layout manually. Open the layout editor window in Microwind. Click File ->
Select Foundry and select X.rul, Vdd and GND rails are of Metal1. The top rail is used as
Vdd and the bottom one as GND. Click on Metal 1 in the palette and then creates the
required rectangle in the layout window.
The next step is to build the NMOS transistors. Click on the transistor symbol in the
palette. Set the W, L of the transistor
Then click on Generate device. The source of the transistor is connected to the GND rail.
Create another NMOS and place it in parallel to the first NMOS device. We share the two
devices' drain diffusions. A DRC check can be run by clicking on Analysis -> Design
Rule Checker.
The next step is to place two PMOS transistors in series. Place the PMOs transistor on
layout close to the Vdd rail on the top. To construct two PMOS transistors in series,
diffusions are shifted to a side and another poly line is added as second transistor. The
diffusion is shared to save area and reduce capacitance.
The next step is to connect the inputs and the output of the two transistors. Poly inputs is
connected. Metal output is connected.
The next step is to connect the poly to metal1 and then to metal2. The first symbol in the
first row of the palette is the poly to metal1 contact.
Then we connect the metal1 to metal2 contact to the previous contact. This is the 4th
contact on the first row
The next step is to connect the output Metal1 to Metal2. Once again use the 4 th contact in
the first row.
Now we connect metal2 to the two inputs and one output and bring them to the top to go
out of the cell. Observe the two inputs (left & right) and an output (middle) above the
Vdd rail in dark blue color.
Now we label the inputs and output as In1, In2 and out. Click on Add a Pulse Symbol in
the palette (5th from the right in the 3rd row). Then click on the metal2 of one of the inputs. A
window appears. Change the name of the input signal. Insert a 01 sequences and click on Insert.
The click on Assign. Similarly assign the 2nd input a pulse.
Select the Visible Node symbol from the palette (7 th in the third row). Select it and click
on the output. The 'Add a Visible Property' window appears. Change the label name to out.
Select Visible in Simulation. Click on Assign. Now the output is also labeled.
Select Vdd Supply and GND from the palette (third row). Also click on the capacitor (3rd
in 2nd row) symbol and add it to the output. Also, extend the pwell into the Vdd Rail. The click
on Edit -> Generate -> Contacts. Select PATH and then in Metal choose Metal1 and N+
polarization.
To run
the
Simulation of your circuit, click on Simulate -> Start Simulation. Depending on the input
sequences assigned at the input the output is observed in the simulation. The power value is also
given.
SIMULATION RESULTS
Ip-dco
MLLFF
SCCER
Proposed PFF
APPLICATION
Future work
To improve the performance design of the P-Flip flop, The Pulse enhancement scheme will be
designed and also these results will be discussed with the existing pulse trigger Flip Flop
REFERENCES
[1]H. Kawaguchi and T. Sakurai, A reduced clockswing flip-flop (RCSFF) for 63% power
reduction, IEEE J. Solid-State Circuits, vol.33, no. 5, pp. 807-811, May 1998.
[2] A. G. M. Strollo, D. De Caro, E. Napoli, and N. Petra,A novel high speed sense-amplifier-
based flip-flop, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 11, pp. 1266-
1274, Nov. 2005.
[3] H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper, Flow-through latch
and edge-triggered flip-flop hybrid elements, in IEEE Tech. Dig. ISSCC, 1996, pp. 138-13.
[4]F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R. Wang, A. Mehta, R. Heald, and G. Yee,
A new family of semi-dynamic and dynamic flip flops with embedded logic for high-
performance processors, IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 712-716, May 1999.
[6] J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De, Comparative delay and
energy of single edge-triggered and dual edge triggered pulsed flip-flops for high-performance
microprocessors, in Proc. ISPLED, 2001, pp. 207-212.
[7] B. Kong, S. Kim, and Y. Jun, Conditional-capture flip-flop for statis- tical power reduction,
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