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8@WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE1 7 6 5 4 3 2 1
REVISIONS
PAGE # COMPONENT/FUNCTION PAGE # COMPONENT/FUNCTION PAGE # COMPONENT/FUNCTION REV DESCRIPTION DFT DATE CHK DATE APVD DATE
1.0 PRELIMINARY 2005
[1. INDEX] [44. IDE_SOUTH_BRIDGE] [86. STANDARD POWER CONNECTOR]
[2. BLOCK DIAGRAM] [45. USB_BACKPANEL_CONN] [87. VREG_1P2_FSB_VTT]
[3. RESET MAP] [46. USB_FP #2 HEADER] [88. VREG_2P5_MCH]
D
[4. CLOCK DISTRIBUTION] [47. USB_FP_HEADER_POWER 1 & 2] [89. VREG_SM_VTT] D
[5. GPIO, IRQ, IDSEL MAP] [48. USB_FP #1 HEADER] [90. PCI VAUX/VREG_USB/V_BATTERY]
[6. CPU-SOCKET] [49. PCI_CONN_1] [91. VREG_USB_BP_RIGHT/LEFT & PS2]
[7. CPU-SOCKET] [50. PCI_CONN_2] [92. 3.3V STANDBY]
[8. CPU TERMINATION & MISC P/U P/D] [51. PCIE_X1_SLOT1] [93. VREG_DCPL_BULK]
[9. CPU-VCCP FILTERED ANALOG SUPPLY] [52. PCI_CONN_3 [94. 5VDUAL VREG & USB_BP_MID]
[10. MCH SECTIONS PAGE 1 OF 6] [53. PCI_CONN_4] [95. VCCP VREG]
[11. MCH SECTIONS PAGE 2 OF 6] [54. ICH_PCI_TERMINATION] [96. VCCP VREG]
[12. MCH SECTIONS PAGE 3 OF 6] [55. BLANK] [97. VCCP VREG]
[13. MCH SECTIONS PAGE 4 OF 6] [56. LAN CONTROLLER, PART 1 OF 2] [98. VCCP VREG DECOUPLING]
[14. MCH SECTIONS PAGE 5 OF 6] [57. LAN EEPROM, DECOUPLING] [99. USB ANTI THEFT
C [15. MCH SECTIONS PAGE 6 OF 6] [58. BLANK] [100. USB ANTI THEFT C
[16. MCH 2P5_DAC & 1P5 FILTER] [59. LAN CONN] [101. DEBUG_XDP]
[17. MCH DECOUPLING AND COMP] [60. AUDIO CODEC] [102. VREG_1P5 CORE]
[18. MCH DCPL & VGA TERMINATION] [61. AUDIO BYPASS & DECOUPLING CAPS] [103. VR_THERMAL THROTTLE]
[19. MCH CHIPSET TERMINATION] [62. ATAPI CD HEADER & SPDIF HEADER] [104. TEST SITE CAPS]
[20. VGA CONNECTOR] [63. AUDIO BACK PORT MIC-IN/LINE-IN/OUT] [105. BLANK PAGE
[21. DDR1 DIMM-A 0/1] [64. AC HEADER FRONT PANEL PORT] [106. BLANK PAGE
[22.
[23.
DDR1 DIMM-A
DDR1 DIMM-A
TERM]
TERM]
[65.
[66.
AUDIO TERMINATION
AUDIO VREG]
P/U & VREF NETWORK]
WOODRIDGE
[24. DDR1 DIMM-A DCPL] [67. PCIE_X1_SLOT2] GRANTSDALE / DDR1 / ICH6 / ATX
[25. DDR1 DIMM-B 0/1] [68. BLANK PAGE
B
[26. DDR1 DIMM-B TERM] [69. BLANK PAGE FAB A B
[27. DDR1 DIMM-B TERM] [70. TPM (TRUSTED PLATFORM MODULE)] REV 1.00
[28. DDR1 DIMM-B DCPL] [71. SATA CONNECTORS] TAPE-OUT: WW15.5
[29. CK410E PAGE 1 OF 2] [72. FIRMWARE HUB]
[30. CK410E PAGE 2 OF 2] [73. PORT ANGELES (1 OF 2)]
[31. BLANK PAGE] [74. PORT ANGELES (2 OF 2)]
[32. PCIE 16-PORT] [75. FDD CONN] POWER SYMBOLS USED:
VCC3
[33. PCIE COUPLING] [76. PS/2 MOUSE DOUBLE-STACKED] VCC
+12V
[34. BLANK PAGE] [77. LPT CONN] NOTES:
-12V
[35. BLANK PAGE] [78. SERIAL PORT A] 1. THIS SCHEMATIC DOCUMENTS THE GENERIC PRODUCT WITH
[36. BLANK PAGE] [79. HARDWARE MANAGEMENT: HECETA] ALL POSSIBLE CONFIGURATIONS.
PLEASE REFER TO SPECIFIC PRODUCT PBA EPL S FOR
[37. ICH 1 OF 6 - CONTROL] [80. SPEAKER & DIAGNOSTIC LED] ITEMS SHOWN AS OPTIONAL IN THE SCHEMATIC.
2. RESISTORS ARE IN OHMS UNLESS OTHERWISE SPECIFIED.
[38. ICH 2 OF 6 - CONTROL] [81. STD_FRONT_PANEL_HDR] 3. VCC = +5V UNLESS OTHERWISE SPECIFIED.
A A
[39. ICH 3 OF 6 - CONTROL] [82. MTG_HOLES/LABELS] 4. * SUFFIX INDICATES ACTIVE LOW SIGNAL.
[40. ICH 4 OF 6 - CONTROL] [83. FAN CONTROL] 5. \I SUFFIX INDICATES SIGNAL EXITS HIERARCHICAL BLOCK.
6. THIS DOCUMENT ALSO EXISTS ON ELECTRONIC MEDIA.
[41. ICH 5 OF 6 - POWER] [84. VREG: VOLTAGE DISTRIBUTION]
[42. ICH 6 OF 6 - GROUND] [85. V_SM SWITCHING VREG] BOM RELEASE DATE 03/16/04 PB NUMBER
[43. ICH TERMINATION] SIGNATURE DATE 3065 BOWERS AVE
DRN BY
SCLIM int e
SANTA CLARA, CA
95051
CHK BY CHTAN 03/16/04
TITLE
ENGR SCH, PBA, WOODRIDGE
APVD
DRAWING
D915PLWDL_FABA.SCH_1.1 APVD INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:08 2005 APVD
CONFIDENTIAL D16704 1/106 1.00
8 7 6 5 4
[PAGE_TITLE=INDEX] 3 2 1
CR-2 :
8@WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE2 7 6 5 4 3 2 1
CK_410 CLOCK
LGA775
D
SUPPLY CONNVREG PROCESSOR SOCKET
D
SM BUS S0
C
LAN C
SM BUS S3 EKRON-R RJ45
DMI: DIRECT MEDIA INTERFACE 10/100
ATX FORM FACTOR
LAN CONNECT INTERFACE
8 7 6 5 4 3 2 1
CR-3 :
8@WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE3 7 6 5 4 3 2 1
MCH: MEMORY
D
CONTROLLER HUB PLTRST* RSTN* D
H_CPURST* H_CPURST*
P_PCIRST*
PWRGD_3V U PGA478 SOCKET
H_CPURST* H_PWRGD
H_PWRGD XDP
PORT ANGELES
RES: P_TRST_SLOTS*
PCIRST_OUT*
RES: PA_P_TRST*
CDC_DWN_RST* TESTPOINT
P_PCIRST*
SLP_S4/S5* PWRGD_3V
SLP_S3* RSMRST*
C PCIE GRAPHICS C
FP_RST* IDE_RST* FWH; FIRMWARE HUB
IDE_RST* PWRGD 1X16 CONN
IDE CONN1 RES:FWM_RST* RST*
P_PCIRST*
B B
PCI SLOT 1
XDP DBR* PCI SLOT 2
FWH PCI SLOT 3
HECETA
ICH TESTIN
PCI SLOT 4
RESET SWITCH
FP_RST* PWRGD_3V PLTRST*
RSMRST* P_PCIRST*
LAN_DISABLE* H_PWRGD
FRONT PANEL CONN
FP_RST* RCIN* ICH6: I/O PORT ANGELES AUDIO CODEC
SW_ON* CONTROLLER HUB CDC_DWN_RST*
SYS_RESET* CONTROL: CDC_DOWN_RST* RESET*
VREG SEQUENCING
CONTROL
SLP_S3*
8 7 6 5 4 3 2 1
CR-4 :
8@WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE4 7 6 5 4 3 2 1
LANCLK 32.7KHZ
14.318MHZ SUSCLK
CLK14
ICH 6
D 32.7KHZ
PCICLK JORDAN EEPROM CLK PROM PORT
3.3 VOLT 33MHZ
PCI SLOT 1
RTCCLK
SMBUS CLK SCLK ANGELES D
33MHZ USBCLK KBCLK
PCI SLOT 2 DMICLK MCLK MS/KB
SATACLK
AUD_BCLK AUDIO
33MHZ XTAL-IN
CODEC
12.288
AUD_BCLK MHZ
33MHZ CLK14
33M
FWH
SUSCLK
3.3 VOLT
ICH
TPM 32.7KHZ
48MHZ
SCLK HECETA
HARDWARE MANAGEMENT
C
100MHZ
100MHZ
100MHZ
XDP PORT CHAN A
XDP CLK-OUT OPTION FROM CPU
MCH DIMM 0
96MHZ XDP PORT VIDEO TEST
MCH GFX DUAL CHANNEL
GCLKIN DDR
HOST 2X200/266MHZ
100/133/167/200 MHZ CPU_CK
PCI E GRAHICS
CHAN B
A
100/133/167/200 MHZ CPU_CK CPU A
CORE DRAWING
D915PLWDL_FABA.SCH_1.4
Wed Apr 06 22:21:09 2005 [PAGE_TITLE=CLOCK DISTRIBUTION]
COPIED CLOCK DISTRIBUTION FROM TGRVP_A, 14/10/2003 INTEL DOCUMENT NUMBER PAGE REV
CLOCK DISTRIBUTION UPDATED: 12/15/2003 CLOCK DISTRIBUTION CONFIDENTIAL D16704 4 1.00
8 7 6 5 4 3 2 1
HERE
ARE NOT IDENTIFIED
CR-5 :
8@WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE5 7 6 5 4 3 2 1
DURING
PIN NAME WELL USAGE RESET S3/S5 NOTES
GPI[0] MAIN P_REQ6* P/U ON PAGE 54, 2.7K TO VCC
GPI[2] MAIN P_REQ5* P/U ON PAGE 54, 2.7K TO VCC
GPI[2] MAIN P_INTE* P/U ON PAGE 54, 8.2K TO VCC3
GPI[3] MAIN P_INTF* P/U ON PAGE 54, 8.2K TO VCC3
MULTI-PLEXED GPIO PINS ON PORT ANGELES USED FOR SPECIFIC FUNCTIONS (NOT AS GPIO)
GPI[4] MAIN P_INTG* P/U ON PAGE 54, 8.2K TO VCC3
GPI[5] MAIN P_INTH* P/U ON PAGE 54, 8.2K TO VCC3
GPI[6] MAIN 1X4_DETECT OFF
D GPI[7] MAIN FP_AUD_DETECT 10K P/D TO 3.3V PG 43
GPI[8] RESUME AC_OK (FOR ENERGY LAKE) - NOT USED 10K P/D TO 3.3V STBY PG 43 D
GPI[9] RESUME OC[4]* HIGH DRIVEN
GPI[10] RESUME OC[5]* HIGH DRIVEN
GPI[11] RESUME SMBALERT* 10K P/U TO 3.3V STBY PG 43
GPI[12] MAIN SATA HOT SWAP NOT USED 10K P/D TO GND PG 43
GPI[13] RESUME IO_PME* DRIVEN
DRIVEN
6
HERE
GPO[23] MAIN NOT ASSIGN
GPIO[24] RESUME BOARD ID 0 HIGH OFF
GPIO[25] RESUME INTERNAL VRM STRAP HIGH DEFINED
GPIO[26] MAIN SATAGP0 4.7K P/U TO 3.3V PG 39
GPIO[27] RESUME BOARD ID 1 HIGH DEFINED
GPIO[28] RESUME RPS_OFF* NOT USE HIGH DEFINED 10K P/D TO GND PG 43
SATAGP1 4.7K P/U TO 3.3V PG 39
ON PORT ANGELES.
GPIO[31] MAIN SATAGP3 4.7K P/U TO 3.3V PG 39
GPIO[32] MAIN NOT USED HIGH OFF
GPIO[33] MAIN BOARD ID 2 HIGH OFF
GPIO[34] MAIN BOARD ID 3 HIGH OFF
GPI[40] MAIN REQ[4]* LOW
GPI[41] MAIN LDRQ[1]* LOW
GPO[48] MAIN GNT[4]* HIGH OFF
GPO[49] CPU CPUPWRGD HI-Z OFF
GPI4 CORE NORM INPUT DEFINED CONFIG JUMPER
FWH
GPIO PINS
PA1.5 PA3.0
GPO0 NA SENSOR_SDA OUTPUT DEFINED DESIGN FEATURE WITH RESISTOR STRAPPING
GPO1 NA FANTACH3 INPUT DEFINED DESIGN FEATURE WITH RESISTOR STRAPPING
B B
GPO2 GPO_LAN_DISABLE FANTACH4 INPUT
GPO3 NA FANPWM1 OUTPUT
POSSIBLE
GPO4 BSKU5/1_WATT FANPWM2 OUTPUT
GPO5 NA FANPWM3 OUTPUT DEFINED
ANGELES
TOTAL OF (37)
GPIO11 5V_DDCSCL 5V_DDCSCL INPUT
GPIO12 3V_DDCSDA 3V_DDCSDA INPUT
GPI013 3V_DDCSCL 3V_DDCSCL INPUT
GPI14 CDC_DWN_ENAB* CDC_DWN_ENAB* INPUT 2X12_DETECT
IO_PME* IO_PME* OUTPUT
GRN_LED GRN_LED OUTPUT
YLW_LED YLW_LED OUTPUT
A IRQ ROUTING
CONFIRMED ++++++++++++++++++++++++++++++++++
TABLE @@@@@@@@@@@@@@ NOT CONFIRMED @@@@@@@@@@@@@
A
PCI-EXPRESS
SLOT1 SLOT2 SLOT3 SLOT4 SLOT5 X1_2 X16 X1_1 LAN USB1-F0 USB1-F1 USB1-F2 USB1-F3 USB #2 SMBUS AZALIA COPIED INFO FROM TGRVP_A, 10/14/2003
P_INTA* IRQD IRQA IRQD INFORMATION UPDATED: 12/12/2003
P_INTB* IRQC IRQA IRQA
P_INTC* IRQA IRQB IRQC
P_INTD* IRQB IRQA IRQB IRQB
P_INTE*
P_INTF*
IRQD
IRQA
IRQC
IRQB IRQC
IRQA
GPIO,
DRAWING
IRQ, IDSEL MAPS
P_INTG* IRQB IRQA IRQD D915PLWDL_FABA.SCH_1.5
P_INTH* IRQC IRQD IRQA IRQA Wed Apr 06 22:21:09 2005 [PAGE_TITLE=GPIO, IRQ, IDSEL MAP]
REQ/GNT 1 2 3 4 DOCUMENT NUMBER PAGE REV
IDSEL 16 17 18 19 24 INTEL
CONFIDENTIAL D16704 5 1.00
8 7 6 5 4 3 2 1
CR-6 :
8@WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE6 7 6 5 4 3 2 1
J3E1
LGA775
H_A<16..3>*
D 10 BI
3 L5 A<3>*
REV=2.0 D2 H_ADS*
ADS* BI 10 D
4 P6 A<4>* BNR* C2 H_BNR* BI 10 J3E1
5 M5 A<5>* HIT* D4 H_HIT* BI 10 LGA775
6 L4 H4
7 M4
A<6>*
A<7>*
RSP*
BPRI* G8
TP_RSP*
H_BPRI* IN 10 ICH_H_SMI* P2 SMI*
REV=2.0 F26 H_TESTHI_0
8 R4 A<8>* DBSY* B2 H_DBSY* 40 IN TESTHI_0 IN 8
9 T5 C1 H_DRDY* BI 10
40 IN H_A20M* K3 A20M* TESTHI_1 W3 H_TESTHI_1 IN 8
A<9>* DRDY* BI 10 H_FERR* R3 P1 H_TESTHI_11
10 U6 A<10>* HITM* E4 H_HITM* 8 IN FERR*/PBE* TESTHI_11 IN 8
11 T4 AB2 H_IERR* BI 10
40 IN H_INTR K1 LINT0 TESTHI_12 W2 H_TESTHI_12 IN 6
A<11>* IERR* OUT 8 H_NMI L1 LINT1 TESTHI_2 F25
12 U5 A<12>* INIT* P3 H_INIT* IN 40
40 IN H_IGNNE* N2 G25
13 U4 A<13>* LOCK* C3 H_LOCK* 40 IN IGNNE* TESTHI_3
14 V5 E3 H_TRDY* BI 10
40 IN H_STPCLK* M3 STPCLK* TESTHI_4 G27
A<14>* TRDY* IN 10
TESTHI_5 G26
15 V4 A<15>* BINIT* AD3 TP_BINIT*
H_VCCA A23 VCCA TESTHI_6 G24
16 W5 A<16>* DEFER* G7 H_DEFER* IN 10
9 IN H_VSSA B23 F24 H_TESTHI_2_7 IN
N4 RSVD EDRDY* F2 H_EDRDY* 9 IN VSSA TESTHI_7 8
10 BI H_REQ<4..0>* P5 AB3
OUT 10 TP_VCCPLL D23 RSVD RSVD AK6 RSVD_AK6 IN 6
TP_CPU_P5 RSVD MCERR* TP_MCERR*
H_VCCIOPLL C23 VCCIOPLL RSVD G6 RSVD_G6
0 K4 REQ<0>* 9 IN IN 6
1 J5 REQ<1>* AP<0>* U2 TP_AP<0> 95 7 OUT H_VID<5..0> 0 AM2 L2 H_SLP*
2 M6 REQ<2>* AP<1>* U3 TP_AP<1> VID<0> SLP* IN 40
3 K6 1 AL5 VID<1> RSVD AH2 TP_H_PSMI*
REQ<3>* 2 AM3 VID<2> PWRGOOD N1 H_PWRGD
4 J6 REQ<4>* BR<0>* F3 H_BR<0>* BI 8 10 3 AL6 AL2 H_PROCHOT* IN 8 40
H_ADSTB0* R6 ADSTB<0>* TESTHI_8 G3 H_TESTHI_8 VID<3> PROCHOT* IN 8 103
10 BI
H_PCREQ* G5 G4 H_TESTHI_9 BI 8 4 AK4 VID<4> THERMTRIP* M2 H_THERMTRIP_ICH*OUT 8 40
C 10 IN PCREQ* TESTHI_9 BI 8 5 AL4 VID<5> C
H_A<31..17>* TESTHI_10 H5 H_TESTHI_10 BI 8 AM5
10 BI 17 AB6 A<17>*
TP_VID6 VID<6>
18 W6 J16 COMP<0> A13 H_COMP0 IN 8
A<18>* DP<0>* TP_DP<0>
CK_H_CPU F28 BCLK<0> COMP<1> T1 H_COMP1
19 Y6 A<19>* DP<1>* H15 TP_DP<1> 30 IN CK_H_CPU* G28 BCLK<1> COMP<2> G2 H_COMP2 IN 8
20 Y4 A<20>* DP<2>* H16 TP_DP<2> 30 IN
COMP<3> R1 H_COMP3 IN 6
21 AA4 A<21>* DP<3>* J17 TP_DP<3>
H_SKTOCC* AE8 SKTOCC* COMP<4> J2 H_RSVD1 IN 6
22 AD6 A<22>* 74 OUT T2 H_RSVD2 IN 6
23 AA5 A<23>* GTLREF1 H2 COMP<5> IN 6
24 AB5 H1 CPU_GTLREF 79 IN H_TEMP_RET AL1 THERMDA
A<24>* GTLREF0 IN 8 H_TEMP_SRC AK1 THERMDC RSVD N5
25 AC5 A<25>* 79 OUT
RSVD AE6
26 AB4 A<26>* RESET* G23 H_CPURST* IN 8 10 VCC_SENSE AN3 C9
27 AF5 A<27>* 6 OUT VCC_SENSE RSVD
28 AF4 B3 0 6 OUT VSS_SENSE AN4 VSS_SENSE RSVD G10
A<28>* RS<0>* VCC_PKGSENSE AN5 VCC_MB_REGULATION RSVD D16
29 AG6 A<29>* RS<1>* F5 1 6 OUT VSS_PKGSENSE AN6 VSS_MB_REGULATION RSVD A20
30 AG4 A<30>* RS<2>* A3 2 6 OUT
31 AG5 A<31>* VTT_PKGSENSE F29 E23
TP_CPU_AH4 AH4 A<32>* OUT RSVD RSVD TP_RSVD_CPU_N5
AH5
H_RS<2..0>* IN 10 RSVD E24 TP_RSVD_CPU_AE6
TP_CPU_AH5 A<33>* RSVD F23 TP_RSVD_CPU_C9
TP_CPU_AJ5 AJ5 A<34>* V1
TP_CPU_AJ6 AJ6 A<35>* MSID<1> TP_RSVD_CPU_G10
E7 NC MSID<0> W1 TP_RSVD_CPU_D16
TP_CPU_AC4 AC4 RSVD F6 J3
TP_CPU_AE4 AE4 RSVD CAD NOTE: NC RSVD TP_RSVD_CPU_A20
1 R2F18 1 R2F28
1 1 R2F21 1 R2F4 1 R3F3 1 R2F6
C2F6 60.4 60.4
.1UF 62 100 100 62 1% 1%
VCC_SENSE R2F16 20% 5% 1% 1% 5%
21 2 25V EMPTY EMPTY
6 IN EMPTY EMPTY CH CH CH 402 402
0 5% 603 402 402 402 402 2 2
402 EMPTY VCC_VRM_SENSE OUT 8 95 2 2 2 2 H_RSVD2 OUT 6
H_RSVD1 6
R2F17 H_TESTHI_12 OUT
6 IN VCC_PKGSENSE 2 1 OUT 6
0 5% H_COMP2 OUT 6
402 CH
H_COMP3 6
VSS_SENSE R1F3 OUT
6 IN 2 1 RSVD_G6
A OUT 6 A
0 5%
402 EMPTY VSS_VRM_SENSE OUT 8 95
7 VTT_OUT_RIGHT
IN
R1F2 1
6 IN VSS_PKGSENSE 2 1 1 R2F11
0 5% 1 C2E1 R2F29
402 CH .1UF 1K
20% 62 5%
2 25V 5% EMPTY
EMPTY
CPU SOCKET
603 EMPTY 2 402
402 CPU_BOOT
2 OUT 6
RSVD_AK6 OUT 6
[PAGE_TITLE=CPU-SOCKET]
DRAWING
CORE PAGE D915PLWDL_FABA.SCH_1.6 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 00:58:48 2005
CONFIDENTIAL D16704 6 1.00
8 7 6 5 4 3 2 1
CR-7 :
8@WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE7 7 6 5 4 3 2 1
J3E1
LGA775
D
101 IN H_TCK AE1 TCK REV=2.0 VTT A29 V_FSB_VTT IN 87
H_TDI AD1 TDI VTT B25 D
101 IN
101 OUT H_TDO AF1 TDO VTT B29
101 IN H_TMS AC1 TMS VTT B30
101 IN H_TRST* AG1 TRST* VTT C29
VTT A26
101 BI H_BPM<5..0>* 0 AJ2 B27
BPM<0>* VTT
1 AJ1 BPM<1>* VTT C28
2 AD2 BPM<2>* VTT A25
3 AG2 BPM<3>* VTT A28
4 AF2 BPM<4>* VTT A27
5 AG3 BPM<5>* VTT C30
VTT A30
81 43 IN FP_RST* AC2 DBR* VTT C25
VTT C26
101 OUT XDP_CLKOUT AK3 ITPCLK<0> VTT C27
101 OUT XDP_CLKOUT* AJ3 ITPCLK<1> VTT B26
VTT D27
G29 BSEL<0> VTT D28 VCC3
H30 BSEL<1> VTT D25
G30 BSEL<2> VTT D26
H_FSBSEL0 1 R4C20 2 H_FSBSEL0_ISOL VTT B28 1
29 17 8 OUT VTT D29 TPEV_VCCFUSEPRGIN 7 R4C22
C 0 5% VTT D30 TPEV_VIDFUSEPRG IN 1K C
29 17 8 H_FSBSEL1 1 R4C25 2 402 CH H_FSBSEL1_ISOL VTT_PWRGD AM6 VTT_PWRGD
7
5%
OUT IN 95
0 5% 1 R4C21 2 EMPTY
H_FSBSEL2 402 CH H_FSBSEL2_ISOL VTT_OUT AA1 VTT_OUT_RIGHT 402
29 17 8 OUT
0 5% VTT_OUT J1 VTT_OUT_LEFT OUT 6 7 8 95 101
2
OUT 6 8 95
402 CH VTT_SEL F27 VTT_SEL
4 of 4 OUT
IC
VCCP=AG22,K29,AM26,AL8,AE12,AE11
VCCP=W23,W24,W25,T25,Y28,AL18,AC25,W30,Y30,AN14,AD28,Y26,AC29,M29,U24,J23,AC27,AM18,AM19,AB8
VCCP=AC26,J8,J28,T30,AM9,AF15,AC8,AE14,N23,W29,U29,AC24,AC23,Y23,AN26,AN25,AN11,AN18,Y27,Y25
J3E1 VCCP=AD24,AE23,AE22,AN19,V8,K8,AE21,AM30,AE19,AC30,AE15,M30,K27,M24,AN21,T8,AC28,N25,AE18,W26
LGA775
VCCP=AD25,M8,N30,AD26,AJ26,AM29,M25,M26,L8,U25,Y8,AJ12,AD27,U23,M23,AG29,N27,AM22,U28,K28
H_D<47..32>* VCCP=U8,AK18,AD8,K24,AH28,AH21,AK12,AH22,T29,AM14,AM25,AE9,Y29,AK25,AK19,AG15,J22,T24,AG21,AM21
10 BI H_D<15..0>*
0 B4
REV=2.0 G16 32
BI 10
VCCP=J25,U30,AL21,AG25,AJ18,J19,AH30,J15,AG12,AJ22,J20,AH18,AH26,W27,AL25,AN8,AH14,U27,T23,R8
D<0>* D<32>* VCCP=AK22,AN29,AG11,AK26,J10,AJ15,AG26,AN9,AH15,AF18,AL15,J26,J18,J21,AG27,AK15,AF11,AD23,AM15,AF8
1 C5 D<1>* D<33>* E15 33 VCCP=AK21,AG30,AJ21,AM11,AL11,AJ11,K30,AL14,AN30,AH25,AL12,AJ9,AK11,AG14,N29,AL30,AJ25,AH9,J29,J11
2 A4 D<2>* D<34>* E16 34 VCCP=K25,P8,K23,AL19,AM8,T26,N28,AH12,AL22,AN15,AJ8,U26,AJ19,T27,AK8,AN12,AG9,N26,AF9,AF22
3 C6 D<3>* D<35>* G18 35 VCCP=AH11,AJ14,AH19,AH29,AH27,AG28,AL26,AM12,J24,J13,T28,W28,J12,J27,AG19,AL9,AD30,AF21,Y24,AK14
B 4 A5 D<4>* D<36>* G17 36 VCCP=J9,M27,AF14,J30,AG18,AA8,AG8,AL29,AD29,W8,AH8,N24,AN22,J14,K26,AF19,N8,AF12,M28,AK9 B
5 B6 D<5>* D<37>* F17 37 GND=C10,D12,AM7,C24,K2,C22,AN1,B14,K7,AE16,B11,AL10,AK23,H12,AF7,AK7
6 B7 D<6>* D<38>* F18 38 GND=H7,E14,L28,Y5,E11,AL16,AL24,AK13,AL3,D21,AL20,D18,AN2,AK16,AK20,AM27,AM1,AL13,AL17,C19
7 A7 D<7>* D<39>* E18 39 GND=E28,AH7,AK30,D24,AL23,A12,L25,J7,AE28,AE29,K5,J4,AE30,AN20,AF10,AE24,AM24,AN23,H9,H8
8 A10 D<8>* D<40>* E19 40 GND=H13,AC6,AC7,AH6,C16,AM16,AE25,AE27,AJ28,AJ7,F19,AH13,AD7,AH16,AK17,E17,AH17,AH20,AE5,AH23
9 A11 D<9>* D<41>* F20 41 GND=AE7,AM13,AH24,AJ30,AJ10,AF3,AK5,AJ16,AF6,AK29,AJ17,F22,AH3,AK10,AM10,F16,AJ23,F13,AG7,F10
10 B10 D<10>* D<42>* E21 42 GND=L26,AD4,H11,L24,L23,AM23,A15,AH10,B24,L3,H27,A21,AE2,AJ29,A24,AK27,AK28,B20,AM20
11 C11 D<11>* D<43>* F21 43 GND=H26,B17,H25,H24,AA3,AA7,H23,AA6,H10,H22,H21,H20,H19,H18,AB7,H17,AJ24,AM17,AC3,H14
12 D8 D<12>* D<44>* G21 44 GND=P28,V6,AK2,P27,P26,AM28,AJ13,W4,P25,AJ20,W7,P23,C7,Y2,L30,L29,D15,AL27,Y7,L27
13 B12 D<13>* D<45>* E22 45 GND=AA29,N6,N7,AA28,AN13,AA27,AA26,P4,AA25,AA24,P7,E26,V30,R2,V29,V28,R5,V27,R7,E20
14 C12 D<14>* D<46>* D22 46 GND=AN10,V25,T3,V24,V23,T6,AL7,E25,U1,R29,R28,R27,R26,R25,U7,R24,R23,P30,V3,P29
15 D11 D<15>* D<47>* G22 47 GND=AF16,AE10,AF13,H6,A18,A2,E2,D9,C4,A6,D6,D5,A9,D3,B1,B5,B8,AJ4,AE26,AH1
10 BI H_DBI<0>* A8 DBI<0>* DBI<2>* D19 H_DBI<2>* BI 10 GND=E29,V7,C13,AK24,AB30,L6,L7,AB29,M1,AB28,AN17,AB27,AB26,AN16,M7,AB25,AB24,AB23,N3,AA30
10 BI H_STBN<0>* C8 DSTBN<0>* DSTBN<2>* G20 H_STBN<2>* BI 10 GND=F4,AG10,AE13,AF30,H28,F7,AF29,AF28,G1,AF27,AF26,AF25,AN28,AN27,AF24,AF23,AG24,AF17,AN24,H3
10 BI H_STBP<0> B9 DSTBP<0> DSTBP<2> G19 H_STBP<2> BI 10 GND=AN7,P24,AE20,AE17,E27,T7,R30,AJ27,AB1,AM4,V26,AA23,AL28,AF20,AG23,AG20,E8,AG17,AG16,AG13
10 BI H_D<31..16>* H_D<63..48>* BI 10 NC=F6,Y3,AE3,E7,B13,D14,E6,D1,E5,
16 G9 D<16>* D<48>* D20 48
17 F8 D<17>* D<49>* D17 49
18 F9 D<18>* D<50>* A14 50
19 E9 D<19>* D<51>* C15 51
20 D7 D<20>* D<52>* C14 52 V_FSB_VTT VTT_OUT_RIGHT
21 E10 D<21>* D<53>* B15 53 87 IN BOM NOTE: 7 IN
22 D10 D<22>* D<54>* C18 54 ALWAYS STUFF ON
23 F11 D<23>* D<55>* B16 55 1 1 PRODUCT BOARDS
A 24 F12 D<24>* D<56>* A17 56 R4C26 R4C27 A
25 D13 D<25>* D<57>* B18 57 0 05%
26 E13 D<26>* D<58>* C21 58 5% 1 1 1 1 1 1
27 G13 D<27>* D<59>* B21 59 CH CH
28 F14 D<28>* D<60>* B19 60 402 402 R1F50 R1F49 R1F48 R1F53 R1F52 R1F51
29 G14 D<29>* D<61>* A19 61 2 2 680 680 680 680 680 680
30 F15 D<30>* D<62>* A22 62 TPEV_VIDFUSEPRG
OUT 7 5% 5% 5% 5% 5% 5%
31 G15 D<31>* D<63>* B22 63 TPEV_VCCFUSEPRG CH CH CH CH CH CH
H_DBI<1>* H_DBI<3>* OUT 7 402 402 402 402 402 402
10 BI G11 DBI<1>* DBI<3>* C20 BI 10 2 2 2 2 2 2
10 BI H_STBN<1>* G12 DSTBN<1>* DSTBN<3>* A16 H_STBN<3>* BI 10
10 BI H_STBP<1> E12 DSTBP<1> DSTBP<3> C17 H_STBP<3> BI 10
3
0
5
1
6 IN H_VID<5..0>
2 of 4
DRAWING
IC D915PLWDL_FABA.SCH_1.7
Thu Apr 07 00:59:35 2005 INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE [PAGE_TITLE=CPU-SOCKET] D16704 7 1.00
CONFIDENTIAL
8 7 6 5 4 3 2 1
CR-8 :
8@WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE8 7 6 5 4 3 2 1
1 1 1 1 1 1
1
D R2F2
R3F1 R2F31 R2F19 R2F25 R7H2 R7H3 V_FSB_VTT D
87 IN
62 62 499 62 62 62 62
5% 5% 1% 5% 5% 5% 5%
CH CH CH EMPTY CH CH CH
402 402 402 402 402 402 402
2 2 2 2 2 2
1 1 1
2
1 1 1
TESTHI PIN NAME MAPPING R4C15 R4C16 R4C14
C 1K 1K 1K C
TESTHI[0] BYPASSEN 5%
EMPTY
5%
EMPTY 5% DESIGN
EMPTY STRAPPING OPTION FOR DEBUG
NOTE:
TESTHI[1] ODT 402 402 402
TESTHI PULLUPS 2 2 2
TESTHI[5:2] MCLK[3:0]
87 IN V_FSB_VTT TESTHI[7:6] MCLKIO[1:0]
7 VTT_OUT_LEFT TESTHI[10:8] BR#[3:1]
IN
TESTHI[11] DPSLP#
1 1 1 1 1 1 1 TESTHI[12] DT_SVR#
R2F3 R2F1 R3F2 R3F4 R2F7 R4C24 R4C23
62 62 62 62 62 62 62
5% 5% 5% 5% 5% 5% 5%
CH CH CH CH CH CH CH
402 402 402 402 402 402 402
2 2 2 2 2 2 2
H_TESTHI_0 OUT 8 6
H_TESTHI_2_7 6
VCC3
H_TESTHI_1 OUT
OUT 6
H_TESTHI_8 OUT 6 R4C29
B H_TESTHI_9 OUT 6 1 2 BOM NOTE: B
H_TESTHI_10 OUT 6 249 1%
H_TESTHI_11 OUT 6 402 EMPTY 1 STUFF THIS FOR
RSVD_DET_RR
R4C11 CPU NWD-T
110
RSVD_DET 3 Q4C4 1%
EMPTY EMPTY
1 402
6 IN VCC_VRM_SENSE 6 IN
2 2
1 J1F1 H_TESTHI_0
NEVER JUMPER 1X2HDR DESIGN NOTE: OUT 8 6
THIS HEADER!!! EMPTY THE PINS WILL BE USED AS TEST/PROBE POINTS ONLY. 1
102276-001
2 R4C13 2
CAD NOTE: 61.9 C4C3
PLACE HEADERS AS CLOSE TO CPU PINS AS POSSIBLE 1% .1UF
20%
6 IN VSS_VRM_SENSE EMPTY 16V
402 1 EMPTY
2 402
PRECISION FSB COMPENSATION RESISTORS 7 VTT_OUT_RIGHT GTLREF VOLTAGE SHOULD BE 0.67*VTT = 0.8V
IN
(FOR THIS DESIGN)
1
R4D1 100 OHMS OVER 210 OHMS RESISTORS
A 1 2 H_COMP0 OUT R2F23 A
6
60.4 1% 100
402 CH
1%
CH EVAL FEATURE
402
R2F5 2 R2F20
1 2 H_COMP1 OUT 6
60.4 1% CPU_GTLREF_DIVIDER 1 2 CPU_GTLREF OUT 6
402 CH 30 5%
1 402 CH
R2F24 1 1
C2F2 C2F1
210 1.0UF 220PF
1% 20% 10%
10V 50V
CH 2 Y5V 2 EMPTY
PLACE RESISTORS OUTSIDE SOCKET CAVITY 402 603 402
2 [PAGE_TITLE=CPU TERMINATION & MISC]
IF NO ROOM FOR VARIABLE RESISTOR DON'T PLACE.
DRAWING
D915PLWDL_FABA.SCH_1.8 INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE Thu Apr 07 00:58:58 2005
CONFIDENTIAL D16704 8 1.00
8 7 6 5 4 3 2 1
CR-9 :
8@WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE9 7 6 5 4 3 2 1
87 IN V_FSB_VTT
1
693286-014 1 10UH
FB4C1 L4C2
FB EMPTY
2 721891-026
2
"125 MA"
"0805"
H_VCCIOPLL OUT 6
1 C4C5
C 1 C
R4C12 1.0UF
0
5% 20%
CH 2 10V
2 402
EMPTY
87 IN V_FSB_VTT 603
"Y5V"
1 10UH
693286-014 1 L4C1
FB4C2 EMPTY
FB
721891-026
2 2 "125 MA"
"0805"
H_VCCA OUT 6
C4C4
C4C1 2 R4C7 1 TP_H_VCCA_STEP
1.0UF
1 33UF 1 0 5%
20% 20% 402 EMPTY
B 25V 10V B
2 ALUM 2 EMPTY DESIGN NOTE:
603 ALWAYS EMPTY. DEBUG HOOK.
"201307-107" RDL "Y5V"
H_VSSA OUT 6
CAD NOTE:
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE NO SMALLER THAN 12MIL
A A
8 7 6 5 4 3 2 1
CR-10 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE10
8 7 6 5 4 3 2 1
U6D1
GDG_DDR1_1210
J4F1 J6D1 6 BI H_A<31..3>* 3 H29 HA3*
REV=1.0
HD0* J33 0 H_D<63..0>* BI 7
1
D 4 1
1
K29 HA4* HD1* H33
NC 5 J29 HA5* HD2* J34 2 D
NC 6 G30 HA6* HD3* G35 3
7 G32 HA7* HD4* H35 4
EMPTY EMPTY 8 K30 HA8* HD5* G34 5
9 L29 HA9* HD6* F34 6
HS6D1 10 M30 HA10* HD7* G33 7
11 L31 HA11* HD8* D34 8
J4D1 J6F1 12 L28 HA12* HD9* C33 9
1
GDG_WAVEHS
1
NC_1 NC_2
K27 HA14* HD11* B34
4 3 15 K33 HA15* HD12* C34 12
NC NC NC_4 NC_3
16 M28 HA16* HD13* B33 13
HEATSINK 17 R29 HA17* HD14* C32 14
EMPTY EMPTY C45196-001 18 L26 HA18* HD15* B32 15
19 N26 HA19* HD16* E28 16
20 M26 HA20* HD17* C30 17
WAVE SOLDER HEAT-SINK = WSHS 21 N31 HA21* HD18* D29 18
22 P26 HA22* HD19* H28 19
23 N29 HA23* HD20* G29 20
24 P28 HA24* HD21* J27 21
25 R28 HA25* HD22* F28 22
26 N33 HA26* HD23* F27 23
C 27 T27 HA27* HD24* E27 24 C
28 T31 HA28* HD25* E25 25
29 U28 HA29* HD26* G25 26
NOTE : 30 T26 HA30* HD27* J25 27
31 T29 HA31* HD28* K25 28
USE D10665-001 FOR GMCH HD29* L25 29
HD30* L23 30
HD31* K23 31
H_REQ<4..0>* HD32* J22 32
6 BI 0 F33 HREQ0* HD33* J24 33
1 E32 HREQ1* HD34* K22 34
2 H31 HREQ2* HD35* J21 35
3 G31 HREQ3* HD36* M21 36
4 F31 HREQ4* HD37* H23 37
6 BI H_ADSTB0* J31 HADSTB0* HD38* M19 38
6 BI H_ADSTB1* N27 HADSTB1* HD39* K21 39
6 OUT H_PCREQ* E31 HPCREQ* HD40* H20 40
HD41* H19 41
HD42* M18 42
HD43* K18 43
7 BI H_STBP<0> E33 HDSTBP0 HD44* K17 44
7 BI H_STBN<0>* E35 HDSTBN0* HD45* G18 45
7 BI H_DBI<0>* E34 HDINV0* HD46* H18 46
B
7 BI H_STBP<1> H26 HDSTBP1 HD47* F17 47 B
7 BI H_STBN<1>* F26 HDSTBN1* HD48* A25 48
7 BI H_DBI<1>* J26 HDINV1* HD49* C27 49
7 BI H_STBP<2> J19 HDSTBP2 HD50* C31 50
7 BI H_STBN<2>* F19 HDSTBN2* HD51* B30 51
7 BI H_DBI<2>* K19 HDINV2* HD52* B31 52
7 BI H_STBP<3> B29 HDSTBP3 HD53* A31 53
7 BI H_STBN<3>* C29 HDSTBN3* HD54* B27 54
7 BI H_DBI<3>* B26 HDINV3* HD55* A29 55
HD56* C28 56
HD57* A28 57
HD58* C25 58
HD59* C26 59
6 BI H_ADS* M31 HADS* HD60* D27 60
6 BI H_BNR* M35 HBNR* HD61* A27 61
6 OUT H_BPRI* E30 HBPRI* HD62* E24 62
8 6 OUT H_BR<0>* R33 HBREQ0* HD63* B25 63
101 6 8 OUT H_CPURST* G24 HCPURST*
6 BI H_DBSY* L35 HDBSY*
6 OUT H_DEFER* J35 HDEFER*
6 OUT H_DRDY* M32 HDRDY* HXSWING A23 HXSWING IN 17
6 IN H_EDRDY* P33 HEDRDY* HXSCOMP D24 HXSCOMP IN 17
6 OUT H_HIT* L34 HHIT* HXRCOMP B23 HXRCOMP IN 17
6 OUT H_HITM* N35 HHITM* HVREF A24 MCH_GTLREF IN 17
A
6 IN H_LOCK* L33 HLOCK* A
0 K34 HRS0*
H_RS<2..0>* 1 P34 HRS1* HCLKINP M23 CK_H_MCH IN 30
6 BI 2 J32 HRS2* HCLKINN M22 CK_H_MCH* IN 30
6 OUT H_TRDY* N34 HTRDY*
1 of 7
IC
8 7 6 5 4 3 2 1
FIN=NB
BOM=CORE
CR-11 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE11
8 7 6 5 4 3 2 1
U6D1
D GDG_DDR1_1210
REV=1.0 D
32 IN EXP_A_RXP_0 E11 EXPARXP0 EXPATXP0 C10 EXP_A_TXP_0 OUT 33
32 IN EXP_A_RXN_0 F11 EXPARXN0 EXPATXN0 C9 EXP_A_TXN_0 OUT 33
32 IN EXP_A_RXP_1 J11 EXPARXP1 EXPATXP1 A9 EXP_A_TXP_1 OUT 33
32 IN EXP_A_RXN_1 H11 EXPARXN1 EXPATXN1 A8 EXP_A_TXN_1 OUT 33
32 IN EXP_A_RXP_2 F9 EXPARXP2 EXPATXP2 C8 EXP_A_TXP_2 OUT 33
32 IN
EXP_A_RXN_2 E9 EXPARXN2 EXPATXN2 C7 EXP_A_TXN_2 OUT 33
32 IN EXP_A_RXP_3 F7 EXPARXP3 EXPATXP3 A7 EXP_A_TXP_3 OUT 33
32 IN EXP_A_RXN_3 E7 EXPARXN3 EXPATXN3 A6 EXP_A_TXN_3 OUT 33
32 IN EXP_A_RXP_4 B3 EXPARXP4 EXPATXP4 C6 EXP_A_TXP_4 OUT 33
32 IN EXP_A_RXN_4 B4 EXPARXN4 EXPATXN4 C5 EXP_A_TXN_4 OUT 33
32 IN EXP_A_RXP_5 D5 EXPARXP5 EXPATXP5 C2 EXP_A_TXP_5 OUT 33
32 IN EXP_A_RXN_5 E5 EXPARXN5 EXPATXN5 D2 EXP_A_TXN_5 OUT 33
32 IN EXP_A_RXP_6 G6 EXPARXP6 EXPATXP6 E3 EXP_A_TXP_6 OUT 33
32 IN EXP_A_RXN_6 G5 EXPARXN6 EXPATXN6 F3 EXP_A_TXN_6 OUT 33
32 IN EXP_A_RXP_7 H8 EXPARXP7 EXPATXP7 F1 EXP_A_TXP_7 OUT 33
32 IN EXP_A_RXN_7 H7 EXPARXN7 EXPATXN7 G1 EXP_A_TXN_7 OUT 33
32 IN EXP_A_RXP_8 J6 EXPARXP8 EXPATXP8 G3 EXP_A_TXP_8 OUT 33
32 IN EXP_A_RXN_8 J5 EXPARXN8 EXPATXN8 H3 EXP_A_TXN_8 OUT 33
32 IN EXP_A_RXP_9 K8 EXPARXP9 EXPATXP9 H1 EXP_A_TXP_9 OUT 33
32 IN EXP_A_RXN_9 K7 EXPARXN9 EXPATXN9 J1 EXP_A_TXN_9 OUT 33
32 IN EXP_A_RXP_10 L6 EXPARXP10 EXPATXP10 J3 EXP_A_TXP_10 OUT 33
C 32 IN EXP_A_RXN_10 L5 EXPARXN10 EXPATXN10 K3 EXP_A_TXN_10 OUT 33 C
32 IN EXP_A_RXP_11 P10 EXPARXP11 EXPATXP11 K1 EXP_A_TXP_11 OUT 33
32 IN EXP_A_RXN_11 R10 EXPARXN11 EXPATXN11 L1 EXP_A_TXN_11 OUT 33
32 IN EXP_A_RXP_12 M8 EXPARXP12 EXPATXP12 L3 EXP_A_TXP_12 OUT 33
32 IN EXP_A_RXN_12 M7 EXPARXN12 EXPATXN12 M3 EXP_A_TXN_12 OUT 33
32 IN EXP_A_RXP_13 N6 EXPARXP13 EXPATXP13 M1 EXP_A_TXP_13 OUT 33
32 IN EXP_A_RXN_13 N5 EXPARXN13 EXPATXN13 N1 EXP_A_TXN_13 OUT 33
32 IN
EXP_A_RXP_14 P7 EXPARXP14 EXPATXP14 N3 EXP_A_TXP_14 OUT 33
EXP_A_RXN_14 EXP_A_TXN_14
SIGNAL NAMING CONVENTION 32
32
32
IN
IN
IN
EXP_A_RXP_15
EXP_A_RXN_15
P8
R6
R5
EXPARXN14
EXPARXP15
EXPARXN15
EXPATXN14
EXPATXP15
EXPATXN15
P3
P1
R1
EXP_A_TXP_15
EXP_A_TXN_15
OUT
OUT
OUT
33
33
33
EXP: PCI EXPRESS
DMI: DIRECT MEDIA INTERFACE 38 BI DMI_ITP_MRP_0 U5 DMIRXP0 DMITXP0 R3 DMI_MTP_IRP_0 BI 38
38 BI DMI_ITN_MRN_0 U6 DMIRXN0 DMITXN0 T3 DMI_MTN_IRN_0 BI 38
ITP: ICH TRANSMIT POSITIVE 38 BI DMI_ITP_MRP_1 T9 DMIRXP1 DMITXP1 T1 DMI_MTP_IRP_1 BI 38
38 BI DMI_ITN_MRN_1 T8 DMIRXN1 DMITXN1 U1 DMI_MTN_IRN_1 BI 38
ITN: ICH TRANSMIT NEGATIVE 38 BI DMI_ITP_MRP_2 V7 DMIRXP2 DMITXP2 U3 DMI_MTP_IRP_2 BI 38
38 BI DMI_ITN_MRN_2 V8 DMIRXN2 DMITXN2 V3 DMI_MTN_IRN_2 BI 38
38 BI DMI_ITP_MRP_3 V10 DMIRXP3 DMITXP3 V5 DMI_MTP_IRP_3 BI 38
IRP: ICH RECEIVE POSITIVE 38 BI DMI_ITN_MRN_3 U10 DMIRXN3 DMITXN3 W5 DMI_MTN_IRN_3 BI 38
B B
IRN: ICH RECEIVE NEGATIVE
30 IN CK_PE_100M_MCH A11 GCLKINP EXPACOMPO Y10 GRCOMP IN 17
MTP: MCH TRANSMIT POSITIVE 30 IN CK_PE_100M_MCH* B11 GCLKINN EXPACOMPI W10
A
SDVO CTRL DATA A
DRAWING
CORE PAGE D915PLWDL_FABA.SCH_1.11 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:10 2005
CONFIDENTIAL D16704 11 1.00
8 7 6 5 4 3 2 1
CR-12 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE12
8 7 6 5 4 3 2 1
U6D1
GDG_DDR1_1210
V_1P5_CORE REV=1.0
102 AC11 VCCNCTF VSSNCTF AC25 U6D1
IN AB11 AB25
VCCNCTF VSSNCTF GDG_DDR1_1210
Y20 VCCNCTF VSSNCTF AA25
Y19 AA11 REV=1.0 V_SM
Y17
VCCNCTF
VCCNCTF
VSSNCTF
VSSNCTF Y25 102 IN V_1P5_CORE AD10 VCC VCCSM AR33 IN 85
D AD9 VCC VCCSM AR31
Y16 VCCNCTF VSSNCTF Y18 AD8
W20 Y11 VCC VCCSM AR26 D
VCCNCTF VSSNCTF AD7 VCC VCCSM AR22
W16 VCCNCTF VSSNCTF W25 AD6 VCC VCCSM AR18
U20 VCCNCTF VSSNCTF W11 AD5 AR14
U16 VCCNCTF VSSNCTF V25 VCC VCCSM
AD4 VCC VCCSM AR10
T20 VCCNCTF VSSNCTF V20 AD3 VCC VCCSM AP28
T19 VCCNCTF VSSNCTF V16
AD2 AP24
T17 V11 VCC VCCSM
VCCNCTF VSSNCTF AD1 VCC VCCSM AP20
T16 VCCNCTF VSSNCTF U25
U11 AC10 VCC VCCSM AP16
VSSNCTF AC9 VCC VCCSM AP12
VSSNCTF T25
T18 AC8 VCC VCCSM AN35
VSSNCTF AC7 VCC VCCSM AM32
VSSNCTF T11
R25 AC6 VCC VCCSM AM28
VSSNCTF AC5 VCC VCCSM AM26
VSSNCTF R11
AC4 VCC VCCSM AM25
VSSNCTF P25 AC3 AM23
102 IN V_1P5_CORE AA13 VCCNCTF VSSNCTF P11
AC2
VCC
VCC
VCCSM
VCCSM AM22
AA14 VCCNCTF VSSNCTF N25
AA16 AC1 VCC VCCSM AM20
VCCNCTF VSSNCTF AD25 AB10
AA18 N11 VCC VCCSM AM19
VCCNCTF VSSNCTF AB9 VCC VCCSM AM17
AA20 VCCNCTF VSSNCTF M11
AA21 AB8 VCC VCCSM AM16
VCCNCTF AB7 VCC VCCSM AM14
AA22 VCCNCTF
AA23 AB6 VCC VCCSM AM13
C VCCNCTF AB5 VCC VCCSM AM11 C
AA24 VCCNCTF
AB13 AA15 AB4 VCC VCCSM AM10
VCCNCTF VSSNCTF AB3 VCC VCCSM AK35
AB14 VCCNCTF VSSNCTF AA17
AB15 AA19 AB2 VCC
VCCNCTF VSSNCTF AB1 VCC
AB16 VCCNCTF VSSNCTF N17
W18 VCC
AB17 VCCNCTF VSSNCTF N19
V19
AB18 P16 VCC
VCCNCTF VSSNCTF V17 VCC
AB19 VCCNCTF VSSNCTF P18
U18 H22
V_FSB_VTT
AB20 VCCNCTF VSSNCTF P20 VCC VTT IN 87
AB21 R17 VTT G22
VCCNCTF VSSNCTF VTT G21
AB22 VCCNCTF VSSNCTF R19 F22
AB23 VCCNCTF VSSNCTF R21 VTT
AB24 T22 VTT F21
VCCNCTF VSSNCTF VTT F20
N13 VCCNCTF VSSNCTF U15
N14 U21 17 IN V_1P5_PCIEXPRESS Y9 VCC3G VTT E22
VCCNCTF VSSNCTF Y8 VCC3G VTT E21
N15 VCCNCTF VSSNCTF U23 Y7 E20
N16 VCCNCTF VSSNCTF V22 VCC3G VTT
Y6 VCC3G VTT E19
N18 VCCNCTF VSSNCTF W15 Y5
N20 W21 VCC3G VTT D22
VCCNCTF VSSNCTF Y4 VCC3G VTT D21
N21 VCCNCTF VSSNCTF W23
P13 Y22 Y3 VCC3G VTT D20
VCCNCTF VSSNCTF Y2 VCC3G VTT D19
P14 VCCNCTF Y1
B VCC3G VTT C22 B
P15 VCCNCTF
P17 W9 VCC3G VTT C21
VCCNCTF W8 VCC3G VTT C20
P19 VCCNCTF
P21 W7 VCC3G VTT C19
VCCNCTF W6 VCC3G VTT B22
P22 VCCNCTF RSVRD AC12 W4 B21
R13
R14
VCCNCTF RSVRD AC13
AC14
DESIGN NOTE: W3
VCC3G
VCC3G
VTT
VTT B20
VCCNCTF RSVRD RSRVD PINS DO NOT NEED TO W2 VCC3G VTT B19
R15 VCCNCTF RSVRD AC15
W1 VCC3G VTT A22
R16 VCCNCTF RSVRD AC16 BE TESTPOINTED IN THIS INSTANCE
R18 AC17 VTT A21
VCCNCTF RSVRD VTT A20
R20 VCCNCTF RSVRD AC18
A19
R22 VCCNCTF RSVRD AC19 VTT
R23 VCCNCTF RSVRD AC20 16 IN VCCA_HPLL A17 VCCAHPLL
T13 VCCNCTF RSVRD AC21 16 IN VCCA_MPLL B17 VCCAMPLL
T14 VCCNCTF RSVRD AC22 16 IN VCCA_DPLLA A12 VCCADPLLA
T15 VCCNCTF 16 IN VCCA_DPLLB B13 VCCADPLLB
T21 VCCNCTF 16 IN VCCA_GPLL A14 VCCA3GPLL
T23 VCCNCTF
T24 VCCNCTF NC N12
U13 VCCNCTF NC N22
U14 VCCNCTF NC N23 88 IN V_2P5_MCH A13 VCCHV
E13 VCCACRTDAC
U22 VCCNCTF NC N24
U24 VCCNCTF NC P12 16 IN V_2P5_DAC_FILTERED D13
F13
VCCACRTDAC
V13 P23 VSSACRTDAC
A VCCNCTF NC A
V14 VCCNCTF NC P24 6 of 7
V15 VCCNCTF NC R12
V21 VCCNCTF NC R24 IC
V23 VCCNCTF NC T12
V24 VCCNCTF NC U12
W13 VCCNCTF NC V12
W14 VCCNCTF NC W12
W22 VCCNCTF NC Y12
W24 VCCNCTF NC AA12
Y13
Y14
VCCNCTF NC AB12
AC23
[PAGE_TITLE=MCH SECTIONS PAGE 3 OF 6]
VCCNCTF NC
Y15 VCCNCTF NC AC24
Y21 VCCNCTF
Y23 VCCNCTF
Y24 VCCNCTF
7 of 7 DRAWING
D915PLWDL_FABA.SCH_1.12 INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE IC
Wed Apr 06 22:21:10 2005
CONFIDENTIAL D16704 12 1.00
8 7 6 5 4 3 2 1
CR-13 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE13
8 7 6 5 4 3 2 1
U6D1
GDG_DDR1_1210
22 21 13 BI M_MAA_A<13..0> 0 AN22 SAMA0 SADQS0 AG1 0 M_DQS_A<7..0> BI 13 21 23
1 AP22 SAMA1 DDRA RSVRD AG2
M_DQM_A<7..0>
2 AN21 SAMA2 SADM0 AF2 0 M_DATA_A<63..0> BI 13 21 22
3 AP21 SAMA3 REV=1.0 SADQ0 AE3 0 BI 13 21 22
4 AM21 SAMA4 SADQ1 AF3 1
5 AP19 SAMA5 SADQ2 AH3 2
6 AR20 SAMA6 SADQ3 AJ2 3
D 7 AN16 SAMA7 SADQ4 AE2 4
8 AN18 SAMA8 SADQ5 AE1 5 D
9 AM15 SAMA9 SADQ6 AG3 6
10 AN23 SAMA10 SADQ7 AH2 7
11 AP15 SAMA11 M_DQS_A<7..0>
12 AP13 SAMA12 SADQS1 AL3 1 BI 13 21 23
AN31 AL2
RSVRD RSVRD
AL1 1 M_DQM_A<7..0> BI 13 21 22
M_WE_A* AP31
SADM1
AK2 8 M_DATA_A<63..0> BI 13 21 22
23 21 OUT SAWE* SADQ8
23 21 OUT M_CAS_A* AL34 SACAS* SADQ9 AK3 9
23 21 OUT M_RAS_A* AN29 SARAS* SADQ10 AN4 10
M_SBS_A<1..0> SADQ11 AP4 11
23 21 BI 0 AN28 SABA0 SADQ12 AJ1 12
1 AP26 SABA1 SADQ13 AJ3 13
AR23 RSVRD SADQ14 AP2 14
M_SCS_A<3..0>* SADQ15 AP3 15
23 21 BI 0 AM34 SACS0* M_DQS_A<7..0>
1 AL35 SACS1* SADQS2 AP7 2 BI 13 21 23
2 AK34 SACS2* RSVRD AR7
M_DQM_A<7..0>
3 AL33 SACS3* SADM2 AN7 2 M_DATA_A<63..0> BI 13 21 22
8 7 6 5 4 3 2 1
CR-14 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE14
8 7 6 5 4 3 2 1
U6D1
GDG_DDR1_1210
26 25 14 BI M_MAA_B<13..0> 0 AM18 SBMA0 SBDQS0 AK5 0 M_DQS_B<7..0> BI 14 25 27
1 AP18 SBMA1 DDRB RSVRD AL4
M_DQM_B<7..0>
2 AN17 SBMA2
REV=1.0 SBDM0 AJ5 0 M_DATA_B<63..0> BI 14 25 26
3 AR16 SBMA3 SBDQ0 AH4 0 BI 14 25 26
4 AR15 SBMA4 SBDQ1 AJ6 1
5 AN15 SBMA5 SBDQ2 AL6 2
6 AP17 SBMA6
FIN=NB SBDQ3
AN6 3
7 AL15 SBMA7 SBDQ4 AG9 4
D 8 AP14 SBMA8 SBDQ5
BOM=CORE
AH7 5
9 AN13 SBMA9 SBDQ6 AL5 6 D
10 AN20 SBMA10 SBDQ7 AM5 7
11 AR12 SBMA11 M_DQS_B<7..0> BI 14 25 27
12 AM12 SBMA12 SBDQS1 AK10 1
AL24 AH10
RSVRD RSVRD
1 M_DQM_B<7..0> 14 25 26
27 25 M_WE_B* AR27 SBWE*
SBDM1
SBDQ8
AH9
AJ8 8 M_DATA_B<63..0> BI
BI 14 25 26
27 25
OUT
M_CAS_B* AN27 SBCAS* SBDQ9 AL8 9
27 25
OUT
M_RAS_B* AP27 SBRAS* SBDQ10 AF11 10
27 25
OUT
BI M_SBS_B<1..0> 0 AM27
SBDQ11 AE11
AJ7
11
12
SBBA0 SBDQ12
1 AR19 SBBA1 SBDQ13 AL7 13
AP23 SBBA2 SBDQ14 AG10 14
M_SCS_B<3..0>* SBDQ15 AG11 15
27 25 BI 0 AP34 SBCS0* M_DQS_B<7..0>
1 AN34 SBCS1* SBDQS2 AK13 2 BI 14 25 27
2 AN33 SBCS2* RSVRD AL14
M_DQM_B<7..0>
3 AM33 SBCS3* SBDM2 AH13 2 M_DATA_B<63..0> BI 14 25 26
8 7 6 5 4 3 2 1
CR-15 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE15
8 7 6 5 4 3 2 1
D
D
U6D1
GDG_DDR1_1210
REV=1.0
17 IN NOA_0 H16 NOA0 CRTHSYNC E12 HSYNC OUT 18
17 IN NOA_1 E15 NOA1 CRTVSYNC D12 VSYNC OUT 18
17 IN NOA_2 D17 NOA2
TP_NOA_3 M16 NOA3 CRTRED F14 VGA_RED OUT 18 20
TP_NOA_4 F15 NOA4 CRTGREEN D14 VGA_GREEN OUT 18 20
17 IN NOA_5 C15 NOA5 CRTBLUE H14 VGA_BLUE OUT 18 20
TP_NOA_6 A16 NOA6
TP_NOA_7 B15 NOA7 CRTREDB G14
17 IN NOA_8 C14 NOA8 CRTGREENB E14
TP_NOA_9 K15 NOA9 CRTBLUEB J14
DRAWING
D915PLWDL_FABA.SCH_1.15 INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE Thu Apr 07 00:59:40 2005
CONFIDENTIAL D16704 15 1.00
8 7 6 5 4 3 2 1
CR-16 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE16
8 7 6 5 4 3 2 1
1 R5D16 2
1 5%
603 CH
202285-623
R5D17 2
102 IN
V_1P5_CORE 2 R5D1 1 I_VCCA_GPLL_R1 VCCA_GPLL OUT 12
D
1A 0 1 5% D
CH 805 603 CH
202285-623 2 2
C5D3 C5D15
4.7UF .1UF
20% 10%
16V 16V
1 Y5V 1 X7R
1206 603
BOM NOTE:
OPTION: USE 721891-009 FOR 10UH INDUCTOR
DEFAULT: USE 108506-002 FOR 0 OHM RESISTOR
M5D3
1 2 VCCA_HPLL OUT 12
MULTI
CH 805 C5D8
108506-002 1 470UF 1
20% C5D21
10V .1UF
10%
2 ALUM 2 16V
X7R
RDL 603
C C
M6D2
1 2 VCCA_DPLLA OUT 12
MULTI
IND SM
721891-009 1 C6D10 1
220UF C6D20
20% .1UF
6.3V 10% 1
EMPTY 16V
2 RDL 2 EMPTY R6D3
603 0
1A
EMPTY
805
2
M5D2
ANALOG FILTERS 1
MULTI
2 VCCA_DPLLB OUT 12
CH 805
B 108506-002 1 C6D11 1 B
220UF C5D19
20% .1UF
6.3V 10%
EMPTY 16V
2 RDL 2 EMPTY
603
BOM NOTE:
OPTION: USE 721891-009 FOR 10UH INDUCTOR
DEFAULT: USE 108506-002 FOR 0 OHM RESISTOR
M5D1
1 2 VCCA_MPLL OUT 12
MULTI
CH 805
108506-002 1 C5D7 1
470UF C5D20
20% .1UF
10V 10%
EMPTY 16V
2 RDL 2 X7R
603
A A
DEBUG ONLY
R5D8 M6D1
V_2P5_MCH 1 2 V_2P5_DAC_FILTERED_PN1 1 2 V_2P5_DAC_FILTERED
88 IN MULTI OUT 12 18
0 5%
402 CH CH 805
1 C6D5 1 C6D16 1 C5D18
BOM NOTE: 100UF .01UF
REPLACE 0 OHM WITH 1 OHM 1% ONLY IF 20% .1UF
DEFAULT: 108506-004 FOR 0 OHM RESISTOR 25V 20% 10%
25V 50V
NECESSARY FOR SIGNAL QUALITY OPTION: USE 693286-026 FOR FERRITE BEAD 2 ELEC
RDL 2 Y5V 2 X7R
603 603
[PAGE_TITLE=MCH 2P5_DAC & 1P5 FILTER]
DRAWING
INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE D915PLWDL_FABA.SCH_1.16
Thu Apr 07 00:59:17 2005 CONFIDENTIAL D16704 16 1.00
8 7 6 5 4 3 2 1
CR-17 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE17
8 7 6 5 4 3 2 1
1
C C
1
402 C5D17
10.0UF
C5D23
10.0UF
C5D13
10.0UF 97 96 IN 1R5D182 VCCP_DRIVER
R5D21
100
20% 20% 20% 619 1% 3 Q5D2 1%
HXSWING 6.3V 6.3V 6.3V 402 EMPTY CH
OUT 10 EMPTY EMPTY EMPTY EMPTY
1 R5D22 C5D14
1206 1206 1206 +12V 1 2 402
2
100 .01UF 2 MCH_GTLREF OUT 10
1
1% 10% 1
"X5R" 1 C5D16 1 C5D12 1
CH 50V R5D20
402 2 X7R R5D15 .1UF 220PF
2 10K
210
1%
20%
25V
10%
50V
603 CAPS FOR FSB GENERIC 5%
CH Y5V 2 EMPTY 2
EMPTY 402 603 603
402
2 2 "X7R"
CAD NOTE:
NOA H L DESCRIPTION RSVD_DET CAP FOR GTLREF INPUTS @GMCH
6 IN USE 12MIL TRACE, ISOLATE W/ 15MIL SPACE
CAP SHOULD BE PLACED NEAR MCH PIN
0 SEE BSEL TABLE BSEL0
B 1 SEE BSEL TABLE BSEL1 B
2 SEE BSEL TABLE BSEL2 R4C8
8 7 IN
H_FSBSEL0 1 2 NOA_0 OUT 15
3 NORM ALL-Z ALL-Z TEST MODE 10K 5%
402 CH
4 NORM XOR XOR CHAIN R4C10
5 DDR1 DDR2 MEMORY TYPE 8 7 IN
H_FSBSEL1 1 2 NOA_1 OUT 15
10K 5%
6 NORM REVERSE PCI-EXPRESS LANE REVERSAL 402 CH
7 DIS ENABLE FSB HARDWARE STRAPS R4C9
8 7 H_FSBSEL2 1 2 NOA_2 15
8 NEW LTSSM OLD LTSSM LTSSM MODE (1.0 OLD, 1.0A NEW) IN
10K 5%
OUT
402 CH
9 NORM BYPASS ICH PCI-EXPRESS RST BYPASS
R5D5
3,4,5,6,7,8,9 ALL HAVE INTERNAL PULL-UP 1 2 NOA_5 OUT 15
1K 5%
402
BSEL TABLE EMPTY
R5D4
A 2 1 0 PSB FREQUENCY 1 2 NOA_8 OUT 15 A
1K 5%
0 0 0 267 MHZ (1067) 402 EMPTY
8 7 6 5 4 3 2 1
CR-18 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE18
8 7 6 5 4 3 2 1
VCC VCC
3 RP2J1 2 RP2J1
2.7K 2.7K
5% 5%
V_FSB_VTT .063W .063W
87 IN EMPTY EMPTY
D 6 SM 7 SM
D
C4C6 74 15 IN MCH_DDC_DATA 74 15 IN MCH_DDC_CLK
.1UF 1 C4C7 1 1
C5D9
20%
25V
.1UF
20%
.1UF
20%
5 RP2J1 8 RP2J1
Y5V 2.7K 2.7K
603 2 25V
Y5V
603
2 25V
Y5V
603
2 BOM NOTE: 5%
.063W
5%
.063W
STUFF FOR GD-G EMPTY EMPTY
EMPTY FOR GD-P 4 SM 1 SM
FSB GENERIC DECOUPLING
15 IN VGA_RED
15 IN VGA_GREEN
V_SM 15 VGA_BLUE
85 IN IN
2 C5F2 2 C5F1 2 C5F4 2 C5F3 2 C4F1 2 C4F2 NOTE:
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF LEAVE EMPTY, 1 R5C29
C 20% 20% 20% 20% 20% 20% INTERFERES WITH 0 CR6C1 C
1 16V
Y5V 1 16V
Y5V 1 16V
Y5V 1 16V
Y5V 1 16V
Y5V 1 16V
EMPTY WS HEAT SINK BOM NOTE: 5% 1 R6C26 3 GP CR6C2 CR6C3
805 805 805 805 805 805 STUFF FOR GD-P 2 CH 0
SOT23S
EMPTY 3 GP GP
SOT23S 3
EMPTY FOR GD-G 402 5% 1 R6C28 EMPTY SOT23S
2 CH 0 EMPTY
402 5% 1 2
2 CH
402 1 2 1 2
16 IN
V_2P5_DAC_FILTERED
MCH MEMORY DECOUPLING
1 C6C15
.1UF
20%
2 25V
Y5V
603
DACREFSET OUT 15
B B
VCC3
1 R6D5
R5D24 BOM NOTE: 15 IN
VSYNC 1 2 VSYNC_BUFFER R6C24
VSYNC_3V
0
5% 39 5% 1
VSYNC_PN1_BUF 2 OUT 20
CH
1 R6D2 402 EMPTY U6C1
39 5%
STUFF WITH 255 OHM, 1% FOR GD-G 10K 74LVC2G125
402 EMPTY
402 5% SLEW RATE 8
2 STUFF WITH 0 OHM, 5% FOR GD-P 2 CH CONTROL
VCC
8 7 6 5 4 3 2 1
CR-19 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE19
8 7 6 5 4 3 2 1
D
R6F3 D
2 1 MCH_VREF_B OUT 14
0 5%
402 CH
1 C6E13
.1UF CAD NOTES:
20% PLACE 0.1UF CAP CLOSE TO MCH
2 25V
Y5V
603
R6F5
85 IN V_SM 1 2
1K 1%
402 CH MCH_VREF_A OUT 13
R6F4 1 C6E14
1 2 .1UF CAD NOTES:
C 20% C
1K 1% 25V PLACE 0.1UF CAP CLOSE TO MCH
402 CH 2 Y5V
603
CAD NOTES:
PLACE CLOSE TO MCH
8 7 6 5 4 3 2 1
CR-20 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE20
8 7 6 5 4 3 2 1
M3A4
BOM NOTE: VCC 1 2
DEFAULT: STUFF WITH FERRITE BEAD (693286-006) FOR 5 POINT FILTER MULTI 1
OPTION: STUFF 0 OHM 0603 FOR 3 POINT FILTER RT3A1 EMPTY 805 C3A2
.1UF
VGA_RED M3A1 20%
15 IN
VGA_GREEN
1 2 1 2 VDO_THERM_PN1
2 25V
EMPTY
15 IN M3A2 MULTI EMPTY 603
15 VGA_BLUE 1 2 EMPTY 603
IN M3A3 MULTI
D
1 2 EMPTY 603
EMPTY 603
MULTI
693286-006
J3A1 D
16
693286-006 1 FB3A1 2 VGA_RED_FB1 VDO_RED_L 1
EMPTY VDO_THERM_9 9
693286-006 1 FB4A1 2 VGA_GREEN_FB1 "47 OHM" VDO_GREEN_L 2
EMPTY 10
1 FB3A2 2 VGA_BLUE_FB1
"47 OHM" VDO_BLUE_L 3
TP_VDOCONN_11_CORE 11
"47 OHM" TP_VDOCONN_4_CORE 4
EMPTY 12
5
18 IN HSYNC_3V 13
VSYNC_3V 6
18 IN 14
7
1 C4A13 1 C4A12 1 C4A6 15
10PF 10PF 8 EMPTY
10PF
5% 5% 5%
2 50V 2 50V 2 50V 17
EMPTY EMPTY
EMPTY
402
BOM NOTE: 402 402 C4A3
C STUFF WITH 3.3PF (A36094-006) FOR 3 POINT FILTER 1 C
STUFF WITH 10PF (A36094-001) FOR 5 POINT FILTER 100PF
5% C4A1
1 100PF
C3A14 C4A4 2 50V
1 22PF
1 C4A9
22PF
1
22PF EMPTY 5%
10% 402 2 50V
10% 10% EMPTY
2 50V 2 50V
EMPTY 2 50V 402
EMPTY BOM NOTE: 402 EMPTY
402 STUFF WITH 3.3PF (A36094-006) FOR 3 POINT FILTER 402
STUFF WITH 22PF (A36095-006) FOR 5 POINT FILTER
1 1
C4A8 1 C4A2
C3A1
10PF 10PF 10PF
5% 5% 5%
50V 2 50V 50V
2 EMPTY EMPTY 2
402 BOM NOTE: 402 "COG" EMPTY
402
A36094-001 EMPTY FOR 3 POINT FILTER
"COG" STUFF WITH 10PF (A36094-001) FOR 5 POINT FILTER "COG"
B B
1 1 1
R4A8 R4A6 R4A1
150 150 150
1% 1% 1%
EMPTY EMPTY EMPTY
402 402 402
2 2 2
CAD NOTE:
PLACE RESISTORS CLOSE TO FILTERS (CAPS/FERITE-BEADS)
VCC
CR4A4
2
3
DDCSDA_5V_R
1
1 1
BAT54C R4A3 R4A5
SOT23C 2.2K 2.2K
EMPTY 5% 5%
1 R4A26 2 EMPTY EMPTY
402 402
0 1A 2 2 R4A4
603 74 DDCSDA_5V 2 1 VDO_MONID1_R
EMPTY BI
A 100 5% A
402 EMPTY
2 R4A2 1
74 BI DDCSCL_5V VDO_MONID2_R
100 5% I36
402 EMPTY 1 3 4 6 CR4A2 1 C4A7 1 C4A5
TVS6_2V 100PF 100PF
5% 5%
6.2V 2 50V 2 50V
2 5 EMPTY EMPTY EMPTY
402 402
8 7 6 5 4 3 2 1
A
C
D
B
CR-21
23
22
22
22
23
22
22
22
:
21
21
21
21
21
21
21
21
8
8
USE A87935-008
USE A87935-007
13
13
13
13
13
13
13
13
CORE PAGE
USE A87935-007
USE A87935-006
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
85
BOM NOTE:
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
FOR
FOR
BOM NOTE:
FOR
FOR
V_SM
BLACK CONN WITH WHITE TABS
M_WE_A*
BLACK CONN WITH BLACK TABS
M_WE_A*
M_CAS_A*
M_RAS_A*
M_CAS_A*
M_RAS_A*
M_DQS_A<7..0>
M_DQM_A<7..0>
DIMM2P_184_1Gb
M_SBS_A<1..0>
M_SCS_A<3..0>*
M_DQS_A<7..0>
M_DQM_A<7..0>
M_MAA_A<13..0>
M_SBS_A<1..0>
J6G2
M_SCS_A<3..0>*
M_MAA_A<13..0>
M_SCKE_A<3..0>
M_SCKE_A<3..0>
63 WE* DQ63 179 DIMM2P_184_1Gb
M_DATA_A<63..0>
63
7
@WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE21
M_DATA_A<63..0>
65 175
62 63 WE* DQ63 179 63
CAS* DQ61 61 154 178
174 RAS* DQ62 62
DQ60 60 65 175
13 CAS* DQ61
CK_M_166M_P_DDR0_A
CK_M_166M_N_DDR0_A
167 A13 DQ59 88 61
CK_M_166M_P_DDR3_A
CK_M_166M_N_DDR3_A
87
59 DQ60 174 60
DQ58 58 167 88
12 115 84 13 A13 DQ59 59
A12 DQ57 57 87
11 118 83 DQ58 58
A11 DQ56 56 115 84
10 141 171 12 A12 DQ57 57
A10 DQ55 55 118 83
9 27 170 11 A11 DQ56 56
A9 DQ54 54 141 171
8 122 166 10 A10 DQ55 55
A8 DQ53 49 27 170
7 29 165 9 A9 DQ54 54
A7 DQ52 48 122 166
6 125 80 8 A8 DQ53 49
A6 DQ51 51 29 165
5 32 79 7 A7 DQ52 48
A5 DQ50 50 125 80
4 37 73 6 A6 DQ51 51
A4 DQ49 53 32 79
3 130 72 5 A5 DQ50 50
A3 DQ48 52 37 73
2 41 162 4 A4 DQ49 53
A2 DQ47 43 130 72
1 43 161 3 A3 DQ48 52
A1 DQ46 42 41 162
0 48 155 2 A2 DQ47 43
A0 DQ45 40 43 161
TP_CHA_0_DM8 153 1 A1 DQ46 42
DQ44 44 48 155
140 69 0 A0 DQ45 40
DM8/DQS17 DQ43 47 TP_CHA_1_DM8 153
DQ44
6
7 177 DM7 DQ42 68 44
6
5
142
TP_CHA_0_CB1 CB6 DQ22 121 28
5
135 117
23 TP_CHA_1_CB7144 CB7 DQ23 123 19
TP_CHA_0_CB2 CB5 DQ21 17 TP_CHA_1_CB6142 121
134 114 CB6 DQ22 23
TP_CHA_0_CB3 CB4 DQ20 20 TP_CHA_1_CB5135 117
51 31 CB5 DQ21 17
TP_CHA_0_CB4 CB3 DQ19 18 TP_CHA_1_CB4134 114
49 28 CB4 DQ20 20
TP_CHA_0_CB5 CB2 DQ18 22 TP_CHA_1_CB3 51 31
45 24 CB3 DQ19 18
TP_CHA_0_CB6 CB1 DQ17 16 TP_CHA_1_CB2 49 28
44 23 CB2 DQ18 22
TP_CHA_0_CB7 CB0 DQ16 21 TP_CHA_1_CB1 45 24
110 CB1 DQ17 16
DQ15 15 TP_CHA_1_CB0 44 23
157 109 CB0 DQ16 21
0 CSO* DQ14 14 110
158 106 DQ15 15
1 CS1* DQ13 9 157 109
105 2 CSO* DQ14 14
DQ12 13 158 106
137 20 3 CS1* DQ13 9
CK0P DQ11 11 105
138 19 DQ12 13
CK0N DQ10 10 137 20
13 CK0P DQ11 11
DQ9 8 138 19
21 12 CK0N DQ10 10
0 CKE0 DQ8 12 13
99 DQ9 8
DQ7 2 21 12
111 98 2 CKE0 DQ8 12
1 CKE1 DQ6 6 99
95 DQ7 2
DQ5 5 111 98
TP_BA2_113_DIMM0_A 113 94 3 CKE1 DQ6 6
BA2 DQ4 4 95
8 DQ5 5
DQ3 3 TP_BA2_113_DIMM1_A
113 94
BA2 DQ4
4
1 52 BA1 DQ2 6 4
4
59 4
7 DQ3 8 3
0 BA0 DQ1 1 52 6
2 1 BA1 DQ2 7
DQ0 0 59 4
183 0 BA0 DQ1 1
SA2 2
182 DQ0 0
SA1 183
181 SA2
SA0 182 SA1
90 3 181 SA0
TP_WP_90_DIMM0_A WP/NC VSS
TP_RESET_10_DIMM0_A 10 RESET* VSS 11 90 3
103 18 TP_WP_90_DIMM1_A WP/NC VSS
TP_FETEN_103_DIMM0_A FETEN/NC VSS 11
91 26 TP_RESET_10_DIMM1_A 10 RESET* VSS
SDA VSS 103 18
92 34 TP_FETEN_103_DIMM1_A FETEN/NC VSS
SCL VSS 91 26
42 SDA VSS
VSS
1
1 50 92 SCL VSS 34
VREF VSS 42
DRAWING
VSS
1
VSS
Y5V
20%
7 81 82 VDDID VSS 66
VDD VSS
.1UF
74
25V
VSS
C6G2
38 VDD VSS 89 7 81
20%
VDD VSS
.1UF
C6G3
46 VDD VSS 93 38 89
VDD VSS
3
22 176
NEAR DIMM PIN
VDDQ 30
62 VDDQ
VDDQ 54
77 9 VDDQ
VDDQ NC 62
96 101 VDDQ
VDDQ NC
TP_VDDID_82_DIMM0_A
CONN
DDR CHANNEL A DIMM 1
CONFIDENTIAL
SMB_CLK_MAIN
SMB_DATA_MAIN
EMPTY
V_SM
V_SM
V_SM
V_SM
TP_DIMM0_SCS2*
SMB_CLK_MAIN
DIMM_VREF_A
[PAGE_TITLE=DDR1
SMB_DATA_MAIN
TP_DIMM1_SCS3*
TP_DIMM1_SCS2*
TP_DIMM0_SCS3*
DIMM_VREF_A
IN
IN
IN
IN
IN
CK_M_166M_P_DDR1_A
CK_M_166M_N_DDR1_A
I2C
I2C
IN
IN
IN
IN
IN
CK_M_166M_P_DDR2_A
CK_M_166M_N_DDR2_A
19
D16704
29
29
85
85
CK_M_166M_P_DDR5_A
CK_M_166M_P_DDR4_A
CK_M_166M_N_DDR5_A
CK_M_166M_N_DDR4_A
19
29
29
85
85
74
74
DIMM-A
IN
1
DOCUMENT NUMBER
74
74
IN
IN
IN
1
IN
IN
IN
IN
13
= 001
13
13
13
0/1]
21
= 000
13
13
13
13
PAGE
1.00
REV
A
C
D
B
CR-22 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE22
8 7 6 5 4 3 2 1
21 13 BI
M_DATA_A<63..0>
21 13 BI
M_MAA_A<13..0>
[PAGE_TITLE=DDR1 DIMM-A 0/1 TERM]
DRAWING DOCUMENT NUMBER PAGE REV
CORE PAGE D915PLWDL_FABA.SCH_1.22 INTEL
Wed Apr 06 22:21:12 2005 CONFIDENTIAL D16704 22 1.00
8 7 6 5 4 3 2 1
CR-23 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE23
8 7 6 5 4 3 2 1
CHANNEL
DESIGN NOTE;
A V_SM_VTT
89 IN
D
KEEP 603 RESISTORS
DO NOT CHANGE TO 402 D
RP2G6
7 1 8
56 5% .063W
SM IC
RP2G4 R3G1 2
6 3 6 1 1
56 5%.063W 47 5%
SM IC 603 CH
1 R2G2 2
RP3G4
5 0 4 5
56 5% M_SBS_A<1..0> 47 5% .063W
603 CH 13 IN SM IC
RP3G2
C
4 3 6
C
56 5%.063W
SM IC
RP4G3
3 3 6 13 IN M_SCS_A<3..0>*
56 5% .063W RP2G1
SM IC 3 1 8
56 5% .063W
RP5G5 SM IC
2 4 5
56 5% .063W RP2G1
SM IC 2 3 6
56 5% .063W
RP5G1 SM IC
1 2 7
56 5%
.063W RP2G1
SM IC 1 2 7
56 5% .063W
RP6G2 SM IC
0 3 6
56 5% .063W RP2G1
B M_DQS_A<7..0> SM IC 0 4 5 B
21 13 IN 56 5% .063W
SM IC
M_SCKE_A<3..0> RP5G3
13 IN 3 3 6
56 5%.063W
SM IC
RP3G4 RP5G3
13 IN M_RAS_A* 3 6 2 2 7
47 5% .063W 56 5%.063W
SM IC SM IC
RP5G3
RP3G4 1 4 5
13 IN M_CAS_A* 1 8 56 5%.063W
47 5% .063W SM IC
SM IC
RP5G3
RP3G4 0 1 8
M_WE_A* 2 7 56 5%.063W
A 13 IN
47 5% .063W SM IC A
SM IC
8 7 6 5 4 3 2 1
CR-24 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE24
8 7 6 5 4 3 2 1
DDR CHANNEL A
D
D
89 IN V_SM_VTT
DECOUPLING CAPACITORS FOR DDR TERMINATION RESISTORS
1
2
C5G5 1
.1UF
20%
25V
Y5V
2
C6G7 1
.1UF
20%
25V
Y5V
2
C6G8 1
.1UF
20%
25V 2
C3G7 1 C3G10 1
.1UF
20%
25V 2
.1UF
20%
25V 2
C5G9 1
.1UF
20%
25V
2
C4G9 1 C3G9
.1UF
20%
25V
.1UF
2
20%
25V
1 C5G10 1
2
.1UF
20%
25V 2
C3G11 1
.1UF
20%
25V
2
C3G8 1
.1UF
20%
25V 2 20%
C2G9 1
.1UF
25V
2
C2G8
.1UF
20%
25V
CHANNEL
DIMM TO MCH
A
603 603 Y5V Y5V Y5V Y5V Y5V Y5V Y5V Y5V Y5V Y5V
Y5V
603 603 603 603 603 603 603 603 603 603 603 BIT SWAPPING
DIMM MCH DIMM MCH
DQ0 DQ0 DQ32 DQ36
DQ1 DQ1 DQ33 DQ32
C 1 C
1 1 C4G8 1 C4G10 1 C3G6 1 C5G11 1 C3G12 1 C5G7 1 C2G6 1 C4G12 1 DQ2 DQ2 DQ34 DQ38
C2G7 1 C5G8 .1UF .1UF
C5G6
.1UF .1UF .1UF C6G6 1 C4G11
.1UF DQ3 DQ3 DQ35 DQ35
.1UF .1UF 20% 2 .1UF .1UF .1UF .1UF 2 20% 2 20% 2 20% .1UF 20% DQ4
2 20% 2 2 20% 2 20% 2 20% 2 20% DQ4 DQ36 DQ37
2 20% 2 20% 25V 20% 25V 25V 25V 2 DQ5 DQ5 DQ37 DQ33
25V 25V 25V 25V 25V 25V 25V Y5V Y5V Y5V 25V 25V
Y5V Y5V Y5V Y5V Y5V Y5V Y5V Y5V 603 Y5V Y5V DQ6 DQ6 DQ38 DQ39
603 603 603 603 603 603 603 603
603 603 603 603 DQ7 DQ7 DQ39 DQ34
8 7 6 5 4 3 2 1
A
C
D
27
27
26
26
26
26
26
26
25
25
25
25
25
25
25
25
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
85
85
CR-25
:
BI
BI
BI
BI
BI
BI
BI
BI
8
8
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
CORE PAGE
V_SM
V_SM
M_WE_B*
M_WE_B*
M_CAS_B*
M_RAS_B*
M_CAS_B*
M_RAS_B*
J6H1
M_DQS_B<7..0>
DIMM2P_184_1Gb
M_DQM_B<7..0>
M_MAA_B<13..0>
63 WE* DQ63 179 58
J6H2
DIMM2P_184_1Gb
M_SBS_B<1..0>
154 178
M_DQS_B<7..0>
RAS* DQ62
M_DQM_B<7..0>
62 63 179
M_SCS_B<3..0>*
WE* DQ63
M_MAA_B<13..0>
M_SCKE_B<3..0>
M_SBS_B<1..0>
65 CAS* DQ61 175 56 154 178
58
M_DATA_B<63..0>
M_DATA_B<63..0>
M_SCS_B<3..0>*
RAS* DQ62
M_SCKE_B<3..0>
DQ60 174 60 65 175
62
13 167 88 CAS* DQ61 56
A13 DQ59 59 174
87 DQ60 60
DQ58 63 88
12 115 84 13 167 A13 DQ59 59
A12 DQ57
CK_M_166M_P_DDR3_B
CK_M_166M_N_DDR3_B
11 118 83
57 DQ58 87 63
A11 DQ56
CK_M_166M_P_DDR0_B
CK_M_166M_N_DDR0_B
10 61 12 115 A12 DQ57 84
7
@WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE25
9 27 170
50 11 118 A11 DQ56 83 61
A9 DQ54 54 171
8 122 166 10 141 A10 DQ55 50
A8 DQ53 49 170
7 29 165 9 27 A9 DQ54 54
A7 DQ52 53 166
6 125 80 8 122 A8 DQ53 49
A6 DQ51 51 165
5 32 79 7 29 A7 DQ52 53
A5 DQ50 55 80
4 37 73 6 125 A6 DQ51 51
A4 DQ49 48 79
3 130 72 5 32 A5 DQ50 55
A3 DQ48 52 73
2 41 162 4 37 A4 DQ49 48
A2 DQ47 43 72
1 43 161 3 130 A3 DQ48 52
A1 DQ46 47 162
0 48 155 2 41 A2 DQ47 43
A0 DQ45 40 161
153 1 43 A1 DQ46 47
TP_CHB_0_DM8 DQ44 45 155
140 69 0 48 A0 DQ45 40
DM8/DQS17 DQ43 42 TP_CHB_1_DM8 153
177 68 DQ44 45
7 DM7 DQ42 46 140 69
169 64 DM8/DQS17 DQ43 42
6 DM6 DQ41 41 177 68
159 61 7 DM7 DQ42 46
5 DM5 DQ40 44 169 64
149 151 6 DM6 DQ41 41
4 DM4 DQ39 34 159 61
129 150 5 DM5 DQ40 44
3 DM3 DQ38 39 149 151
119 147 4 DM4 DQ39 34
2 DM2 DQ37 32 129 150
107 146 3 DM3 DQ38 39
1 DM1 DQ36 37 119 147
2 DM2 DQ37
6
0 97 DM0 DQ35 60 32
6
5
DQ15 110 16
5
157 109
15 TP_CHB_1_CB0 44 CB0 DQ16 23 21
0 CSO* DQ14 14 110
158 106 DQ15 15
1 CS1* DQ13 9 157 109
105 2 CSO* DQ14 14
DQ12 8 158 106
137 20 3 CS1* DQ13 9
CK0P DQ11 11 105
138 19 DQ12 8
CK0N DQ10 10 137 20
13 CK0P DQ11 11
DQ9 13 138 19
12 CK0N DQ10 10
0 21 CKE0 DQ8 12 13
99 DQ9 13
DQ7 2 21 12
98 2 CKE0 DQ8 12
1 111 CKE1 DQ6 7 99
95 DQ7 2
DQ5 0 111 98
TP_BA2_113_DIMM0_B
113 94 3 CKE1 DQ6 7
BA2 DQ4 4 95
8 DQ5 0
DQ3 3 TP_BA2_113_DIMM1_B 113 94
6 BA2 DQ4 4
1 52 BA1 DQ2 6 8
4 DQ3 3
0 59 BA0 DQ1 1 52 6
2 1 BA1 DQ2 6
DQ0 5 59 4
183 0 BA0 DQ1 1
SA2 2
182 DQ0 5
SA1 183
181 SA2
SA0 182 SA1
181 SA0
4
4
TP_RESET_10_DIMM0_B 10 RESET* VSS 11 90 3
TP_FETEN_193_DIMM0_B 103 18 TP_WP_90_DIMM1_B WP/NC VSS
FETEN/NC VSS TP_RESET_10_DIMM1_B 10 11
91 26 RESET* VSS
SDA VSS TP_FETEN_103_DIMM1_B 103 18
92 34 FETEN/NC VSS
SCL VSS 91 26
42 SDA VSS
VSS
1
1 50 92 SCL VSS 34
VREF VSS 42
VSS
1
VDDSPD VSS
25V
Y5V
74
20%
VSS
.1UF
7 81 82 VDDID VSS 66
VDD VSS
603
25V
C6H2
VSS 74
.1UF
38 VDD VSS 89 7 81
VDD VSS
C6H9
46 93
EMPTY
VDD VSS 38 89
70 100 VDD VSS
VDD VSS 46 93
85 116 VDD VSS
VDD VSS 70 100
108 124 VDD VSS
VDD VSS 85 116
120 132 VDD VSS
VDD VSS
20% NEAR
108 124
DRAWING
VSS 152
DDR CHANNEL B DIMM 0
NEAR DIMM
30 VDDQ
DIMM
77 9 54 VDDQ
Wed Apr 06 22:21:13
VDDQ NC 62
96 101 VDDQ
VDDQ NC 77 9
PIN
VDDQ NC 96 101
112 173 VDDQ NC
VDDQ NC
D915PLWDL_FABA.SCH_1.25
2
INTEL
V_SM
V_SM
V_SM
V_SM
CONFIDENTIAL
TP_DIMM0_SCS_B2*
TP_DIMM0_SCS_B3*
SMB_CLK_MAIN
SMB_DATA_MAIN
SMB_CLK_MAIN
CK_M_166M_P_DDR4_B
CK_M_166M_N_DDR4_B
DIMM_VREF_B
CK_M_166M_P_DDR2_B
CK_M_166M_P_DDR1_B
CK_M_166M_N_DDR2_B
CK_M_166M_N_DDR1_B
TP_DIMM1_SCS_B3*
TP_DIMM1_SCS_B2*
SMB_DATA_MAIN
DIMM_VREF_B
[PAGE_TITLE=DDR1
CK_M_166M_P_DDR5_B
CK_M_166M_N_DDR5_B
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
USE A87935-008
USE A87935-007
BOM NOTE:
USE A87935-007
USE A87935-006
BOM NOTE:
19
19
29
29
85
85
29
29
85
85
74
74
74
74
IN
IN
IN
IN
IN
IN
IN
IN
DIMM-B
D16704
FOR
FOR
14
14
14
14
14
14
14
14
I2C
FOR
FOR
1
DESIGN
I2C
DOCUMENT NUMBER
1
0/1]
DESIGN
25
= 011
NOTE:
PAGE
BLUE CONN WITH WHITE TABS
BLACK CONN WITH BLACK TABS
BLACK CONN WITH WHITE TABS
= 010
NOTE:
BLACK CONN WITH WHITE TABS
1.00
REV
A
C
D
B
CR-26 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE26
8 7 6 5 4 3 2 1
CHANNEL B
IN
RP1H1 RP5H2
63 3 6 47 3
RP2H1
6 312
RP4H4
7 153 6
56
SM
5%
.063W
IC 56 5%.063W 56 5%.063W 56
SM
5%
.063W
IC
D SM IC SM IC D
RP1H1 RP2H1 RP4H4 RP5H2
DESIGN NOTE; 62 4
56
SM
5%
IC
5
.063W
46 4
56
SM
5%
IC
5
.063W
30 3
56
SM
5%
IC
6
.063W
144
56
SM
5%
IC
.063W
5
13 1
47
R2H2
5%
2
KEEP 603 RESISTORS RP2H4 RP6H3
603 CH
61 1 8 1 R3H2 2 291
RP4H2 13 1 8
DO NOT CHANGE TO 402 56
SM
5%
.063W
IC
45
56 5% 56 5%
.063W
8 56
SM
5%
IC
.063W
1 R5H1 2
603 CH SM IC 12
RP2H4 RP4H2 RP6H3 47
603
5%
CH
60 2 7 44 1
RP3H3
8 28 2 7 122 7
56 5%
.063W 56 5%
.063W 56 5%
.063W 56 5%.063W R5H2
SM IC SM IC SM IC SM IC
11 1 2
47
603
5%
CH
RP1H1 RP2H1 RP4H4 RP5H2
59 1 8 43 1 8 27 1 8 11 1 8 RP4H5
56
SM
5%
.063W
IC 56 5%
.063W 56 5%.063W 56
SM
5%
.063W
IC 10 1 8
SM IC SM IC 47 5%
.063W
RP1H1 RP5H2
SM IC
C 58 2 7 RP2H1 RP4H4 102 7 C
56 5% .063W
42 2 7 26 4 5
56 5%
.063W
SM IC 56
SM
5%
.063W
IC
56
SM
5%
IC
.063W SM IC 9 1 R5H3 2
25 14 BI
M_DATA_B<63..0>
25 14 BI
M_MAA_B<13..0> [PAGE_TITLE=DDR1 DIMM-B 0/1 TERM]
DRAWING
D915PLWDL_FABA.SCH_1.26 INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE Wed Apr 06 22:21:13 2005
CONFIDENTIAL D16704 26 1.00
8 7 6 5 4 3 2 1
CR-27 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE27
8 7 6 5 4 3 2 1
CHANNEL B 89 IN
V_SM_VTT
DESIGN NOTE;
D KEEP 603 RESISTORS D
DO NOT CHANGE TO 402
RP2H5
7 1 8
56 5% .063W
SM IC
RP2H3 1 R3H1
6 3 6 1 2
56 5% .063W 47 5%
SM IC 603 CH
1 R3H4 2 RP3H4
5 0 4 5
56 5% M_SBS_B<1..0>
14 IN 47 5% .063W
603 CH IC
RP3H2 SM
4 4 5
56 5% .063W
SM IC
C C
RP4H3
3 2 7 14 IN M_SCS_B<3..0>*
56 5%.063W RP3H5
SM IC 3 3 6
56 5% .063W
RP5H5 SM
IC
2 4 5
56 5%.063W RP3H5
SM IC 2 4 5
56 5% .063W
RP5H1 SM IC
1 3 6
56 5% .063W RP3H5
SM IC 1 1 8
56 5% .063W
RP6H2 SM IC
0 4 5
56 5% .063W RP3H5
25 14
M_DQS_B<7..0> SM IC 0 2 7
IN 56 5% .063W
SM
B IC B
M_SCKE_B<3..0> RP5H3
14 IN 3 4 5
56 5% .063W
RP3H4 SM IC
RP5H3
14 IN M_RAS_B* 3 6 2 2 7
47 5% .063W 56 5% .063W
SM IC
SM IC
RP5H3
RP3H4 1 3 6
14 IN
M_CAS_B* 1 8 56 5% .063W
SM IC
47 5%.063W
SM IC RP5H3
RP3H4 0 1 8
M_WE_B* 2 7 56 5% .063W
14 IN SM IC
47 5% .063W
A SM IC A
8 7 6 5 4 3 2 1
CR-28 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE28
8 7 6 5 4 3 2 1
DDR CHANNEL B
DECOUPLING CAPACITORS FOR DDR TERMINATION RESISTORS
D
V_SM_VTT D
89 IN
1 1 1 1 1 1 1 1 1 1 1 1 1 1
C4H6 C4H10 C3H6 C3H10 C3H9 C4H9 C6H12 C3H5 C4H11 C4H7 C5H8 C6H13 C2H11 C6H11
.1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V
2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V
603 603 603 603 603 603 603 603 603 603 603 603 603 603
1 1 1 1 1 1 1 1 1 1 1 1 1 1
C5H6 C5H5 C5H4 C2H8 C2H12 C5H7 C1G13 C2G10 C3H8 C2H9 C1H8 C2H10 C3H7 C4H8
.1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V
2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V
CHANNEL B
603 603 603 603 603 603 603 603 603 603 603 603 603 603
V_SM_VTT
89 IN
C3J1 C6H4 DIMM TO MCH
C C1H5 BIT SWAPPING C
1 2 1 2 1 2
85 IN V_SM
4.7UF 20% 4.7UF 20% 4.7UF 20% DIMM MCH DIMM MCH
16V 16V 16V
Y5V EMPTY EMPTY C4H3 C6H3 C2H6 DQ0 DQ5 DQ32 DQ36
1206 1206 1206
1 2 1 2 1 2 DQ1 DQ1 DQ33 DQ33
.1UF 20% .1UF 20% .1UF 20% DQ2 DQ6 DQ34 DQ38
25V 25V 25V
Y5V Y5V Y5V DQ3 DQ3 DQ35 DQ35
603 603 603
C4H2 C2H2 C5H2 DQ4 DQ4 DQ36 DQ37
PLACED AT LEFT AND RIGHT ENDS 1 2 1 2 1 2
DQ5 DQ0 DQ37 DQ32
OF VTT ISLAND .1UF 20%
25V
.1UF 20%
25V
.1UF 20%
25V
DQ6 DQ7 DQ38 DQ39
Y5V Y5V Y5V DQ7 DQ2 DQ39 DQ34
603 603 603
C2H4 C4H5 C3H2
1 2 1 2 1 2
DQ8 DQ12 DQ40 DQ44
85 IN V_SM
.1UF 20% .1UF 20% .1UF 20% DQ9 DQ13 DQ41 DQ41
25V 25V 25V
Y5V
603
Y5V
603
Y5V
603
DQ10 DQ10 DQ42 DQ46
1 C1H7 1
C2F12
1
C4J4 1
C2H7 1 C5G4 1
C4G7 1 1 C5H3 C3H3 C1H2 C2H1 DQ11 DQ11 DQ43 DQ42
B 470UF
20% 22UF .1UF .1UF .1UF .1UF
C3H4 .1UF 1 2 1
B
10V 20% 20% 20% 20% 20%
.1UF
20% 20%
1 2 2
DQ12 DQ8 DQ44 DQ45
ALUM 2 6.3V
2
25V
2
25V
2
25V
2
25V 25V 2
25V
.1UF 20% .1UF 20% .1UF 20% DQ13 DQ9 DQ45 DQ40
2 RDL X5R Y5V Y5V Y5V Y5V 2 Y5V Y5V
25V 25V 25V
1206 603 603 603 603 603 603
Y5V
603
Y5V
603
Y5V
603
DQ14 DQ14 DQ46 DQ47
C3H1 C5H1 C2H5 DQ15 DQ15 DQ47 DQ43
1 2 1 2 1 2
.1UF 20% .1UF 20% .1UF 20% DQ16 DQ21 DQ48 DQ52
25V 25V 25V
Y5V Y5V
603
Y5V
603
DQ17 DQ16 DQ49 DQ48
603
DQ18 DQ23 DQ50 DQ55
DQ19 DQ18 DQ51 DQ51
DQ20 DQ20 DQ52 DQ53
DQ21 DQ17 DQ53 DQ49
DQ22 DQ22 DQ54 DQ54
DQ23 DQ19 DQ55 DQ50
89 IN V_SM_VTT
DQ24 DQ28 DQ56 DQ61
A DQ25 DQ24 DQ57 DQ57 A
DQ26 DQ30 DQ58 DQ63
1 C1G12
470UF DQ27 DQ26 DQ59 DQ59
20%
10V DQ28 DQ29 DQ60 DQ60
ALUM
2 RDL DQ29 DQ25 DQ61 DQ56
DQ30 DQ31 DQ62 DQ62
DQ31 DQ27 DQ63 DQ58
8 7 6 5 4 3 2 1
CR-29 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE29
8 7 6 5 4 3 2 1
5%
CH
33
402
OUT 29 72
2.40 5%
402 CH 1
C6C4
1
C6C1 REV=1 R6B18
4.7UF .01UF 1 VDD REF0 52 CK_PCIF1_R 2 1 CK_P_33M_1394OUT 29
20% 20% 7 VDD 5% 33
EMPTY 402
2
16V
Y5V 2
50V
X7R 48 VDD_REF R6B17
1206 603 11 VDD_48 PCIF_2 10 2 1 CK_P_33M_TPM
OUT 29 70
5% 22
C 202170-004 PCIF_1 9 EMPTY 402 R6B16 C
VTT_PWRGD* 16 CK_PCIF0_R 2 1 CK_P_33M_PAOUT 29 73
30 IN VTT_PWRGD*/PD 5% 22
PCIF_0/TP_EN 8 CH 402
92 IN V_3P3_STBY\G 53 VDD_SUSPEND R6B13
Y6B1 CK_PCI4_R 2 1 CK_P_33M_S2OUT
14.318MHZ 25 21 74 BI SMB_DATA_MAIN 46 SDA 5% 33
29 50
1 2 SMB_CLK_MAIN 47 SCL PCI_4 5 CH 402 R6B12
XTAL
25 21 74 BI CK_PCI3_R 2 1 CK_P_33M_S1OUT 29 49
SM PCI_3 4 5% 33
OSC_CK14M_XTALOUT 49 XTAL_OUT R6B11 CH 402
OSC_CK14M_XTALIN 50 XTAL_IN PCI_2 3 CK_PCI2_R 2 1 CK_P_33M_S4OUT 29 53
5% 33 R6B10
R5C7 PCI_1 56 CK_PCI1_R CH 402 2 1 CK_P_33M_S5 OUT 29
39
2
1
2
8 7 IN FSB USB_48
8 7 IN
H_FSBSEL0 54 FSA
VSS 2 R6C3
VSS 6 2 1 CK_48M_USB_ICHOUT 29 38
B VSS_REF 51 5% 33 B
VCC VCC VSS_48 13 CH 402
VCC3 VCC
1 of 2
402 IC
1 C7F2 C7H8 EMPTY
1 1 16V
.1UF .1UF
20% 20% 20%
2 16V 16V
Y5V 2 Y5V 2 .1UF
402 402 C8D11 VDD_SRC_CLKA
29 IN
BOM NOTE:
STUFF FOR XDP
EMPTY FOR X1 SLOT2
R6B14
1 10K
5%
EMPTY
29 IN CK_48M_USB_ICH 402
CK_P_33M_ICH 2
29 IN
29 IN CK_P_33M_TPM CK_P_33M_PA IN 29
29 IN CK_P_33M_S3
A CK_P_33M_S2 A
29 IN
29 IN CK_P_33M_S1 R6B15
29 IN CK_P_33M_S4 1 10K
5% BOM NOTE:
CK_P_33M_S5 1 1 1 1
1 C6B19 1 1
CH STUFF FOR X1 SLOT2
29 IN C6B13 C6B14 C6B15 C5B5 10PF C6B21 C6C3 2 402 EMPTY FOR XDP
CK_P_33M_1394 10PF 10PF 10PF 10PF 5% 10PF 10PF
29 IN 5% 5% 5% 5% 50V 5% 5%
CK_P_33M_FWH 2 50V
2 50V
2 50V 50V 2 EMPTY 2 50V
2 50V
29 IN EMPTY EMPTY EMPTY 2 EMPTY EMPTY EMPTY
1 1
402 402 402 402 402 402 402
1
C6B20 C7B8 C6B9
10PF 10PF
10PF 5% 5%
5% 50V 50V
50V 2 EMPTY 2 EMPTY
2 EMPTY
402
402 402
[PAGE_TITLE=CK410E PAGE 1 OF 2]
DRAWING
D915PLWDL_FABA.SCH_1.29 INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE Wed Apr 06 22:21:14 2005
CONFIDENTIAL D16704 29 1.00
8 7 6 5 4 3 2 1
CR-30 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE30
8 7 6 5 4 3 2 1
DESIGN NOTE:
STUFF FOR EVALUATION OF COST REDUCTION ON VOLTAGE SOURCE
R5C1 CK_PE_SRC6_R* R5C19
VCC3 VCC3 29 VDD_SRC_CLKA 2 1 2 1 CK_PE_100M_LAN* OUT 56
IN 5% 33
0 5% CH 402
402 CH
D
FB6C2 R5C17
CK_PE_SRC6_R 2 1 CK_PE_100M_LAN OUT 56 D
1 2 VCC3_CLKA 5% 33 1 R5C20 1 R5C18
EMPTY CH 402 49.9 49.9
A51464-001 1 C6C11 1 C5C3 1 C5C1 1 C6C10 1 C6C5 CAD NOTE: 1% 1%
0402, 120 OHM, 200MA 4.7UF .01UF .01UF .01UF .01UF PLACE (1) PER PIN 2 CH 2 CH
20% 20% 20% 20% 20% 402 402
2 16V 50V 50V 50V 2 50V R5C24
Y5V
1206
2 X7R
603
2 X7R
603
2 X7R
603
X7R
603
CK_PE_SRC5_R* 2 1 CK_PE_100M_MCH* OUT 11
5% 33
CH 402
FB6C1 R5C21
1 2 VDD_A_FB CK_PE_SRC5_R 2 1 CK_PE_100M_MCH OUT 11
FB 5% 33 1 R5C23 1 R5C22
CH 402 49.9 49.9
A51464-001 1 C6C12 1 C6C7 1% 1%
0402, 120 OHM, 200MA
4.7UF .01UF 2 CH 2 CH
20% 20% 402 402
16V 2 50V R6C22
2 Y5V
1206
X7R
603
CK_PE_SRC4_R* 2 1 CK_ICHSATA* OUT 39
5% 33 DESIGN NOTE:
CH
CK_H_XDP_NODE* R5C11
1 2
U6B2
CK_410E CK_PE_SRC4_R
R6C21
2
402
1 CK_ICHSATA
SATA MUST BE ON PIN_26,
OUT 39
PIN_27
30 CK_H_XDP_R*
OUT 5% 33 1 R6C23 1 R6C20
C 33 5% REV=1 CH C
402 CH 19 VDD_SRC SRC6* 32 402 49.9 49.9
1%
R5C10 34 VDD_SRC SRC6 33 1%
30 OUT CK_H_XDP_NODE 1 2 CK_H_XDP_R 43 VDD_CPU 2 CH 2 CH
33 5% 28 VDD_SATA SRC5* 30 R6C18
402 402
1 R5C9
49.9
1 R5C14
49.9
402
CH SRC5 31 CK_PE_SRC3_R* 2 1 CK_PE_100M_ICH* OUT 38
1% 1% 5% 33
SATA_SRC4* 27 CH 402
2 CH
402
2 CH
402 SATA_SRC4 26 R6C16
35 CPU2_ITP_SRC7* CK_PE_SRC3_R 2 1 CK_PE_100M_ICH OUT 38
R5C5 36 CPU2_ITP_SRC7 SRC3* 24 5% 33 1 R6C19 1 R6C17
6 OUT CK_H_CPU* 1 2 CK_H_CPU_R* SRC3 23 CH 402 49.9 49.9
33 5% 41 CPU_1* 1% 1%
402 CH 42 CPU_1 SRC2* 22 2 CH 2 CH
R5C4 SRC2 21 402 402
6 OUT CK_H_CPU 1 2 CK_H_CPU_R 44 CPU_0*
33 5% 45 CPU_0 SRC1* 18 R6C15 CK_PE_100M_X1_1*
1 R5C3 1 R5C6 402 CH SRC1 17 CK_PE_SRC2_R* 2 1 OUT 51
49.9 49.9
5% 33
1% 1%
25 VSS_SATA DOT_96* 15 CH 402
2 CH 2 CH 40 VSS_CPU DOT_96 14 R6C13
402 402
20 VSS_SRC CK_PE_SRC2_R 2 1 CK_PE_100M_X1_1 OUT 51
B
R5B15 29 VSS_SRC
2 of 2 5% 33 1 R6C14 1 R6C12 B
10 OUT CK_H_MCH* 1 2 CK_H_MCH_R* CH 402 49.9 49.9
33 5% IC 1% 1%
402 CH 2 CH 2 CH
R5B14 402 402
CK_H_MCH 1 2 CK_H_MCH_R
10 OUT
33 5%
1 R5B13 1 R5B17 402 CH R6C11
49.9
1%
49.9
1%
CK_PE_SRC1_R* 2 1 CK_PE_100M_16PORT* OUT 32
2 CH 2 CH
5% 33
402 402
CH 402
R6C9
CK_PE_SRC1_R 2 1 CK_PE_100M_16PORT OUT 32
5% 33 1 R6C10 1 R6C8
CORE PAGE CH 402 49.9 49.9
1% 1%
2 CH 2 CH
402 402
R6C7
CK_96M_DOT_R* 2 1 CK_96M_DREF* OUT 15
LOCATION X1 SLOT2 XDP DESIGN NOTE: 5% 33
EMPTY 402
R5C12 STUFF EMPTY REMOVE OFF-PAGE
R6C5
FOR UATX CK_96M_D0T_R 1 CK_96M_DREF
A R5C13 STUFF EMPTY 2
OUT 15
A
R5C15 5% 33 1 R6C6 1 R6C4
EMPTY STUFF 1 R5C12 2 CK_PE_100M_X1_2* EMPTY 402 49.9 49.9
OUT 67
R5C16 EMPTY STUFF
0 5%
1% 1%
2 EMPTY 2 EMPTY
402 CH VREG FEATURE 402 402
8 7 6 5 4 3 2 1
CR-31 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE31
8 7 6 5 4 3 2 1
D
D
C C
BLANK PAGE
B B
A A
8 7 6 5 4 3 2 1
CR-32 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE32
8 7 6 5 4 3 2 1
1
33 IN EXP_A_TXP_0_C B14 HSOP0 REFCLK- A14 CK_PE_100M_16PORT* IN 30 C6B16 C7B6
33 IN EXP_A_TXN_0_C B15 HSON0 GND A15 .1UF .1UF
B16 GND HSIP0 A16 EXP_A_RXP_0 OUT 11 20% 20%
11 IN SDVO_CTRL_CLK B17 PRSNT2* HSIN0 A17 EXP_A_RXN_0 OUT 11
25V
Y5V
25V
Y5V
B18 GND GND A18 603 603
2
33 IN EXP_A_TXP_1_C B19 HSOP1 RSVD A19 TP_3G16RSVD_A19
33 IN EXP_A_TXN_1_C B20 HSON1 GND A20
B21 GND HSIP1 A21 EXP_A_RXP_1 OUT 11
B22 GND HSIN1 A22 EXP_A_RXN_1 OUT 11
33 IN EXP_A_TXP_2_C B23 HSOP2 GND A23
33 IN EXP_A_TXN_2_C B24 HSON2 GND A24
C B25 A25 EXP_A_RXP_2 V_3P3_PCIVAUX C
GND HSIP2 OUT 11 90 IN
B26 GND HSIN2 A26 EXP_A_RXN_2 OUT 11
33 IN EXP_A_TXP_3_C B27 HSOP3 GND A27
EXP_A_TXN_3_C B28 A28
1
33 IN HSON3 GND
B29 GND HSIP3 A29 EXP_A_RXP_3 OUT 11 C7C1
B30 RSVD HSIN3 A30 EXP_A_RXN_3 OUT 11
.1UF
20%
11 IN SDVO_CTRL_DATA B31 PRSNT2* GND A31 25V
B32 GND RSVD A32 TP_3G16_RSVD_A32 Y5V
603
2
33 IN
EXP_A_TXP_4_C B33 HSOP4 RSVD A33 TP_3G16_RSVD_A33
33 EXP_A_TXN_4_C B34 HSON4 GND A34
IN B35 A35 EXP_A_RXP_4
GND HSIP4 OUT 11
B36 GND HSIN4 A36 EXP_A_RXN_4 OUT 11
33 IN EXP_A_TXP_5_C B37 HSOP5 GND A37
33 IN EXP_A_TXN_5_C B38 HSON5 GND A38
B39 GND HSIP5 A39 EXP_A_RXP_5 OUT 11
B40 GND HSIN5 A40 EXP_A_RXN_5 OUT 11
33 IN EXP_A_TXP_6_C B41 HSOP6 GND A41 VCC3 +12V
33 IN EXP_A_TXN_6_C B42 HSON6 GND A42
B43 GND HSIP6 A43 EXP_A_RXP_6 OUT 11
B44 GND HSIN6 A44 EXP_A_RXN_6 OUT 11
B 33 EXP_A_TXP_7_C B45 HSOP7 GND A45 C7B5 B
IN EXP_A_TXN_7_C B46 A46 1 C7B7 1
33 IN HSON7 GND 470UF
B47 A47 EXP_A_RXP_7 100UF 20%
GND HSIP7 OUT 11 20% 16V
TP_16PRSNT_B43 B48 PRSNT2* HSIN7 A48 EXP_A_RXN_7 OUT 11 25V ALUM
B49 GND GND A49 2
ELEC
RDL
2 RDL
8 7 6 5 4 3 2 1
CR-33 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE33
8 7 6 5 4 3 2 1
BOM NOTE:
ALWAYS STUFF
C6C13
11 EXP_A_TXN_1 1 2
IN
.1UF 20% C6C14 EXP_A_TXN_1_C 32
11 IN EXP_A_TXP_1 603 25V Y5V 1 2 EXP_A_TXP_1_C OUT
OUT 32
.1UF 20%
25V Y5V
C6C17
11 EXP_A_TXN_2 603 1 2 C6C16 EXP_A_TXN_2_C 32
IN EXP_A_TXP_2 1 2 EXP_A_TXP_2_C OUT
11 IN OUT 32
.1UF 20%
C6D2 603 25V Y5V .1UF 20%
11 EXP_A_TXN_3 1 2 C6C20 603 25V Y5V EXP_A_TXN_3_C 32
IN EXP_A_TXP_3 2 OUT
11 IN
1 EXP_A_TXP_3_C OUT 32
.1UF 20%
603 25V Y5V .1UF 20%
603 25V Y5V
C C
C6D4
11 EXP_A_TXN_4 1 2 C6D3 EXP_A_TXN_4_C 32
IN EXP_A_TXP_4 1 2 EXP_A_TXP_4_C OUT
11 IN OUT 32
.1UF 20%
C6D7 603 25V Y5V .1UF 20%
11 EXP_A_TXN_5 1 2 C6D6 603 25V Y5V EXP_A_TXN_5_C 32
IN 1 2 OUT
11 IN EXP_A_TXP_5 EXP_A_TXP_5_C OUT 32
.1UF 20%
603 25V Y5V .1UF 20% C6D9
11 EXP_A_TXN_6 603 25V Y5V 1 2 C6D8 EXP_A_TXN_6_C 32
IN EXP_A_TXP_6 1 2 EXP_A_TXP_6_C OUT
11 IN OUT 32
.1UF 20%
C6D13 603 25V Y5V .1UF 20%
11 EXP_A_TXN_7 1 2 C6D12 603 25V Y5V EXP_A_TXN_7_C 32
IN EXP_A_TXP_7 1 2 EXP_A_TXP_7_C OUT
11 IN OUT 32
.1UF 20%
603 25V Y5V .1UF 20%
603 25V Y5V
C6D15
11 EXP_A_TXN_8 1 2 C6D14 EXP_A_TXN_8_C 32
IN EXP_A_TXP_8 1 2 EXP_A_TXP_8_C OUT
B 11 IN .1UF OUT 32 B
20%
C6D18 603
25V Y5V .1UF 20%
11 EXP_A_TXN_9 1 2 C6D17 603
25V Y5V EXP_A_TXN_9_C 32
IN EXP_A_TXP_9 1 2 EXP_A_TXP_9_C OUT
11 IN OUT 32
.1UF 20%
25V Y5V .1UF 20% C6D21
603
EXP_A_TXN_10 603
25V Y5V 1 2 C6D19 EXP_A_TXN_10_C OUT 32
11 IN
EXP_A_TXP_10 1 2 EXP_A_TXP_10_C OUT
11 IN 32
.1UF 20%
C6D23 603 25V Y5V .1UF 20%
25V Y5V
11 EXP_A_TXN_11 1 2 C6D22 603 EXP_A_TXN_11_C 32
IN
11 IN EXP_A_TXP_11 1 2 EXP_A_TXP_11_C OUT
OUT 32
.1UF 20%
603 25V Y5V .1UF 20% C6E1
11 EXP_A_TXN_12 603 25V Y5V 1 2 C6D24 EXP_A_TXN_12_C OUT 32
IN 1 2
11 IN EXP_A_TXP_12 EXP_A_TXP_12_C OUT 32
.1UF 20%
C6E3 603 25V Y5V .1UF 20%
11 EXP_A_TXN_13 1 2 C6E2 603
25V Y5V
EXP_A_TXN_13_C OUT 32
IN EXP_A_TXP_13 1 2
11 IN EXP_A_TXP_13_C OUT
.1UF 20% 32
603 25V Y5V .1UF 20% C6E5
11 EXP_A_TXN_14 603 25V Y5V 1 2 C6E4 EXP_A_TXN_14_C OUT 32
IN EXP_A_TXP_14 1 2 EXP_A_TXP_14_C OUT
A 11 IN 32 A
.1UF 20%
C6E7 603 25V Y5V .1UF 20%
11 EXP_A_TXN_15 1 2 C6E6 603 25V Y5V
EXP_A_TXN_15_C OUT 32
IN EXP_A_TXP_15 1 2
11 IN .1UF 20%
EXP_A_TXP_15_C OUT 32
603 25V Y5V .1UF 20%
603 25V Y5V
[PAGE_TITLE=PCIE COUPLING]
DRAWING
CORE PAGE D915PLWDL_FABA.SCH_1.33 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:15 2005
CONFIDENTIAL D16704 33 1.00
8 7 6 5 4 3 2 1
CR-34 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE34
8 7 6 5 4 3 2 1
D
D
C C
BLANK PAGE
B B
A A
DRAWING
D915PLWDL_FABA.SCH_1.34 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:15 2005
CONFIDENTIAL D16704 34 1.00
8 7 6 5 4 3 2 1
CR-35 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE35
8 7 6 5 4 3 2 1
D
D
C C
BLANK PAGE
B B
A A
DRAWING
D915PLWDL_FABA.SCH_1.35 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:15 2005
CONFIDENTIAL D16704 35 1.00
8 7 6 5 4 3 2 1
CR-36 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE36
8 7 6 5 4 3 2 1
D
D
C C
BLANK PAGE
B B
A A
DRAWING
D915PLWDL_FABA.SCH_1.36 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:15 2005
CONFIDENTIAL D16704 36 1.00
8 7 6 5 4 3 2 1
CR-37 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE37
8 7 6 5 4 3 2 1
D
D
U8G1
ICH6
REV=2.0 P_AD<31..0>
53 52 50 49 BI P_PAR E1 PAR AD_0 E2 0 BI 49 50 52 53
54 53 52 50 49 BI P_DEVSEL* C3 DEVSEL* AD_1 E5 1
29 IN CK_P_33M_ICH G6 PCICLK AD_2 C2 2
53 52 50 49 OUT P_PCIRST* R2 PCIRST* AD_3 F5 3
73 72 70 56 55 15 OUT PLTRST* R5 PLTRST* AD_4 F3 4 VCC3
C 54 53 52 50 49 BI P_IRDY* A3 IRDY* AD_5 E9 5 C
57 53 52 50 49 BI P_PME* P6 PME* AD_6 F2 6 C8F10
54 53 52 50 49 BI P_SERR* G5 SERR* AD_7 D6 7 1 2
VCC3 54 53 52 50 49 BI P_STOP* J1 STOP* AD_8 E6 8
54 53 52 50 49 BI P_PLOCK* C5 PLOCK* PCI AD_9 D3 9 .1UF 20%
54 53 52 50 49 BI P_TRDY* J2 TRDY* AD_10 A2 10 25V
54 53 52 50 49 BI P_PERR* E3 PERR* AD_11 D2 11 Y5V
603
54 53 52 50 49 BI P_FRAME* J3 FRAME* AD_12 D5 12 C9G2
AD_13 H3 13 1 2
1 OUT P_GNT0* C1 GNT_0* AD_14 B4 14
49 OUT P_GNT1* B6 GNT_1* AD_15 J5 15 .1UF 20%
R8D10 50 OUT P_GNT2* F1 GNT_2* AD_16 K2 16 25V
4.7K
5% 52 OUT P_GNT3* C8 GNT_3* AD_17 K5 17 Y5V
603
53 P_GNT4*
OUT BOOT_BIOS_DIS_SEL E7 GNT_4*_GPIO48 AD_18 D4 18
EMPTY
402 37 OUT F6 GNT_5*_GPIO17 AD_19 L6 19 C9G5
2 TP_P_GNT6* D8 GNT_6*_GPIO16 AD_20 G3 20 1 2
AD_21 H4 21
54 IN P_REQ0* L5 REQ_0* AD_22 H2 22 .1UF 20%
25V
BIOS_BOOT_3VINPUT 54 49 IN P_REQ1* B5 REQ_1* AD_23 H5 23 Y5V
J8D2 54 50 IN P_REQ2* M5 REQ_2* AD_24 B3 24 603
1X3HDR
1 BOOT_BIOS_DIS_SEL 54 52 IN P_REQ3* B8 REQ_3* AD_25 M6 25 C9G4
2 54 53 IN P_REQ4* F7 REQ_4*_GPIO40 AD_26 B2 26 1 2
3 OUT 37
54 IN P_REQ5* E8 REQ_5*_GPIO1 AD_27 K6 27
B 54 IN
P_REQ6* B7 REQ_6*_GPIO0 AD_28 K3 28 .1UF 20% B
EMPTY AD_29 A5 29 25V
54 52 IN P_INTA* N2 PIRQA* AD_30 L1 30 Y5V
603
54 52 IN P_INTB* L2 PIRQB* AD_31 K4 31
54 53 52 IN P_INTC* M1 PIRQC* P_C/BE<3..0>*
54 53 52 IN P_INTD* L3 PIRQD* C_BE_3* G2 3 BI 49 50 52 53
54 50 49 IN P_INTE* D9 PIRQE*_GPIO2 C_BE_2* G4 2
54 53 50 49 IN P_INTF* C7 PIRQF*_GPIO3 C_BE_1* H6 1
54 53 50 49 IN P_INTG* C6 PIRQG*_GPIO4 C_BE_0* J6 0
54 50 49 IN P_INTH* M3 PIRQH*_GPIO5
1 of 6
IC
CAD NOTE:
[PAGE_TITLE=ICH 1 OF 6 - CONTROL]
DRAWING
D915PLWDL_FABA.SCH_1.37 DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:15 2005 INTEL
CONFIDENTIAL D16704 37 1.00
8 7 6 5 4 3 2 1
CR-38 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE38
8 7 6 5 4 3 2 1
DMI
38 IN HSO_N0 1 2 HSO_N0_C OUT 51 11 OUT DMI_ITP_MRP_1 U26 DMI_1TXP USBP_3P B18 USB_FRONT3 BI 46
11 IN DMI_MTN_IRN_2 Y25 DMI_2RXN USBP_4N E17 USB_BACK3* BI 45 100
.1UF 20%
25V 11 IN DMI_MTP_IRP_2 Y24 DMI_2RXP USBP_4P D17 USB_BACK3 BI 45 100
Y5V 11 OUT DMI_ITN_MRN_2 W27 DMI_2TXN USBP_5N B16 USB_FRONT4* BI 46
603
11 OUT DMI_ITP_MRP_2 W26 DMI_2TXP USBP_5P A16 USB_FRONT4 BI 46
11 IN DMI_MTN_IRN_3 AB24 DMI_3RXN USBP_6N C15 USB_BACK2* BI 59 99
11 IN DMI_MTP_IRP_3 AB23 DMI_3RXP USBP_6P D15 USB_BACK2 BI 59 99
11 DMI_ITN_MRN_3 AA27 DMI_3TXN USBP_7N A14 USB_BACK1* 59 99
USB
OUT BI
11 OUT DMI_ITP_MRP_3 AA26 DMI_3TXP USBP_7P B14 USB_BACK1 BI 59 99
PCI
IN HSI_N1 K25 PERN_2 OC_4*_GPIO9 C23 USB_OC_BACK_RIGHT* IN 91
IN HSI_P1 K24 PERP_2 OC_5*_GPIO10 D23
OUT HSO_N1 J27 PETN_2 OC_6*_GPIO14 C25
OUT HSO_P1 J26 PETP_2 OC_7*_GPIO15 C24 USB_OC_BACK_LEFT* IN 91
HSI_N2 M25
EXPRESS
67 IN PERN_3
67 IN
HSI_P2 M24 PERP_3 USBRBIAS B22 R8F12
C 38 OUT HSO_N2 L27 PETN_3 USBRBIAS* A22 USBRBIAS_ICH 1 2 C
38 OUT HSO_P2 L26 PETP_3 402 CH
TP_HSI_N3 P24 PERN_4 CLK48 A27 CAD NOTE:
22.6 1%
TP_HSI_P3 P23 PERP_4
38 OUT HSO_N3 N27 PETN_4 TRACES TIED TOGETHER CLOSE TO PINS
38 OUT HSO_P3 N26 PETP_4 LENGTH NO LONGER THAN 200 MIL TO RESISTOR
HSO_N2 1
C7G6 2 HSO_N2_C
38 IN OUT 67
.1UF 20%
25V
Y5V
603
USB CLASSIC FILTER USB HS (HI-SPEED) FILTER
C8F12 C7F12
92 IN
V_3P3_STBY\G 1 2 102 IN V_1P5_CORE 1 2
.1UF 10% .01UF 20%
16V 50V
X7R
X7R 603
HSO_P3 1
C7G11 2 TP_HSO_P3_C 603
38 IN
.1UF 20%
25V EMPTY C8F13 C7F11
603 1 2
1 2
C7G10 .1UF 10% .1UF 10%
38 IN HSO_N3 1 2 TP_HSO_N3_C 16V 16V
X7R
X7R 603
.1UF 20% 603
25V EMPTY
A 603 CAD NOTE: CAD NOTE: A
PLACE (2) 0.1UF NEAR A17 PLACE 0.01UF NEAR A25
PLACE 0.01UF NEAR A24 PLACE 0.1UF NEAR D27
[PAGE_TITLE=ICH 2 OF 6 - CONTROL]
DRAWING
D915PLWDL_FABA.SCH_1.38 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:15 2005
CONFIDENTIAL D16704 38 1.00
8 7 6 5 4 3 2 1
CR-39 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE39
8 7 6 5 4 3 2 1
D
D
U8G1
ICH6
ICH_IDE_DD<15..0> REV=2.0
44 BI 15AD13 DD_15 SATA_0RXN AE3 SATAHDR_RX0N IN 71
14AG15 DD_14 SATA_0RXP AD3 SATAHDR_RX0P IN 71
13AE15 DD_13 SATA_0TXN AG2 SATAHDR_TX0N OUT 71
12AC13 DD_12 SATA_0TXP AF2 SATAHDR_TX0P OUT 71
11 AB13 DD_11 SATA_1RXN AC5 SATAHDR_RX1N IN 71
10AB12 DD_10 SATA_1RXP AD5 SATAHDR_RX1P IN 71
9 AF13 DD_9 SATA_1TXN AF4 SATAHDR_TX1N OUT 71
8 AE13 DD_8 SATA_1TXP AG4 SATAHDR_TX1P OUT 71
C 7 AB11 DD_7 SATA_2RXN AD7 SATAHDR_RX2N IN 71 C
IDE
6 AD11 DD_6 SATA_2RXP AC7 SATAHDR_RX2P IN 71
5 AC11 DD_5 SATA_2TXN AF6 SATAHDR_TX2N OUT 71
4 AE14 DD_4 SATA_2TXP AG6 SATAHDR_TX2P OUT 71
3 AD12 DD_3 SATA_3RXN AC9 SATAHDR_RX3N IN 71
2 AF14 DD_2 SATA_3RXP AD9 SATAHDR_RX3P IN 71
1 AF15 DD_1 SATA_3TXN AF8 SATAHDR_TX3N OUT 71 V_3P3_STBY\G
0 AD14 DD_0 SATA_3TXP AG8 SATAHDR_TX3P OUT 71
92 IN
ICH_IDE_DDACK* AB15 DDACK* SATA_CLKN AC2 CK_ICHSATA*
SATA
44 BI IN 30
44 ICH_IDE_DDREQ AB14 DDREQ SATA_CLKP AC1 CK_ICHSATA 30
CAD NOTE:
BI IN
44 BI ICH_IDE_DIOR* AE16 DIOR* TIE TRACES TOGETHER
R8H1 R9H1
44 BI ICH_IDE_DIOW* AC14 DIOW* SATARBIAS* AG11 SATARBIAS_ICH CLOSE TO ICH 1 2 2 1
44 BI ICH_IDE_IORDY AF16 IORDY SATARBIAS AF11 24.9 1% 10K 5%
ICH_IDE_DA<2..0> 402 CH 402 CH
44 BI 0AC16 DA0 SMBCLK Y4 SMB_CLK_RESUME BI 32 49 50 51 52 53 56 67 74 79
R9G21
1AB17 DA1 SMBDATA W5 SMB_DATA_RESUME BI 32 49 50 51 52 53 67 74 79 56
2 1
2AC17 DA2 10K 5%
LINKALERT* Y5 SMLALERT_ICH 402 CH
44 BI ICH_IDE_DCS1* AD16 DCS1* SMLINK_0 W4 SMLLINK0_ICH
R9G18
44 BI ICH_IDE_DCS3* AE17 DCS3* SMLINK_1 U6 SMLINK1_ICH 2 1
10K 5%
B 44 IN ICH_IDE_IRQ AB16 IDEIRQ SATALED* AC19 ICH_SATA_LED* OUT 43 74 VCC3 402 CH
B
SATA_0GP/GPIO26 AF17 SATAGP_PU
SATA_1GP/GPIO29 AE18 SATAGP_PU
R8H6
SATA_2GP/GPIO30 AF18 SATAGP_PU
1 2
SATA_3GP/GPIO31 AG18 SATAGP_PU
INTRUDER* AA3 ICH_INTRUDER_HDR* IN 43 4.7K 5%
402 CH
RSMRST* Y3 ICH_RSMRST* IN 55 74
RTCX1 Y1 ICH_RTCX1 IN 43
RTCX2 Y2 ICH_RTCX2 IN 43
90 IN V_3P0_BAT_VREG
SATA FILTER RTCRST*
INTVRMEN
AA2
AA5
ICH_RTCRST_PULLUP
INTVRMEM IN 43
1 R9H8 2
C8H1 5% 390K
102 V_1P5_CORE 1 2 SPKR F8 SPKR OUT 61 72 80
BOM NOTE: CH 402
IN
.1UF 20%
3 of 6 ALWAYS STUFF PULL-UP TO ENABLE INTERNAL VRM.
25V
Y5V EXTERNAL VRM IS NOT SUPPORTED ON THIS DESIGN.
603 IC
C8H2
1 2
.1UF 20%
A 25V A
Y5V
CAD NOTE: 603
PLACE AT ENDS OF PWR CORRIDORS
P-ATA FILTER
VCC3
C8H4 2
1
8 7 6 5 4 3 2 1
CR-40 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE40
8 7 6 5 4 3 2 1
D U8G1
D
ICH6
LPC
LAD_2/FB2 SMBALERT*/GPIO11 ICH_GPIO11_R 43
IN
3 N4 LAD_3/FB3 GPI12 M2 ICH_GPI12_PU IN 43
73 BI L_DRQ* N6 LDRQ_0* GPI13 R6 IO_PME* IN 73
73 72 70 BI L_FRAME* P3 LFRAME* STP_PCI*/GPO18 AC21 TP_ICH_GPO18*
GPO19 AB21 ICH_GPO19* OUT 80
43 IN AUD_LINK_BCLK_R C10 ACZ_BIT_CLK STP_CPU*/GPO20 AD22 ICH_GPO20 OUT 85
60 OUT AUD_LINK_RST* A10 ACZ_RST* GPO21 AD20 ICH_GPO21 OUT 85
F11 AD21
AUDIO
TP_AUD_LINK_SDI0 ACZ_SDIN_0 GPO23 HW_SW_WARNING_SEL 99
OUT
TP_AUD_LINK_SDI1 F10 ACZ_SDIN_1 GPIO24 V3 0
61 IN AUD_LINK_SDI2 B10 ACZ_SDIN_2 GPIO25 P5 ICH_GPIO25_R IN 43
43 OUT AUD_LINK_SDO_R C9 ACZ_SDOUT GPIO27 R3 1 BOARDID<5..0>
43 OUT AUD_LINK_SYNC_R B9 ACZ_SYNC GPIO28 T3 ICH_GPIO28_R OUT 43 IN 43 72 73
29 IN CK_14M_ICH E10 CLK14 CLKRUN*/GPIO32 AF19 TP_ICH_GPIO32
GPIO33 AF20 2
58 OUT ICH_EE_CS D12 EE_CS EPROM GPIO34 AC18 3
58 OUT ICH_EE_DIN F13 EE_DIN CPUPWRGD/GPO49 AG25 H_PWRGD OUT 8 6 101
C IN ICH_EE_DOUT D11 EE_DOUT C
58 OUT ICH_EE_CLK B12 EE_SHCLK MCH_SYNC* AG21 ICH_SYNC* IN 15 1
PWRBTN* U1 SW_ON* 81 C2F16
56 IN ICH_LAN_JCLK F12 LAN_CLK RI* T2 COM_RI_WAKE* IN IN 43 78
100.0PF
5%
56 OUT ICH_LAN_JRST B11 LAN_RSTSYNC SLP_S3* T4 SLP_S3* OUT 74 2 50V
56 IN ICH_LAN_JRX0 E12 LAN_RXD_0 SLP_S4* T5 SLP_S4_R* OUT 43
COG
E11 T6 TP_SLP_S5* 603
LAN
56 IN ICH_LAN_JRX1 LAN_RXD_1 SLP_S5*
56 IN ICH_LAN_JRX2 C13 LAN_RXD_2 SUS_STAT*/LPCPD* W3 LPCPD* OUT 70 73 V_3P3_STBY\G
56 OUT ICH_LAN_JTX0 C12 LAN_TXD_0 SUSCLK V6 SUSCLK OUT 73
92 IN
56 OUT ICH_LAN_JTX1 C11 LAN_TXD_1 SYS_RESET* U2 FP_RST* IN 43 81 CLOSE ICH
56 OUT ICH_LAN_JTX2 E13 LAN_TXD_2 LAN_RST* V5 LAN_DISABLE* 73 74
TP_0 V2 ICH_BATLOW_PU IN 1 R9G19 2
AF22 U3 TP_DXFTEST
MISC
73 IN A20GATE A20GATE TP_3 10K 5% DESIGN NOTE:
6 OUT H_A20M* AF23 A20M* VRMPWRGD AF21 ICH_VRMPWRGD_PU IN 43 402 CH MOBILE BATTERY STRAP
6 OUT H_SLP* AE27 CPUSLP* THRM* AC20 ICH_THRM_PU* IN 43
TP_ICH_AB24 AE20 DPRSLPVR/TP_1 WAKE* U5 WAKE* IN 32 43 51 56 67
TP_DPRSTP AE24 TP_4 PWROK AA1 PWRGD_3V IN 74
TP_ICH_AD23 AD27 TP_2
6 OUT H_IGNNE* AG26 IGNNE*
72 OUT ICH_INIT_33V AE22 INIT3_3V*
H_INIT* AF27
HOST
6 OUT INIT*
6 OUT H_INTR AG24 INTR
DESIGN NOTE: 8 IN H_FERR* AF24 FERR*
B VALIDATION FEATURE 6 OUT
H_NMI AF25 NMI B
73 IN KBRST* AD23 RCIN*
81 73 70 BI SER_IRQ AB20 SERIRQ
R7H1 6 OUT ICH_H_SMI* AG27 SMI*
6 OUT H_STPCLK* 1 2 H_STPCLK_ICH* AE26 STPCLK*
0 1A AE23 THRMTRIP*
603 CH
A A
[PAGE_TITLE=ICH 4 OF 6 - CONTROL]
DRAWING
D915PLWDL_FABA.SCH_1.40 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:15 2005
CONFIDENTIAL D16704 40 1.00
8 7 6 5 4 3 2 1
CR-41 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE41
8 7 6 5 4 3 2 1
U8G1 ICH6
DESIGN NOTE:
CIRCUIT REMAINS IN DESIGN FOR ENGINEERING EVALUATION OF CHIPSET. REV=2.0 VCC1_5 AA19 V_FSB_VTT
ISOLATION OF VOLTAGE SOURCE BY MAKING THE MIC5255 REGULATOR EMPTY. V_REF5V A8 V5REF VCC1_5 AA20 V_1P5_CORE IN 102
87 IN
VCC3 74 IN AA18 V5REF VCC1_5 AA21
U8H1 VCC1_5 L11 CAD NOTE: 2 C8H7
MIC5255
V_2P5_ICH_VREGOUT VCC1_5 L12 PLACE NEAR ONE OF PINS: .1UF
1 IN OUT 5 OUT 41 41 IN V_2P5_ICH AB18 VCC2_5 VCC1_5 L14 AB22, AD26 OR AG23 20%
25V
3 EN P7 VCC2_5 VCC1_5 L16 1 Y5V
D
1
C8H9 1
C9G1 2 GND BYP 4 ICH_REG_BYP VCC1_5 L17 603
4.7UF .1UF VCC1_5 M11 D
10% 10% EMPTY 1
C8H8
1
C8H11 41 IN F21
V_REF5V_SUS V5REF_SUS VCC1_5 M17
2
10V
EMPTY 2
16V
EMPTY .01UF 4.7UF VCC1_5 P11
1206 603 20% 10% VCC1_5 P17 V_2P5_ICH
"X5R" "X7R" 2
50V
EMPTY 2 10V
EMPTY VCC1_5 T11 41 IN
603 1206 VCC1_5 T17
"X7R" "X5R" VCC1_5 U11 1
C8H10
VCC1_5 U12 .1UF
VCC1_5 U14 20%
VCC1_5 U16 CAD NOTE: 2 25V
Y5V
M7G1
VCCA_PWR_GPLL_PN1_ICH VCC1_5 U17 PLACE NEAR A18 603
R7G7 VCC1_5 G8
POWER
102 IN
V_1P5_CORE 1
MULTI
2 1 2 VCCDMI_PLL_ICH AC27 VCCDMIPLL VCC1_5 D24
1 5% VCC1_5 D25
IND SM 402 CH AE1 VCCSATAPLL VCC1_5 D26
201005-525 2
C7H2 2
C7H1 VCC1_5 D27
4.7UF .01UF 102 IN V_1P5_CORE A25 VCCUSBPLL VCC1_5 E20 R8H4
BOM NOTE 20% 20% VCC1_5 E21 41 IN V_2P5_ICH_VREGOUT 1 2 V_2P5_ICH OUT 41
CHANGE TO 108506-007 IN MOD FILE
1 16V
EMPTY 1 50V
X7R
AA22 VCCDMIPWR VCC1_5 E22 0 5%
1206 603 AA23 VCCDMIPWR VCC1_5 E23 402 EMPTY
AA24 VCCDMIPWR VCC1_5 E24 DESIGN NOTE:
V_1P5_CORE AA25 VCCDMIPWR VCC1_5 F9 STUFF ONLY FOR ENGINEERING EXPERIMENT
102 IN AB25 VCCDMIPWR VCC1_5 F20 ISOLATES 2P5 VREG
C V_5P0_STBY 2 AB26 VCCDMIPWR VCC1_5 G20 C
86 IN C8H6 AB27 VCCDMIPWR
.01UF
10% F25 VCCDMIPWR VCC3
1 R3J6 50V F26 VCCDMIPWR VCC_CPU_IO AB22 V_FSB_VTT IN 87
10 1 X7R
603
F27 VCCDMIPWR VCC_CPU_IO AD26
5%
G22 VCCDMIPWR VCC_CPU_IO AG23
2 CH
402
G23 VCCDMIPWR
G24 VCCDMIPWR
3 G25 VCCDMIPWR VCC3_3 E26
43 41 OUT V_REF5V_SUS 1 V_3P3_STBY\G IN 92 H21 VCCDMIPWR VCC3_3 AA10 VCC3
H22 VCCDMIPWR VCC3_3 AA12 CAD NOTE: C7G1
2 J21 VCCDMIPWR VCC3_3 AA14 PLACE NEAR E26 1 2
R3J2
Q7G1 J22 VCCDMIPWR VCC3_3 AA15 .1UF 20%
V_REF5V_SUS_SIO 1 2
MMBT3904
XSTR K21 VCCDMIPWR VCC3_3 AA17 25V
74 IN K22 VCCDMIPWR VCC3_3 AC15 Y5V
0 5% L21 VCCDMIPWR VCC3_3 AD17 603
402 EMPTY
L22 VCCDMIPWR VCC3_3 AG10
M21 VCCDMIPWR VCC3_3 AG13 VCC3
450
M22 VCCDMIPWR VCC3_3 AG16 CAD NOTE:
80
N21 VCCDMIPWR VCC3_3 AG19
400MA
N22 VCCDMIPWR VCC3_3 A6 PLACE NEAR AG10
BROAD
N23 VCCDMIPWR VCC3_3 B1
B M7G2 N24 VCCDMIPWR VCC3_3 E4 C8H5 B
V_1P5_CORE 1 2 V_PCIEXPRESS_PWR N25 VCCDMIPWR VCC3_3 H1 1 2
102 IN MULTI OUT 38 41 P21 VCCDMIPWR VCC3_3 H7
P25 VCCDMIPWR VCC3_3 J7 .1UF 20%
FB P26 VCCDMIPWR VCC3_3 L4 25V
1 C7G8
220UF
P27 VCCDMIPWR VCC3_3 L7 Y5V
603
BOM NOTE:
20% R21 VCCDMIPWR VCC3_3 M7
CHANGE TO 108506-002 6.3V R22 VCCDMIPWR VCC3_3 P1 VCC3
IN MOD FILE 2 ALUM
RDL T21 VCCDMIPWR
T22 VCCDMIPWR
U21 VCCDMIPWR VCCSUS3_3 A13
U22 VCCDMIPWR VCCSUS3_3 F14
V21 VCCDMIPWR VCCSUS3_3 G13
V22 VCCDMIPWR VCCSUS3_3 G14
V_PCIEXPRESS_PWR W21 VCCDMIPWR VCCSUS3_3 A11 V_3P3_STBY\G IN 92
41 IN W22 VCCDMIPWR VCCSUS3_3 A24
Y21 VCCDMIPWR VCCSUS3_3 U4 2
Y22 VCCDMIPWR VCCSUS3_3 V1 C8F8
VCCSUS3_3 V7 .01UF
PCI EXPRESS DECOUPLING FILTER C7G15 AA6 VCC1_5 VCCSUS3_3 W2 1
20%
50V
2 1 AB4 VCC1_5 VCCSUS3_3 Y7 X7R CAD NOTE:
AB5 VCC1_5 VCCSUS3_3 A17 603
.01UF 20% AB6 VCC1_5 VCCSUS3_3 B17 PLACE 0.01UF NEAR A24
50V AC4 VCC1_5 VCCSUS3_3 C16 V_3P0_BAT_VREG
A
X7R
603 AD4 VCC1_5 VCCSUS3_3 C17 IN 90
A
AE4 VCC1_5 VCCSUS3_3 D16
CAD NOTE: C7G12 AE5 VCC1_5 VCCSUS3_3 E16
PLACE THESE CAPS AT 2 1 AG5 VCC1_5 VCCSUS3_3 F15 C9G6 1
ENDS OF POWER CORRIDORS
AF5 VCC1_5 VCCSUS3_3 F16 2
.01UF 20% AA7 F18
2C9G7 1
50V VCC1_5 VCCSUS3_3 .01UF 20%
X7R AA8 VCC1_5 VCCSUS3_3 G15 VCCSUS_1P5A_ICH 50V
603 AA9 VCC1_5 VCCSUS3_3 G16 X7R C7F9
AB8 VCC1_5 VCCSUS3_3 G17 VCCSUS_1P5B_ICH 603 .01UF
50V
20% 2 1
C7G2 AC8 VCC1_5 VCCSUS3_3 G18 X7R
2 1 AD8 VCC1_5 VCCSUS_1P5C_ICH 603 .01UF
50V
20%
AE8 VCC1_5 VCCRTC AB3 X7R
.01UF
50V
20% AE9 VCC1_5 603
X7R AF9 VCC1_5 VCCSUS1_5_A R7
603 AG9 VCC1_5 VCCSUS1_5_B U7
VCCSUS1_5_C G19 [PAGE_TITLE=ICH 5 OF 6 - POWER]
VCCSUS1_5_D G10 DRAWING
102 V_1P5_CORE 5 of 6 VCCSUS1_5_E G11 D915PLWDL_FABA.SCH_1.41 INTEL DOCUMENT NUMBER PAGE REV
IN
IC
Wed Apr 06 22:21:15 2005
CONFIDENTIAL D16704 41 1.00
8 7 6 5 4 3 2 1
CR-42 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE42
8 7 6 5 4 3 2 1
U8G1
ICH6
REV=2.0
A1 VSS VSS G21
D
A12 VSS VSS G7
A15 VSS VSS G9 D
A19 VSS VSS H23
A21 VSS VSS H26
A23 VSS VSS H27
A26 VSS VSS J23
A4 VSS VSS J24
A7 VSS VSS J25
A9 VSS VSS J4
AA11 VSS VSS K1
AA13 VSS VSS K23
AA16 VSS VSS K26
AA4 VSS VSS K27
AB1 VSS VSS K7
AB10 VSS VSS L13
AB19 VSS VSS L15
AB2 VSS VSS L23
AB7 VSS VSS L24
AB9 VSS VSS L25
AC10 VSS VSS M12
AC12 VSS VSS M13
AC22 VSS VSS M14
AC23 VSS VSS M15
AC24 VSS VSS M16
C AC26 VSS VSS M23 C
AC3 VSS VSS M26
AC6 VSS VSS M27
AD1 VSS VSS M4
AD10 VSS VSS N1
AD15 VSS VSS N11
AD18 VSS VSS N12
AD2 VSS VSS N13
AD24 VSS VSS N14
AD6 VSS VSS N15
AE10 VSS VSS N16
AE11 VSS VSS N17
AE12 VSS VSS N7
AE2 VSS VSS P12
AE21 VSS VSS P13
AE25 VSS VSS P14
AE6 VSS VSS P15
AE7 VSS VSS P16
AF1 VSS VSS P22
AF12 VSS VSS R11
AF26 VSS VSS R12
AF3 VSS VSS R13
B
AF7 VSS VSS R14 B
AG1 VSS VSS R15
AG12 VSS VSS R16
AG14 VSS VSS R17
AG17 VSS VSS R23
AG20 VSS VSS R24 HS8G1
AG22 VSS VSS R25 ICH6_HSK C46655-001
AG3 VSS VSS R4 1 NC_1 NC_2 2
AG7 VSS VSS T1
B13 VSS VSS T12 4 NC_4 NC_3 3
B15 VSS VSS T13
B19 VSS VSS T14 EMPTY
B21 VSS VSS T15 NOTE:
B23 VSS VSS T16 NO PHYSICAL PINS
B25 VSS VSS T23 ON ALLEGRO MODEL
C14 VSS VSS T26
C18 VSS VSS T27
C20 VSS VSS T7
C22 VSS VSS U13
C4 VSS VSS U15
D1 VSS VSS U23
D10 VSS VSS U24
D13 VSS VSS U25
D14 VSS VSS V23 TH TH
A
D18 VSS VSS V26 J9H1 J7F1 A
D20 VSS VSS V27
D22 VSS VSS V4 1 1
D7 VSS VSS W1
E14 VSS VSS W23 NC NC
E15 VSS VSS W24 EMPTY
E18 VSS VSS W25 EMPTY
E19 VSS VSS W7
E25 VSS VSS Y23 A13494-005 A13494-005
F17 VSS VSS Y26
F19 VSS VSS Y27
F22 VSS VSS Y6
F4 VSS VSS E27
G1 VSS VSS AF10
G12 VSS VSS B24
GND [PAGE_TITLE=ICH 6 OF 6 - GROUND]
6 of 6 DRAWING
D915PLWDL_FABA.SCH_1.42 INTEL DOCUMENT NUMBER PAGE REV
IC Wed Apr 06 22:21:16 2005
CONFIDENTIAL D16704 42 1.00
8 7 6 5 4 3 2 1
CR-43 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE43
8 7 6 5 4 3 2 1
1 R8H18
1
R8H7 R7H7
1
1 OUT 39
1
402 5%
2
8 7 6 5 4 3 2 1
CR-44 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE44
8 7 6 5 4 3 2 1
DESIGN NOTE:
SERIES RESISTORS INTEGRATED INTO ICH: 39 IN ICH_IDE_DD<15..0>
VALUES VARY BETWEEN 18.7 OHMS - 30.2 OHMS
2 R1J7 1 IDE_PRI_RST_R
33 5%
402 CH BOM NOTE:
D J6J1
VCC3 DEFAULT IS BLACK IDE HDR. D
2X20HDR_20
74 IN IDE_RST* 1 2
R8H9 7 3 4 8 PRIMARY IDE FOR WHITE IDE HDR,
2 1 6 5 6 9 USE IPN A22253-001
5 7 8 10 CONNECTOR
4.7K 5%
402 CH 4 9 10 11
39 OUT ICH_IDE_DDREQ 3 11 12 12
2 13 14 13
ICH_IDE_DIOW* 1 15 16 14
39 IN 0 17 18 15
19
39 IN ICH_IDE_DIOR* 21 22
23 24
ICH_IDE_IORDY 25 26
39 OUT 27 28
29 30
R8H10 39 IN ICH_IDE_DDACK* 31 32 TP_IDE_PRI_32
2 1 33 34 GPIO_DMA66_DETECT_PRI OUT 72
8.2K 5% ICH_IDE_IRQ 35 36
402 CH 39 OUT 37 38
39 40
39 IN
ICH_IDE_DA<1>
C HDR IDE_PRI_ACT* C
39 IN ICH_IDE_DA<0> OUT 74
C8J3 2 R8J3 1
39 IN ICH_IDE_DCS1* 1 .047UF
20% 15K 5%
402 CH
ICH_IDE_DCS3* 50V
39 IN
2 EMPTY
ICH_IDE_DA<2> 603
39 IN
"X7R" (+/- 10%)
CAD NOTE:
PLACE CLOSE TO CONNECTOR PIN
B B
A A
DESIGN NOTE:
DATA LINES SHOULD BE MATCHED TO STROBES (XDIOR*, XIORDY*) WITHIN +/-250MIL
STROBES SHOULD BE MATCHED TO THEIR COMPLEMENT WITHIN +/-10MIL
[PAGE_TITLE=IDE_SOUTH_BRIDGE]
DRAWING
D915PLWDL_FABA.SCH_1.44 INTEL DOCUMENT NUMBER PAGE REV
PCI IDE
Wed Apr 06 22:21:16 2005
CONFIDENTIAL D16704 44 1.00
8 7 6 5 4 3 2 1
CR-45 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE45
8 7 6 5 4 3 2 1
CAD NOTE:
OVERLAPPING FOOTPRINTS
DO NOT CHANGE TO 402
DOUBLE STACK USB
D
R5A6
1 2 J5A2
VREG_USB_BP_RIGHT 2 X USB D
0 1A 91 IN
603 CH L5B3
90OHM USB_BACK4_R* 1 9
IND 4PIN 45 2
BI USB_BACK4_R 3
100 38 BI USB_BACK3* 1 4 USB_BACK3_R* BI 45
45 BI 4 10
5 11
100 38 BI USB_BACK3 2 3 USB_BACK3_R BI 45 USB_BACK3_R* 6
45 BI
45 BI USB_BACK3_R 7
R5A7 752402-009EMPTY 8 12
1 2
CONN
0 1A
603 CH
R5A8
1 2
0 1A
603 CH
L5B4
C 90OHM C
IND 4PIN
100 38 BI USB_BACK4* 1 4 USB_BACK4_R* BI 45
B B
A A
[PAGE_TITLE=USB_BACKPANEL_CONN]
DRAWING
D915PLWDL_FABA.SCH_1.45 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 17:12:06 2005
CONFIDENTIAL D16704 45 1.00
8 7 6 5 4 3 2 1
CR-46 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE46
8 7 6 5 4 3 2 1
D
D
USB_FRONT3 1 4 7 8 2 3 USB_FRONT4
38 BI 10 USB_OC_FRONT34 BI 38
IND 4PIN
752402-009 HDR 752402-009
R9H13
1 2
R9H15 1
1 2
C9H7
470PF
0
603
1A
CH
0 1A 10%
603 CH 2
50V
X7R DO NOT CHANGE TO 402
DO NOT CHANGE TO 402 603
STUFF FOR
OPT-P10-GND
B 1 R9H16 2 1 R9J1 B
0 FRONT PANEL
0 1A 5%
805 EMPTY 2 EMPTY SUPPORT
402
STUFF FOR
FUSE ON
FRONT PANEL
SUPPORT
STUFF FOR
FUSE ON MB
FRONT PANEL
SUPPORT
A A
[PAGE_TITLE=USB_FP #2 HEADER]
DRAWING
D915PLWDL_FABA.SCH_1.46 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:16 2005
CONFIDENTIAL D16704 46 1.00
8 7 6 5 4 3 2 1
CR-47 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE47
8 7 6 5 4 3 2 1
1 R9J3 RT9G1
15K
5% 94 IN
5VDUAL 2 1 USB_FRONT12_PWR
OUT 48
2 CH THRMSTR 1 R9G24 1 C9H2
402 10K 470UF
1.50 5% 20%
2 CH 2 10V
USB_OC_FRONT12* OUT 38
1 R9G20 2
402 ALUM
RDL
0 1A
1 R9J2 805 EMPTY
BOM NOTE:
"202008-016"
10K
5% 1 R9G26 2
STUFF FOR CAD NOTE:
2 CH PRODUCT WITH FUSE
PLACE DECOUPLING AS CLOSE AS POSSIBLE
402 0 1A ON FRONT PANEL
C 805 EMPTY C
TO USB CONNECTOR
USB_OC_FRONT12_R*
48 IN
[PAGE_TITLE=USB_FP_HEADER_POWER]
DRAWING
D915PLWDL_FABA.SCH_1.47 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:16 2005
CONFIDENTIAL D16704 47 1.00
8 7 6 5 4 3 2 1
CR-48 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE48
8 7 6 5 4 3 2 1
D
D
L9G1 L9G2
90OHM J9G3 90OHM
IND 4PIN IND 4PIN
2X5HDR_9 USB_FRONT1*
USB_FRONT2* 2 3 4 1
38 BI 1 2 BI 38
USB_FRONT2_INDUCTOR* 3 4 USB_FRONT1_INDUCTOR*
USB_FRONT2_INDUCTOR 5 6 USB_FRONT1_INDUCTOR
USB_FRONT2 1 4 7 8 3 2 USB_FRONT1
38 BI 10 NET_USB_FNT_P10 BI 38
1
R9G12 2 R9G1
1
0 1A 0
805 EMPTY 5%
2 EMPTY
STUFF FOR 402 STUFF FOR CUSTOMER
FUSE ON FUSED (OPT-P10-GND)
FRONT PANEL FRONT PANEL
SUPPORT SUPPORT ONLY
R9G10
USB_FRONT12_PWR 1 2 USB_OC_FRONT12_R*
47 IN OUT 47
0 1A
805 CH
STUFF FOR
FUSE ON MB
A SUPPORT A
[PAGE_TITLE=USB_FP_HEADER #1]
DRAWING
D915PLWDL_FABA.SCH_1.48 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:16 2005
CONFIDENTIAL D16704 48 1.00
8 7 6 5 4 3 2 1
CR-49 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE49
8 7 6 5 4 3 2 1
A1 B1 .1UF 20%
A2
TRST* M12V_1
B2 100UF
.1UF 20%
25V 25V
P12V_1 TCK Y5V
A3 B3 20% 25V EMPTY 603
TMS GND1 603
A4 TDI TDO B4 TP_PCI1_B4 ELEC
RDL
A5 P5V_2 P5V_0 B5
37 54 53 50 OUT P_INTF* A6 INTA* P5V_1 B6
37 54 50 OUT P_INTH* A7 INTC* INTB* B7 P_INTG* OUT 50 53 54 37
A8 P5V_3 INTD* B8 P_INTE* OUT 50 54 37
TP_PCI1_A9 A9 RSVD1 PRST1* B9 TP_PCI1_B9
R8B11 A10 P5V_4 RSVD2 B10 TP_PCI1_B10
81 53 52 50 OUT SERIRQ 1 2 SERIRQ_PCI1 A11 RSVD3 PRST2* B11 TP_PCI1_B11
0 5% A12 GND10 GND2 B12
EMPTY
A13 GND16 GND3 B13
402 A14 3.3VAUX RSVD5 B14 TP_PCI1_B14
37 IN P_PCIRST* A15 RST* GND4 B15
A16 P5V_6 CLK B16 CK_P_33M_S1
IN 29
37 IN P_GNT1* A17 GNT* GND7 B17
C A18 GND5 REQ* B18 P_REQ1* OUT 54 37 C
57 53 52 50 37 OUT P_PME* A19 PME P5V_11 B19
30 A20 AD30 AD31 B20 31
VCC3 A21 P3_3V AD29 B21 29
28 A22 AD28 GND8 B22
26 A23 AD26 AD27 B23 27
A24 GND6 AD25 B24 25
24 A25 AD24 P3_3V B25
16 A26 IDSEL C_BE3* B26 3
A27 P3_3V AD23 B27 23
1 R8D3 1 R8D4 22 A28 AD22 GND12 B28
5.6K 5.6K 20 A29 AD20 AD21 B29 21
5% 5% A30 B30 19
2 CH 2 CH GND9 AD19
402 402 18 A31 AD18 P3_3V B31
16 A32 AD16 AD17 B32 17
A33 P3_3V C_BE2* B33 2
54 53 52 50 37 BI P_FRAME* A34 FRAME* GND14 B34
A35 GND13 IRDY* B35 P_IRDY* BI 37 50 52 53 54
54 53 52 50 37 BI P_TRDY* A36 TRDY* P3_3V B36
A37 GND22 DEVSL* B37 P_DEVSEL* BI 37 50 52 53 54
54 53 52 50 37 BI P_STOP* A38 STOP* GND15 B38
A39 P3_3V LOCK* B39 P_PLOCK* BI 37 50 52 53 54
I_SMB_CLK_RES A40 SMB_CLK PERR* B40 P_PERR* OUT 37 50 52 53 54
B I_SMB_DATA_RES A41 SMB_DAT P3_3V B41 B
A42 GND25 SERR* B42 P_SERR* OUT 37 50 52 53 54
53 52 50 37 BI P_PAR A43 PAR P3_3V B43
15 A44 AD15 C_BE1* B44 1
A45 P3_3V AD14 B45 14
13 A46 AD13 GND23 B46
11 A47 AD11 AD12 B47 12
A48 GND17 AD10 B48 10 RP8E1
R8D6 9 A49 AD09 GND24 B49 TP_RP8_1 1 8 TP_RP8_8
52 51 50 39 32 BI SMB_CLK_RESUME 1 2 2.7K 5%.063W
79 74 67 56 53 0 5% KEY A50 B50 KEY
402 EMPTY KEY A51 B51 KEY SM IC
R8D5 0 A52 C_BE0* AD08 B52 8
52 51 50 39 32 BI SMB_DATA_RESUME 1 2 A53 B53 7
56 79 74 67 53 0 5% P3_3V AD07
402 EMPTY 6 A54 AD06 P3_3V B54
4 A55 AD04 AD05 B55 5
VCC A56 GND21 AD03 B56 3 VCC
2 A57 AD02 GND19 B57
0 A58 AD00 AD01 B58 1
RP8E1 A59 B59 RP8E1
P5V_8 P5V_9
4 5 REQ64A* A60 REQ64* ACK64* B60 6 3
2.7K 5%.063W A61 P5V_12 P5V_5 B61 2.7K 5%.063W
SM IC A62 P5V_10 P5V_7 B62 SM IC
A
53 52 50 37 P_AD<31..0> NC=1,2 A
BI
53 52 50 37 BI P_C/BE<3..0>*
53 50 IN ACK64*
[PAGE_TITLE=PCI_CONN_1]
DRAWING DOCUMENT NUMBER PAGE REV
D915PLWDL_FABA.SCH_1.49 INTEL
Wed Apr 06 22:21:17 2005 CONFIDENTIAL D16704 49 1.00
8 7 6 5 4 3 2 1
CR-50 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE50
8 7 6 5 4 3 2 1
V_3P3_PCIVAUX
J8B1 C8B10
1 2
RDL
603
RDL D
A
53 52 49 37 P_AD<31..0> NC=1,2 732431-002 A
BI
53 52 49 37 BI P_C/BE<3..0>*
[PAGE_TITLE=PCI_CONN_2]
DRAWING
D915PLWDL_FABA.SCH_1.50 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:17 2005
CONFIDENTIAL D16704 50 1.00
8 7 6 5 4 3 2 1
CR-51 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE51
8 7 6 5 4 3 2 1
BOM NOTE:
USE C55845-001
FOR X1 CONN
+12V
KEY
TP_PCIE_RSVD_B12_1 B12 RSVD GND A12
B13 GND REFCLK+ A13 CK_PE_100M_X1_1 IN 30
38 IN HSO_P0_C B14 HSOP0 REFCLK- A14 CK_PE_100M_X1_1* IN 30
38 IN HSO_N0_C B15 HSON0 GND A15
B16 GND HSIP0 A16 HSI_P0 OUT 38
TP_PCIE_PRSNT_B16_1 B17 PRSNT2* HSIN0 A17 HSI_N0 OUT 38
B18 GND A18
B
1 OF 1 GND B
CONN
VCC3
A A
C9B16
1 2
.1UF 20%
25V
Y5V
603
[ TITLE=PCIE_X1_CONN_2]
DRAWING
D915PLWDL_FABA.SCH_1.51 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:17 2005
CONFIDENTIAL D16704 51 1.00
8 7 6 5 4 3 2 1
CR-52 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE52
8 7 6 5 4 3 2 1
PCI
(CLOSEST
SLOT
TO CPU)
3 VCC
C10B1
1 2
C11C1
1 2
C10D1
1
.1UF 20%
2
25V
.1UF 20% 470UF Y5V
25V 20% 10V 603
Y5V ALUM
D 603 RDL
VCC3 VCC +12V -12V VCC VCC3 D
J10B4 VCC VCC3 VCC3
C10D2
90 IN V_3P3_PCIVAUX PCI CONN2_2 CONN C11E1 C10C1 1 2
1 2 1 2
A
53 50 49 37 P_AD<31..0> NC=1,2 A
BI
53 50 49 37 BI P_C/BE<3..0>*
53 50 IN ACK64*
[PAGE_TITLE=PCI_CONN_1]
DRAWING
D915PLWDL_FABA.SCH_1.52 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 19:35:30 2005
CONFIDENTIAL D16704 52 1.00
8 7 6 5 4 3 2 1
CR-53 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE53
8 7 6 5 4 3 2 1
.1UF 20%
C11D1
1 2
V_3P3_PCIVAUX
J11B1 C11D3
1
RDL RDL D
.1UF 20%
25V VCC3
A1 TRST* M12V_1 B1
A2 P12V_1 TCK B2 EMPTY C11C2
A3 TMS GND1 B3 603 1 2
A4 TDI TDO B4
A5 P5V_2 P5V_0 B5 .1UF 20%
25V
37 54 52 OUT P_INTD* A6 INTA* P5V_1 B6 Y5V
37 54 50 49 P_INTF* A7 INTC* INTB* B7 P_INTC* 52 54 37
603
OUT A8 B8 P_INTG* OUT
P5V_3 INTD* OUT 49 50 54 37
R11B2 A9 RSVD1 PRST1* B9
A10 P5V_4 RSVD2 B10
81 52 50 49 SERIRQ 1 2 SERIRQ_PCI4 A11 RSVD3 PRST2* B11
OUT A12 B12 VCC3
0 5% GND10 GND2
402 EMPTY A13 GND16 GND3 B13 C11C3
A14 3.3VAUX RSVD5 B14
37 P_PCIRST* A15 RST* GND4 B15 1 2
IN A16 B16 CK_P_33M_S4
P5V_6 CLK IN 29
.1UF 20%
37 IN
P_GNT4* A17 GNT* GND7 B17 25V
C A18 GND5 REQ* B18 P_REQ4* OUT 54 37 EMPTY C
57 52 50 49 37 P_PME* A19 PME P5V_11 B19 603
OUT A20 B20
30 AD30 AD31 31
A21 P3_3V AD29 B21 29
28 A22 AD28 GND8 B22
26 A23 AD26 AD27 B23 27
A24 GND6 AD25 B24 25
24 A25 AD24 P3_3V B25
19 A26 IDSEL C_BE3* B26 3
A27 P3_3V AD23 B27 23
22 A28 AD22 GND12 B28
20 A29 AD20 AD21 B29 21
A30 GND9 AD19 B30 19
18 A31 AD18 P3_3V B31
16 A32 AD16 AD17 B32 17
A33 P3_3V C_BE2* B33 2
54 52 50 49 37 BI P_FRAME* A34 FRAME* GND14 B34
A35 GND13 IRDY* B35 P_IRDY* BI 37 49 50 52 54
54 52 50 49 37 BI P_TRDY* A36 TRDY* P3_3V B36
A37 GND22 DEVSL* B37 P_DEVSEL* BI 37 49 50 52 54
54 52 50 49 37 BI P_STOP* A38 STOP* GND15 B38
A39 P3_3V LOCK* B39 P_PLOCK* BI 37 49 50 52 54
79 74 67 56 52 51 50 49 39 32 BI SMB_CLK_RESUME A40 SMB_CLK PERR* B40 P_PERR* OUT 37 49 50 52 54
B SMB_DATA_RESUME A41 SMB_DAT P3_3V B41 B
56 79 74 67 52 51 50 49 39 32 BI A42 GND25 SERR* B42 P_SERR* OUT 37 49 50 52 54
52 50 49 37 BI P_PAR A43 PAR P3_3V B43
15 A44 AD15 C_BE1* B44 1
A45 P3_3V AD14 B45 14
13 A46 AD13 GND23 B46
11 A47 AD11 AD12 B47 12
A48 GND17 AD10 B48 10
9 A49 AD09 GND24 B49
KEY A50 B50 KEY
KEY A51 B51 KEY
0 A52 C_BE0* AD08 B52 8
A53 P3_3V AD07 B53 7
VCC 6 A54 AD06 P3_3V B54
4 A55 AD04 AD05 B55 5
A56 GND21 AD03 B56 3
2 A57 AD02 GND19 B57
0 A58 AD00 AD01 B58 1
A59 P5V_8 P5V_9 B59
1 R10E4 2 REQ64B* A60 REQ64* ACK64* B60 ACK64* OUT 50 49 52
2.7K 5% A61 P5V_12 P5V_5 B61
603 CH A62 P5V_10 P5V_7 B62
A
52 50 49 37 P_AD<31..0> NC=1,2 732431-002 A
BI
52 50 49 37 BI P_C/BE<3..0>*
[PAGE_TITLE=PCI_CONN_2]
DRAWING
D915PLWDL_FABA.SCH_1.53 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 17:11:05 2005
CONFIDENTIAL D16704 53 1.00
8 7 6 5 4 3 2 1
CR-54 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE54
8 7 6 5 4 3 2 1
VCC
PCI PULL-UPS
53 52 50 49 37 P_SERR* 1 R9D8 2
OUT
2.7K 5%
402 CH
D
P_DEVSEL* 1 R9D4 2 D
53 52 50 49 37 OUT
2.7K 5%
402 CH
53 52 50 49 37 P_IRDY* 1 R9D2 2
OUT
2.7K 5%
402 CH
53 52 50 49 37 P_PLOCK* 1 R9D6 2
OUT
2.7K 5%
402 CH
53 52 50 49 37 P_PERR* 1 R9D7 2
OUT
2.7K 5%
402 CH
C C
53 52 50 49 37 P_FRAME* 1 R9D1 2
OUT
2.7K 5%
402 CH
53 52 50 49 37 P_TRDY* 1 R9D3 2
OUT
2.7K 5%
53 52 50 49 37 P_STOP* 1 R9D5 2 402 CH
OUT
2.7K 5%
402 CH
RP8C1
37 53 OUT P_REQ4* 1 8
2.7K 5% .063W
SM IC
RP8C1
37 52 OUT P_REQ3* 2 7
2.7K 5% .063W
SM IC
RP8C1
B P_REQ2* 4 5 B
37 50 OUT
2.7K 5% .063W
SM IC
RP8C1
37 49 OUT P_REQ1* 3 6
2.7K 5% .063W
SM IC
P_REQ0* 1 R8E1 2
37 OUT
2.7K 5%
402 CH
37 P_REQ6* 1 R8E3 2
OUT
2.7K 5%
402 CH
VCC3 37 P_REQ5* 1 R8E2 2
OUT
2.7K 5%
RP9C1 402 CH
37 52 OUT P_INTA* 8 1
8.2K 5% .063W
RP9C1 SM IC
37 52 OUT P_INTB* 6 3
8.2K 5% .063W
SM IC RP9C1
A P_INTC* 7 2 A
37 53 52 OUT
RP9C1 8.2K 5%.063W
SM IC
37 53 52 OUT P_INTD* 5 4
8.2K 5% .063W
SM IC
RP8B2
37 50 49 OUT P_INTE* 4 5
RP8B2
8.2K 5% .063W
SM IC
37 53 50 49 OUT P_INTF* 2 7
8.2K 5% .063W
SM IC RP8B2
37 53 50 49 OUT P_INTG* 3 6
8.2K 5% .063W
RP8B2 SM IC
37 50 49 OUT P_INTH* 1 8
8.2K 5% .063W DRAWING
SM IC
D915PLWDL_FABA.SCH_1.54 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:18 2005
[MODULE=ICH] [PAGE_TITLE=ICH_PCI_TERMINATION] CONFIDENTIAL D16704 54 1.00
8 7 6 5 4 3 2 1
CR-55 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE55
8 7 6 5 4 3 2 1
LAN_DISABLE*
74 73 IN
1 C8B4
.1UF
20%
16V
2 EMPTY
D
402 BOM NOTE:
D
EMPTY FOR EKRON R
37 IN PLTRST*
1
C8A19
.1UF BOM NOTE:
20%
16V
2 EMPTY EMPTY FOR EKRON R
402
C R8B6
C
74 73 IN LAN_DISABLE* 1 2 LAN_DISABLE_NC* OUT 55 56
1K 5%
402 EMPTY
BOM NOTE:
EMPTY FOR EKRON R
V_3P3_STBY\G
IN 92
1
1
R2J18 R2H8
5.1K
5% 5.1K
5%
EMPTY
402 EMPTY LAN_DISABLE*
402 IN 73 74
2
LAN_DISABLE_NC* 2
56 55 OUT
A V_3P3_STB_R_R A
Q2J1
2
BOM NOTE 402 MBT3904DUAL 3 6
CH
STUFF OPTION B FOR LAN DISABLE
R2H7 5 2 R2H9
5% 1 2 V3P3_STB_RR LAN_DISABLE#_R 1 2
0
R2J20 2.2K 5% 2.2K 5% 2
402 EMPTY 402 EMPTY 402 DRAWING
1 4 1 EMPTY CH
LAN_OR_FAN* 5%
D915PLWDL_FABA.SCH_1.55
73 OUT 0 BOM NOTE Thu Apr 07 15:10:17 2005
R2J21 STUFF OPTION B FOR LAN DISABLE
1
8 7 6 5 4 3 2 1
CR-56 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE56
8 7 6 5 4 3 2 1
U8A1
NORTHWAY
REV=3.0
TP_NWY_D1 D1 PE_TXP MDI_0P C13 LAN_MDI0_P
BI 59
TP_NWY_C1 C1 PE_TXN MDI_0N C14 LAN_MDI0_N BI 59
TP_NWY_G1 G1 PE_RXP MDI_1P E13 LAN_MDI1_P BI 59
TP_NWY_F1 F1 PE_RXN MDI_1N E14 LAN_MDI1_N
BI 59
D MDI_2P F13 LAN_MDI2_P
BI 59
CK_PE_100M_LAN J1 PE_CLKP MDI_2N F14 LAN_MDI2_N D
30 BI BI 59
30 BI CK_PE_100M_LAN* H1 PE_CLKN MDI_3P H13 LAN_MDI3_P BI 59
MDI_3N H14 LAN_MDI3_N BI 59
90 IN V_3P3_PCIVAUX 40 67 51 43 32 OUT WAKE* P10 PE_WAKE*
37 IN PLTRST* P7 PE_RST* XTAL_1 K14 LAN_X1
IN 58
1 XTAL_2 J14 LAN_X2 OUT 58
BOM NOTE: R8B5 74 67 53 52 51 50 49 39
79
32 IN SMB_DATA_RESUME
SMB_CLK_RESUME
M11
P11
SMB_DATA
SMB_CLK LED_1* C11 LAN_LED_ACT
1K 53 52 51 50 49 39 32 BI BI 59
5% 79 74 67 56 IN SMB_ALERT_LAN_PU N11 SMB_ALRT* LED_0* B11 LAN_LED_10
BI 59
EMPTY FOR EKRON R EMPTY LED_2* A12 LAN_LED_100
BI 59
402 TP_NWY_M8 M8 FLB_SD LED_3* A10 LAN_LED_1000
BI 59
2 TP_NWY_M9 M9 FLB_INTEX
56 OUT LAN_NW_CE* VCC33 N2 V_3P3_PCIVAUX
IN 90
58 OUT LAN_NW_EEDI
LAN_NW_EEDO
A9
B9
EEDI VCC33 P2
P3 LAN_1P0_CTRL
BOM NOTE:
58 IN EED0 CTRL_1P0 OUT 58
58 OUT LAN_NW_EECS* B10 EECS* VSS N3 EMPTY FOR EKRON R
58 OUT LAN_NW_EESK C9 EESK CTRL_1P8 M1 LAN_1P8_CTRL
OUT 58
VSS N1
56 OUT LAN_NW_S0 P13
56 OUT FLSH_S0
1 R7A23 2 N13 FLSH_CE* RCMP_PEN J2 LAN_NW_RCMP_0N
LAN_NW_SI M12 FLSH_SI J3 LAN_NW_RCMP_0P 1 R8A16 2
56 OUT RCMP_PEP 1 R7A2 2
1.4K 1% LAN_NW_SK M13 FLSH_SK
402 EMPTY 56 IN 1.4K 1%
C BOM NOTE: RBIASP B12 LAN_NW_RBIAS 402 EMPTY 1.4K
402
0.1%
EMPTY C
MANUALLY STUFF FOR EXPERIMENTS 56 IN LAN_NW_ATEST_2P L14 RSVD RBIASN D11 LAN_NW_RBIAS_VSS
56 IN LAN_NW_ATEST_2N L13 RSVD
TEST A13 LAN_NW_STRAP1
N14 D10
56 IN
LAN_NW_RCMP_1N
LAN_NW_RCMP_1P M14
RSVD
RSVD
NC
NC D12
LAN_NW_STRAP2
LAN_NW_STRAP3 R7A6 BOM NOTE:
NC D14 LAN_NW_STRAP4 1 2
LAN_NW_ATEST_0P B14 N10 TP_NWY_N10 STUFF 220 OHMS FOR EKRON R/R+
56 IN IEEE_TEST_P RSVD 220 5%
LAN_NW_ATEST_0N B13 IEEE_TEST* RSVD N9 TP_NWY_N9 V_3P3_PCIVAUX 402 CH
M10 IN 90
RSVD TP_NWY_M10
LAN_NW_ATEST_3P L1 RSVD RSVD P9 TP_NWY_P9 1 R8A13 2
DB7A2 LAN_NW_ATEST_3N K1 RSVD RSVD M7 TP_NWY_M7
EMPTY RSVD C5 TP_NWY_C5 1K 5%
56 IN
90 V_3P3_PCIVAUX 1 R8A3 2 LAN_NW_AUXPWR C6 AUX_PRSNT RSVD C4 TP_NWY_C4
603 CH
R7A11 BOM NOTE:
IN
1K 5% LAN_DISABLE_R* A5 LAN_DSBL* RSVD N7 TP_NWY_N7 1 2 STUFF FOR EKRON R
402 EMPTY TP_ICH_RSMRST_R* P5 LAN_PWRGD 1 R8B3 2
BOM NOTE: TP_LAN_DEV_DISABLE* A6 DEV_DISBL* JTDI P4 TP_NWY_P4
220
402
5%
EMPTY
JTDO P6 TP_NWY_P6 1K 5% R7A10
I110 603 CH LAN_KIN_CNTRL
LAN_NW_STRAP_RR
B6 N4 IN 55
EMPTY FOR EKRON R
TP_NWY_B6 RSVD JTMS TP_NWY_N4 1 2
DB7A1 DB8A2 DB8A1 TP_NWY_B5 B5 RSVD JTCK N5 LAN_NWY_N5 220
EMPTY EMPTY EMPTY 5% 2
TP_NWY_B4 B4 RSVD 402 CH 402
TP_NWY_A4 A4 RSVD DEV_OFF* L7 LAN_DISABLE_NC* R7A8 BOM NOTE:
IN 55 EMPTY
C3 EMPTY FOR EKRON R
TP_NWY_C3 RSVD 1 2 5%
B LAN_NW_A2 A2 RSVD T_TESTP L3 TP_NWY_L3 0 B
220 5%
TP_NWY_A8 A8 SDP0_0 T_TESTN L2 TP_NWY_L2 402 CH R7A21
CAD NOTE: TP_NWY_B8 B8 SDP0_1 R7A9
DEBUG PAD TRACES NEED TO BE ROUTED LIKE THE 1
R8A5 TP_NWY_C8 C8 SDP0_2 RSVD_GND M5 1 2
MDI LINE GOING TO THE RJ45 CONNECTOR
90 IN V_3P3_PCIVAUX 1 2 TP_NWY_C7 C7 SDP0_3 RSVD_GND M4 220 5%
0 5% 402 EMPTY 1 2
V_3P3_STBY\G
B1 IN 92
I92 402 EMPTY TP_NWY_B1 RSVD BOM NOTE:
0 R7A20 5%
40 OUT
ICH_LAN_JRX0 LAN_NW_S0
IN 56 TP_NWY_B2 B2 RSVD 1 of 2 FOR EKRON MODE1
402 CH
R8A2 STUFF R7A10,R7A8
1 2 IC EMPTY R7A11,R7A9 BOM NOTE:
I93 0 1A STUFF FOR EKRON R
ICH_LAN_JRX1 LAN_NW_CE* 603 EMPTY
40 OUT IN 56
BOM NOTE:
STUFF FOR NWY
I94 EMPTY FOR KINNERETH R8A17 BOM NOTE:
40 ICH_LAN_JRX2 LAN_NW_SI 56 1 2
OUT IN
1 R8A19 2 1K 5% EMPTY FOR EKRON R
SMB_ALERT_LAN_PU 56 402 EMPTY
VCC3 OUT
R7A26 1K 5%
40 ICH_LAN_JRST 1 2 LAN_NW_SK 56 402 EMPTY
IN OUT
0 5%
402 CH
R7A3
1 2 LAN_NW_ATEST_0P 56
R7B1 OUT
ICH_LAN_JTX2 1 2 LAN_NW_ATEST_2P 619 1%
40 IN OUT 56 CH
A 402 A
0 5%
402 CH R7A4
R7A25 1 2 LAN_NW_ATEST_0N OUT 56
40 IN ICH_LAN_JTX1 1 2 LAN_NW_ATEST_2N OUT 56 649 1%
0 5% 402 CH
402 CH IPN A93548-011 BOM NOTE:
R7A22 STUFF FOR EKRON R
40 OUT ICH_LAN_JCLK 1 2 LAN_NW_RCMP_1N IN 56
22 5%
402 CH
R7A24
40 IN ICH_LAN_JTX0 1 2 LAN_NW_RCMP_1P OUT 56
0 5% DEFAULT LAN IS EKRON R
402 CH
8 7 6 5 4 3 2 1
CR-57 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE57
8 7 6 5 4 3 2 1
NC L8
NC M2
NC M3
A A
2 of 2
IC
8 7 6 5 4 3 2 1
CR-58 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE58
8 7 6 5 4 3 2 1
402 IN SO 2
1K 5%
1 C8B1 1 1
4.7UF 1 C8A18 C8A5 EMPTY
20% C7A11 .1UF 4.7UF C14313-001
Y5V 1000PF 20% 20% 56 LAN_NW_EEDO
2 10% 16V 10V OUT
4 2 10V
2 50V 2 Y5V 2 Y5V
Q8A1 805 X7R 402 805
LAN_1P8_CTRL 1
PBSS5540Z
402
56 IN EMPTY
3
90 IN V_3P3_PCIVAUX
1
C7A1
1 C7A2
C 1 1 C
C8B2 C8A20 .1UF 1UF
4.7UF .1UF 20% 20%
20% 20% 16V 6.3V BOM NOTE:
10V 16V
2 Y5V 2 EMPTY
2 EMPTY 2 EMPTY 402 603
805 402 EMPTY FOR EKRON R
U8F1
AT93C46A
BOM NOTE: 1 C7A16 2 40 OUT ICH_EE_DIN
IN ICH_EE_DOUT 3 DI
1UF 20% 40 ICH_EE_CS 1 CS DO 4
EMPTY FOR EKRON R 6.3V 40
IN
ICH_EE_CLK 2 SK
IN 6
402 ORG TP_EEPROM_6
VCC=8 IC
2
4 GND=5 109868-001
56 LAN_1P0_CTRL 1 Q7A1 NC=7
IN PBSS5540Z VCC=V_3P3_STBY
LAN_V_1P0 58 57
B
3 OUT
PLACEHOLDER: ICH/EKRON R EEPROM B
90 IN V_3P3_PCIVAUX
BOM NOTE:
1 1
C7A18 C6A3
4.7UF .1UF STUFF FOR EKRON R
20% 20%
10V 16V
2 2
805 402
LAN_X1 OUT 56 LAN CRYSTAL
C7A12
1 2
Y7B1 22PF 5%
25.000MHZ 50V
1 2 NPO
LAN DECOUPLING 603
0603 REQUIREMENT PER DESIGN ENGINEER SM C7A13
XTAL 1 2
90 V_3P3_PCIVAUX
BOM NOTE: IN LAN_X2 22PF 5%
56 IN 50V
NPO
STUFF FOR EKRON R 603
1 1 1 1 1 1 1 1 C8A9 1
C8A2 C7A6 C7A10 C7A8 C7A14 C7A9 C8A1 4.7UF C8A13
4.7UF 4.7UF 4.7UF .1UF .1UF .1UF 1000PF .1UF
20% 20% 20% 20% 20% 20% 10% 20% 20%
10V 10V 10V 16V 16V 16V 50V BOM NOTE: 10V 16V
2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 EMPTY 2 Y5V 2 Y5V
805 805 805 402 402 402 402 805 402
EMPTY FOR EKRON R
8 7 6 5 4 3 2 1
CR-59 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CR-60 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE60
8 7 6 5 4 3 2 1
D U9A1 ALC880
PORT C
JACKDR 36 AUD_PORT_D_R BI 63 64
62
62
IN
IN
AUD_CD_IN_L
AUD_CD_GND
18
19
CDL
CDGND JACKEL 14 AUD_PORT_E_L BI 62 64
DESIGN NOTE:
C
62 IN AUD_CD_IN_R 20 CDR JACKER 15 AUD_PORT_E_R BI 62 64 AZALIA:
CMEDIA: CMI9880
C
JACKHR 46 AUD_PORT_H_R BI 61 65
VCC3
1 DVDD1 DVSS1 4
A 9 DVDD2 DVSS2 7 A
49 NC
VCC3
C49087-001 IC
R9B10
1 2 VDD_IO_CODEC OUT 60 CK_14M_AUD
29 IN
0 5%
402 EMPTY
1
C9B1 2 R9B2
1 2 VSS_CLOCK_CODEC OUT 60
0 5%
R9B18
0
402
1
5%
2
EMPTY
5.6PF
"COG"
50V
EMPTY
402
9% 402
0
1
EMPTY
R9B3
2
5% DRAWING
AUDIO CODEC
DOCUMENT NUMBER PAGE REV
402 EMPTY D915PLWDL_FABA.SCH_1.60 INTEL
Wed Apr 06 22:28:59 2005
CONFIDENTIAL D16704 60 1.00
8 7 6 5 4 3 2 1
CR-61 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE61
8 7 6 5 4 3 2 1
CAD NOTE: 61 60
60
IN
IN
AUD_VREF_28
AUD_VREF_29 66 61 IN V_5P0_AUD_ANALOG
R9A25
PLACE NEAR ICH PINS 60 IN AUD_VREF_30
61 60 IN AUD_VREF_31 1 2
R9B12 10K 5%
1 1 1 1 402 EMPTY
D AUD_LINK_SDI2_R AUD_LINK_SDI2 C9A10 C9A11 C9A12 C9A13
60 1 2 40 1UF 1000PF 1000PF 1UF
IN
33 5%
OUT 20% 10% 10% 20% R9A34 D
402 CH 2
6.3V
EMPTY 2
6.3V
EMPTY 2 6.3V
EMPTY 2
6.3V
EMPTY 64 63 OUT AUD_SENSE_B 1 2 AUD_CDC_SENSE_B IN 60
402 402 402 402 C9A3 0 5%
1 2 402 CH
BOM NOTE: 4.7UF 20%
CHANGE TO 820PF 10V
FOR SIGMATEL. AUD AUD 805
EMPTY
64 60 AUD_VREF_32 "Y5V"
IN FRONT PANEL NEED TO CHANGE TO 5K
61 60 IN AUD_VREF_33
61 60 IN AUD_VREF_37 JACK SENSE NETWORK
61 60 IN AUD_VREF_40
R9A45
AUD_VREF_33 1 1 1 1
66 61 IN
V_5P0_AUD_ANALOG 1 2
OUT 60 61 C9A24 C9A19 C9A8 C9A9
5% 64 65 1UF 1UF 1UF 1UF
4.7K 20% 20% 20% 20% V_5P0_AUD_ANALOG
402 EMPTY 6.3V 6.3V 6.3V 6.3V 66 61 IN
2 2 2 2
EMPTY
402
EMPTY
402
EMPTY
402
EMPTY
402 R9A44
R9A48 1 2
1 2 AUD_VREF_40 OUT 60 61 10K 5%
4.7K 5% AUD
402 EMPTY
402 EMPTY
C R9B11 C
R9A50 63 OUT AUD_SENSE_A 1 2 AUD_CDC_SENSE_A IN 60 62
1 2 C8B5 2 0 5%
20K
402
1%
CH CAD NOTE: 1
4.7UF 20%
402 CH
0
1 2
5%
AUD_VREF_31 OUT 60 61 65
2 6.3V
X5R
805
2 6.3V
X5R
402 DECOUPLING AND
63 IN AUD_JS_C
402 EMPTY
0
R9A43
1
5%
2 AUD_PORT_F_L
OUT 60 64
VCC3
AUD
JACK SENSE
402 EMPTY R9A47 DIGITAL SUPPLY 1 2 3 4 RP9F1
1 2 AUD_VREF_40 1 1 1 0
0 5%
OUT 60 61 C9B6
.1UF
C9B2
.1UF
C9B4
.1UF
CAD NOTE: 5%
.063W
R9A36 402 EMPTY 10%
6.3V
10%
6.3V
10%
6.3V
PLACE ONE NEAR DRAWING EMPTY
63 IN AUD_JS_D 1 2 AUD_PORT_F_R 2 X5R 2 X5R 2 X5R SM
OUT 60 64 402 402 402 PINS 1, 3, 9 D915PLWDL_FABA.SCH_1.61 8 7 6 5
0 5% Thu Apr 07 09:23:42 2005
402 EMPTY
R9A11
1 2 AUD_FP_RET_R OUT 64 63
INTEL DOCUMENT NUMBER PAGE REV
402
0 5%
EMPTY SUPPLY DECOUPLING CONFIDENTIAL D16704 61 1.00
8 7 6 5 4 3 2 1
CR-62 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE62
8 7 6 5 4 3 2 1
D
C8A17 R8B4 D
60 AUD_CD_IN_L 2 1 AUD_CD_IN_L_PN1 1 2
OUT
EMPTY 1UF 20% 4.7K 5%
402 EMPTY
6.3V
603 R9B19 J9C11X4HDR
CD IN
1 2
C8B6
60 OUT AUD_CD_GND 2 1 AUD_CD_GND_PN1
4.7K
402
5%
EMPTY
AUD_CD_IN_L_HDR
AUD_CD_GND_HDR
1
2 ATAPI HEADER
3
EMPTY 1UF 20%
6.3V R9B22 AUD_CD_IN_R_HDR 4
1 2
603 4.7K 5% EMPTY
402 EMPTY BLACK
C8A15 R9B20 VCC3
AUD_CD_IN_R 2 1 AUD_CD_IN_R_PN1 1 2
60 OUT
1UF 20% 4.7K 5%
EMPTY 6.3V 1 R9B17 1 R8B9 1 R9B21 1 R8B1 402 EMPTY
B 402 402 B
10K
402
5% 2 J8B2
EMPTY 1X3HDR
STAC R9B24 1 V_5P0_AUD_ANALOG 61 66
IN
1 2 2
10K 5% 3
402 CH
EMPTY
R9B38
SPDIF
AUD_PORT_A_R 603 R9B9 R9B4
1 2 4.7K 4.7K
64 60 OUT 5% 5%
0 5%
EMPTY EMPTY
402 EMPTY
402 402
2 2
DRAWING
D915PLWDL_FABA.SCH_1.62 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 09:25:10 2005
CONFIDENTIAL D16704 62 1.00
8 7 6 5 4 3 2 1
CR-63 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE63
8 7 6 5 4 3 2 1
402
0 5%
CH
4.7UF
6.3V
X5R
20% R8A1
MULTI
600 FB C4A10
2 1
LINE IN
1 2 0.2A
805 BROAD 220PF 10%
10K 5% 50V AUD_JACK_GND OUT 63 66
402 CH X7R
402
R9A27 C9A5 2 AUD_SENSE_B R8A10 C4A15
1 2 NET_AUD_SENSE_B 1 61 64 2 1
BI
4.7K 5% 1 2
402 1UF 20% 220PF 10%
EMPTY 6.3V 10K 5% 50V 61 OUT AUD_JS_D J4A1
EMPTY 402 CH X7R
C 603 402 3 STACK AUDIOJACK_SW C
DESIGN NOTE: 22
KEEP AS 100UF BROAD
600 25
1 R4B3 2
AUDIO 0.2A R4A10
AUD_FP_RET_R
64 61 IN C4B1 M4A6 1 2 23
0 5% AUD_FP_RET_R_R 1 2 AUD_PORT_LINE_R_D
BI 63 65 65 63 BI AUD_PORT_LINE_R_D 1 2 AUD_R_LINEOUT_D 5.11K 1%
402 EMPTY MULTI CH 24
402
64 60 AUD_PORT_D_R 1 R4B4 2 100UF 20% FB AUD_SENSE_A
BI 6.3V
1 MIDDLE
0 5% ALUM 202008-250
402 CH TH 61 IN
1 R4A21 2
AUDIO JACK
AUD_PORT_D_L
BI 0 5% C4B2 M4A5
402 CH AUD_PORT_D_L_R 1 2 AUD_PORT_LINE_L_D
AUD_PORT_LINE_L_D 1 2 AUD_L_LINEOUT_D
1
R4A11
2
FB C4A11
2 1
220PF 10%
50V
MIC
10K 5% X7R
402 CH 402 AUD_JACK_GND OUT 63 66
A C4A14
2 1
A
R4A16
1 2 220PF 10%
50V
10K 5% X7R
402 CH 402
8 7 6 5 4 3 2 1
CR-64 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE64
8 7 6 5 4 3 2 1
D C9B13
D
62 60 AUD_PORT_E_R 1 R8A18 2 AUD_PORT_1_R_SPLIT 1 2 AUD_PORT_1_R_HDR 64 65
BI BI
5% 0 20%
CH 402 100UF
6.3V 202008-250
2 R9A51
ALUM 1
TH 40 43 OUT FP_AUD_DETECT
AUD_PORT_F_R 1 R9A39 2
64 61 60 BI 0 5%
EMPTY 0 402 CH
402
5%
63 60 AUD_PORT_B_R 1 R9A41 2
BI
5% 4.7K
EMPTY 402
1 R9A46 2
AUD_CDC_SENSE_B 66 61 IN V_5P0_AUD_ANALOG
1 R9A37 2 0 5%
60 IN 402
5% 0 EMPTY
402
EMPTY
C C
J8A2
2X5HDR_8
65 64 AUD_PORT_1_L_HDR 1 2
C9A2 BI AUD_PORT_1_R_HDR 3 4 AUD AUD_FP_PWR IN
65 64 BI 63
1 R8A20 2 1 2 AUD_PORT_1_L_HDR AUD_PORT_2_R_HDR 5 6 AUD_FP_RET_R
62 60 BI AUD_PORT_E_L AUD_PORT_1_L_SPLIT
BI 64 65
65 64 BI AUD_SENSE_B 7
OUT 61 63 64
63 61 IN
5% 0 65 64 AUD_PORT_2_L_HDR 9 10 AUD_FP_RET_L 63 64
CH 402 100UF 20% BI OUT
6.3V 1
R8B10 1 1
AUD_PORT_F_L 1 R9B27 2 R9A21 HDR C9A22
64 61 60 BI ALUM 202008-250 1 2 R9A16
109717-755 .1UF
5% 0 TH 47K 5%
20K 39.2K 20%
EMPTY 402 1% 1% 16V
402 CH
CH CH
2 Y5V
402
65 61 60 AUD_VREF_32 1 R8B2 2
R9A2 2
402
2
402
BI 1
5% 0 2
EMPTY 402 47K 5%
R8B8 402 CH
1 2 AUD AUD AUD
R9B29 2 47K 5%
61 60 IN AUD_VREF_33 1
402 CH
EMPTY 0 1
R9A28
2 BOM NOTE:
B 402 USE IPN 109717-755 FOR YELLOW HDR B
5% 47K 5%
C10A3 402 CH
USE IPN 109717-205 FOR BLACK HDR
63 60 AUD_PORT_D_R 1 R9A33 2 AUD_PORT_2_R_SPLIT 1 2 AUD_PORT_2_R_HDR 64 65
BI BI
EMPTY 0
402 100UF 20% 65 64 BI AUD_PORT_1_L_HDR
5%
6.3V AUD_PORT_1_R_HDR
62 60 AUD_PORT_A_R 1 R9A40 2 ALUM
65 64 BI
AUD_PORT_2_R_HDR
BI 65 64 BI
EMPTY 0 TH 63 61 AUD_SENSE_B
5% 402 IN
202008-250 65 64 BI AUD_PORT_2_L_HDR
64 61 IN AUD_FP_RET_R
64 61 60 AUD_PORT_F_R 1 R9A38 2 64 IN AUD_FP_RET_L
BI
5% 0 1 1 1
CH 402 1
C8A11 1
C9B10 1
C9B8 M9B9 C9B11 C8B3 1
C8B7
220PF 220PF 220PF
220PF 220PF 220PF 10% 10% 10% 220PF
10% 10% 10% 50V 50V 50V 10%
2 50V
2 50V
2 50V 2 EMPTY 2 EMPTY 2 EMPTY 2 50V
EMPTY EMPTY EMPTY 402 402 402 EMPTY
402 402 402 402
C10A4
A 63 60 BI AUD_PORT_D_L R9A19 2
1 AUD_PORT_2_L_SPLIT 1 2 AUD_PORT_2_L_HDR A
BI 64 65
5% 0
EMPTY 402 100UF 20%
6.3V
62 60 BI AUD_PORT_A_L 1
EMPTY
R9B25 2
5% 0
402
ALUM
TH 202008-250 AC HEADER
64 61 60 BI AUD_PORT_F_L 1 R9B26 2
FRONT PANEL PORTS
5%
CH
0
402
DRAWING
D915PLWDL_FABA.SCH_1.64 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 16:14:07 2005
CONFIDENTIAL D16704 64 1.00
8 7 6 5 4 3 2 1
CR-65 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE65
8 7 6 5 4 3 2 1
D
3 STACK 1 FRONT PANEL
D
R9A4
60 IN AUD_PORT_G_R 1 2
R9A8 4.7K 5%
61 60 IN AUD_PORT_H_L 1 2 402 EMPTY
4.7K 5%
402 EMPTY R9A14
61 60 IN AUD_VREF_31 1 2
R9A3
61 60 AUD_VREF_37 1 2 0 5%
IN EMPTY FOR AC97 402 CH
1.2K 5% CR9A1
402 CH
R9A1 AUD_PORT_1_R_HDR
5 AUD_PORT_1_R_DIODE 1 2 64
CR8B1 OUT
R8A9 R9A9 1.2K 5%
1 1
AUD_LINE_IN_R_DIODE 2 AUD_PORT_LINE_R_C
OUT 63 61 60 IN AUD_VREF_37 1 2 3 402 CH
R8A12 2.2K 5% 0 5% R9A7
60 IN AUD_VREF_29 1 2 3 402 EMPTY 402 EMPTY 4 AUD_PORT_1_L_DIODE 1 2 AUD_PORT_1_L_HDR
OUT 64
0 5% R8B7 BAW56S 1.2K 5%
402 CH 2 AUD_LINE_IN_L_DIODE 1 2 AUD_PORT_LINE_L_C
OUT 63 SOT363 402 CH
R8A15 .45V 2.2K 5% DIO
61 60 IN AUD_VREF_33 1 2 SOT23A 402 EMPTY
0 5% EMPTY
R9A10
402 EMPTY R8A11 1 2
C AUD_VREF_R 1 2 65 IN AUD_PORT1_BIAS_DIODE C
3.3K 5%
1.2K 5%
402 CH 402 EMPTY
R9A17
61 60 IN AUD_VREF_33 1 2
ASK ABOUT THIS 4.7K 5%
402 EMPTY
R4A18 R9A15
60 IN AUD_PORT_G_L 1 2 61 60 IN AUD_VREF_31 1 2
4.7K 5% 0 5% CR9A1
402 EMPTY STAC 402 EMPTY
R9A13
R4A14 2 AUD_PORT_2_R_DIODE 1 2 AUD_PORT_2_R_HDR 64
AUD_VREF_37 OUT
1 2 R9A18
61 60 IN
CR4A3
AUD_VREF_30 1 2 6
1.2K 5%
0 5% R4A23
60 IN 402 CH
402 EMPTY
5 AUD_LINE_OUT_R_DIODE 1 2 AUD_PORT_LINE_R_D 0 5% R9A22
OUT 63 402 CH 1 AUD_PORT_2_L_DIODE 1 2 AUD_PORT_2_L_HDR OUT 64
R4A15 2.2K 5% BAW56S
64 60 IN AUD_VREF_32 1 2 3 402 EMPTY
SOT363
1.2K 5%
CH
402
0 5% R4A19 DIO
402 EMPTY 4 AUD_LINE_OUT_L_DIODE 1 2 AUD_PORT_LINE_L_D OUT 63
BAW56S 2.2K 5%
SOT363 402 EMPTY
R9B28
B 65 AUD_PORT2_BIAS_DIODE 1 2 B
EMPTY IN
R9A12 R4A20 4.7K 5%
60 IN AUD_VREF_30 1 2 AUD_LINE_OUT_L_VREF_DIODE 1 2 402 EMPTY
0 5% 4.7K 5%
402 EMPTY 402 EMPTY
TERMINATION/PULL-UPS
R8A7
61 60 AUD_PORT_H_R 1 2
IN
4.7K 5%
402 EMPTY
R4A7 R9A5
AUD_VREF_32
1 2
60
64
IN 1 2 AUD_PORT1_BIAS_DIODE
OUT 65
1.2K 5%
402 CH 0 5%
R9B8 402 EMPTY
CR4A3 66 61 IN V_5P0_AUD_ANALOG 1 2 AUD_PORT1_2_BIAS_DIODE_R R9B14
R4A12
2 AUD_MIC2_DIODE 1 2 AUD_PORT_LINE_R_B 510 5%
1 C9B7 1 2
OUT 63 402 AUD_PORT2_BIAS_DIODE
OUT 65
R4B2 2.2K 5% EMPTY 470.0UF 0 5%
60 IN AUD_VREF_28 1 2 6 402 EMPTY 20% EMPTY
61 402
A 0 5% R4A22 16V A
1 1 EMPTY
402 CH AUD_MIC1_DIODE 2 AUD_PORT_LINE_L_B
OUT 63 2 RDL
BAW56S 2.2K 5%
SOT363 402 EMPTY
EMPTY
AUD
R4B1
AUD_MIC1_DIODE_MIC_BIAS 1 2
1.2K 5%
402 CH
8 7 6 5 4 3 2 1
CR-66 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE66
8 7 6 5 4 3 2 1
1
603 EMPTY
C10C2 0OHM
.1UF
20%
SM EMPTY
16V
EMPTY R9A31
402
2
1 2
0OHM
REGULATOR THERMAL TAB SHOULD BE SOLDERED SM EMPTY
TO A COPPER PAD THAT IS LARGE ENOUGH
TO ALLOW 5 TO 10 GROUND VIAS AROUND
C THE COMPONENT FOR COOLING AUD C
+12V
U10A1
78M05C R9A42
1 2 V_5P0_AUD_FILTERED 1 2 V_5P0_AUD_ANALOG 61 60 62 64 65
IN OUT OUT
0OHM
SM EMPTY
1
C9C3 GND 1
C9A7
1
C9A15 1 C9A18 NOTE:
CLOSE TO REGULATOR 1UF 3 EMPTY .1UF 1.0UF 100UF
20%
20% 20% 20%
16V 16V 10V 25V
2 2
EMPTY
805
Y5V
402
2 Y5V
603 2 ELEC
RDL LAYOUT SHOULD GO FROM PIN 2 TO
AUD
CAPS AND THEN THROUGH SEVERAL
AUD VIAS TO V_5P0_AUD_ANALOG
B B
C6A1 1
1 .01UF R9A24
20% 0
5%
50V
A 2 CH A
X7R 402
603 2
PLACE NEXT TO CODEC
AUD
GND AT MOUNTING HOLE
DRAWING [PAGE_TITLE=AUDIO_VREG]
D915PLWDL_FABA.SCH_1.66 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 09:31:17 2005
CONFIDENTIAL D16704 66 1.00
8 7 6 5 4 3 2 1
CR-67 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE67
8 7 6 5 4 3 2 1
BOM NOTE:
USE C55845-001
FOR X1 CONN
+12V
KEY
B12 RSVD GND A12
B13 GND REFCLK+ A13 CK_PE_100M_X1_2 IN 30
38 IN HSO_P2_C B14 HSOP0 REFCLK- A14 CK_PE_100M_X1_2* IN 30
38 IN HSO_N2_C B15 HSON0 GND A15
B16 GND HSIP0 A16 HSI_P2 OUT 38
B17 PRSNT2* HSIN0 A17 HSI_N2 OUT 38
B18 GND A18
B
1 OF 1 GND B
CONN
VCC3
A A
C10B2
1 2
.1UF 20%
25V
Y5V
603
[ TITLE=PCIE_X1_CONN_2]
DRAWING
D915PLWDL_FABA.SCH_1.67 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 23:06:25 2005
CONFIDENTIAL D16704 67 1.00
8 7 6 5 4 3 2 1
CR-68 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE68
8 7 6 5 4 3 2 1
D
D
C C
BLANK
B B
A A
DRAWING
D915PLWDL_FABA.SCH_1.68 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:20 2005
CONFIDENTIAL D16704 68 1.00
8 7 6 5 4 3 2 1
CR-69 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE69
8 7 6 5 4 3 2 1
D
D
C C
BLANK
B B
A A
DRAWING
D915PLWDL_FABA.SCH_1.69 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:20 2005
CONFIDENTIAL D16704 69 1.00
8 7 6 5 4 3 2 1
CR-70 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE70
8 7 6 5 4 3 2 1
VCC3
L_AD<3..0>
U8J1 SLD9630
73 72 40 BI
3 7 LAD<3> VDDC 19
2 6 LAD<2> VDD_5 5
C 1 3 LAD<1> VDD_11 11 1 C
0 2 25
CK_P_33M_TPM 8
LAD<0> VDD_25
R8H20
29 IN LCLK 4.7K
40 IN L_FRAME* R8H12 13 LFRAME* 5%
37 PLTRST* 1 2 LRESET#_R 27 EMPTY
VCC3
IN LPCPD* 26
LRESET*
PENABLE 22 PENABLE
40 47 5% 603
IN SER_IRQ 12
LPCPD*
PACCESS 21 PACCESS 2
81 73 40 BI 603 EMPTY SERIRQ 202285-065
20
9
BADDR
CLKOVD TESTIO 16 TP_TPM_TESTIO
J8J1
1X3HDR
I_CLKRUN* 23 CLKRUN* TESTEN 17 1 1-2 OPTION
2
TPM_CLKOVD
NC=1,14,15,28 EMPTY TP_NC 3
GND=4,10,18,24
VCC3 A98822-001 1 2-3 NORMAL*
EMPTY
R8J1
4.7K
R8H15 5% * = DEFAULT
1 2 1
EMPTY
4.7K 5% R8H16 603
603 EMPTY 1 10K 2
5% 202285-065
1 202285-065
R8H17 EMPTY
R8H14 4.7K 603
4.7K 5% 2 202285-073
B 5% EMPTY B
EMPTY 603
603 2 202285-065
2 202285-065
I_BADDR
1
R8H13
4.7K CAD NOTE:
5%
EMPTY
CK_P_33M_TPM SHOULD
603 HAVE 20MIL SPACING
VCC3 2 202285-065
P_PCIRST* SHOULD
HAVE 20 MIL SPACING
LAD<3..0> HAS 5 MIL
SPACING BETWEEN OTHER LAD
SIGNALS, BUT 10 MILS TO ALL
1
C9D9 1
C8H13 1 1 OTHER SIGNALS.
1
C8H18 .1UF .1UF C8J2 C8H15
20% 20% .1UF .1UF
1.0UF 20% 20%
20% 25V 25V
2 EMPTY 2 EMPTY 25V 25V
10V 2 EMPTY 2 EMPTY
2 EMPTY 603 603
603 603
A 603 A
202341-008 202341-002 202341-002 202341-002 202341-002
CAD NOTE:
PLACE ONE PER POWER
PIN NEXT TO PIN.
DRAWING
D915PLWDL_FABA.SCH_1.70 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 09:33:17 2005
CONFIDENTIAL D16704 70 1.00
8 7 6 5 4 3 2 1
CR-71 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE71
8 7 6 5 4 3 2 1
BOM NOTE:
FOR M-SITES, USE
A36096-008 (.01UF, 0402)
D
C9J9 D
SATAHDR_TX2P_R 1 2 SATAHDR_TX2P 39
IN
J9J1
.01UF 10%
1X7HDR
SATA 402 25V X7R
C9J10
TXP 2 SATAHDR_TX2N_R 1 2 SATAHDR_TX2N
1 IN 39
GND
TXN 3 .01UF 10%
4 GND 402 25V X7R
RXN 5 M9J3
7 GND SATAHDR_RX2N_R 1 2 SATAHDR_RX2N
RXP 6 MULTI OUT 39
CH 402
HDR
A71107-007 M9J4
SATAHDR_RX2P_R 1 2 SATAHDR_RX2P 39
MULTI OUT
CH 402
C8J5
J9J2 SATAHDR_TX3P_R 1 2 SATAHDR_TX3P 39
1X7HDR IN
C SATA C
.01UF 10%
TXP 2 402 25V X7R
1 GND C8J6
TXN 3 SATAHDR_TX3N_R 1 2 SATAHDR_TX3N
4 GND IN 39
RXN 5 .01UF 10%
7 GND 402 25V X7R
RXP 6 M8J3
SATAHDR_RX3N_R 1 2 SATAHDR_RX3N 39
HDR MULTI OUT
A71107-007 CH 402
M8J4
SATAHDR_RX3P_R 1 2 SATAHDR_RX3P 39
MULTI OUT
CH 402
C9H8
SATAHDR_TX0P_R 1 2 SATAHDR_TX0P 39
IN
J9H3 .01UF 10%
1X7HDR 402 25V X7R
B SATA C9H9 B
TXP 2 SATAHDR_TX0N_R 1 2 SATAHDR_TX0N IN 39
1 GND
TXN 3 .01UF 10%
4 GND 402 25V X7R
RXN 5 M9J1
7 GND SATAHDR_RX0N_R 1 2 SATAHDR_RX0N 39
6 MULTI OUT
RXP
CH 402
HDR M9J2
A71107-007 SATAHDR_RX0P_R 1 2 SATAHDR_RX0P 39
MULTI OUT
CH 402
C8H16
J9H4 SATAHDR_TX1P_R 1 2 SATAHDR_TX1P
1X7HDR IN 39
SATA
.01UF 10%
TXP 2 402 25V X7R
1 GND C8H17
TXN 3 SATAHDR_TX1N_R 1 2 SATAHDR_TX1N
4 GND IN 39
RXN 5 .01UF 10%
A 7 A
GND 402 25V X7R
RXP 6 M8J1
SATAHDR_RX1N_R 1 2 SATAHDR_RX1N 39
HDR MULTI OUT
A71107-007 CH 402
M8J2
SATAHDR_RX1P_R 1 2 SATAHDR_RX1P 39
MULTI OUT
CH 402
DRAWING
D915PLWDL_FABA.SCH_1.71 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 16:25:09 2005
[PAGE_TITLE=SATA CONNECTORS]
CONFIDENTIAL D16704 71 1.00
8 7 6 5 4 3 2 1
CR-72 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE72
8 7 6 5 4 3 2 1
RECOVER/CONFIGURE HEADERMODE
CH
FGPI4 30 PN_FWH_GPI4 402
2
VCC3 FGPI3 3 PN_FWH_GPI3
4 4 BOARDID<5..0> BI 43 73 40
1 Q7H2 FGPI2
28 GNDA/NC
ID3 9 TP_FWH_9
B 16 GND ID2 10 TP_FWH_10 B
ID1 11 TP_FWH_11
26 GND ID0 12 TP_FWH_12
IC
VCC3
1 1 1
C8H20 C7H11 C7J1
.1UF .1UF .1UF
20% 20% 20%
25V 25V 25V
2 EMPTY 2 Y5V 2 Y5V
603 603 603
A A
[PAGE_TITLE=FIRMWARE HUB]
DRAWING
D915PLWDL_FABA.SCH_1.72 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 09:34:14 2005
CONFIDENTIAL D16704 72 1.00
8 7 6 5 4 3 2 1
CR-73 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE73
8 7 6 5 4 3 2 1
VCC3 92 V_3P3_STBY\G
IN
R2J15
SMSC_VCC3_OR_TPM_HDR
2
0 1
5% VCC3
BOM NOTE: CH 402
FLOPPY
75 PA_FDD_WGATE*
CH 402 OUT 10
WGATE*
103 TP_PA_SENSOR_SDA 4.7K 5%
75 PA_FDD_HDSEL*
OUT 20
HDSEL* GP10
104 TP_FRONT_FAN_TACH EMPTY 402
2 R7J2 1 75 IN PA_FDD_INDEX* INDEX* GP11
GPIO
75 PA_FDD_WRTPRT* 99
CH 402 IN 11
WRTPRT* GP13
108 OUT BOARDID<5..0>
BI 43 72 40
75 IN PA_FDD_RDATA* RDATA* GP14 5
75 IN PA_FDD_DSKCHG* 9 DSKCHG* GP15 109 FNT_REAR_FAN_CTRL_PD
BI 73 R3J1
VCC3 1 2 1-WATT 90
OUT
5.6K 5%
2 R1J9 1
99 IO_PME* KDAT 4 PA_KBDATA
BI 76 402 CH
10K 5%
KCLK 3 PA_KBCLOCK
BI 76
VCC3
C CH 402 0 62 LAD<0> MDAT 2 PA_MSDATA
BI 76 C
1 61 1 PA_MSCLOCK
BI 76
PS/2
LAD<1> MCLK
R1J11 59 7 R7H5
2 1 2 LAD<2> KBDRST* 1 2
10K
CH
5%
402
72 70 40 BI L_AD<3..0>
3 57 LAD<3> GA20M 5 10K
CH
5%
402
L_FRAME* 56 R7H8
LPC
40 IN LFRAME*
1 2
40 OUT L_DRQ*
R8H8
54 LDRQ* INITP* 48 PA_LPT_INIT*
BI 77
37 IN PLTRST* 1 2 PA_PLTRST* 63 PCI_RESET* SLCTIN* 47 PA_LPT_SLCTIN*
OUT 77
10K
CH
5%
402
40 IN LPCPD* 0
CH
5% 52 LPCPD*
402
29 IN CK_P_33M_PA 55 PCI_CLK PD<0> 44 0 KBRST*
OUT 40
81 70 40 BI SER_IRQ 53 SER_IRQ PD<1> 43 1
DESIGN NOTE: PD<2> 42 2 A20GATE
OUT 40
SIGNAL QUALITY OPTION C8H12 1 PD<3> 41 3
.1UF
78 IN PA_COM_RXD1 25 RXD1 PD<4> 40 4
20%
25V 78 OUT PA_COM_TXD1 27 TXD1 PD<5> 39 5
24 38
PARALLEL
EMPTY 2 78 IN PA_COM_DSR1* DSR1* PD<6> 6
603
26 37 7 PA_LPT_PD<7..0>
BI 77
1
78 PA_COM_RTS1*
"Y5V" OUT 28
RTS1* PD<7>
78 PA_COM_CTS1*
IN 30
CTS1*
33
PA_COM_DTR1*
SERIAL
78 PA_LPT_SLCT 77
OUT 32
DTR1*/XOR SLCT
34 IN
78 PA_COM_RI1* PA_LPT_PE 77
78
IN
PA_COM_DCD1* 23
RI1* PE
35 PA_LPT_BUSY
IN
77
BOM NOTE: 1 R2J12 2
IN DCD1* BUSY
36 IN STUFF FOR PA3.0
PA_LPT_ACK* 77 10K 5%
ACK*
45 IN
PA_LPT_ERR* 77 EMPTY 402
B
ERROR*
IN B
65 50
CLOCK
29 CK_14M_PA PA_LPT_ALF* 77
IN 91
CLOCKI14 ALF*
51 OUT
40 SUSCLK PA_LPT_STROBE* 77
IN CLOCKI32 STROBE*
OUT
LAN_OR_FAN*
110 VSS<7>
73 55 IN
96 VSS<6> GP16/TACH1 111 TP_CPU_FAN_TACH
78 112
FAN
VSS<5> GP17/TACH2 TP_ATX_FAN_TACH
58 VSS<4>
46 VSS<3>
1 R2J14 2 LAN_DISABLE*
BOM NOTE: 29 OUT 74 40
STUFF ONLY 8
VSS<2>
VSS<1>
BOM NOTE: 0 5% 55 73
STUFF FOR PA1.5 EMPTY 402
FOR PA3T
78 IN PA_COM_RXD2 119 RXD2
EMPTY FOR LAN_DISABLE OPTION B
78 OUT 78 OUT PA_COM_TXD2 120 TXD2
R1J8 78 IN PA_COM_DSR2* 121 DSR2*
1 2 PA_COM_RTS2* 122 RTS2*
SERIAL 2 IRTX2 128 PA_IRTX2
78 PA_COM_CTS2* 124 127 PA_IRRX2 LAN_DISABLE* R8A4
1K 5% IN 125
CTS2* IRRX2
74 73 IN 1 2
402 EMPTY 78 PA_COM_DTR2*
OUT 118
DTR2*
10K 5%
78 PA_COM_RI2*
IN 126
RI2*
402 CH
78 PA_COM_DCD2*
IN DCD2*
1 OF 2 VCC
NOTE:
NC=129 PULLS GPIO LOW AT POWERUP SINCE
IC
GPIO DEFAULT IS INPUT
C54396-001 J1J4
1X5HDR2
VCC3 1
A 92 V_3P3_STBY\G A
IN
VCC3 3
4
5
1 C1J1
1 C2J6
1 1 1 1 1 EMPTY 1 1 1
C2J4 C2J11 C9F10 C1J5 C1J6
.1UF .1UF .1UF .1UF .1UF .1UF .1UF 102276-006 C2J12 C2J10 C2J9
20% 20% 20% 20% 20% 20% . 20% 470PF 470PF 470PF
25V 25V 25V 25V 25V 25V 25V 10% 10% 10%
2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2 Y5V 2
50V
2
50V
2
50V
603 603 603 603 603 603 603 EMPTY EMPTY EMPTY
603 603 603
8 7 6 5 4 3 2 1
CR-74 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE74
8 7 6 5 4 3 2 1
VCC3
V_5P0_STBY
R2J8 86 IN
74 IN
LAN_DISABLE_CTRL* 1 2 LAN_DISABLE*
OUT 73 40 55
0 5%
D 1 1 BOM NOTE: 402 1 C1J2
R2H6 R2H4 EMPTY
.1UF D
STUFF FOR PA3.0 20%
8.2K 8.2K 25V
5% 5% 2 Y5V
CH CH 603
402 402
2 2
6 IN H_SKTOCC*
86 IN V_5P0_STBY 1 R1H9
92 IN V_3P3_STBY\G 0
5%
1 1 2 CH
R2H5 R2H3 402
1 SLOTOCC* OUT 74
2.7K 2.7K
5% 5% R1H6
CH CH 1K DEBUG/EV FEATURE: POWER-ON FORCING HEADER
402 402 5%
2 2
U1J1 CH
402
87
PORT ANGELES 1.6
71
2
25 21 29 BI SMB_CLK_MAIN SMB_CLK_M V_5P0_STBY
52 51 50 49 39 32 BI SMB_CLK_RESUME 88 SMB_CLK_R REF_5V_STBY 72 V_REF5V_SUS_SIO OUT 41
POWER
C 25 21 29 79 67 56 53
BI SMB_DATA_MAIN 89 SMB_DAT_M REF_5V 70 V_REF5V OUT 41 43 74 C
52 51 50 49 39 32 BI SMB_DATA_RESUME 90 SMB_DAT_R
56 79 67 53 PWRGD_PLATFORM 84 PWRGD_3V_PA OUT 74
DDCSDA_5V 116 82 PWRGD_PS
VGA DDC VT
20 BI 5V_DDCSDA/GP20 PWRGD_PS
IN 86
20 DDCSCL_5V 114 R1J2
18 15
BI
MCH_DDC_DATA 115
5V_DDCSCL/GP21
73 P_RST_SLOTS_R* 1 2 P_RST_SLOTS* 32 51 67
BI 113
3V_DDCSDA/GP22 PCIRST_OUT*
74 OUT
18 15 BI MCH_DDC_CLK 3V_DDCSCL/GP23 PCIRST_OUT2* TP_PCIRST_OUT2_R* 33 5%
IDE_RSTDRV* 64 IDE_RST* OUT 44 74 402 CH 1
C1J3
81 OUT GPIO_GRN_BLNK_HDR 94 GRN_LED RSMRST* 92 ICH_RSMRST* OUT 55 39 47PF
81 OUT GPIO_YLW_BLNK_HDR 95 YLW_LED 5%
HD_LED* 66 77 BACKFEED_CUT 2 50V
81 OUT HD_LED* BACKFEED_CUT*
OUT 74 90 103 COG
67 79
PWR SEQ
LED
44 IN IDE_PRI_ACT* PRIMARY_HD* LATCHED_BF_CUT LATCHED_BACKFEED_CUT
OUT 89 90 402
43 39 IN ICH_SATA_LED* 68 SECONDARY_HD* SCK_BJT_GATE 80 TP_SCK_BJT_GATE
TP_SCSI_ACT_PIN2 69 SCSI* PS_ON* 81 PS_ON_SIO* OUT 74 86 PWRGD_PS
81 43 IN FP_RST* 75 FPRST* CPU_PRESENT* 83 SLOTOCC* IN 74 IN 86
40 IN SLP_S3* 85 SLP_S3* AUD_LINK_RST* 100 LAN_DISABLE_CTRL* OUT 74 VCC3 OLD PWRGD PATH
43 IN SLP_S4* 86 SLP_S5* CDC_DWN_ENAB/GP24* 101 PA_GPIO12 IN 86
CDC_DWN_RST* 102 PA_102
PA_TESTEN_1 98 TEST_EN1 1
V_3P3_STBY\G 1 R2J4 2 NC 117 1 R8J10
92 IN R1H4 0 NEEDS TO BE
1 VOLT. DIVIDED
B 402
0 5%
EMPTY
PA_F_CAP 97 F_CAP
2 OF 2
C2J1
1.0UF
1K 5%
DOWN FROM 5V B
BOM NOTE: IC
20%
10V
5% EMPTY
402 TO 3.3V
NEVER STUFF NC=129
C54396-001 2 EMPTY
EMPTY
402 2
603 2
EMPTY THESE FOR PA1.6 OR 3.0
1 1
C2J3
.1UF
C2J2
4.7UF 92
V_3P3_STBY\G 2 R1H5 1
IN
10% 20% 10K 5% PWRGD_3V
16V 10V OUT 15 40 72
2 X7R 2 Y5V 402 EMPTY
603 805
I_3P3_STBY_74
CAD NOTE: 1
PLACE AS CLOSE TO R8J9
PIN AS POSSIBLE Q1H1 0
MBT3904DUAL 3 6 5%
R1H2 5 2 EMPTY
PWRGD_3V_PA 1 2 I_PWRGD_3V_PA 402
74 IN
5%
2
100K
92
V_3P3_STBY\G 402 EMPTY 1
C1H10 EMPTY
IN 1.0UF 4 1
20%
10V
2 EMPTY
603
A VCC VCC "Y5V" A
1 1 1
R1J1 R1J3 R1H7 86 74 OUT PS_ON_SIO*
1K 1K 1K
5% 5% 5%
CH CH CH 1 R1H1 2
402 402 402
2 2 2 0 5%
74 IN V_REF5V 402 CH
8 7 6 5 4 3 2 1
CR-75 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE75
8 7 6 5 4 3 2 1
D VCC
D
1 1
R2J6 R2J10
PLACE NEAR 1K 1K
5%
5%
CH CH
FDD CONN 402 402
2 2
1 1 1
R2J11 R2J13 R2J16
1K 1K 1K
5% 5% 5%
CH CH CH
402 402 402 J4J1
2 2 2
2X17HDR_3_5
C 1 P1 C
73 IN PA_FDD_DRVDEN0 2 P2
KEY
TP_301S 4 P4
KEY
73 IN PA_FDD_DRVDEN1 6 P6
7 P7
73 OUT
PA_FDD_INDEX* 8 P8
9 P9
73 IN PA_FDD_MTR0* 10 P10
11 P11
TP_302S 12 P12
13 P13
73 IN PA_FDD_DS0* 14 P14
15 P15
TP_303S 16 P16
17 P17
73 IN PA_FDD_DIR* 18 P18
19 P19
73 IN PA_FDD_STEP* 20 P20
21 P21
73 IN PA_FDD_WDATA* 22 P22
23 P23
B PA_FDD_WGATE* 24 P24
B
73 IN 25 P25
73 OUT PA_FDD_TRK0* 26 P26
27 P27
73 OUT PA_FDD_WRTPRT* 28 P28
29 P29
73 OUT PA_FDD_RDATA* 30 P30
31 P31
73 IN PA_FDD_HDSEL* 32 P32
33 P33
73 OUT PA_FDD_DSKCHG* 34 P34
HDR
A A
[PAGE_TITLE=FDD CONN]
DRAWING
D915PLWDL_FABA.SCH_1.75 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 09:39:25 2005
CONFIDENTIAL D16704 75 1.00
8 7 6 5 4 3 2 1
CR-76 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE76
8 7 6 5 4 3 2 1
D
D
91 IN VREG_PS2
PS2 KEYBOARD
1 1 1 1
R1A4 R1A3 R1A6 R1A5
2.7K 2.7K 2.7K 2.7K
5% 5% 5% 5%
CH CH CH CH
402 402 402 402 J1A1
2 2 2 2 PS2 STACK
73 PA_KBDATA 1 R1A8 2 SIO_KBDATA_FB 1 P1
BI TP_401S 2 749231-001
0 5% P2
402 CH 3 P3
4
73 PA_KBCLOCK 1 R1A7 2 SIO_KBCLOCK_FB 5
P4
P5
BI TP_402S 6
0 5% P6
402 CH
P13 13
1
C1A7 P14 14
C 15 C
1UF P15
20% P16 16
6.3V 17
2 X5R P17
A A
DRAWING
D915PLWDL_FABA.SCH_1.76 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 09:39:30 2005
CONFIDENTIAL D16704 76 1.00
8 7 6 5 4 3 2 1
CR-77 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE77
8 7 6 5 4 3 2 1
PA_LPT_PD<7..0>
73 IN 6 1 R2A5 2 SIO_LPT_PD6_R
33 5%
CH 402
7 1 R2A6 2 SIO_LPT_PD7_R
33 5%
CH 402
D 0 1 R3A9 2 SIO_LPT_PD0_R
33 5%
D
CH 402
1 1 R3A10 2 SIO_LPT_PD1_R
33 5%
CH 402
2 1 R3A11 2 SIO_LPT_PD2_R
33 5%
CH 402
3 1 R3A12 2 SIO_LPT_PD3_R
33 5%
CH 402
4 1 R3A13 2 SIO_LPT_PD4_R
VCC
33 5%
CH 402
5 1 R3A14 2 SIO_LPT_PD5_R
33 5%
CH 402
2 2 2 2
R3A1 R3A3 R3A2 R3A4
C 2.7K 2.7K 2.7K 2.7K J3A2 C
5% 5% 5% 5% TALL DSUB 25
CH CH CH CH
402 402 402 402 749179-001
R3A15 1 1 1 1
73 IN PA_LPT_STROBE* 1 2 SIO_LPT_STROBE_R* 1
33 5% 14
CH 402 2
15
R3A6 3
73 IN PA_LPT_ALF* 1 2 SIO_LPT_ALF_R* 16
33 5% 4
CH 402 17
5
R3A7 18
73 IN
PA_LPT_INIT* 1 2 SIO_LPT_INIT_R* 6
33 5% 19
CH 402 7
20
PA_LPT_SLCTIN* 1 R3A8 2 SIO_LPT_SLCTIN_R* 8
73 IN 21
33 5% 9
CH 402 22
B VCC 10 B
23
11
24
2 2 2 2 2 12
R2A2 R2A3 R2A4 R2A1 R3A5 25
10K 10K 10K 10K 10K 13
5% 5% 5% 5% 5%
CH CH CH CH CH 1
402 402 402 402 402 C2A11 1 C3A12 1 C3A5 1 C3A4
1 1 1 1 1 220PF DSUB
10% 220PF 220PF 220PF GND=26,27,28
73 OUT PA_LPT_ACK* 50V 10% 10% 10%
2 X7R 2 50V 2 50V 2 50V
73 OUT PA_LPT_BUSY 402 X7R X7R X7R
402 402 402
73 OUT PA_LPT_PE
PA_LPT_SLCT 1 1 1 1
73 OUT C2A12 C3A13 C3A10 C3A8
220PF 220PF
73 OUT PA_LPT_ERR* 10% 10% 220PF
10%
220PF
10%
2 50V 2 50V
X7R X7R 2 50V 2 50V
402 402 X7R X7R
402 402
1 C2A13 1 1 C3A6 1
220PF C2A9 220PF C3A7
A 10% 220PF 10% 220PF A
50V 10% 50V 10%
2 X7R 2 50V 2 X7R 2 50V
PLACE NEAR 402 X7R 402 X7R
402 402 1
1 C3A3
1 C2A14 1 C2A10 1 C3A9 220PF
LPT CONN C3A11 220PF 10%
50V
220PF 220PF 10% 2
10% 10% 220PF 50V X7R
50V 50V 10% 2 X7R 402
2 X7R 2 X7R 2 50V 402
402 402 X7R
402
[PAGE_TITLE=LPT CONN]
DRAWING
D915PLWDL_FABA.SCH_1.77 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 09:39:34 2005
CONFIDENTIAL D16704 77 1.00
8 7 6 5 4 3 2 1
CR-78 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE78
8 7 6 5 4 3 2 1
SERIAL PORT B
A A
+12V -12V V_5P0_STBY IN 86
"Y5V"
1 C1G4 1 C1G7 1 C1H6
.1UF .1UF .1UF
20% 20% 20%
2 25V 2 25V 2 25V
EMPTY EMPTY EMPTY
603 603 603
PLACE NEAR 232'S PINS 1, 10, AND 20 RESPECTIVELY DRAWING [PAGE_TITLE=SERIAL PORT A]
D915PLWDL_FABA.SCH_1.78 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 09:46:55 2005
CONFIDENTIAL D16704 78 1.00
8 7 6 5 4 3 2 1
HECETA6 WILL BE EMPTY & "SATELLITE" HECETA WILL BE STUFFED IF PORT ANGELES 3.0 IS STUFFED
CR-79 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE79
8 7 6 5 4 3 2 1
USB-AT_PIN3_BUTTON_R
1 2 99
IN
0 5%
HECETA_PIN22_2.5V_R
CAD NOTE: CAD NOTE: 402 EMPTY
SOUTHEAST THERMAL ZONE SENSOR R1F20 USB_AT_PIN3_BUTTON
1 2 79
PLACE BELOW DIMMS 10MIL TRACE ON SE_ZONE_TDN AND _TDP CPU_FAN_CTRL 2 IN
OUT 83 0 5% NOTE:
D R1F24 402 EMPTY STUFF FOR ALTERNATE USB ANTI THEFT SUPPORT
56 74 67 53 52 51 50 49 39 32 BI
SMB_DATA_RESUME 0
D
SMB_CLK_RESUME 5%
74 67 56 53 52 51 50 49 39 32 IN
3 R1F12
CH R1F55 V_1P5_CORE
PRELIMINARY 402 1 2 102
1 H_TEMP_RET 1 2 1 IN
Q2F1
MMBT3904
6 OUT U2F1 0 5%
0 5%
HECETA6 402 CH
XSTR 402 CH
2 108969-001 24 PWM1/NTESTOUT VCCP_IN 23 VCCP 96 97
1 22 IN
2.5V
C2F7 1 20 402
100.0PF R1F9 SDA 5V +12V 1 EMPTY
5% 6 IN H_TEMP_SRC 1 2 2 SCL 3.3SBY 4 H4_H6_V_3P3STBY
IN 79 16V
2 50V
COG 12V 21 20%
0 5% REMOTE1+_R 18 .1UF
603
402 CH REMOTE1+ C2F15
603275-120 REMOTE1-_R 17 REMOTE1-/NTESTIN PWM2 10 USB_AT_PIN1_LED
OUT 79 2
SE_ZONE_TDP 16 REMOTE2+ PWM3 13 FNT_REAR_FAN_CTRL
OUT 83
SE_ZONE_TDN 15 REMOTE2-
11
83
TACH1 CPU_FAN_TACH 83
TP_HECETA6_19 19 12 ATX_FAN_TACH
IN
VID4 TACH2 IN
TP_V_1P5_CORE 8 VID3 TACH3 9 FRONT_FAN_TACH
IN 83
7 VID2 TACH4 14 REAR_FAN_TACH
IN 1 83
TP_HECETA6_5 6 VID1 R9J10
VID0_R 5 VID0 GND 3 NOTE: 1 R2F34
USE C58244-001 FOR 10K 2 5.6K
R8F17 IC HECETA 6 5% 5%
C 1 2 A57150-001 2 CH C
0 5% R2F40
EMPTY 402
VID2_R 402 EMPTY 1 2 402
0 5%
402 EMPTY
R2F22
92 IN
V_3P3_STBY\G 2 1 H4_H6_V_3P3STBY
OUT 79
0 5%
NOTE: 402 CH
STUFF FOR VID0 AND VID2 FOR PRIMARY 1 C2F5
USB ANTI THEFT SUPPORT BOM NOTE: .1UF
DEFAULT FOR S3 SUPPORT 20%
2 25V
Y5V
603
VCC3
R2F30
1 2
0 5%
BOM NOTE: 402
DEFAULT: HECETA6 CIRCUITRY STUFFED W/PA1.5 OPTION FOR "NO-WAKE" EMPTY
B B
92 IN
V_3P3_STBY\G
J1J1
2X3HDR_5
1 USB_AT_PIN1_LED_HDR 1 2 V_5P0_STBY
402 79 IN IN 86
EMPTY 3 4
5% 6
10K
R1H10 EMPTY
USB_AT_PIN3_BUTTON 2 R1J4 1 USB_AT_PIN3_BUTTON_R
2 79 OUT
5% 1K
EMPTY 402
USB_AT_PIN1_LED R1H3
1 2 USB_AT_PIN1_LED_HDR
79 IN OUT 79
0 5%
402 EMPTY
A A
D
D
BOM NOTE:
STUFF TO DISABLE NO-REBOOT OPTION AT
POWER-UP (CONFIGURATION STRAPPING).
VCC3
VCC
1
R9C6
1K
5%
EMPTY
402
2
3
SPKR R9C5 CORE_SPKR_R
1 Q9D1
39 IN 1 2
C
MMBT3904 C
1K 5% XSTR LS9C1
402 CH 1 C9D1 2 108969-001 XDCR
1000PF
10% SPKR_OUT 1 +
2 50V
EMPTY AT-08
603 2 IN
"X7R"
1
R9C7
47
5%
EMPTY
402
2
1
VCC3
R7G2
220
5%
EMPTY
402
1 2
LED_RR
R7G4
4.7K 2 716805-005
5% CR7G1
EMPTY RED
402 EMPTY
2 1
LED_3904
3
ICH_GPO19* 2 R7G3 1 1 Q7G2
40 IN ICH_GPO9#_R
MMBT3904
220 5% EMPTY
402 EMPTY 2
A A
[PAGE_TITLE=SPEAKER_DIAGNOSTIC_LED]
DRAWING
D915PLWDL_FABA.SCH_1.80 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 09:46:40 2005
CONFIDENTIAL D16704 80 1.00
8 7 6 5 4 3 2 1
CR-81 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE81
8 7 6 5 4 3 2 1
J8C3
1X2HDR
SERIRQ SER_IRQ 73
53 52 50 49 IN 1 2 BI 40
D 70
EMPTY D
R9J6 2 R8C2
0
1 2 BOM NOTE FOR J9J4: V_5P0_STBY 1 R9J9 2 5%
VCC3 R9J12 86 IN
10K 5% 1 2 330 5% 1 EMPTY
402 CH 94 IN 5VDUAL USE IPN 109717-756 402 CH 402
0 1A SER_TEMP
603 EMPTY
FOR 2X5 MULTI-COLOR HDR J8C1
1 R9J8 2 1X2HDR
USE IPN 109717-742 330 5% TP_SERIRQ_TEST 1 2
BOM NOTE: R9J13 FOR 2X5 WHITE HDR 402 CH
UNSTUFF FOR C 1 2 74 IN GPIO_GRN_BLNK_HDR
VCC EMPTY
0 1A 74 IN GPIO_YLW_BLNK_HDR
R9J11 603 CH
VCC 1 2 J9J4
330 5% 2X8HDR_10_14
402 CH
VCC_HDLED_PWR 1 2
81 IN HD_LED_G* 3 4
5 6 SW_ON_R* OUT 81
101 74 40 7 43 OUT FP_RST* 7 8
FP_5V_IN 9
SIO_IRRX2 11 12
C 13 C
SIO_IRTX2 15 16 VCC
HDR
VCC
HD_LED_G* OUT 81
DESIGN NOTE:
GPIO_GRN_BLNK_HDR_R
STUFF ONLY FOR
ENERGY LAKE, THEN 3 1 R1J5
EMPTY 0 OHM BYPASS. 1 R1H8 2 1 Q1J1 0
MMBT3904 5%
10K 5% EMPTY 2 CH R9J4
402 EMPTY 2 402 81 IN SW_ON_R* 1 2 SW_ON* OUT 40 43
A36093-023 33 5%
402 CH 1
HD_LED* C9J1
IN 74 1.0UF
A36093-005 20%
2 10V
Y5V
J9J3 603
1X3HDR2
A 1 GPIO_GRN_BLNK_HDR IN 74 A
102276-304 3 GPIO_YLW_BLNK_HDR IN 74
HDR
DESIGN NOTE:
IF LED HEADER IS NOT PLACED RIGHT NEXT TO FP HEADER,
THEN NEED TO ADD A 470UF 0603 CAP TO EACH OF THESE SIGNALS.
OTHERWISE, THEY CAN SHARE CAP WITH FP HEADER PINS 2 AND 4...
DRAWING
D915PLWDL_FABA.SCH_1.81 INTEL DOCUMENT NUMBER PAGE REV
[PAGE_TITLE=STD_FRONT_PANEL_HDR] Thu Apr 07 09:46:45 2005
CONFIDENTIAL D16704 81 1.00
8 7 6 5 4 3 2 1
CR-82 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE82
8 7 6 5 4 3 2 1
D
D
PB MOUNTING HOLES
J8A1 J7J1
MTG_HOLE MTG_HOLE
NC9 9 NC9 9
EMPTY EMPTY
J1G1 J1B1
MTG_HOLE MTG_HOLE
C NC9 9 NC9 9 C
J7A1 J9G1
MTG_HOLE MTG_HOLE LAN HECETA
9 9 SPD ADD: N/A SPD ADD: N/A
NC9 NC9
EMPTY EMPTY
B DIMMS B
DB800
SPD ADD: N/A SMB_CLK/DATA_RESUME SPD ADD: A0, A2, A4, A6
ICH
A30094-001 J11A2
LB6F1 MTG_HOLE J11J1 J11F1
LABEL
NC9 9 MTG_HOLE MTG_HOLE PWRGD_PS PORT
NC9 9 NC9 9 ANGELES
EMPTY
EMPTY EMPTY
1500X150_TARGET TESTIN LPC HDR SMBUS HDR TPM CLOCK
SPD ADD: ?? SPD ADD: ?? A8 SPD ADD: ?? SPD ADD: N/A SPD ADD: D3 D2
SMB_CLK/DATA_MAIN
200956-001; "CE" MARK SHOULD BE COVERED WITH A BLANK LABEL UNTIL CERTIFIED
628492-001; "FCC" MARK SHOULD BE COVERED WITH A BLANK LABEL UNTIL CERTIFIED (SECONDARY SIDE)
622954-001; "C-TICK" MARK SHOULD BE COVERED WITH A BLANK LABEL UNTIL CERTIFIED
SMB_CLK/DATA_MAIN SMB_CLK/DATA_RESUME
SECURITY (TPM) PCI (4 TIMES)
LB4F2 'KOREAN CERT' SILKSCREEN COVERED UNTIL CERTIFIED PORT ANGELES
LABEL LAN
A LPC BUS LAI HEADER HECETA A
SILK CLOCK
1
LB4F1
LABEL 'INTEL-BRANCH"
MAKE EMPTY ON BOM
[PAGE_TITLE=MTG_HOLES/LABELS/SMBUS_MAP]
DRAWING
1
8 7 6 5 4 3 2 1
CR-83 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE83
8 7 6 5 4 3 2 1
CPU_FAN_CTRL
79 IN
BOM NOTE:
VCC3 BOM NOTE:
+12V +12V
CPU ALWAYS-ON FAN
STUFF FOR 3-PIN
STUFF FOR 4-PIN
OR 3-PIN ALWAYS
FAN
ON
J1F2 1
(PLACE BELOW/RIGHT CPU SOCKET)
1 1X4HDR
CONTROLLED FAN R1F6
R1F4
CPU_DRIVER 1 3.3K
D 2.2K 1 2 5%
CPU_FAN_TACH
5%
1
3 CH 1 OUT 79
D
EMPTY R1F14 C1F4 4 402
1
3 0 .1UF
402 Q1F1 2 R2F37
2 EMPTY 1A 20%
25V HDR 6.2K C2F8
.047UF
79 INCPU_FAN_CTRL 1 CH 2 EMPTY 5% 20%
2 805 603
CPU_TACH_OUT R1F5 CH 50V
A50095-001 2 1 2
402 EMPTY
15K 5% 2 603
2
402 CH 602433-001
VCC3
+12V
1 R2F44 2
FRONT_REAR_FAN_CTRL
0 5% FAN_NET3
402 CH +12V
8 7 6 5 4 3 2 1
CR-84 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE84
8 7 6 5 4 3 2 1
MODIFY THIS PAGE TO REFLECT APPROPRIATE SIGNALS VREG_12V_FILTERED (+12V FILTERED FROM 12V POWER-SUPPLY)
VCCP (VTT, FOR NWD 1.29 - 1.45V)
V_1P25_MEMVTT (1.25V DERIVED FROM V_2.5)
V_2P5_SM (2.5V DERIVED FROM VCC)
VREG_USB_BP_LEFT (5.0 FROM VCC OR 5.0-STANDBY)
D MCH SIO VREG_USB_BP_RIGHT (5.0 FROM VCC OR 5.0-STANDBY) D
X.X (VCCP) 3.3 (VCC3) VREG_PS2 (5.0 FROM VCCC OR 5.0-STANDBY)
USB_FNT_PWR (5.0 FROM VCC OR 5.0-STANDBY)
1.5 CORE 5.0 (VCC) USB_CNR_PWR (5.0 FROM VCC OR 5.0-STANDBY)
V_3P3_PCI_VAUX (3.3V OR 3.3-STANDBY SOURCE)
2.5 SM 3.3 STBY (VCC3 STBY) V_3P3_STBY (3.3V DERIVED FROM 5.0-STANDBY)
2.5 STBY V_5P0_STBY (5.0V FROM POWER-SUPPLY)
V_BAT_VREG_R_CR (3.0V FROM THE BATTERY)
V_3P0_BAT_VREG (~3.0V FROM THE BATTERY THROUGH A DIODE)
+12V (PLUS 12V FROM POWER-SUPPLY)
ICH GLUECHIP -12V (MINUS 12V FROM POWER-SUPPLY)
VCC3 (3.3V FROM POWER-SUPPLY)
3.3 (VCC3) 3.3 STBY (VCC3_STBY) VCC (5.0V FROM POWER-SUPPLY)
5.0 STBY
KINNERETH +
FWH
HEC6
3.3 (VCC3)
3.3 STBY (VCC3 STBY)
5.0 (VCC)
B B
12
X.X (VCCP)
1.5 (CORE)
8 7 6 5 4 3 2 1
CR-85 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE85
8 7 6 5 4 3 2 1
L5J1
94 IN 5VDUAL 2 1 5VDUAL_FILTERED
1UH IND
1 C5J6 PLACE + NODE NEAR
1200UF HIGH-FET DRAIN
20% PLACE GND SIDE
D 16V
2 ALUM CLOSE TO LOW-FET GND D
RDL
CR5J1
1N4148
1 3 I_5VDUAL
1 +12V SOT23
R5J3 DIO
0
1A CAD NOTE:
CH CR5H1 PLACE CLOSE TO FET
PLACE NEAR 603 1 2 1 1
2 1 C5J4 C5J1
CONTROLLER VCC
.1UF 10.0UF
1 C5J7 R4J1 10% 20%
C
.1UF
20%
25V
C5J8
4.7UF
20%
1
MMBD4148CC
SOT23C
3
0
1A
EMPTY
2 16V
X7R
603
KEEP THIS 0603
10V
Y5V
1206
2
3 Q6H1 V_SM OUT 12 18 19 21 24 25 28 89
C
2 Y5V 10V 2 DIO 2 603 D
STD38NH02L - 12MOHMS
603 Y5V AND X7R THERE ARE SIX
805
I_BOOT_VC 470UF CAPS
I_UGATE 1 R6J1 2 I_UGATE_R 1 G S
FET L6J1
ON PAGE 24
2.2 5% C30380-001 1UH
EMPTY ALL
APW & RT
FOR 805
ISL6520
CH
SAYS USE 0-OHM
2 PHASE_NODE_S 1 2
IND
1 A83634-001 1 C7H7 1 C7H9
I_5VDUAL_U5J2
15A PART
1 C6J1 4.7UF .1UF
R5J1 1 1000UF 20% 20%
15K
5% ISL6520 SAYS USE 0-OHM
3 R6J2
20%
10V 2 10V
Y5V 2 25V
Y5V
CH D Q5J1 2.2
5%
2 ALUM
TH 805 603
603 1 "A65154-001"
2 C5J2
470PF
CH 1 C1H1
805 560.0UF
I_5VDUAL_FILTERED_R 10%
50V 1 R5J5 2 1 2 20%
1 2 X7R I_LGATE I_LGATE_R PHASE_NODE_S_R 4V
C5J3 603 0 1A G S
FET 2 EMPTY
RDL
6800PF
20%
50V 1
805 CH 1
C6J3
1000PF
2
C30380-001 1
C6J2
4700PF
2 X7R U5J1 C4J3 10% STD38NH02L - 12MOHMS 20%
B 603 IRU3037A 1UF 50V 50V B
20% 2 EMPTY 2 X7R
1 16V 2 NEED 16V
603 603
1 FB HDRV 5 Y5V
805 PLACE THESE 3
IRU3037/A (IR), 2 VCC VC 6 NEAR EACH OTHER
RT9209/A (RICHTEK) & 3 LDRV COMP 7
APW7037/A (ANPEC) Q5J2
4 GND SS 8 I_IRU_SS MMBT3906
HAVE SAME FOOTPRINT 2 EMPTY
AND PINOUT 1 SLP_S4#_R 1 R5J6 2 SLP_S4*
IC IN 43
DEFAULT STUFFING: 1K 1%
A: 400KHZ, VFB=0.8V IRU3037A 1 3 402 EMPTY
STD: 200KHZ, VFB=1.25V C5J5
.1UF BOM NOTE:STUFF THIS WHEN USE USB AT
20%
2 25V TSTART=75*C (MS) 825 GIVES .8V REF
Y5V AND 1.817V
I_COMP_U5J2 603
202341-002 287 GIVES 1.25V REF
AND 1.803V OUTPUT
Q4J1 649
1C4J7 2
A 1% 1 R4J2 2 A
MBT3906DUAL 3 6 CH
603 0 1A I_5VDUAL_FILTERED_RR .1UF 10%
40 ICH_GPO20 2 R5J4 1 ICH_GPO20_R5 2 2 603 EMPTY 16V
IN EMPTY
1K 5% 603
402 EMPTY
4 EMPTY
1 ICH_GPO20_SW1
ICH_GPO20_SW4 USE FOR ADDITIONAL COMPENSATION
2 2
R4J5 R4J4
20K 10K
5% 5%
EMPTY EMPTY
402 402
1 1
DRAWING
MEMORY OVER-VOLTAGE CONTROL CORE PAGE D915PLWDL_FABA.SCH_1.85 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 09:46:49 2005
CONFIDENTIAL D16704 85 1.00
8 7 6 5 4 3 2 1
CR-86 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE86
8 7 6 5 4 3 2 1
-12V J3J1
2X12 PWR
13 1
14 2 PWRGD_PS OUT 74
R3J4 R3J3 15 3
86 IN V_5P0_STBY 1 2 1 2 PS_ON_HEADER* 16 4
22K 5% 0 5% 17 5
402 CH 402 CH VCC 18 6
19 7
74 PS_ON_SIO* TP_MINUS5V 20 8
IN 21 9 V_5P0_STBY 41 57 66 74 78 79 81 86 90 91 92 93
OUT
22 10 94 95 99 100
1
C3J4 1 C3J3
23 11 1
1UF 470PF 24 12 2X12_DETECT
OUT 86 1
C2J13 C2J7
1 C3J6
1
C5J9
20% 10% 1.0UF 470PF .1UF .1UF
6.3V 50V
2 Y5V 2 X7R CONN 20%
10V
10%
50V
20%
25V
20%
25V
402 603 2 Y5V 2 X7R 2 Y5V 2 EMPTY
603 603 603 603
C C
R2J2
86 IN 2X12_DETECT 2 1 PA_GPIO12 OUT 74
1K 5%
402 CH 1
R2J3
DESIGN NOTE: 2.2K
USED TO DETECT 2X12 POWER 5%
CONNECTOR CH
402
2
B B
VREG_12V_FILTERED
OUT 98 96 97
A27641-001
C4J6
1 2 1C2J8 2 1C4J9 2
J4B2
2X2HDR
.1UF 20% .1UF 20% .1UF 20% 1 2
25V 25V 25V
Y5V Y5V Y5V 3 4
603 603 603
CONN
DRAWING
D915PLWDL_FABA.SCH_1.86 INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE Thu Apr 07 09:54:50 2005
CONFIDENTIAL D16704 86 1.00
8 7 6 5 4 3 2 1
CR-87 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE87
8 7 6 5 4 3 2 1
R5C35 R5C36
V_FSB_VTT 1 2 VTT_CORE_358_MINUS_6
1 2
87 IN
5% 0 1% 499 3
CH 402 EMPTY 402 D Q5D1 CAD NOTE:
OVERLAP SITES FOR D2-PAK
WITH D-PAK
C4C9 R5C32 C5C16 1
1 2 VTT_CORE_358_MINUS_RES 1 2 1 2
G S
.1UF 20% 0 5% .1UF 20% 2 FET
16V 402 EMPTY 16V
EMPTY EMPTY
B 402 402 V_FSB_VTT OUT 7 8 9 12 17 18
B
41 43 87
R4C5 1 C4D1 1 1
1 C5C5 C4C11
1 2
C5D1 3300UF 4.7UF 4.7UF
1K 5% .1UF 20% 20% 20%
10% 6.3V 16V 16V
402 CH
6.3V 2 ALUM 2 Y5V 2 Y5V
2 EMPTY RDL 1206 1206
402
DESIGN NOTE:
D EMPTY
A 3 A
8 7 6 5 4 3 2 1
CR-88 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE88
8 7 6 5 4 3 2 1
D
D
V_3P3_STBY\G IN 92
DESIGN NOTE: SHARED OP-AMP WITH
VCC3 VREG FOR MCH (PROVIDES VOLTAGE TO FILTER)
BOM NOTE: V_2P5_MCH
USING MOD FILE TO CHANGE TO
FSB_VTT ON PAGE 76. 88 IN
4.75K(A36092-375) -12V
UNTIL SYMBOL IS UPDATED
1 R5C25 VEE=-12V CR5C1
1.37K VCC=+12V 1 1
1% C5C14 C5C15
4.7UF .1UF 102 V_1P5_CORE 2
2 CH U5C1 3 20% 20%
IN
402 4 Q5C3 10V 25V
V_2P5_MCH_CNTL_PIN3 3 V- FET 2 Y5V 2 Y5V 3
C + C
1 V_2P5_MCH_CNTL_FET 1 SOT23 805 603
2 2 1
V+
1 R5C26 1 8
BAT54C
15K C5C11 R5C31 SOT23C
1% 2.2UF IC 1 2
10% TL072 DIO
2 CH 6.3V
402 2 X5R
603
1K
603
5%
EMPTY V_2P5_MCH
OUT 12 15 16 88
+12V
CAD NOTE: CAD NOTE:
1
1
R5C28 PLACE NEAR MCH 1 1 PLACE NEAR MCH
1 2 C6D1
C6C18 C6C19
C5D4
.01UF .1UF
10% 10.0UF .1UF 20%
V_2P5_MCH_CNTL_GND 0 5% 20% 20%
25V 25V
402 CH 2 X7R 10V
2 25V 2 Y5V
402 Y5V EMPTY 603
C5C12 R5C30 1206 603
2
1 1 R5C27 1 2 1 2
C5C13 499
.1UF 1% .1UF 20% 0 5%
20% 16V 402 EMPTY
2 16V 2 CH EMPTY
Y5V 402 402
402
B B
A A
8 7 6 5 4 3 2 1
CR-89 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE89
8 7 6 5 4 3 2 1
D
D
85 IN
V_SM
C
SM_VTT 1
R6H5
1.1K
CAD NOTE: VCC CAD NOTE:
C
REGULATION 2
1%
CH
402
MAXIMIZE SHAPE CONNECTING
VCNTL PIN ON TOP LAYER
MAX VIAS
NO TRACES UNDER PART
MAY NEED GROUND PLANE
3
74 LATCHED_BACKFEED_CUT 1 2 5VDUAL_SW_N_R
1 Q6G1
IN
1K 5% MMBT3904
603 EMPTY 2 EMPTY
R7H11
A A
[PAGE_TITLE=VREG_SM_VTT]
DRAWING
D915PLWDL_FABA.SCH_1.89 INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE Thu Apr 07 00:17:16 2005
CONFIDENTIAL D16704 89 1.00
8 7 6 5 4 3 2 1
CR-90 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE90
8 7 6 5 4 3 2 1
BATTERY CR7J1
92 IN V_3P3_STBY\G 2 V_3P3_STBY\G
92 IN
3 V_3P0_BAT_VREG 1 RP9C2 2 RP9C2 3 RP9C2 4 RP9C2
OUT 39 41 43 3 0 0 0 0
1 R7J1 2 I_VREG_VBAT_R 1 D Q8C3 5% 5% 5% 5%
1 .063W .063W .063W .063W
1K 5% BAT54C C9H4 IC IC IC IC
D 402 CH SOT23C 1.0UF
DIO 20%
VREG_USB_NCH_PCI 8 7 6 5 D
2 10V
90 1
Y5V IN G S
EMPTY
XBT7J1 603
2
VREG_VBAT_R 1 2 CAD NOTE:
PLACE NEAR ICH VCC3
THROUGH-HOLE 2PCOIN
FLAT BATTERY
A05835-001
CAD NOTE: DO NOT PLACE BATTERY NEAR CAD NOTE: PLACE AT PCI SLOTS
MOUNTING HOLES, GROUND OR VIAS
V_3P3_PCIVAUX OUT 90 32 49 50 51 52 53
56 57 58 59 67
5 V_3P3_STBY\G 2
RP9J2
92 IN
3 2.7K
C RP9J2 5% C
2.7K .063W
5% IC [PAGE_TITLE=PCI VAUX]
.063W SM
IC 4 CONTROL SIGNAL FOR 4-DIMM VREG CONTROLLER
SM 6
RP9J1 VREG_USB_NCH_L OUT 90
74
LATCHED_BACKFEED_CUT 3 6 VREG_BFEED_R_NU
IN
2.7K 5% .063W VREG_USB_PCH_L OUT 90
SM IC
1 R9J7 2
Q9J1 90 IN VREG_USB_NCH_L VREG_USB_NCH
OUT 90 94
MBT3904DUAL 3 6 0 5%
RP9J1 RP9J1
402 CH R9C9
5 4 5 2 1 8 VREG_BFEED_R1_NU 1 R9J5 2 1 2 53 56 57
IN VREG_USB_PCH_L VREG_USB_PCH
VREG_BFEED_RR_NU VREG_BFEED_R2_NU V_3P3_STBY\G V_3P3_PCIVAUX
90 OUT 90 94 92 IN OUT 90 32 49
2.7K 5% .063W 2.7K 5% .063W 0 5% 0 2A
50 51 52
58 59 67
SM IC
XSTR
SM
RP9J1
IC 402 CH 2010 EMPTY
4 1 2 7
2.7K 5% .063W
A NOTES: DESIGN NOTE: COST REDUCTON EXPERIMENT
SM IC
USB/PS2WAKE A B
S3 ONLY STUFF EMPTY
B S3, S4, S5 EMPTY STUFF
B
RP8B3 VREG_USB_NCH_PCI 90
BACKFEED_CUT 2 7 VREG_BFEED_R
OUT
74 IN
.063W 5% 2.7K VREG_USB_PCH_PCI OUT 90
IC SM
Q8C1
MBT3904DUAL 3 6
RP8B3 RP8B3
8 1 VREG_BFEED_RR
5 2 VREG_BFEED_R2 4 5 VREG_BFEED_R1
A 2.7K 5% .063W .063W 5% 2.7K A
SM IC IC SM
EMPTY Q3J1
4 1 MMBT3904
3 EMPTY
1 1-WATT IN 73
2 R8C3 1 2
5% 0
EMPTY 402 LATCHED_BACKFEED_CUT 74
IN
RP8B3
3 6
.063W 5% 2.7K
IC SM
DRAWING
D915PLWDL_FABA.SCH_1.90 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 00:17:21 2005
CORE PAGE
CONFIDENTIAL D16704 90 1.00
8 7 6 5 4 3 2 1
CR-91 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE91
8 7 6 5 4 3 2 1
D
D
R6B9
2 1 USB_OC_BACK_LEFT* OUT 38
15K 5% 2
402 CH
R6B8
10K
5% CAD NOTE:
CH PLACE AS CLOSE AS POSSIBLE
RT5B2 402 TO USB CONNECTOR
1
1 2 VREG_USB_BP_LEFT OUT 59
THRMSTR 2
C5A3 1
R6B7 1 C6B5 1
470UF
C6B4
5VDUAL 1.50 470PF
94 IN 10K 470UF 20% 10%
5% 20% 10V 50V
10V ALUM 2 X7R
CH EMPTY 2 RDL
1 2 3 4 402 2 603
RP6B1 1
RDL
0
5%
C .063W VREG_USB MUST BE SPLIT C
IC AMONSGT ALL USB CHANNELS.
8 7 6 5 SM DO NOT DAISY CHAIN
USB_OUT
DO NOT CHANGE TO 402 SITE
RT1A2 M1A1
1 2 VREG_PS2_FB 1 2 VREG_PS2 76
MULTI OUT
THERMISTOR OPTION (PER CUSTOMER REQUEST):
EMPTY USB_OUT CH 603
STUFF SITE AND EMPTY 0 OHM R-PACK
DECOUPLING ON CONNECTOR PAGE,
1.50 RT1A1 FERRITE BEAD OPTION: PLACED NEAR PS2 CONNECTOR.
V_5P0_STBY 1 2 A51464-001
86 IN
EMPTY
1.50
B B
1 R5B3 2 USB_OC_BACK_RIGHT* 38
OUT
15K 5%
402 CH
2
R5B2
10K
5%
CH CAD NOTE:
402 PLACE AS CLOSE AS POSSIBLE
RT5B3 1 TO USB CONNECTOR
1 2 VREG_USB_BP_RIGHT OUT 45
THRMSTR
1.50
2 1 C5A5
1 C5B1 1 C5A2
R5B1 470UF 470UF 470PF
10%
10K 20% 20% 50V
5% 10V 10V 2 X7R
CH 2 EMPTY
RDL 2 ALUM
RDL 603
A 402 A
1
VREG_USB MUST BE SPLIT
AMONSGT ALL USB CHANNELS.
DO NOT DAISY CHAIN
DRAWING
D915PLWDL_FABA.SCH_1.91 INTEL DOCUMENT NUMBER PAGE REV
[PAGE_TITLE=USB_BP_RIGHT/LEFT PS2] Thu Apr 07 00:17:31 2005
CONFIDENTIAL D16704 91 1.00
8 7 6 5 4 3 2 1
CR-92 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE92
8 7 6 5 4 3 2 1
D
D
CAD NOTE:
OVERLAPPING SITE.
DESIGN NOTE:
C DUAL-SITE INCLUDED TO FORCE FOOTPRINT KEEPOUT: C
UN-STUFFED, BUT MAY BE USED IN PRODUCTION DESIGNS.
ADJ
U10E2
MC33269
2 IN OUT 3
ADJ
1 SM
B B
U10E1
EZ1086
OUT 2 V_3P3_STBY\G 29 38 39 40 41 43 55 56 73 74
V_5P0_STBY 3 OUT 79 87 88 90 93 95 99
86 IN IN
OUT 4
ADJ/GND 1 C9E1
1 C9D6 3.3V 1 EMPTY 220UF
1.0UF 20%
20% 25V
ELEC
2 10V 2 RDL
Y5V
603
1
R10E2
274
1%
CH NOTE:
402
2 EMPTY FOR EZ1086
I_ADJUST_R STUFF FOR MC33269
A A
1
C9E5 1
.1UF R10E1
20%
25V 453 NOTE:
EMPTY 1%
603
2
[PAGE_TITLE=3.3V STANDBY]
DRAWING
D915PLWDL_FABA.SCH_1.92 INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE Thu Apr 07 00:17:49 2005
CONFIDENTIAL D16704 92 1.00
8 7 6 5 4 3 2 1
CR-93 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE93
8 7 6 5 4 3 2 1
STITCHING CAPS
92 IN V_3P3_STBY\G
VCC VCC3 +12V
C7H6
1 2
86 IN V_5P0_STBY
.1UF 20%
C2F10 C8E8 25V
1 2 1 2 EMPTY
D 603
.1UF 20% .1UF 20% C1G1 D
C7H10 25V 25V 1 2
1 2 EMPTY
603
EMPTY
603 .1UF 20%
.1UF 20% 25V
1 C9D8 EMPTY
25V C9F2 C9D4 22UF 603
Y5V 1 2 1 2 20%
603 25V C5C6
.1UF 20% .1UF 20% 2 RDL
EMPTY
1
C9H1
2
1 2
25V 25V
EMPTY EMPTY .1UF 20%
603 603 .1UF 20% 25V
25V EMPTY
VCC EMPTY 603
+12V "THMNT ALUM ELEC" 603
1
C7B4 2 C9C4
C9C8
1 2
1 2
20% .1UF .1UF 20%
25V 25V .1UF 20%
Y5V EMPTY 25V
603 603 EMPTY
603
C7H12 C9E10
1 C6B7
2
C8B9
2 1 1 2
94 IN 5VDUAL
1 2
.1UF 20% .1UF 20% .1UF 20%
.1UF 20% 25V 25V 25V
25V EMPTY EMPTY 1 EMPTY
C Y5V 603 603 1 C5B2 603 C
603 C1J4 .1UF
.1UF 20% 1 C5C10
2
94 IN 5VDUAL 2
C7H13
1 1 C9D2
2 20% 25V
2 25V 2 Y5V
Y5V 603 .1UF 20%
20% .1UF .1UF 20% 603 25V
+12V 25V 25V EMPTY
EMPTY EMPTY 603
603 603
C4J8 C9E2
1 2 1 2
1 C7B3 2
.1UF 20% .1UF 20%
25V .1UF 20% 25V
Y5V 25V EMPTY
603 EMPTY 603
603
VCC3
VCC VCC
VCC
B B
1 C9C2 2
.1UF 20%
25V C8E2 C9E3
EMPTY 1 2 1 2
603
.1UF 20% .1UF 20%
C9H6 25V VCC3 25V
1 2 Y5V EMPTY
C6B18
1 2 603 603
.1UF 20%
25V .1UF 20%
EMPTY 25V C9C6
603 EMPTY 1 2
603
C6B6 .1UF 20%
1 2 25V
EMPTY
.1UF 20% VCC3 603
25V
1 C2F9 2
EMPTY C7G13
1 2
603
.1UF 20% .1UF 20%
1 C9D3 2 25V
EMPTY
25V
EMPTY
603 603
C1J7
.1UF 20% 1 2
A 25V VCC A
EMPTY
603 .1UF 20%
25V
EMPTY
C8J1 603
1 2 2
C6C2
.1UF 20% 1 C8D2 2 .1UF
25V 20%
25V
EMPTY .1UF 20% 1 Y5V
603 25V 603
EMPTY
603 FOR HBL_66 TRANSITION
1 C9G3 2
.1UF 20%
25V
EMPTY
603
[PAGE_TITLE=VREG_DCPL_BULK]
DRAWING
D915PLWDL_FABA.SCH_1.93 INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE ROOM=DCPL_BULK
BOM=VREG_DCPL_BULK
Thu Apr 07 00:17:35 2005
CONFIDENTIAL D16704 93 1.00
8 7 6 5 4 3 2 1
CR-94 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE94
8 7 6 5 4 3 2 1
SLP_S3#
PS_ON#
D
D
3 Q9H1
VCC D PMOSFET
MIN 100MS BOM NOTE:
MAX 500MS MOD FILE CHANGE TO
1
G S USE IPN C58707-001
PWRGD_PS 2
120MS
PWRGD_PS# PWRGD_3V(SIO) Q9G1
AND'D W/
SLP_S3
C
P-CHANNEL
4.5A 1.0 C
L_BF_CUT# RDS~50MOHMS FDC638P
FORWARD BODY 3 GATE DRN 1
DIODE D->S DRN 2
+12V DRN 5
4 SOURCE DRN 6
USB_NCH NFET OFF
EMPTY
+5VSB 86 V_5P0_STBY
IN
USB_PCH PFET ON
5VDUAL 47 81 85 91 93
VREG_USB_PCH OUT
90 IN
B B
2
D Q5H1
NOTE: .1 INCH COPPER ON
90 IN VREG_USB_NCH 1 DRAIN AND SOURCE
G S
FET
3
C16435-001
VCC
STMICRO
D40NF3LL
40A - <11MOHMS
A A
[PAGE_TITLE=5VDUAL/USB_BP_MID]
DRAWING
D915PLWDL_FABA.SCH_1.94 INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE Thu Apr 07 11:31:29 2005
CONFIDENTIAL D16704 94 1.00
8 7 6 5 4 3 2 1
CR-95 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE95
8 7 6 5 4 3 2 1
1
C1F3 1
1.0UF C1F10 402
10% 1 2 EMPTY
6 IN H_VID<5..0> 16V
CPU_PWRGD_FET_SOURCE
X5R 5%
805 680PF 5% 0
603
2
50V
R1E7 CAD NOTE: EMPTY R1F19
1 2 PLACE AS CLOSE TO SE CORNER U1F1
ADP3168
VCC_IN_CPU_VREG
R1F34 2
0 5% OF CPU SOCKET AS POSSIBLE 1 2
402 EMPTY 4 1 VID4 VCC 28 3
3 2 VID3 PWM1 27 511K 1% Q1F2
603 EMPTY
2 3 VID2 PWM2 26 EMPTY
1
VSS_VRM_SENSE 1 4 VID1 PWM3 25 201924-001
6 IN 0 5 VID0 PWM4 24 2
SOT23 R1E5
5 6 VID5 SW1 23 I_PWM1_SW1 1 2 VREG_PWM1_SENSE IN 96
C1F9 7 22 I_PWM1_SW2
VCC_VRM_SENSE 1 2 VCC_SENSE_FB 8
FBRTN SW2
21
1K 5% VREG_PWM2_SENSE IN 96
6 IN FB SW3 I_PWM1_SW3 402 CH
CPU_VREG_COMP 9 COMP SW4 20 I_PWM1_SW4 VREG_PWM3_SENSE IN 97
820PF 20% C1F6 VCCP_12V_PWRGD 10 19 R1F27 R1F30
R1F22
50V 1 2 11
PWRGD GND
18 1 1 2 1 2 VREG_PWM4_SENSE IN 97
C X7R EN CSCOMP CPU_VREG_CSCOMP 2 C
603 VREG_DELAY 12 DELAY CSSUM 17 CPU_VREG_CSSUM 0 5%
CH
39PF 5%
50V
VREG_RT 13 RT CSREF 16 C1F1 28K 1% 64.9K 1%
402
NPO 14
VREG_RAMPADJ RAMPADJ ILIMIT 15 1 2 402 CH 402 CH R1F23
603 CPU_VREG_CSCOMP_THERMISTOR 1 2
C1F5 R1F32 IC 1800PF 5%
97 96 VCCP 1 R1E1 2 1 R1F29 2 1 2 CPU_VREG_COMP_PN1 1 2
25V COG
1 CAD NOTE:
2K
402
5%
CH R1F16
IN 603
603
1
0 5% 931 1% X7R 5.6K 1% 96 IN
VCCP_VREG_CNTL_CSREF
RT1D1
2
402 EMPTY 603 CH 560PF 10% 97
50V 402 CH C1F2 THRMSTR 2K 5%
CAD NOTE: 1 2 PLACE 1 R1F15 2 402 CH CPU_VREG_CSSUM_R
1 A63992-003
VTT_PWRGD CLOSE TO
PLACE AS CLOSE TO SE CORNER 95 IN 1.21K 1% 1 R1F13 1 R1F10 1 R1E6
R1F33 2200PF 5% INDUCTOR 603 CH 1 R1F17
OF CPU SOCKET AS POSSIBLE 603 25V 2 75K 75K 75K
243K COG 75K 1% 1% 1%
1% 1%
1 1 2 2 2
CH 1 R1F31 2 CH
CH CH CH
1 C1F15 VREG_ILIM_R VREG_ILIMIT 402 402 402
C1F7 R1F35 R1F36
1
603 .01UF 1 2
OUT 96 97 402
.039UF 453K 110K 2 10%
10% C1F14 1 0 5%
1% 5% .01UF 50V
16V 10% 2 X7R 402 CH
2 X7R CH CH R1F37
402 603 2 50V 603
603
2 2 EMPTY
603
150K
1% 92 IN V_3P3_STBY\G
95 IN A_GND CH
402 95 7 OUT VTT_PWRGD 1 R2F46
2 C1F8 10K
B 95 IN
A_GND 1 2 5% B
R1G3 2 CH
100.0PF 5% 1 2
R1F38 50V 2.2K 5%
402
1 2 A_GND COG
95 402 CH
OUT 603
0OHM EMPTY
SM
PWRGD_3906_5_6
CAD NOTE: 1
402
SINGLE POINT CONNECTION BETWEEN GND AND CH
A_GND CLOSE TO CONTROLLER. 5%
1K
DESIGN NOTE: R2F39
EMPTY SITE (PADS OVERLAP) 2
Q2F4 3 6
PWRGD_3906_5_5_R 5 Q2F4 2
VTT_OUT_RIGHT 92 IN V_3P3_STBY\G IC IC
86 IN V_5P0_STBY 7 IN 4 1
1
C1G14 SOT23 2 VTT_OUT_LEFT 1 R2F47 1 R2F43
.1UF 7 IN
20% CPU_PSC_XSTR_GATE 1 Q1G1
MMBT3906
1 R1F46 1
37.4K
1%
10K
5%
16V 0
2 EMPTY EMPTY 5% 2 CH 2 CH
402 1 1 3 101421-601
2 CH R1F47 402 402
R1G1 R1F39 402 2 0 PWRGD_INT_6_2
2.7K 10K 5%
A 5% 5% EMPTY
A
PWRGD_3904_2_3
EMPTY EMPTY 402
402 402 Q2F5
2 2 MBT3904DUAL 3 6
CPU_TJS_HI
SOT23 2 R1F40 1 PWRGD_FET_PN2 5 2
LOAD_LINE_SELECT OUT 95
1 4.7K 5%
R2F41 3 402 CH 2 C2F13
6 LL_ID0 2 1 1 Q2F3 R1F43 1
C2F14
1 R2F45
4 1 XSTR
IN CPU_SELECT_XSTR_GATE
8 7 6 5 4 3 2 1
CR-96 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE96
8 7 6 5 4 3 2 1
D
D
98 86 IN VREG_12V_FILTERED
1 C87580-001 1206 1 1 1206 1 1206
CR4B1 3 EMPTY EMPTY X5R
1N4148 16V 16V 16V
SOT23 D Q4B4 20%
4.7UF
20%
4.7UF 2
20%
4.7UF
3 DIO
201593-001 3 C3B1
2 2
C4B10 C4B9
D Q3B1
VREG_1_BST 1 SOT L3B2
G S
FET 245NH
1 C4B5 2 1 1 2
.22UF G S
10% EMPTY IND
16V 2
2 X7R
U4B1
ADP3418
805
L3B1
1 8 2 R4B7 1 VREG_PWM1_G_DRV_H 250NH
BST DRVH VREG_PWM1_G_DRV_H_R
C4B8
95 IN VREG_PWM1 2 IN SW 7 VREG_SW1_OUT 0 1A 603
1 2 VCCP OUT 96 97 17 30 79 95 98
95 IN VREG_ILIMIT 3 OD* PGND 6 805 CH 1 X7R
EMPTY
50V
4 VCC DRVL 5 VREG_PWM1_G_DRV_L C50935-001 C50935-001 20% 1
2 2 4700PF
C 1206 IC 603
Q4C2 R3N1 R3C1 VCCP_VREG_CNTL_CSREF C
1 X7R
16V
1 EMPTY
50V
D
D Q4C1 2 0OHM 1 2
OUT 96 97 95
10% 10% VREG_SW1_GND
EMPTY 10 5%
1UF 1000PF 1 SM 402 CH
C4B3 C4B7
2 2 1 LS 1 R4B14 2
G S
EMPTY S
LS 2.2
G FET 5%
3 3
R4B13 1 CH
805
VREG_PWM1_SENSE OUT 95
2 VREG_PWM1_G_DRV_L_L 2
1A 0
CH 805
98 86 IN VREG_12V_FILTERED
1206 1206 1206
1 EMPTY 1 X5R 1 EMPTY
16V 16V 16V
C87580-001 C87580-001
1 3
20%
4.7UF
20%
4.7UF
20%
4.7UF
CR1E1
B 1N4148 D Q1D1 2
C1C1
2
C1C3
2
C1C4
B
SOT23 3
3 DIO
D Q1C2
VREG_2_BST 1 SOT
G S
EMPTY
1 2 L1D2 245NH
C1E5 1
S
SOT
.22UF G FET 1 2
10%
2
2
16V
X7R
IND
U1E1
ADP3418
805
L1D1
1 VREG_PWM2_G_DRV_H_R
8 2 R1E4 1 250NH
BST DRVH VREG_PWM2_G_DRV_H
95 IN VREG_PWM2 2 IN SW 7 VREG_SW2_OUT
0 1A 603
1 2 VCCP OUT 96 97 17 30 79 95 98
95 IN VREG_ILIMIT 3 OD* PGND 6 805 CH 1 X7R
50V EMPTY
4 VCC DRVL 5 VREG_PWM2_G_DRV_L C50935-001 C50935-001 20%
2 2 4700PF VCCP_VREG_CNTL_CSREF
1206 IC 603
D Q1D2 C1E3 1 2 R1D1 OUT 96 97 95
1 X7R 1 EMPTY D Q1E1 2 1 10 5%
16V 50V VREG_SW2_GND 402 CH
10% 10%
1 R1R1
1UF 1000PF 0OHM
C1E2 C1E4
2 2 1 LS 1 R1E3
G S LS 2.2 EMPTY
FET G S
EMPTY SM
3 3
5%
2
CH
A R1E2 805 A
2 1 VREG_PWM2_G_DRV_L_L 2
1A 0 VREG_PWM2_SENSE
CH 805 OUT 95
[PAGE_TITLE=VCCP VREG]
DRAWING
D915PLWDL_FABA.SCH_1.96 INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE Thu Apr 07 20:49:18 2005
CONFIDENTIAL D16704 96 1.00
8 7 6 5 4 3 2 1
CR-97 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE97
8 7 6 5 4 3 2 1
D
VREG_12V_FILTERED D
98 86 IN
C87580-001 1 1 C1B4 1 C2B2
3 C1B3
C87580-001
1
CR2B1 D Q1B2 3
4.7UF
20%
4.7UF
20%
4.7UF
20%
1N4148 2 16V 2 16V 2 16V
SOT23
DIO
D Q1B1 X5R
1206
EMPTY
1206
EMPTY
1206
3
1 SOT
VREG_3_BST G S
FET
2 1 SOT
1 G S
EMPTY L1B2
C2B4
.22UF 2 245NH
10% 1 2
2 16V
X7R IND
U2B1 805 CH 805
ADP3418 L1B1
1 8 21A R2B1 0 1 250NH
BST DRVH VREG_PWM3_G_DRV_H_R VREG_PWM3_G_DRV_H
95 IN VREG_PWM32 7 VREG_SW3_OUT 1 2 VCCP 96 97 17 30 79 95 98
VREG_ILIMIT 3
IN SW
6 OUT
95 IN OD* PGND
4 5 VREG_PWM3_G_DRV_L 1 EMPTY
VCC DRVL C50935-001 C50935-001 C2B7
2 4700PF 1 R1B1 VCCP_VREG_CNTL_CSREF
IC
C D Q2B6 2 20%
50V
1 2
OUT 96 97 95
C
1
C2B1
1
C2B5 D Q2B5 2 X7R
603
R1N1
0OHM 10
402
5%
CH
1000PF VREG_SW3_GND
1UF
10%
10% 1
50V 1 EMPTY
2 16V 2 EMPTY LS R2B4 SM
X7R 603 G S
EMPTY 1 LS 2.2 2
1206 3 G S
FET 5%
3 CH
2 R2B2 1 VREG_PWM3_G_DRV_L_L 805
1A 0
2 VREG_PWM3_SENSE
OUT 95
CH 805
98 86 VREG_12V_FILTERED
IN
C87580-001 C2A15 1 C3A15 1 1
3 C87580-001 4.7UF C2B6
1 20% 4.7UF
CR3B1 D Q2B1 16V 20%
4.7UF
20%
1N4148 3 X5R 16V 16V
1206 2 2
B SOT23 D Q3B6 EMPTY 2
1206
EMPTY
1206
B
3 DIO
1 SOT
VREG_4_BST G S
EMPTY
2 1 SOT
1 G S
FET
L2B2
C3B6 2 245NH
.22UF
10% 1 2
16V
2 X7R IND
U3B1 805 R3B4
ADP3418
CH 0
L2B1
1 BST DRVH 8
VREG_PWM4_G_DRV_H_R 2
1A
1 805 VREG_PWM4_G_DRV_H 250NH
VREG_PWM4
95 IN 2 IN SW 7 VREG_SW4_OUT 1 2 VCCP OUT 96 97 17 30 79 95 98
95 3 6
IN VREG_ILIMIT
OD* PGND
VREG_PWM4_G_DRV_L
1 EMPTY
4 VCC DRVL 5 C50935-001 C50935-001 C3B7
2 4700PF R2C1
1206 IC 1 VCCP_VREG_CNTL_CSREF
1 X7R D Q3B3 2 20%
50V
1 2 OUT 96 97 95
16V 1
C3B5 D Q3B5 2 X7R
R2B3
0OHM 10 5%
10% 1000PF 603 402 CH
1UF VREG_SW4_GND
C3B2 10% 1
2 2
50V 1 LS EMPTY
EMPTY
G S 1 R3B5 SM
603 EMPTY LS 2.2 2
3 G S
FET 5%
3 CH
A 2 R3B3 1 VREG_PWM4_G_DRV_L_L 805 A
2 VREG_PWM4_SENSE 95
1A 0
OUT
CH 805
[PAGE_TITLE=VCCP VREG]
DRAWING
CORE PAGE D915PLWDL_FABA.SCH_1.97 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 20:48:33 2005
CONFIDENTIAL D16704 97 1.00
8 7 6 5 4 3 2 1
CR-98 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE98
8 7 6 5 4 3 2 1
CAD NOTE: PLACE AS MANY 1206 CAPACITORS AS POSSIBLE WITHIN CPU CAVITY
644066-024
97 96 IN VCCP
D
1 1 1 1 1 1 1 1 1 1 D
C3D4 C2D12 C2D1 C3D3 C3D6 C2D10 C3D5 C2D9 C3D1 C2D4
10.0UF 10.0UF 10.0UF 10.0UF 10.0UF 10.0UF 10.0UF 10.0UF 10.0UF 10.0UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 EMPTY 2 EMPTY 2 X5R 2 EMPTY 2 EMPTY 2 X5R 2 X5R 2 X5R 2 EMPTY 2 X5R
1206 1206 1206 1206 1206 1206 1206 1206 1206 1206
1 1 1 1 1 1 1 1
C2D3 C3D2 C2D11 C2D2 C2D7 C2D6 C2D5 C2D8
10.0UF 10.0UF 10.0UF 10.0UF 10.0UF 10.0UF 10.0UF 10.0UF PLACEMENT NOTE FOR 1206:
20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
2 6.3V
2 6.3V
2 6.3V
2 6.3V
2 6.3V
2 6.3V
2 6.3V PLACE 18 INSIDE CPU SOCKET (STUFF ALL)
EMPTY EMPTY EMPTY X5R X5R X5R X5R X5R
1206 1206 1206 1206 1206 1206 1206 1206
C C
B B
1 C1D1 1 C1E6 1 C1E1 1 C3C3 1 C3C2 1 C3C1 1 C1C2 1 C2C1 1 C2C3 1 C2C2
560UF 560UF 560UF 560UF 560UF 560UF 560UF 560UF 560UF 560UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
ALUM ALUM EMPTY ALUM EMPTY EMPTY EMPTY ALUM EMPTY ALUM
2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL
VREG_12V_FILTERED OUT 86 96 97
A A
8 7 6 5 4 3 2 1
CR-99 : @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE99
8 7 6 5 4 3 2 1
V_5P0_STBY V_3P3_STBY\G
86 IN IN 92
1 1
V_5P0_STBY R8F28 R8F29
NOTE: 10K 10K
86 IN 5% 5%
STUFF 10K RESISTOR
EMPTY EMPTY
NOTE:
STUFF 10K RESISTOR
IF HECETA IS LM96000 402 402 IF HECETA IS EMC6D103
OR ADT7476
2 2 2 2 2
HW_WARNING 99
D R8E5 R8E4 R8E16 OUT 100
10K 10K 10K D
5% 5% 5%
2 EMPTY EMPTY EMPTY
VCC=V_5P0_STBY
402
EMPTY 402 402 402
1 1 1 U8E1
5% 74AHCT1G08
1K 1
USB_BACK_NET13
R8F27 4 1 R8E20 2
USB_BACK_NET 12
1 USB_BACK_NET14 2 100 5%
EMPTY 402 EMPTY
VCC=5 1
C8E10
GND=3 4.7UF
20%
16V
2 EMPTY VCC=V_5P0_STBY
1206 USB_BACK_NET7 Q8E1
USB_BACK_NET15
U8E2 MBT3906DUAL 3 6
74AHCT1G08
USE VERSION 3 1 1
2 4 USB_BACK_NET0
1 R8E11 2 USB_BACK_NET6
5 2
USB_BACK_NET8
402 EMPTY 3 402 R8F21 2 100 5%
10K 5%
Q8F5 EMPTY 1K EMPTY 402 EMPTY
EMPTY 5% VCC=5 EMPTY
59 38 BI USB_BACK1* 1
USB_BACK1#_R SOT23
5% 4 1
2 1 2
10K EMPTY GND=3
R8F7 201924-001
R8E6 402
2
1
C USE VERSION 3 Q8E4 C
USB_BACK_NET11
3 MBT3906DUAL 3 6
402 EMPTY Q8F4
10K 5% EMPTY 1 C8E3 R8E10 5 2
BI USB_BACK1 1
USB_BACK1_R_R SOT23 100UF 1 2 USB_BACK_NET10
2 1 20% USB_BACK_NET5
2 25V 1K 5%
R8F8 201924-001
402 EMPTY
2 EMPTY EMPTY
38
RDL 4 1
59
VCC=V_5P0_STBY
R9E7 USB_BACK_NET9
1 2
1K 5% 2
402 EMPTY
U9E1
74AHCT1G08 R9E8
V_5P0_STBY 2 R9E9 1 USB_BACK_NET16
1 R9E10 100
86 IN USB_BACK_NET3
4 USB_BACK_NET2 1 2 5%
10K 5% EMPTY
402 EMPTY 2 100 5% 402
2 EMPTY 402 EMPTY 1
B 402 VCC=5 1 B
EMPTY C9E8
GND=3 4.7UF VCC=V_5P0_STBY
5% 20%
1K 16V
R8F26 2 EMPTY U9E2
1206 74AHCT1G08
1 1
4 USB_BACK_NET4
USB_BACK2_NET 2
EMPTY
VCC=5
USE VERSION 3 1 GND=3
3 R9E11
402 EMPTY Q8F6 1 1K
10K 5% USB_BACK2#_R EMPTY 5%
BI USB_BACK2* 1 SOT23 R9E3 EMPTY
1 2 1K 402
R8F25 2 USE VERSION
201924-001
3 5% 2
EMPTY USB_BACK_NET1
U9F3
402 EMPTY 3 74LVC2G53
Q8F7 402
10K 5% EMPTY 2 1 C9E4
HECETA_PIN22_2.5V 1 5 HW_SW_WARNING_SEL
USB_BACK2 USB_BACK2_RR
1 SOT23
100UF 79 OUT COM A IN 40
BI 1 2 20%
2 25V
2 6 SW_WARNING
R8F24 201924-001 EMPTY INH Y2 IN 73 1
2 RDL
38
3 7 HW_WARNING R9F13
1 C9F4 GND Y1 IN 99 100
10K
59
100.0UF V_5P0_STBY
A 20% 4 GND VCC 8 5% A
25V IN 86
EMPTY
EMPTY 402
2 RDL REV=1 EMPTY 2
DRAWING
DOCUMENT NUMBER PAGE REV
D915PLWDL_FABA.SCH_1.99 INTEL
Thu Apr 07 11:26:54 2005
CONFIDENTIAL D16704 99 1.00
8 7 6 5 4 3 2 1
CR-100
8: @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE100
7 6 5 4 3 2 1
86 IN V_5P0_STBY
2 2 2
R8E13 R8E15 R8E12 HW_WARNING OUT 99
10K 10K 10K
5% 5% 5%
D EMPTY EMPTY EMPTY
VCC=V_5P0_STBY
402 402 402 D
1 1 1
U8F3
USB_BACK_NET30
2 74AHCT1G08
1 R8F20
R8F30 1
4 USB_BACK_NET29 2 USB_BACK_NET28
1K
5% USB_BACK_NET31 2 100 5%
EMPTY
EMPTY 402 EMPTY
402 VCC=5 1
1 GND=3 C8F16 VCC=V_5P0_STBY
4.7UF Q9F3
20%
USB_BACK_NET19 16V U8F2 MBT3906DUAL 3 6
2 EMPTY 74AHCT1G08
1206 1
4 1
USB_BACK_NET27
R8F6 2 5
USB_BACK_NET26 2
USB_BACK_NET17
2 100 5%
EMPTY 402 EMPTY
Q8F1 VCC=5 4 1 EMPTY
USB_BACK_NET25
MBT3906DUAL 3 6 GND=3
USE VERSION 3
1 R8F5
3 1 5
2 USB_BACK_NET18 2
402 EMPTY Q7F1 R8E25
10K 5% USB_BACK_NET34 EMPTY 1K 1K 5%
45 38 BI USB_BACK3* 1 SOT23 5% 402 EMPTY
1 2
2 I32 EMPTY 4 1 EMPTY
C R8F23 201924-001 402 C
USE VERSION 3 1 402 2
EMPTY USB_BACK_NET32
3 VCC=V_5P0_STBY
402 EMPTY Q7F2 5% 1 C9E7
10K 5% EMPTY 10K 100UF
USB_BACK_NET20
45 38 BI USB_BACK3 USB_BACK_NET33 1 SOT23 R8F2 20%
25V
1 2
2
R7F2
2
201924-001 2 EMPTY
RDL
U9F1
V_5P0_STBY 74AHCT1G08 2
2 R9F2 1USB_BACK_NET21
1
86 IN R9F10
1 R9F20 2
4 USB_BACK_NET22 USB_BACK_NET23
10K 5% 100
402 EMPTY 2 100 5% 5%
EMPTY 402 EMPTY EMPTY
VCC=5 402
2 R9F9 GND=3 1 1
1K C9F3
5% 4.7UF
20%
1 EMPTY
2 16V
86 IN V_5P0_STBY 402 EMPTY
1206
B 2 B
R8F22
1K VCC=V_5P0_STBY
5%
EMPTY U9F2
402 74AHCT1G08
1 1
4 USB_BACK_NET24
USB_BACK_NET35 2
EMPTY
VCC=5
GND=3
USE VERSION 3 2
402
402 EMPTY 3 EMPTY
Q7F4 1
10K 5% EMPTY 402 5%
45 38 BI USB_BACK4* USB_BACK_NET37 1 SOT23 EMPTY 10K
1 2 R8F19
2 5%
201924-001
10K 1
R7F3 USE VERSION 3 R9F3
3
2 USB_BACK_NET36
402 EMPTY Q7F3
10K 5% EMPTY
45 38 BI USB_BACK4 USB_BACK_NET38 1 SOT23
A 1 2 2 1 C9F1 A
R7F1 201924-001 100UF
20%
25V
EMPTY
2 RDL
8 7 6 5 4 3 2 1
CR-101
8: @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE101
7 6 5 4 3 2 1
7 IN VTT_OUT_RIGHT
1 1 1 1 1 1
D 1 1
1
C2F3 C2F4 R2F12 R2F9 R2F14 R2F15 R2F10 R2F13
.1UF .1UF 49.9 49.9 49.9 49.9 49.9 49.9 D
UNSTUFF FOR R2F33 10% 10% 1% 1% 1% 1% 1% 1%
49.9 2 16V 2 16V
CH CH CH CH CH CH
ITPUSB 1% X7R X7R
2 2 2 1 2 603 603 402 402 402 402 402 402
EMPTY 2 2 2 2 2 2
R2E3 R2F26 R2E1 R2F8 R2E2 402
49.9 49.9 49.9 49.9 49.9
2
1% 1% 1% 1% 1%
5
1
3
CH CH CH CH CH H_BPM<5..0>*
402 402 402 402 402 BI 7 101
1 1 1 2 1 TESTIN* BI 15 101
H_TDO IN 7
H_TDI OUT 7 101
H_TMS OUT 7 101
H_TCK OUT 7 101
H_TRST* OUT 7 101
C CAD NOTES: C
XTG ROUTING RULES: CAD NOTES:
NOA MATCH LENGTHS WITHIN 50PS *
BPM MATCH LENGTHS WITHIN 50PS * PLACE BPM TERMINATION NEAR CONNECTOR
IDEALLY INCLUDE PACKAGE LENGTHS PLACE TCK/TDI TERMINATION NEAR CPU
NO LENGTH GUIDELINES FOR TCK, WITHIN 1.5" OF CPU, IDEALLY NEXT TO IT.
TDI, TDO, TRST, TMS J2T1 PLACE TDO TERMINATION NEAR CONNECTOR
XDP PLACE TRST* TERMINATION ANYWHERE ON ROUTE
FP_RST* 48 1.0
1 2 81 43 IN DBR
30 IN CK_H_XDP* R2T4 42 XDP_CLKN BPM5* 3 5
0 5% 40 XDP_CLKP BPM4* 5 4
402 EMPTY 39 PWRGOOD BPM3* 9 3
101 IN H_CPURST_XDP_R* 46 RESET* BPM2* 11 2
CK_H_XDP 1 R2T3 2 TP_XDP_PIN53 53 15 1
30 IN SCL BPM1*
0 5% TP_XDP_PIN51 51 SDA BPM0* 17 0 H_BPM<5..0>*
402 EMPTY 101 15 BI TESTIN* 41 TESTIN* OUT 7 101
EMPTY
XDP
DRAWING
D915PLWDL_FABA.SCH_1.101 INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE Thu Apr 07 00:59:02 2005
CONFIDENTIAL D16704 101 1.00
8 7 6 5 4 3 2 1
CR-102
8: @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE102
7 6 5 4 3 2 1
VCC
D 5V_FILTERED_MCH
D
PLACE NEAR
CONTROLLER VCC 1 C7B9
1000UF A65154-012
1 C7E9 C7D10 1 1 1 1
20%
10V PLACE + NODE NEAR
.1UF C7D7 C7D8 C7D9 2 ALUM HIGH-FET DRAIN
20% 4.7UF 10.0UF 10.0UF 10.0UF TH PLACE GND SIDE
25V 20% 20% 20% 20%
2 Y5V 10V 2 6.3V
2 6.3V
2 6.3V 2 CLOSE TO LOW-FET GND
603 EMPTY EMPTY X5R X5R
805 1206 1206 1206
V_1P5_CORE OUT 12 15 16 17 18 38
39 41 79 87 88
CAD NOTE:
PLACE CLOSE TO FET
+12V
1
C7D1 1
C 10.0UF C7E6 C
20% .1UF
6.3V
X5R 2 3 Q7D1 20%
25V
1 C7F1
470UF
1206 2 Y5V 20%
D 10V
1 603
ALUM
C8E4 2 RDL
1UF
BOM NOTE:
20%
16V
EMPTY 2
NEEDS 16V
1 R7E1 2 I_CORE_UGATE_R
1 FET 15A PART
G S
EMPTY ALL FOR APW & RT 805 10 5% L7E1
A87318-001
ISL6520
805 CH
SAYS USE 0-OHM
2 1
1UH
2
I_CORE_PHASE
I_CORE_COMP I_CORE_UGATE
IND
A83634-001 1 C7E8 1 C7E5
1 1 C7E7 1000UF 1 C7F4
20% .1UF
R8E17
5.6K
I_CORE_LGATE
3 Q7E2 1 560.0UF
20% 10V
EMPTY
4.7UF
20%
20%
25V
D R7E5 4.0V 2 TH 10V 2 Y5V
5%
2.2 2 ALUM 2 Y5V 603
CH ISL6520 SAYS USE 0-OHM 5%
RDL 805
603
2 CH
1 R7F6 2 1 FET 805
I_CORE_LGATE_R G S 2
0 1A I_CORE_PHASE_R
B 2 B
805 CH C28887-001
1 1
C7F13 C7E4
U7E1 1000PF 4700PF
I_CORE_COMP_R
1 C8E6
10% 20%
IRU3037A 2 50V
2 50V
1 470PF EMPTY X7R
C8E7 10% 1 603 603
8200PF
20% 2 50V
X7R 1 FB HDRV 5
50V 603 2 VCC VC 6
2 X7R 3 LDRV COMP 7
603 4 8
IRU3037/A (IR), GND SS I_CORE_SS
NEAR EACH OTHER
RT9209/A (RICHTEK) &
APW7037/A (ANPEC) IC PLACE THESE 3
HAVE SAME FOOTPRINT
AND PINOUT DEFAULT STUFFING: 1
C8E5
.1UF
IRU3037A 10%
A: 400KHZ, VFB=0.8V 16V
STD: 200KHZ, VFB=1.25V
2 X7R 562 GIVES .8V REF
603 TSTART=75*C (MS) AND 1.509V
133 GIVES 1.25V REF
I_CORE_FB AND 1.51V OUTPUT
1 R8F18 2
A A
562 1%
1 603 CH
1 C7E3 C7E1 1 R8E18
.1UF 4.7UF 634
C8F1
20% 20% 1% 1 R8E19 2 1 2
25V 10V I_CORE_FB_R
2 Y5V EMPTY 2 CH
0 1A
603 805 603 .1UF 10%
2 603 EMPTY 16V
EMPTY
603
DRAWING
D915PLWDL_FABA.SCH_1.102 INTEL DOCUMENT NUMBER PAGE REV
CORE PAGE Thu Apr 07 17:12:13 2005
CONFIDENTIAL D16704 102 1.00
8 7 6 5 4 3 2 1
CR-103
8: @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE103
7 6 5 4 3 2 1
D
D
1
RP8B1 2 RP8B1 3 RP8B1 4 RP8B1
22 22 22 22
5% 5% 5% 5%
.25W .25W .25W .25W
EMPTY EMPTY EMPTY EMPTY
SM 7 SM 6 SM 5 SM
8
PASSIVE_BLEED_PATH
3
Q8B1
BACKFEED_CUT EMPTY
74 1
IN
2
C C
VCC3
H_PROCHOT* OUT 8 6
VCC3
VCC3
TP_H_FORCEPH_N
1 R5B25
680
1 R5B33 1 R5B28 5%
2 EMPTY
Q5B4
4.3K 4.3K MBT3904DUAL 3 6
5% 5% 402
B 2 EMPTY 2 EMPTY R5B27 5 2 R5B26 B
603 603 1 2 1 2
H_THRM_THROT_D
1 R5B30 H_THRM_THROT_OUT 0 5% 0 5%
1K 402 EMPTY 402 EMPTY
5% 4 1 EMPTY
2 EMPTY
Q5B5
402
R5B32 1 MBT3904DUAL 3 6
1K
5%
H_THRM_THROT_P 5 2
EMPTY 2
402
4 1 EMPTY
1
1 R4C28 C5B9 H_T HRM_T HROT _P_R
.1UF
499 20% 1 R5B34
1% 16V 300
2 EMPTY
2 EMPTY 5%
402 402
2 EMPTY
603
H_THRM_THROT_BJT R5B35
1 2
7.5K 5%
603 EMPTY
1
A 402 A
R5B31 1 EMPTY
16V
EMPTY 20%
.1UF
CURRENT=UNKNOWN C5B6
2 2
CAD NOTE: PLACE
PLACE THERMISTOR INSIDE. VR THERMAL THROTTLE CIRCUITRY
THE VR PHASES.
8 7 6 5 4 3 2 1
CR-104
8: @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE104
7 6 5 4 3 2 1
TEST SITE
D
D
R5A1
TP_TEST03 1 2 TP_TEST04
10M 5%
603 EMPTY
202285-145
1 C8C4 1 1 1
22PF C6A2 C4J5 C7B2
10% 10PF 10PF 10PF
50V 5% 5% 5%
2 EMPTY 2 50V 2 50V 2 50V
402 EMPTY EMPTY EMPTY
603 402 402
C A36095-006 C
603275-109 A36094-001 A36094-001
1 C8D7 1 1 1
47PF C8D3 C8D1 C7B1
5% 15PF 22PF 10PF
50V 5% 5% 5%
2 EMPTY 2 50V 2 50V 2 50V
402 EMPTY EMPTY EMPTY
603 603 402
A36095-010
B 603275-110 603275-112 A36094-001 B
TP_ATEDUM_25 TP_ATEDUM_19
1 C8D6 1
39PF C5A1
5% 33PF
50V 5%
2 EMPTY 2 50V
603 EMPTY
603
603275-115
603275-114
TP_ATEDUM_26 TP_ATEDUM_20
A A
DRAWING
D915PLWDL_FABA.SCH_1.104 INTEL DOCUMENT NUMBER PAGE REV
Thu Apr 07 00:58:44 2005
CONFIDENTIAL D16704 104 1.00
8 7 6 5 4 3 2 1
CR-105
8: @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE105
7 6 5 4 3 2 1
D
D
C C
BLANK
B B
A A
DRAWING
D915PLWDL_FABA.SCH_1.105 DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:26 2005 INTEL
[PAGE_TITLE=1394A] CONFIDENTIAL D16704 105 1.00
8 7 6 5 4 3 2 1
CR-106
8: @WOODRIDGE_LIB.WOODRIDGE(SCH_1):PAGE106
7 6 5 4 3 2 1
D
D
C C
BLANK
B B
A A
DRAWING
D915PLWDL_FABA.SCH_1.106 INTEL DOCUMENT NUMBER PAGE REV
Wed Apr 06 22:21:26 2005 106 1.00
CONFIDENTIAL
8 7 6 5 4 3 2 1