Hardware Accelerator for Minimum Mean Square
Error Interference Alignment
Markus Kock Steffen Busch
Institute of Microelectronic Systems Institute of Cartography and Geoinformatics Institute of Microelectronic Systems
Leibniz Universitt Hannover Leibniz Universitt Hannover
Hannover, Germany Hannover, Germany
kock@ims.uni-hannover.de steffen.busch@ikg.uni-hannover.de
AbstractA dedicated hardware architecture for the digital
baseband processing of minimum mean square error interfer-
ence alignment is presented. The computationally intensive task
of calculating the precoding and decoding matrices has been
implemented and the underlying algorithm has been optimized
for real-time capability, efciency and exibility. The required
number of iterations has been optimized and appropriate low-
latency algorithms for the computation of basic operations
have been identied to meet a real-time constraint of 1 ms
processing latency. The architecture has been veried and syn-
thesized for a Xilinx Virtex-6 LX550T FPGA. The maximum
number of antennas, users and data streams is congurable
at synthesis time. The actual parameters are congurable
at runtime. Different degrees of parallelism allow a trade-
off between resource requirements, latency and throughput.
The target FPGA resources are sufcient for real-time system
congurations up to 5 users with 3 antennas.
Index TermsInterference Alignment; Hardware Accelera-
tor; Testbed;
I. INTRODUCTION
Channel capacity in multi-user wireless communication
systems is limited by interference. A well known approach
towards exploiting the available channel capacity is In-
terference Alignment (IA) [1]. Depending on the context
and application, different approaches to IA are feasible. A
multitude of different algorithms for IA in a variety of
applications and constraints exist to leverage system channel
capacity in multi-user (MU) multiple-input-multiple-output
(MIMO) systems [2]. The focus of this paper is on minimum
mean square error interference alignment as presented in [3].
Here, linear precoding and decoding matrices are applied at
the transmitter and receiver, respectively. From the hardware
point of view, current general purpose and Software-Dened
Radio (SDR) systems are unable to compute these precoding
and decoding matrices in real-time.
Due to its iterative nature and the required type of
operations, the computational complexity of this algorithm is
demanding, especially for mobile devices [4]. Thus, for high
data rate systems, a high throughput real-time Minimum
978-1-4799-8058-1/15/$31.00 2015 IEEE. 575
Holger Blume
Leibniz Universitt Hannover
Hannover, Germany
blume@ims.uni-hannover.de
Mean Square Error (MMSE) IA architecture is required.
Furthermore, the acceptable latency depends on the varying
channel. In this paper, the acceptable latency requirement is
assumed to be 1 ms for fast changing channels. The precod-
ing matrices have to be adapted to the time-varying channel
sufciently fast to achieve real-time operation. Especially,
outdated precoding matrices result in insufciently aligned
interference at the receivers. Thus, the channel has to be
tracked and the precoding matrices have to be updated at a
sufciently low latency. The energy budget for computing
one set of precoding and decoding matrices is limited,
especially in mobile high subcarrier count OFDM systems.
From the hardware perspective, previous testbeds focused
on demonstrating the real-world feasibility of Interference
Alignment with questions in system level integration and
algorithmics [5] [6] [7] [8] [9]. These testbeds have provided
the proof-of-concept for IA by leveraging rapid-prototyping
approaches to hardware implementation. However, real-time
capability for fast changing channels and hardware efciency
are not within the scope of these papers. Processing latency
and hardware resource requirements have usually not been
published. For real-world usage, highly efcient hardware
architectures with sufcient latency, throughput and power
consumption are required. Very few has been published
about resource-efcient digital hardware implementations
feasible for low-power and mobile devices. In this contri-
bution, we focus on efcient digital hardware architectures
for the computation of the linear precoding and decoding
matrices according to the Minimum Mean Square Error
criterion. An estimate of the computational complexity of
MMSE IA has been previously published in [4].
The rest of the paper is organized as follows. The system
model and MMSE IA algorithm are recapitulated in Sec-
tions II and III. Algorithm optimizations aiming at hardware
implementation are presented in Section IV. The hardware
architecture and synthesis results are discussed in Sections
V and VI, respectively.
 II. MIMO SYSTEM MODEL (0) Init V k

The interference channel model is shown in Fig. 1. K  1

users share a common transmission medium in a point-to- (1) U k = ( K f (V )) f (H, V k )
point communication scenario. Each transmitter TX multi- 
plies the vector of d discrete transmit data streams with a (2) Rk = K f (U )
precoding matrix V k and applies the result to Nt transmit
antennas. The receiver RXk applies the decoding matrix (3) k = 0
U k to the signals picked up by Nr receive antennas. The
received signal y i at each receiver i is (4) V k = (Rk + k I)
1
f (H, U k )

y i = H ii V i si + H ij V j sj + ni (1)
j=i (6) update k (5) P = V k 2F 1
with sj being the transmit data at transmitter j and ni
being the noise picked up by receiver i. H ii are the desired (7)
channels, all H ij convey interference. no |P | < ?

yes
7; 5;
(8) MSE
9 + 8
+  + 


(9)
7; 5; no MSE < ?


yes
+

9 + 8
nished
+


+

7; 5;
Fig. 2. MMSE IA algorithm owchart

+

9 + 8

IV. ALGORITHM OPTIMIZATION

Fig. 1. Multi-user 3 3 MIMO system with precoding matrices V j and Two reference software models have been implemented
decoding matrices U i in MATLAB using oating-point representation. Emphasis
was put on numerical stability by using MATLABs SVD-
III. MMSE IA ALGORITHM based pinv() function for matrix inversion and fzero()
The MMSE IA algorithm used to compute the precoding function for root-nding to solve for k . This MATLAB
and decoding matrices V and U is taken from [3]. This model serves as the base and verication reference for the
section presents the algorithm details required throughout algorithmic optimizations described below. The optimized
the rest of the paper. model serves as a reference for hardware verication.
Arbitrary initial values are chosen for the precoding The algorithm loop structure shown in Fig. 2 allows the
matrices V k in the rst algorithm step. Then, the decoding identication of the most often executed core operations. The
matrices U k are computed according to Eq. 2. In an iterative data dependencies dictate the sequential execution of the
process, the precoding matrices V k are updated according shown loops. The following optimization approaches have
to Eq. 3 based on the current set of decoding matrices. This been considered in order to achieve real-time execution with
outermost loop continues until convergence. For each update a maximum latency of 1 ms:
of V k , the Lagrange multiplier k 0 has to be chosen reduced number of loop iterations
iteratively to satisfy the transmit power scaling constraint use of low latency operations
V k 2F 1. parallelization
1 The required iteration counts of both loops in Fig. 2 are
K
Uk = H kj V j V H H 2
j H kj + I H kk V k (2) data dependent. Proper system setups within the bounds of
j=1
Nt = Nr = 2..11, d = 1..5, K = 3..19 were used to
1 simulate 100 random channels each. Evaluating the conver-
K
gence has shown that the nal channel capacity has been
Vk = HH H
jk U j U j H jk + k I
HHkk U k (3) reached within 1% after at most 100 iterations. Therefore,
j=1 the maximum number of outer loop iterations has been xed
Figure 2 shows the corresponding owchart. to 100.

576
 Now consider the inner loop. An explicit solution of
V k (k )2F = 1 can not be given. Therefore, the equation
has to be solved for k numerically. However, it can be
shown that a unique solution exists [3]. Several standard
root-nding approaches have been evaluated in this work
including Newton iterations, secant method and Brents
method. It must be noted that the standard algorithms do
not always nd the desired root for k 0, but instead
somtimes get stuck at negative k .
The knowledge about the function can be used to guar-
antee convergence and improve convergence speed, i.e. the
number of iterations in the numerical root-nding loop. We
propose a modied secant method. Based on the curvature of
the function, simple heuristic rules have been established for
a correction of the root estimated by the secant method. De-
pending on the system parameters, this reduces the number
of required iterations by a factor between 3 and 10 compared
to the unmodied secant method. The second modication
is the choice of the initial value for in step (3). If the last
accepted from the previous global iteration is reused as
the initial value, the average number of root-nding function
evaluations can be reduced to about 3.9. Fig. 3 shows the
number of iterations for the standard and optimized root-
nding algorithms. Representative system setups from the
space of proper setups as discussed above have been chosen
for simulation. The discrete setups are plotted on the x-axis.
80
Modied secant method
Secant method
Newtons iterations
60 Binary search
Iterations
40
20
0
0 20 40 60 80
Setup
Fig. 3. Average number of root-nding function evaluations vs. system
congurations
Matrix inversion is the most time-demanding operation in
the innermost loop in step (4) from a hardware perspective.
All matrix inversions shown in Fig. 2 have to be carried
out sequentially. The other required basic mathematical
operations are not discussed here in detail in order to focus
on the most latency-relevant operations. For example, the
matrix multiplications can be fully parallelized and require
577
only the delay of one real MAC operation and thus have a
small latency compared to matrix inversions.
Computing a decoding matrix U k in step (1) depends on
all matrices V k from the previous iteration. As there is no
data dependency between the computation of individual U k ,
they can be computed in parallel for all users. Steps (2)
through (7) update the precoding matrices V k , including
a numerical root-nding in steps (4) through (7). These
computations depend on all U k from step (1). It can be
noted that computing V k can also be parallelized across all
users.
V. HARDWARE ARCHITECTURE
A xed-point dedicated hardware accelerator has been
implemented for the use in an OCP- or AXI-based System-
on-Chip. Its structure is shown in Fig. 4. All processing
units and data ow is controlled by a top-level controller.
The outer loop from Fig. 2 and communication with external
memory is handled here. In the initialization phase, channel
matrices H and initial values for V are loaded from external
memory into an on-chip BRAM cache. Then, the matrices
V and U are updated iteratively according to Eq. 2 and 3 by
processing elements (PEs). Each PE handles the update of
either V or U for one user at a time, and up to K PEs work
in parallel. The number of instantiated PEs is congurable
at synthesis time. The MSE unit computes the total mean
square error for the current set of matrices in parallel to the
next matrix update. When a predened threshold has been
reached, the outer iteration loop is stopped.
Fig. 5 shows the block structure of a PE. It can be
congured to compute either an update of the encoding
matrix V or the decoding matrix U for one user according
to steps (1) or (2) to (7), respectively. Computing U requires
a subset of the hardware resources needed to compute V .
The matrix multipliers denoted as x sequentially compute
H kj V j V H H H H
j H kj or H jk U j U j H jk for all users j = 1..K
and sum up the result. The matrix multiplications can be
congured to either use three matrix multipliers in parallel
(nM M = 3) as shown in Fig. 5 or sequentially com-
pute the expressions above using a single matrix multiplier
(nM M = 1) to save resources. Each pipelined matrix
multiplier computes one full complex matrix multiplication
per clock cycle.
The latency of the equation system solver required in steps
(1) and (4) is crucial for the overall system latency. Several
approaches including LU- and QR-decomposition with back-
substitution as well as Singular Value Decomposition have
been evaluated for their achievable latency in hardware and
for precision in the context of this application.
Gaussian elimination has been chosen as the equation
system solver. The Bareiss algorithm [10] is a division-free,
integer-preserving variant of Gaussian elimination especially
suitable for low latency hardware implementation. Here,
division-free means that no divisions are required in the
elimination loop, the elimination is achieved with multiply +98 98
and add operations. Only one nal division is required per 3(98
result variable, but all divisions can be computed in parallel.
In this work, a two-step Bareiss algorithm Systolic Array
# #
Processor has been implemented as a tradeoff between re-
source requirements, stability and latency. Two variables are
eliminated per step, requiring two clock cycles. To achieve
sufcient numerical stability, a row-wise renormalization #
step has been inserted after each elimination using shifts,
requiring one additional clock cycle. Table I summarizes %
the required number of clock cycles per operation. M is the
data word length in bits. The worst-case evaluated system 
setup (Nt = Nr = 11, K = 19) requires a total of 26022
clock cycles including overhead, leading to a minimum clock    

frequency of 26.02 MHz for 1 ms latency. The hardware
implementation has been veried against the MATLAB
oating-point reference model. 

 !!!!"&

TABLE I
C LOCK CYCLES PER OPERATION (PE MODULE )   

Operation Clock cycles

Matrix mult. block, nM M = 3
Matrix mult. block, nM M = 1
Gaussian elimination (Bareiss)
Matrix norm
update

006(,$
K+1
3K Fig. 5. V/U Processing Element detail
2 Nt,r + M/2
2
3 + M/2
of parallelism. System K = 3, Nt = Nr = 2 and d = 1 is
the smallest feasible IA system. The system congurations
shown in Table II have been successfully mapped to the
target FPGA. System congurations with more users or
antennas require more DSP48E1 blocks than available on the
target FPGA. Although optimization and deeper pipelining
  could increase the throughput, the potential for an improved

  total latency is fundamentally limited by the logic depth in
the iterative loops.

 TABLE II




S YNTHESIS RESULTS FOR X ILINX V IRTEX -6 XC6VLX550T FPGA

K Nt,r d nP E nM M FF LUT DSP48E1

3 51,531 81,560 364
   3
 3 2 1
1
20,942 32,702 148
89 89 1 16,585 25,682 80
3 32,980 56,974 330
5 3 1 1
1 24,916 43,514 232
Available 687,360 343,680 864

Fig. 4. MMSE IA hardware accelerator top level block diagram
VI. SYNTHESIS RESULTS
The system has been synthesized for a Xilinx
XC6VLX550T-2 FPGA using Xilinx ISE 14.7. A 50 MHz
clock constraint was met for all congurations. It has been
chosen to enable the sequential computation of two sets
of matrices within 1 ms. Table II summarizes the resource
requirements for certain system congurations and degrees
VII. CONCLUSION
The minimum mean square error interference alignment
algorithm has been optimized for low latency hardware
implementability. The overall required operation count has
been reduced and the algorithm has been implemented on
an FPGA. It has been shown that the computation of the
precoding and decoding matrices is possible in hardware
under a real-time latency constraint of one millisecond. The
synthesis results show high DSP resource requirements even
for small system congurations.

578
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