Lecture Overview

Buses
Microprocessors & Interfacing Computer buses
I/O Addressing
Memory mapped I/O
Buses and Parallel Separate I/O
Input/Output Parallel Input/Output
AVR examples

Lecturer : Dr. Annie Guo

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Five Components of Computers Buses

A collection of wires through which data is
Computer transmitted from one of sources to destinations
Processor Memory Devices Keyboard source 1 dest 1

(active) (passive) Mouse

Input source 2 dest 2
Disk
Control (where
(brain) programs, source n dest n
data live Output Disk,
Datapath when Display, Basically buses consist of three parts:
running) data bus
(brawn) Printer
transfer actual data
address bus
transfer information about where the data should go.
control bus
Transfer control signals
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 Typical Computer Bus Structure Computer Buses
Parallel Serial
I/O I/O
CPU is connected to memory and I/O devices
Device Device via data, address and control buses.
Data bus is bi-directional and transfers
information (memory data and instructions,
I/O
CPU Memory
Interface I/O data) to and from CPU.
Address bus is most often unidirectional
Data Bus because CPU is the only source of the
Address Bus
addresses.
Control Bus Control bus carries all control signals required
to control the operation of the data transfer.

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Computer Buses (cont.) Input Interface

Each line of a bus has multiple sources and Connects multiple data sources
destinations. The bus transfers data from one Only one source data is sent to the bus at a time
source each time. Often implemented with three-state buffers for
Multiple Destinations data buses
For example,

a parallel, eight-bit input data is connected to eight three-
state gates whose enable lines are tied together
Data Bus When the data is to sent to the bus the eight three-state
CPU gates are enabled.
The open-collector gate is often used for
control signals such as request for interrupts
Since one way switch is often required.
Multiple Sources

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 Typical Bus Interface Gates Output Interface
Vcc
Data source input
Bus line
The output interface between the data bus
A Y and a destination or output device contains a
External latch.
G Pull-up
Resistor DBn

G A Y Open D Q
Collector Destination or
0 0 0 74116 Dual 4-bit
Output Device
0 1 1 Latch with Clear
1 0 X Clock
1 1 X C1
High
Impedance C2 CLR

(a) Three-state (b) Typical open-collector

gate gate
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Address Decoding for Input

Address Decoding
Devices
74LS139
The interface must provides the ability for 2-of-4
Decoder
CPU to select one of many sources and A1
A1
From
destinations. CPU A0 O0
A0 O1
The address decoder is used. Read O2
Control E
O3

Info Info Info Info

Source Source Source Source

To/From
CPU

Data Bus
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 Address Decoding for Output
CPU Timing Signals
Devices
74LS139
2-of-4 CPU must provide timing and synchronization
Decoder
A1
A1
so that the transfer of information occurs at
From
CPU A0 O0 the right time.
A0 O1
Write O2
CPU has its own clock.
Control E
O3 I/O devices may have a separate I/O clock.
Typical timing signals include READ and WRITE.

74116 74116 74116 74116

Dual 4-Bit Dual 4-Bit Dual 4-Bit Dual 4-Bit
Latch Latch Latch Latch

To/From
CPU

Data Bus
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Typical CPU Read Cycle Typical CPU Read Cycle

CPU places the address on the address bus
CPU Clock
at point A.
A The control signal READ is asserted at point
Address
Bus address from CPU valid B to signal the external device that CPU is
C
ready to take the data from the data bus.
Data Bus data from device
valid
CPU reads the data bus at point C whether
or not the input device has put it ready
READ
Control
If NOT, some form of synchronization is required.
Signal
B

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 Typical CPU Write Cycle Typical CPU Write Cycle
CPU places the address on the address bus at point
CPU Clock
A.
The data bits are supplied by CPU at point B.
A
Address The control signal WRITE is asserted by CPU at
Bus address from CPU valid
point C to signal the external device that the data is
B ready to be taken from the data bus.
Data Bus data from CPU This signal is used to create the clock to latch the data at the
valid
correct time.
WRITE Depending on the type of latch and when WRITE is
Control
Signal
asserted, the data may be captured on the falling
C D
edge or rising edge.

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Complete I/O Interface Complete I/O Interface (cont.)

Data Bus

READ and WRITE control the enable (E).

74LS139
2-of-4
Decoder
74LS244 Octal
Buffer
Three state enables and the latch clock
A1
signals are not asserted until the correct
A0
A1
O0
SOURCE_ADR_OK address is on the address bus AND the
A0 O1
Source correct time in the read or write cycle has
READ O2
E
O3
arrived.
74116 Dual
4-Bit Latch
Destination

A1
A1 DES_ADR_OK

A0 O0
A0 O1
WRITE O2
E
O3

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 I/O Addressing Memory Mapped I/O
If the same address bus is used for both The entire memory address space is divided
memory and I/O, how does hardware into memory space and I/O space.
distinguish between memory reads/writes and
I/O reads/writes?
Two approaches:
Memory-mapped I/O.
Memory
Separate I/O.
AVR supports both.

I/O

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AVR Memory Mapped I/O Memory Mapped I/O (cont.)

In AVR, 64 I/O Advantages:
registers are mapped Simple CPU design.
into memory space No special instructions for I/O accesses.
$0020 ~ $005F Disadvantages:
2 bytes I/O devices reduce the amount of memory space
With such memory available for application programs.
addresses, the The address decoder needs to decode the full
access to the I/Os address bus to avoid conflict with memory
uses memory access addresses.
type of instructions.

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 I/O Interface for Memory-Mapped
Separate I/O
I/O
ADR_OK Two separate spaces for memory and I/O.
Less expensive address decoders than those
Address to memory needed for memory-mapped I/O (Why?)
Bus Data Bus
Additional control signal, called IO/M, is
required to prevent both memory and I/O
ADR_OK
D Q
Information
Destination trying to place data on the bus
Decoder
to input devices
CL
simultaneously.
Information
IO/M is high for I/O use and low for memory use.
ADR_OK Source
Special I/O instructions are required.
READ
to output devices

WRITE

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I/O Interface for Separate I/O Separate I/O (cont.)

Data Bus
In AVR, 64 I/O registers can also be
Reduced addressed with separate addresses $00 ~
Address Bus
ADR_OK
$3F
Decoder
1 byte
IO_READ
With such separate addresses, the access to
Information Source -
memory
the I/Os uses I/O specific instructions.
READ
E.g. IN and OUT
IO/M

Information Source
input device

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 I/O Synchronization Software Synchronization
CPU is typically much faster than I/O devices.
Two software synchronization approaches:
Real-time synchronization
Therefore, synchronization between CPU and Uses a software delay to match CPU to the timing
I/O devices is required. requirements of the I/O device.
The timing requirement must be known
Two synchronization approaches: Sensitive to CPU clock frequency.
Software synchronization. Waste CPU time.

Hardware synchronization. Polling I/O

A status register, with a DATA_READY bit, is added to the
device. The software keeps reading the status register until
the DATA_READY bit is set.
Not sensitive to CPU clock frequency.
Still waste CPU time, but CPU can do other tasks.

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Handshaking I/O Input Handshaking Hardware

A hardware synchronization approach with control
signal READY or WAIT.
For an input device, when CPU is asking for input data, the To CPU WAIT INPUT DEVICE
input device will assert WAIT if the input data is NOT Wait State
available. When the input data is available, it will deassert Logic
WAIT. While WAIT is asserted, CPU must wait until this
DATA_REQUEST
control signal is deasserted. Data Register

For an output device, when CPU is sending output data via

the data bus, the output device will assert WAIT if it is not Address Bus INFO_ADD_OK
ready to take the data. When it is ready, it will deassert
WAIT. While WAIT is asserted, CPU must wait until this
control signal is deasserted. READ

Data Bus

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 Read Cycle with Wait States Parallel Input/Output in AVR
Communication through ports
There are two special instructions designed
for parallel input/output operations
In
Out

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Atmega64 Pin Configuration

Source: Atmega64 Data Sheet

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Source: Atmega64 Data Sheet COMP9032 Week5 36
 AVR PORTs Load I/O Location to Register
Can be configured to receive data or send out data Syntax: in Rd, A
Include physical pins and related circuitry to enable Operands: 0 d 31, 0 A 63
input/output operations.
Different AVR microcontroller devices have different
Operation: Rd I/O(A)
port design Words: 1
ATmega64 has 64 pins, most of them form six ports for Cycles: 1
parallel input/output.
Port A to Port F Example:
Three I/O memory addresses (in data memory) are allocated In r25, $16 ; read port B
for each port
PORTx for data register
DDRx for data direction register
PINx for port input pins

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One-bit Port Circuitry

Store Register to I/O Location
Syntax: out A, Rr
Operands: 0 r 31, 0 A 63
Operation: I/O(A) Rr
Words: 1
Cycles: 1
Example:
out $18, r16 ; write to port B

Source: Atmega64 Data Sheet

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 How does it work? How does it work? (cont.)

Each port pin consists of three register bits When the pin is configured as an input pin,
DDxn, PORTxn, and PINxn. the pull-up resistor can be
DDxn bits are accessed at the DDRx I/O address, activated/deactivated.
PORTxn bits at the PORTx I/O address
To active pull-up resistor for input pin,
PINxn bits at the PINx I/O address.
PORTxn needs to be written logic one.
The DDxn bit in the DDRx Register selects
the direction of this pin.
If DDxn is written logic one, Pxn is configured as
an output pin. If DDxn is written logic zero, Pxn is
configured as an input pin.

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Sample Code for Output Sample Code for Input

.include m64def.inc .include m64def.inc

clr r16 ; clear r16 clr r15

ser r17 ; set r17 out DDRB, r15 ; set Port B for input operation
out DDRB, r17 ; set Port B for output operation
in r25, PINB ; read Port B
out PORTB, r16 ; write zeros to Port B cpi r25, 4 ; compare read value with constant
nop ; wait (do nothing) breq exit ; branch if r25=4
out PORTB, r17 ; write ones to Port B ...
exit: nop ; branch destination (do nothing)

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 Example 1 LED and Its Operation
Design a simple control system that can
control a set of LEDs to display a fixed
pattern.

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Example 1 (solution) Example 2

Consists of a number of steps:
Set a port for the output operation, each pin of the
ports is connected to one LED
Write the pattern value to the port so that it drives
the LEDs to display the related pattern.
Design a simple control system that can
control a set of LEDs to display a fixed
pattern for one second then turn the LEDs off.

.include m64def.inc
ser r16
out DDRB, r16 ; set Port B for output

ldi r16, 0xAA ; write the pattern

out PORTB, r16
end:
rjmp end
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 Example 2 (solution) Counting One Second
Consists of a number of steps: Assume we know the clock cycle period that is 1 ms
Set a port for the output operation, each pin of the (very very slow, not a real value). Then we can write
ports is connected to one LED a program that executes
Write the pattern value to the port so that it drives 1 3 = 1 103
the display of LEDs 10
single cycle instructions.
Count one second
Write a pattern to set all LEDs off.
Execution of the code will take 1 second if each
instruction in the code takes one clock cycle.
An implementation example is given in the next slide

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Code for One Second Delay Code for Example 2

.include m64def.inc
.equ loop_count = 124
.def iH=r25
.def iL=r24
.def countH = r17
.include m64def.inc
.def countL = r16 ser r15
.macro oneSecondDelay out DDRB, r15 ; set Port B for output
ldi countL, low(loop_count) ; 1 cycle
ldi countH, high(loop_count) ldi r15, 0xAA ; write the pattern
clr iH ;1 out PORTB, r15
clr iL oneSecondDelay ; 1 second delay
loop: cp iL, countL ;1 ldi r15, 0x00
cpc iH, countH
out PORTB, r15 ; turn off the LEDs
brsh done ; 1, 2 (if branch)
adiw iH:iL, 1 ;2
end:
nop rjmp end
rjmp loop ;2
done:
.endmacro
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 Example 3 Example 3 (solution)
Design a simple control system that can Consists of a number of steps:
control a set of LEDs to display a fixed Set the switches and connect the switches to the
pattern specified by the user. pins of a port
Set the port for input
Read the input
Set another port for the output operation, each pin
of the ports is connected to one LED
Write the pattern value to the port so that it drives
the display of LEDs

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Code for Example 3 Example 4

Design a simple control system that can
.include m64def.inc control a set of LEDs to display a pattern
clr r17 specified by the user during the execution.
out DDRC, r17 ; set Port C for input
ser r17
out PORTC, r17 ; activate the pull up
in r17, PINC ; read pattern set by the user
; from the switches
ser r16
out DDRB, r16 ; set Port B for output

out PORTB, r17 ; write the input pattern

end:
rjmp end

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 Example 4 (solution) Code for Example 4
Set an extra input bit for signal from user when the
One solution is that the processor continuing input is ready.
checking if there is an input for read. If there .include m64def.inc
is, then read the input and go to next task, cbi DDRD, 7 ; clear Port D bit 7 for input
otherwise the processor is in a waiting state waiting: in r16, PIND ; check if that bit is 1
for the input. Such an approach to hand sbic PIND, 7 ; if yes skip to the next instruction
rjmp waiting ; waiting
dynamic input is called polling.
clr r17
out DDRC, r17 ; set Port C for input
ser r17
out PORTC, r17 ; activate the pull up
in r17, PINC ; read pattern set by the user
; from the switches
ser r16
out DDRB, r16 ; set Port B for output

out PORTB, r17

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Reading Materials Homework

Chapter 7: Computer Buses and Parallel 1. Refer to the AVR Instruction Set manual,
Input and Output. Microcontrollers and study the following instructions:
Microcomputers by Fredrick M. Cady. Arithmetic and logic instructions
ser
Mega64 Data Sheet. Data transfer instructions
AVR CPU Core in, out
PORTS Bit operations
sbi, cbi
Program control instructions
sbic, sbis
MCU control instructions
nop

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 Homework
2.One of very common functions a microcontroller
application usually has is timing control. The function
below is such a timing control function. Convert it to
assembly program.
static int iSeconds, iMinutes:
void timing-control (void)
{
++iSeconds;
if (iSeconds >= 60)
{
iSeconds = 0;
++iMinutes;
if (iMinutes >30){
//do something
//and reset the timer
}
}
}

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