University Detailing

Unit VI- Introduction to Microcontroller 8051
Introduction to the Microprocessor

and Microcontroller
Mr. Mantri D S, SIT, Lonavala Mr. Paithane A A, RSCOE, Pune

dsmantri.sit@sinhgad.edu ajaypaithane@yahoo.co.in
+91-9922431612 +91-9922837483
SPPU PUNE : Digital Electronics Expert: D. S. Mantri (SIT, Lonavala) and A.N. Paithane (RSCOE,Pune)
Unit VI- Introduction to Microcontroller 8051
Microprocessors and Microcontrollers comparison, 8051 architecture, Pin description,
addressing modes, instruction set of 8051, concepts of Counters and Timers with the help
of status registers, Serial communication, Port Structure and Interrupts. Simple
programming examples for addition, subtraction, multiplication.
Unit Objectives:
To understand the basics of Microprocessors & Microcontrollers.
To lean in depth concepts of hardware in Microcontroller.
To understand architecture and features of typical Microcontroller
To understand the programming details of Microcontroller.
Unit outcomes:
Able to select the microcontroller according to application
Able to learn use of hardware and software tools
Able to do programming using assembly
Reference Books:
1. Muhammad Mazidi, Janice Mazidi and Rolin McKinley, The 8051 Microcontroller
and Embedded Systems using Assembly and C, Pearson Education, 2nd edition.
2. Kenneth J. Ayala, The 8051 Microcontroller, Cengage Learning.
3. Myke Predko, Programming and customizing the 8051 microcontroller, TMH.
Aspects of a microprocessor/controller
It is a Multifunctional , Reprogrammable logic device
Without memory and I/O---- Its Microprocessor

Single chip Microcomputer ---- Microcontroller
Hardware : Interface to the real world

Software: order how to deal with inputs
It is a Multifunctional , programmable, Clock driven, register based electronic device that

reads binary instruction from a storage device called memory, accepts binary data as a
input and process data according to instruction and provide result as a output.
Microprocessor Basic concept
ADDRESS BUS
16/32/ 64-bit wide
CPU contains
ALU CONTROL BUS

CCU Timing signals, ready signals,
data registers interrupts etc
and
pointer registers
DATA BUS bidirectional

4bit/8-bit / 16-bit / 32-bit /
64bit/128-bit
Microprocessor, by-itself, completely useless must have external peripherals to Interact

with outside world
The Necessary Tools for MP/ MC
CPU: Central Processing Unit

I/O: Input /Output
Bus: Address bus & Data bus
Memory: RAM & ROM
Timer / Counter
Interrupt
Serial Port
Parallel Port
Microprocessors and Microcontrollers
CPU Bus- Clock- Mem
bit MHz
4004 4
8085 8 3.07 64 K b
8086 16 5-10 1Mb
80286 16 6-12.5 16 Mb
80386 32 16-33 4 Gb
Pentium 64 60-100 4 Gb
CPU for Computers, No RAM, ROM, I/O on CPU chip itself
Pen-Pro 64 150-200 4 Gb
ExampleIntels x86, Motorolas 680x0
Features 8031 8051 8052
ROM -- 4K 8K
RAM (Bytes) 128 128 256
I/O Pins 32 32 32
Timers 2 2 3
A smaller computer, On-chip RAM, ROM, I/O ports... Serial ports 1 1 1
ExampleMotorolas 6811, Intels 8051, and PIC 16X Interrupts 6 6 8
Microprocessor vs. Microcontroller
Microprocessor Microcontroller
CPU is stand-alone, RAM, CPU, RAM, ROM, I/O and timer
ROM, I/O, timer are external are all on a single chip
Expensive and versatile for Fixed amount of on-chip ROM,
design RAM, I/O ports
General-purpose Application Specific
High power consumption Low power consumption
Instruction sets focus on Instruction sets focus on control
processing-intensive operations and bit-level operations
Typically 32/64 bit Typically 8/16 bit
Typically deep pipeline (5-20 Typically single-cycle/two-stage
stages) pipeline
Clock speed range from 3.07 - Clock speed range from 6-64 MHZ
100 MHZ
Uses Von Neumann May be with Harward
Architecture- CISC Architecture Towards RISC
Applications of Microcontroller
Home
Appliances, intercom, telephones, security systems, garage door
openers, answering machines, fax machines, home computers, TVs,
cable TV tuner, VCR, camcorder, remote controls, video games,
cellular phones, musical instruments, sewing machines, lighting
control, paging, camera, pinball machines, toys, exercise equipment
Office
Telephones, computers, security systems, fax machines, Microwave,
copier, laser printer, colour printer, paging
Auto
Trip computer, engine control, air bag, ABS, instrumentation, security
system, transmission control, entertainment, climate control, cellular
phone, keyless entry.
Three criteria in Choosing a Microcontroller
1. Meeting the computing needs of the task efficiently and cost

effectively
Speed, the amount of ROM and RAM, the number of I/O ports
and timers, size, packaging, power consumption
easy to upgrade, cost per unit
2. Availability of software development tools
assemblers, debuggers, C compilers, emulator, simulator,
technical support.
3. wide availability and reliable sources of the microcontrollers.
Architecture of MP and MC
Address
Address
Input Control CPU ALU Output

Data Data
Address Data Von Neumann Architecture:
Memory
(Program and Data)
Address
Address
Input Control CPU ALU Output
Data Data Data
Address Data Address Data

Harvard Architecture:
Program Data
Memory Memory
Comparison of Von Neumann and Harvard
Von Neumann architecture Harvard architecture
Fetches instructions and data Fetches Instruction and Data

from a single memory space from two separate memory
spaces
Limits operating bandwidth Improved operating bandwidth
Allows for fixed bus widths Allows for different bus widths
Architecture --- CISC Architecture --- RISC
Variable instruction format Fixed instruction format
RISC vs CISC: Characteristics
RISC CISC
1. Simple Instruction taking 1 cycle 1. Complex Instruction taking multiple cycles
2. Only LOADs, STOREs access memory 2. Any Instruction. may access memory
3. Designed around pipeline 3. Designed around Instruction. Set
4. Instruction. executed by h/w 4. Instruction interpreted by micro program
5. Fixed format Instruction 5. Variable format Instruction
6. Few Instruction and modes 6. Many Instruction and modes
7. Complexity in the compiler 7. Complexity in the micro program
8. Multiple register sets 8. Single register set
9. Operates at 50-150 MHz 9. Operates at 33-50 MHz
Limitation of 8 bit controller
Data bus width limits speed of execution

Addressable memory is limited for given application
Very small RAM & Flash memory
Does not have high performance interrupt system
Does not have DMA & cache memory for faster
execution
Does not have memory protection unit (MPU)
Does not have protected modes of operation
Can not implement RTOS which is current need of
embedded system
FEATURES of 8051
8-bit CPU optimized for control applications
On-chip clock oscillator 6-12 MHz
4K bytes of on-chip Program Memory
128 bytes of on-chip Data RAM
64K Program Memory address space
64K Data Memory address space
32 bidirectional and individually addressable 1/0 lines
Can operate on Bits, Bytes, Words
34- general purpose, 3- pointers , 21 SFRs
Extensive boolean processing (Single-bit logic) capabilities
Two 16-bit timer/counters
Full duplex UART
6-source/5-vector interrupt structure with two priority levels
BLOCK DIAGRAM
INT0
INT1
T0
TF0
Interrupt TF1
Timer 0
4K 128
Control TI/RI
ROM RAM Timer 1
T1
CPU
OSC Bus Serial

4 I/O Ports
Control Port
TXD RXD
SPPU PUNE : Digital Electronics P0Mantri (SIT,
Expert: D. S. P1 Lonavala)
P2 and A.N.
P3Paithane (RSCOE,Pune)
BLOCK DIAGRAM
Accumulator A & B with 32 GPR, 21 SFRs

Parallel Input/Output Ports
Memory RAM/ROM
System Clock Generator
Serial Port
Timers/counters
Interrupt Control
Registers
A PSW (8)
R0 SP (8)
R1
R2
DPH DPL DPTR (16)
R3
R4
PC PC (16)
R5
R6 Some 8051 16-bit Register hold

R7 addresses
Some 8-bitt Registers of

the 8051
34- general purpose, 3- pointers , 21 SFRs
Registers A, B , R0-7
Accumulator (A ,8 bit 0E0 )
It is a general-purpose register used for storing intermediate results obtained during
operation.
Prior to executing an instruction upon any number or operand, it is necessary to store it in
the accumulator first.
All results obtained from arithmetical operations performed by the ALU are stored in the
accumulator.
Data to be moved from one register to another must go through the accumulator.
In other words, the A register is the most commonly used register in performing
operations on Data.
Accumulator (B ,8 bit - 0F0)
It is a general-purpose register used for performing Multiplication and Division operation
with A
Multiplies 8 bit unsigned values in A and B and leaves the 16 bit result in A (low byte) and B
(high byte)
Divided A by B, leaving the integer result in A and remainder in B
It is bit-addressable
Registers (r0-r7 , 8 bit - 00-1F)
These are general-purpose register available in Banks -- Total 32
Out of that r0 & r1 act as pointers for internal memory related operations
Program status word (PSW ,8 bit , 0D0)
Flags are 1-bit registers used to store the result of program instructions
Has 4 math flags (CY, AC, OV, P), 3 - General purpose flags set by User
It is Bit addressable
Pointers SP, DPTR, PC
Stack Pointer (SP ,8 bit 81)

It contains the address of the data item currently on top of the stack.
Stack operations include pushing data on the stack and popping data off the stack
Pushing increments SP before writing the data and Popping from the stack reads
the data and decrements the SP
8051 stack is kept in the internal RAM
Depending on the initial value of the SP, stack can have different sizes
power on reset gives contents of SP =07h address ( By default)
On 8051 this would limit the stack to 32 bytes since the uppermost address of on
chip RAM is 7FH
Data Pointer (DPTR , 16 bit DPH -83, DPL-82)
It is used to access external data or code memory
It can be used as 8 bit register as DPH and DPL separately
Program Counter (PC, 16 bit 81)

It Holds the address of next instruction to be executed
Registers --- SFRS
Special Function Registers (SFRs) are a sort of control table used for
running and monitoring the operation of the microcontroller.
SFR has only 21 such registers.
TH0-TL0 and TH1-TL1 ---16 bit timer registers

P0-P3 port latches
SP, PSW, IP Interrupt Priority, IE enable
TCON Timer/Counter control reg
Interrupt control flags for ext. interrupt like INT1 and INT0
TMOD modes of operation of timer/counter
SCON serial port mode control reg
SBUF serial data buffer for transmit and receive
PCON Power control reg power down bit, idle bit
Map of SFRS (80-FF)
F8 FF
F0 B F7
E8 EF
E0 Acc E7
D8 DF
D0 PSW D7
C8 CF
C0 C7
B8 IP BF
B0 P3 B7
A8 IE AF
A0 P2 A7
98 SCON SBUF 9F
90 P1 97
88 TCON TMOD TL0 TL1 TH0 TH1 8F
80 P0 SP DPL DPH PCON 87
Mapping of Internal RAM
Internal : RAM - 128 Bytes : 00- 7F SFRS : 80- FFH , ROM: 4 KBytes
External : Ram and Rom : 64 KB
7F
General Purpose
Area
30
2F
BIT Addressable
Area
128 BYTE 20
1F
Reg Bank 3
17
Reg Bank 2
Register Banks 0F
Reg Bank 1
07
Reg Bank 0
00
Programming Model of 8051
PIN DETAILS
P1
P0
RESET
+
_
P3
P2
XTAL
Important points
Power On reset -- Restore initial setting 2M/C
Clock circuit --- uses 11.0592 MHz clock- need to maintain std baud rate
T= [No. of M/c Cycles * 12]/Crystal frequency
Normally clock frequency for 8051 is chosen as 11.0592 MHz yield
921.6KHz which can be evenly divided by standard communication
baud rates 300,600 ,1200, 2400,4800,9600 and so on
By default all I/O lines go high on Reset
Ioh= 60 A, -Current sinking capacity
Iol =1.6 ma - current sourcing capacity
EA & PSEN used to access internal and External memory
ALE - Differentiate Address and data on AD0- AD7 port0
Important pins
PSEN (out): Program Store Enable, the read signal for

external program memory (active low).
ALE (out): Address Latch Enable, to latch address outputs
at Port0 and Port2
EA (in): External Access Enable, active low to access
external program memory locations 0 to 4K
RXD,TXD: UART pins for serial I/O on Port 3
XTAL1 & XTAL2: Crystal inputs for internal oscillator.
RST : clear all the content of register and set the default
values two m/c cycles
PORT OPERATIONS
PIN DETAILS
P1
P0
RESET
+
_
P3
P2
XTAL
Port Operation
One of the most useful features of the 8051 is that it contains four I/O
ports (P0 - P3) By default all lines are HIGH
Port 0 pins 32-39P0P0.0P0.7

8-bit R/W - General Purpose I/O
Or acts as a multiplexed low byte address and data bus for external memory design
hence needs Pull up registers (10K)
Port 1 pins 1-8 P1P1.0P1.7

Only 8-bit R/W - General Purpose I/O

8-bit R/W - General Purpose I/O
Or high byte of the address bus for external memory design

General Purpose I/O
if not using any of the internal peripherals (timers) or external interrupts.
Each port can be used as input or output (bi-direction)
Hardware Structure of I/O Pin
Each pin of I/O ports
Internally connected to CPU bus
A D latch store the value of this pin
Write to latch1write data into the D latch
2 Tri-state buffer
TB1: controlled by Read pin
Read pin1really read the data present at the pin
TB2: controlled by Read latch
Read latch1read value from internal latch
A transistor M1 gate
Gate=0: open
Gate=1: close
Ports of 8051
Port0- Pins 32-39, SFR 80]-needs external pull ups Port1- [ Pins 1-8, SFR 90]- does not needs external pull ups
RD
WR
Port 2- [ Pins 21-28, SFR A0]- used for high byte Address Port 3- [pin 10-17, SFR-B0]- Multi functional port
A Pin of Port 1
Read latch Vcc

TB2
Load(L1)
Internal CPU D Q P1.X

bus P1.X pin
Write to latch Clk Q M1
TB1
Read pin
Port 1 pins 1-8 P1P1.0P1.7

Only 8-bit R/W - General Purpose I/O
Writing 1 to Output Pin P1.X
Read latch Vcc

TB2
Load(L1) 2. output pin is
1. write a 1 to the pin Vcc
1 P1.X
Internal CPU D Q
bus P1.X pin
0 output 1
TB1
Read pin
Writing 0 to Output Pin P1.X
Read latch Vcc

TB2
Load(L1) 2. output pin is
1. write a 0 to the pin ground
0 P1.X
Internal CPU D Q
bus P1.X pin
1 output 0
TB1
Read pin
Reading High at Input Pin
Read latch Vcc 2. MOV A,P1

TB2 external pin=High
1. write a 1 to the pin MOV Load(L1)
P1,#0FFH
1 1 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q
TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
Reading Low at Input Pin
Read latch Vcc 2. MOV A,P1

TB2
1. write a 1 to the pin Load(L1) external pin=Low
MOV P1,#00H
1 0 P0.X pin
Internal CPU bus D Q
P0.X
0 M1
Write to latch Clk Q
TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
Addressing Modes
The way of specifying operand of an instruction is called addressing modes
1. Register : mov a,b; mov a, r0
2. Direct : add a, 55h; mov@r0, 20h; mov 6,2; mov 56h,a
3. Register Indirect: mov a,@r0, mov@r1, a
4. Immediate : mov r0, #23h, add a, #1234h, mov @r0, #55h;
5. Implicit : CPL A; STB,C
6. Indexed Addressing: movc a, @a+dptr
7. Relative
Short : SJMP with in 256 byes (-128 to +127)
Absolute : ACAll, AJMP with in 2Kb
Long : LCALL, LJMP -- with in 64Kb
Instruction Set
5 Groups
Data Transfer Group
Arithmetic Operation Group
Logical Operation Group
Boolean Variable Manipulation Group
Program Branching Group
Data Transfer Group [ MOV, PUSH, POP, XCHG]
MOV A,Direct MOV @Ri, A PUSH Direct

MOV A,Rn MOV @Ri,#Data POP Direct
MOV A,@Ri XCH A,Rn
MOV @Ri, Direct
XCH A,Direct
MOV A,#Data MOV DPTR, #DATA16 XCH A,@Ri
MOV Rn,Direct MOVC A, @A+DPTR XCHD A,@Ri
MOV Rn,@Ri MOVC A, @A+PC
MOV Rn,#Data MOVX A, @Ri
MOV Direct, Direct MOVX @Ri, A
MOV Direct, Rn MOVX @DPTR, A
MOV Direct, @Ri
MOV Direct, #Data
MOV Direct, A
Data Transfer Group [ MOV, PUSH, POP, XCHG]
Arithmetic Instructions
[Add, SUB, INC, DEC, Multi, Divide, Decimal
ADD A,Direct
SUBB A, Direct INC A DEC A MUL AB
ADD A,Rn Direct DEC Direct DIV AB
SUBB A, Rn INC
ADD A,@Ri DEC Rn DA A
SUBB A,@Ri INC Rn
ADD A,#Data DEC @Ri
SUBB A,#Data INC @Ri
ADDC A,Direct INC DPTR
ADDC A,Rn
ADDC A,@Ri
ADDC A,#Data
Logic Instructions
Logic operations, Clear, Rotate, Swap, Complement
ANL A, Direct ORL A, Direct
ANL A, Rn ORL A, Rn 00001111
00001111
ORL A, @Ri ORL 10101100
ANL A, @Ri ANL 10101100
ORL A, #Data 10101111
ANL A, #Data 00001100
ANL Direct, A ORL Direct, A
ANL Direct, #Data ORL Direct, #Data
CLR ( Set all bits to 0)
XRL A, Direct 00001111 CLR A 10101100
XRL CLR
XRL A, Rn 10101100 CLR byte (direct mode) 00000000
XRL A, @Ri 10100011 CLR Ri (register mode)
XRL A, #Data CLR @Ri(register
XRL Direct, A indirect) 10101100
CPL
XRL Direct, #Data CPL A 01010011
ANL C, bit; ORL C, bit; CLR C; CLR bit; CPL C; CPL bit; SETB C; SETB bit.
Logical Operation Group - Rotate
Rotate instructions operate only on a

RL a [D7--D0]
RL A Mov a,#0xF0
Rl a
;a 11110000
a 11100001
RLC A C
RLC a
RR A [D7-CY-D0]
RRC A RR a [D0-D7]
SWAP A Mov a,#0xF0

RR a
; a 11110000
; a 01111000
RRC a C
[D0-CY-D7]
Logic Instructions
Logic operations, Clear, Rotate, Swap, Complement
Boolean Variable Manipulation Group
SETB C JC rel
SETB bit JNC rel
CLR C JB bit,rel
CLR bit JNB bit,rel
CPL C JBC bit,rel
CPL bit
MOV C, bit
MOV bit, C
ANL C, bit
ANL C,/bit
ORL C, bit
ORL C,/bit
Program Branching Group
ACALL addr11 JMP @A+DPTR DJNZ Rn, rel
LCALL addr16 JZ rel DJNZ Direct, rel
RET JNZ rel NOP
RETI CJNE A, Direct,rel
AJMP addr11 CJNE A, #Data, rel
LJMP addr16 CJNE Rn, #Data, rel
SJMP rel CJNE @Ri, #Data, rel
LJMP(long jump)
LJMP is an unconditional jump. It is a 3-byte instruction. It allows a jump to any memory
location from 0000 to FFFFH.
AJMP(absolute jump)
In this 2-byte instruction, It allows a jump to any memory location within the 2k block of
program memory.
SJMP(short jump)
In this 2-byte instruction. The relative address range of 00-FFH is divided into forward and
backward jumps, that is , within -128 to +127 bytes of memory relative to the address of the
current PC.
Program control group of instructions
8051 Instruction Set
ACALL: Absolute Call JC: Jump if Carry Set PUSH: Push Value Onto Stack
ADD, ADDC: Add Acc. (With Carry) JMP: Jump to Address RET: Return From Subroutine
AJMP: Absolute Jump JNB: Jump if Bit Not Set RETI: Return From Interrupt
ANL: Bitwise AND JNC: Jump if Carry Not Set RL: Rotate Accumulator Left
CJNE: Compare & Jump if Not Equal JNZ: Jump if Acc. Not Zero RLC: Rotate Acc. Left Through Carry
CLR: Clear Register JZ: Jump if Accumulator Zero RR: Rotate Accumulator Right
CPL: Complement Register LCALL: Long Call RRC: Rotate Acc. Right Through Carry
DA: Decimal Adjust LJMP: Long Jump SETB: Set Bit
DEC: Decrement Register MOV: Move Memory SJMP: Short Jump
DIV: Divide Accumulator by B MOVC: Move Code Memory SUBB: Sub. From Acc. With Borrow
DJNZ: Dec. Reg. & Jump if Not Zero MOVX: Move Extended Memory SWAP: Swap Accumulator Nibbles
INC: Increment Register MUL: Multiply Accumulator by B XCH: Exchange Bytes
JB: Jump if Bit Set NOP: No Operation XCHD: Exchange Digits
JBC: Jump if Bit Set and Clear Bit ORL: Bitwise OR XRL: Bitwise Exclusive OR
POP: Pop Value From Stack Undefined: Undefined Instruction
TIMERS
SERIAL PORT
INTERRUPTS
BLOCK DIAGRAM
INT0
INT1
T0
TF0
Interrupt TF1
Timer 0
4K 128
Control TI/RI
ROM RAM Timer 1
T1
CPU
OSC Bus Serial

4 I/O Ports
Control Port
TXD RXD
P2 and A.N.
Timer/ Counters
Set the initial value of registers Count the number of events
Start the timer and then the Show the number of events on
8051 counts up. registers
Input from internal system External input from Tx input pin.
clock (machine cycle) We use Tx to denote T0 or T1.
When the registers equal to 0 for counter0 or 1
and the 8051 sets a bit to
denote time out
8051 TH0
P1
P2 P1 TL0
Set
Timer TH0 P3.4
a switch T0
8051
TL0
Counters
Timers
Timer/Counters
8051 has two 16-bit Timer/Counter registers
Timer/Counter 0
Timer/Counter 1
These registers can be used as timers or as event
counters
When a register is in Timer state, it is incremented
every machine cycle
In Counter state, the register is incremented when
there is a 1-to-0 transition at its external input pin, pin
T0 (P 3.4) or T1 (P 3.5)
Both registers have additional four operating modes
Has Two SFRs TMOD & TCON
PIN DETAILS
P1
P0
RESET
+
_
P3
Timer/Counter
P2
XTAL
TIMER / COUNTER-- schematic
OSC 12
C T
C // T 0
0 TL TH TF
(8 Bit) (8 Bit) (1 Bit)
C /T 1
T PIN
INTERRUPT
TR
TR
Gate
Gate GATE =0 , C/T=0. TR0/1 -Effective -- Internal operation -Timer
GATE =0 , C/T=1. TR0/1 -Effective -- Internal operation Counter
GATE =1 , C/T=0. TR0/1 -Effective -- External Control INT0/1
INT PIN
INT PIN
SFRs Related to TIMER
TMOD(89) - Byte Addressable
Gate C/ M1 M0 Gate C/ M1 M0
Timer 1 Timer 0
TCON(88) - Bit Addressable
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TR=0: off (stop)

Timers TR=1: on (start) Interrupt
TMOD(89): Timer/Counter Mode Control Register
Gate C/ M1 M0 Gate C/ M1 M0
Timer 1 Timer 0
Gate : When gate=1, and TRx in TCON =1, Timer/counter will only runs while INT(0,1) is high.
(hardware Control)
When gate=0, Timer/counter will only runs while TRx in TCON =1, No use of INT(0,1)
(Software control)
C/T : Counter/Timer select bit = 0, Timer Input from Internal system clock Delay
= 1, Counter- Input from Tx pin Event count
M1 : Mode bit 1. M0 : Mode bit 0.
M1 M0 Mode Explanation Over flow
0 0 0 3 bit Timer [TL= 5, TH=8 bit] 0000-1FFF
0 1 1 16 bit Timer/counter [TL=TH=8 bit] 0000- FFFF
1 0 2 8 bit auto reload Timer/Counter[TH TL] 00-FF
1 1 3 Split Separate TL0 - T0 control and TH0- T1 control 00- FF
TCON Register
Timer 1 Timer0 for Interrupt
Timer control register: TMOD
Upper nibble for timer/counter, lower nibble for interrupts
TR (run control bit)
TR0 for Timer/counter 0; TR1 for Timer/counter 1.
TR is set by programmer to turn timer/counter on/off.
TR=0: off (stop) TR=1: on (start)
TF (timer flag, control flag)
TF0 for timer/counter 0; TF1 for timer/counter 1.
TF is like a carry. Originally, TF=0. When TH-TL roll over to 0000 from
FFFFH, the TF is set to 1.
TF=0 : not reach TF=1: reach
If we enable interrupt, TF=1 will trigger ISR.
TIMER / COUNTER-- Summary
Parameter Internal External
Application Timer Counter
Purpose Delay Event Counting
Dependant On Oscillator External Pulses
Control Software Hardware
SFRS TMOD, Upper Nibble TMOD, Lower Nibble
of TCON of TCON
Flags used TF0, TF1 IE0, IE1

Control Signals C/T=0, G=0 C/T=1, G=1
Timer/Counter Modes
The selection for Timer or Counter is done by

control bits C/T in the TMOD register
Both Timer/Counters have four operating modes,
which Modes 0, 1 and 2 are the same for both
Timer/Counters, Mode 3 is different
Modes are selected by bit pairs (M1, M0) in TMOD
SFR
Another SFR used for work with Timer/Counters is
TCON containing flag (TFx) and control (TRx) bits
TIMER / COUNTER --Modes
TIMERS
Timer 0 Timer 1
Mode 0 Mode 0
Mode 1 Mode 1
Mode 2
Mode 2
Mode 3
TIMER 0/1 Mode 0 (Prescaler)
Both Timer 1 and Timer 0 in Mode 0 operate as an 8-bit Counters (with a

divide-by-32 prescaler)
Timer register is configured as a 13-bit register consisting of all 8 bits of TH1
and the lower 5 bits of TL1
The upper 3 bits of TL1 are indeterminate and should be ignored
Setting the run flag (TR1) does not clear the register
Timer interrupt flag TF1 is set when the count rolls over from all 1s to all 0s
13 Bit Timer / Counter Pre scale
OSC 12
TL0 TH0
TF0 INTERRUPT
C /T 0 (5 Bit) (8 Bit)
TR 0
Maximum Count = 1FFFh (0001 1111 1111 1111)

TIMER 0/1- Mode 1 (General)
16 Bit Timer / Counter

OSC 12
TL0 TH0
TF0
INTERRUPT
C /T 0 (8 Bit) (8 Bit)
16-bit timer (TH0 and TL0)

TH0-TL0 is incremented continuously when TR0 is set to 1. And the 8051 stops to
increment TH0-TL0 when TR0 is cleared.
The timer works with the internal system clock. In other words, the timer counts up
each machine cycle.
When the timer (TH0-TL0) reaches its maximum of FFFFH, it rolls over to 0000, and
TF0 is raised.
Programmer should check TF0 and stop the timer 0.
Maximum Count = FFFFh (1111111111111111)
TIMER 0/1 Mode 2 (Auto reload)
8 Bit Timer / Counter with AUTORELOAD

OSC 12
TL0
TF0 INTERRUPT
C /T 0 (8 Bit)
Both Timer registers are configured

as an reload8-bit Counters (TL1 and
Reload
TL0) with automatic Overflow from TL1 (TL0) sets TF1
(TF0) and also reloads TL1 (TL0)
with the contents of TH1 (TH0),
TH0 which is preset by software
(8 Bit)
The reload leaves TH1 (TH0) unchanged TH0/1 TL0/1
Maximum Count = FFh (1111 1111)

TIMER 0 Mode 3 ( Split mode)
Two - 8 Bit Timer / Counter

OSC 12
TL0
TF0 INTERRUPT
C /T 0 (8 Bit)
It uses the Timer 0 flag for the control operation
OSC TH0
12 TF1 INTERRUPT
(8 Bit)
TR1
It uses the Timer 1 flag for the control operation even though
timer 0s , TH0 is used
TIMER 0 Mode 3 ( Split mode)
Mode 3 is different for Timer 1 and Timer 0
Timer 1 just holds its count. It operates the same as when TR1
is set to 0
For Timer 0 is different, TL0 and TH0 of Timer 0 are
established as two separate counters
TL0 uses Timer 0 control bits for its work: C/T, GATE, TR0,
~INT0, and TF0
TH0 is locked into a timer function (counting machine cycles)
and takes over the use of TR1 and TF1 from Timer 1. TH0 is
now actually in control of Timer 1 interrupt
Mode 3 is provided for applications that require an extra 8-bit
timer or counter
With Timer 0, 8051 looks like it has three Timer/Counters
When Timer 0 in Mode 3, Timer 1 can be turned on and off by
switching it out of and into its own Mode 3, or can still be used in any
application not requiring an interrupt
TIMER Mode 0-3
INTERRUPTS
71 SPPU PUNE : Digital Electronics

SKB's
Expert: D. S. Mantri (SIT, Lonavala) and A.N. Paithane (RSCOE,Pune)
BLOCK DIAGRAM
INT0
INT1
T0
TF0
Interrupt TF1
Timer 0
4K 128
Control TI/RI
ROM RAM Timer 1
T1
CPU
OSC Bus Serial

4 I/O Ports
Control Port
TXD RXD
P2 and A.N.
PIN DETAILS
P1
P0
RESET
+
_
P3
Hardware
Software
P2
XTAL
SFRs Related to interrupts
IE
EA - - ES ET1 EX1 ET0 EX0

IP
- - - PS PT1 PX1 PT0 PX0
Priority Within Level
RI / TI TF1 IE1 TF0 IE0
LOW HIGH
TCON
INTERRUPTS
The Interrupt structure has the following features:
6 sources / 5 vectored interrupts
Each interrupts can be individually programmable
Each interrupts can have two priority levels
Priority levels can be programmed
All interrupts can be masked by a single bit - EA
External interrupt type can be programmed
Edge triggered
Level Triggered
What if two interrupt sources interrupt at the same time?

The interrupt with the highest PRIORITY gets serviced first.
All interrupts have a power on default priority order.
Interrupt
Original 8051 provides 6 interrupt sources
1 Reset
2 external interrupts [ External Interrupt 0 -- INT0
External Interrupt 1 -- INT1]
2 timer interrupts [ Timer 0 overflow- TF0;
Timer 1 overflow - TF1]
1 Serial Port events (buffer full, buffer empty, etc [TI/RI] )
They are controlled via two SFRs, IE and IP

Each interrupt source can be individually enabled or disabled by setting or
clearing a bit in IE (Interrupt Enable). IE also exists a global disable bit, which
can be cleared to disable all interrupts at once
All interrupt are disabled after reset
Interrupts structure
0 IE0
IT
IT 0
INT
INT00 0
TCON.1
1
TF
TF00
INTERRUPT
0 IE1 SOURCES
IT11
INT
INT11 IT TCON.3
1
TF
TF11
TI
TI
RI
RI
Interrupt structure
IE Reg IP Reg High Priority
Interrupt
0
INT 0 IT 0 IE0
1
TF 0
0 Interrupt
INT 1 IT1 IE1 Polling
1 Sequence
TF1
TI
RI
Global
Individual Enable Disable EA=0
Low Priority Interrupt
DSM
Interrupt ISR (Vector)Address
Each interrupt has a specific place in code memory where program execution
(interrupt service routine) begins.
This internal priority structure determined by the polling sequence and
the vector addresses is shown in the following table
Interrupt ISR address Priority/pin Flag Clearing
System Reset 0000 /9 Auto
External INT0 0003 Highest/P3.2 (12) Auto
Timer0 TF0 000B Auto
External INT1 0013 /P3.3 (13) Auto
Timer1 TF1 001B Auto
Serial port RI/TI 0023 Lowest Manual
Programmer
Timer 2 overflow(8052+) 002bh
Note: that there are only 8 memory locations between vectors.
IE: Interrupt Enable Register (bit addressable)
All interrupt are disabled after reset

We can enable and disable them by IE
Interrupt enables for the 5 original 8051 interrupts:

Timer 2
Serial (UART0)
Timer 1
Global Interrupt Enable 1 = Enable
External 1
must be set to 1 for any 0 = Disable
Timer 0
interrupt to be enabled External 0
IP: Interrupt Priorities Register (Bit)
--- --- PT2 PS PT1 PX1 PT0 PX0

IP.7: reserved
IP.6: reserved
IP.5: timer 2 interrupt priority bit (8052 only)
IP.4: serial port interrupt priority bit
IP.3: timer 1 interrupt priority bit
IP.2: external interrupt 1 priority bit
IP.1: timer 0 interrupt priority bit
IP.0: external interrupt 0 priority bit
A high-priority interrupt can interrupt a low-priority interrupt
If the bit is 0, the corresponding interrupt has a lower priority and if the bit
is 1, the interrupt has a higher priority
All interrupt are latched internally
Low-priority interrupt wait until 8051 has finished servicing the high-
priority interrupt
Priority can also be set to high or low by IP register
External Interrupts
External interrupts ~INT0 and ~INT1 have two ways of activation

Level Triggered
Edge Triggered
This depends on bits IT0 and IT1 in TCON

The flags that actually generate these interrupts are bits IE0 and IE1
in TCON
On-chip hardware clears that flag that generated an external
interrupt when the service routine is vectored to, but only if the
interrupt was Edge-activated
When the interrupt is level-activated, then the external requesting
source is controlling the request flag, not the on-chip hardware
External interrupts- Edge Triggered
1. Upon power on reset INT0 and INT1 becomes the low level triggered
[ TCON.0 and TCON.2 are zero(0) ] [IE0 ,1 Not used at all]
2. To make them edge triggered ,we must program the bits of TCON register
TCON
Timers Interrupt
3. IF TCON.0 and TCON.2 are set one (1) INT0,1 becomes edge triggered
4. High to low signal will interrupt the processor and jumps to ISR.
5. IE0 and IE1 is used to keep track of edge triggered Interrupts
6. While executing ISR no transition of H-L is detected on INT0,1 , only RETI will
clear IEx
Internal Interrupts
Timer interrupts are generated by TF0 and TF1 flags in their respective Timer/Counter registers
Roll-over timer flag and interrupt
if the timer interrupt is enabled, whenever TF=1, the microcontroller is

interrupted in whatever it is doing, and jumps to the interrupt vector
table to service the ISR
In this way, the microcontroller can do other things until it is notified
that the timer has rolled over
Similarly like in the case of transition-activated external interrupts, the flag

that generated an interrupt is cleared by the on-chip hardware when the
service routine is vectored to
SERIAL PORT
BLOCK DIAGRAM
INT0
INT1
T0
TF0
Interrupt TF1
Timer 0
4K 128
Control TI/RI
ROM RAM Timer 1
T1
CPU
OSC Bus Serial

4 I/O Ports
Control Port
TXD RXD
P2 and A.N.
Basics of serial communication
Parallel: expensive - short distance fast no modulation
Serial :cheaper long (two different cities by modem)-slow
Packaging Data- Asynchronous
In asynchronous transmission : each character is placed between
start and stop bits ( Framing Bits) , When there is no transfer
the signal is high
Transmission begins with a start (low) bit It is always one bit
Stop bit can be one or Two , Stop bit is high
LSB is send out First
Data transfer rate (baud rate) is stated in bps
Asynchronous serial transmission is widely used for the character oriented Transmission
Computer Baud Rates : 150, 300,600, 1200,2400, 4800, 9600, 19200 etc
Pin out diagram
+
+
+
+
P1 + P0
+
RESET + +
Serial + _
P3
+
P2
XTAL
SFRs Related to Serial Port
SCON [98]- bit Addressible
SM0 SM1 SM2 REN TB8 RB8 TI RI
PCON [87] Byte Addressible
SMOD - - - GF1 GF0 PD IDL
Serial control (SCON) Register
7 6 5 4 3 2 1 0
SM0 SM1 SM2 REN TB8 RB8 TI RI
SM0 SM1 MODE operation transmit rate

SM0 : mode specifier 0 0 0 shift register fixed (xtal /12)
SM1 : mode specifier 0 1 1 8 bit UART variable (timer1)
1 0 2 9 bit UART fixed (xtal /32 or xtal /64)
1 1 3 9 bit UART variable (timer1)
SM2 : used for multi processor communication used In mode 2 &3

REN : receive enable (by software enable/disable) required for both transmit
and receive ( 1= Enable Tx and Rx , 0= Disable Tx and Rx )
TB8 : transmit bit8: used for mode 2 and 3
RB8 : receive bit 8 : used for mode 2 and 3
TI : transmit interrupt flag set by HW after send , clear by SW, it is raised
when transfer is complete at the beginning of Stop bit
RI : receive interrupt flag set by HW after received ,clear by SW, It is raised at
the middle of stop bit
Importance
Importance of the TI flag
of the TI and RI flag
check the TI flag bit, we know whether can transfer another byte
TI flag bit is raised by the 8051
TI flag cleared by the programmer
writing a byte into SBUF before the TI flag bit is raised, may lead to
loss of a portion of the byte being transferred
Importance of the RI flag bit

1. it receives the start bit, next bit is the first bit of the character
2. when the last bit is received, a byte is formed and placed in SBUF
3. when stop bit is received, makes RI = 1
4. when RI=1, received byte is in the SBUF register, copy SBUF
contents to a safe place
5. after the SBUF contents are copied the RI flag bit must be cleared
to 0
SBUF ( Serial Buffer register) [99]
A byte of data to be transferred via the TxD line must be placed in the SBUF register
SBUF holds the byte of data when it is received by the RxD line
can be accessed like any other register
MOV SBUF,#'D ;load SBUF=44H, ASCII for 'D
MOV SBUF,A ;copy accumulator into SBUF
MOV A,SBUF ;copy SBUF into accumulator
when a byte is written, it is framed with the start and stop bits and transferred
serially via the TxD pin
when the bits are received serially via RxD, it is deframe by eliminating the stop
and start bits, making a byte out of the data received, and then placing it in the
SBUF
Mode 0 - 8 bit shift-Fixed Baud rate
Serial data enters and exits through RxD

TxD outputs the shift clock.
8 bits are transmitted/received(LSB first)
The baud rate is fixed a 1/12 the oscillator frequency.
Application
Port expansion
8051
TXD clk
RXD Shift register
data
Mode 1- Variable Baud Rate
Ten bits are transmitted (through TxD) or received (through RxD)
(A start bit (0), 8 data bits (LSB first), and a stop bit (1) )
On receive, the stop bit goes into RB8 in SCON
the baud rate is determined by the Timer 1 overflow rate.
Timer1 clock is 1/32 machine cycle (MC=1/12 XTAL)
Timer clock can be programmed as 1/16 of machine cycle

Transmission is initiated by any instruction that uses SBUF as a
destination register.
By default Serial mode1 uses Timer1 in mode2 ( Auto-reload)
(MSB) (LSB)
GATE C/T M1 M0 GATE C/T M1 M0
Timer 1 Timer 0
rate in the 8051 is programmable
Baud rate in the 8051
done with the help of Timer 1, mode2
relationship between the crystal frequency and the baud rate in the
8051
1. 8051 divides the crystal frequency by 12 to get the machine cycle
frequency = (XTAL /12)=11.0592 MHz/12, is 921.6 kHz
2. 8051's UART divides the machine cycle frequency of 921.6 kHz by
32 once more before it is used by Timer 1 to set the baud rate
3. 921.6 kHz divided by 32 gives 28,800 Hz
4. Timer 1 must be programmed in mode 2, that is 8-bit, auto-reload
16 57,600 Hz
11.0592 MHz by UART
XTAL 921.6 kHz (SMOD=1)
12 Timer 1
OSC
32 28,800 Hz
by UART
(SMOD=0)
Baud rate in the 8051
Mode2- 9 bit shift
Eleven bits are transmitted (through TxD), received (through RxD)
A start bit (0)
8 data bits (LSB first)
A programmable 9th data bit
and a stop bit (1)
On transmit, the 9th bit (TB8) can be assigned 0 or 1.
On receive, the 9the data bit goes into RB8 in SCON.
the 9th can be parity bit
The baud rate is programmable to 1/32 or 1/64 the oscillator frequency in Mode
2 by SMOD bit in PCON register
Mode 3- 9 bit Variable Baud rate
The Serial Port in Mode-3 has the following features:
Serial data enters RXD

Serial data exits through TXD
9th data bit (TB8) can be assign value 0 or 1
On receive, the 9th data bit goes into RB8 in SCON
11 bits are transmitted / received
Start bit (0)
Data bits (9)
Stop Bit (1)
Baud rate is determined by the Timer 1
over flow rate.
Mode of operation
Programming Examples
Thank you

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Unit VI- Introduction to Microcontroller 8051

Introduction to the Microprocessor

Mr. Mantri D S, SIT, Lonavala Mr. Paithane A A, RSCOE, Pune

It is a Multifunctional , Reprogrammable logic device

Without memory and I/O---- Its Microprocessor

Hardware : Interface to the real world

It is a Multifunctional , programmable, Clock driven, register based electronic device that

ALU CONTROL BUS

DATA BUS bidirectional

Microprocessor, by-itself, completely useless must have external peripherals to Interact

CPU: Central Processing Unit

8086 16 5-10 1Mb

RAM (Bytes) 128 128 256

A smaller computer, On-chip RAM, ROM, I/O ports... Serial ports 1 1 1

ExampleMotorolas 6811, Intels 8051, and PIC 16X Interrupts 6 6 8

1. Meeting the computing needs of the task efficiently and cost

Input Control CPU ALU Output

Address Data Von Neumann Architecture:

Data Data Data

Address Data Address Data

Fetches instructions and data Fetches Instruction and Data

1. Simple Instruction taking 1 cycle 1. Complex Instruction taking multiple cycles

3. Designed around pipeline 3. Designed around Instruction. Set

4. Instruction. executed by h/w 4. Instruction interpreted by micro program

5. Fixed format Instruction 5. Variable format Instruction

6. Few Instruction and modes 6. Many Instruction and modes

7. Complexity in the compiler 7. Complexity in the micro program

8. Multiple register sets 8. Single register set

9. Operates at 50-150 MHz 9. Operates at 33-50 MHz

Data bus width limits speed of execution

OSC Bus Serial

Accumulator A & B with 32 GPR, 21 SFRs

R6 Some 8051 16-bit Register hold

Some 8-bitt Registers of

34- general purpose, 3- pointers , 21 SFRs

Stack Pointer (SP ,8 bit 81)

Program Counter (PC, 16 bit 81)

TH0-TL0 and TH1-TL1 ---16 bit timer registers

PSEN (out): Program Store Enable, the read signal for

Port 0 pins 32-39P0P0.0P0.7

Port 1 pins 1-8 P1P1.0P1.7

Port 2 pins 21-28P2P2.0P2.7

Port 3 pins 10-17P3P3.0P3.7

Each port can be used as input or output (bi-direction)

Read latch Vcc

Internal CPU D Q P1.X

Write to latch Clk Q M1

Port 1 pins 1-8 P1P1.0P1.7

Read latch Vcc

Read latch Vcc

Read latch Vcc 2. MOV A,P1

Read latch Vcc 2. MOV A,P1

1. Register : mov a,b; mov a, r0

2. Direct : add a, 55h; mov@r0, 20h; mov 6,2; mov 56h,a

3. Register Indirect: mov a,@r0, mov@r1, a

4. Immediate : mov r0, #23h, add a, #1234h, mov @r0, #55h;

5. Implicit : CPL A; STB,C

6. Indexed Addressing: movc a, @a+dptr

MOV A,Direct MOV @Ri, A PUSH Direct

Rotate instructions operate only on a

SWAP A Mov a,#0xF0

DA: Decimal Adjust LJMP: Long Jump SETB: Set Bit

DEC: Decrement Register MOV: Move Memory SJMP: Short Jump

INC: Increment Register MUL: Multiply Accumulator by B XCH: Exchange Bytes