6.

012 - Microelectronic Devices and Circuits

Lecture 14 - Digital Circuits: Inverter Basics - Outline

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Review - Linear Equivalent Circuits

Everything depends on the bias; only low frequency for now
Digital building blocks - inverters
A generic inverter

MOS inverter options

Digital inverter performance metrics

Transfer characteristic: logic levels and noise margins
Power dissipation
Switching speed
Fan-out, fan-in
Manufacturability
Comparing the MOS options
And the winner is.
Clif Fonstad, 10/29/09 Lecture 14 - Slide 1
 Reviewing our LECs: Important points made in Lec. 14

We found LECs for BJTs and MOSFETs in both strong inversion

and sub-threshold. When vbs = 0, they all look very similar:
in iin Cm iout out
+ +
v in gi gmv in go v out
Ci Co
- -
common common

Most linear circuits are designed to operate at frequencies where

the capacitors look like open circuits. We can thus do our
designs neglecting them.*
Bias dependences: BJT ST MOS SI MOS
gi : q IC " F kT 0 0
gm : q IC kT q ID n kT 2K o ID # ST = sub-threshold

go : $ IC $ ID $ ID SI = strong inversion

The LEC elements all depend on the bias levels. Establishing a

known, stable bias point is a key part of linear circuit design.

We use our large signal models in this design and analysis.

!
* Only when we want to determine the maximum frequency to which
Clif Fonstad, 10/29/09 Lecture 14 - Slide 2
our designs can usefully operate must we include the capacitors.
 LECs: Identifying the incremental parameters in the characteristics
ln iB, ln iC iC
iC
BJT: IC
Q
iB
" "
IC
Q go Inc. i B

vCE vCE

gm = qIC/kT; g = gm with = diC/diB|Q; go = diC/dvCE|Q

MOSFET: iD (iD)1/2
gm Inc. |v BS |

go Q !
Q
Inc. v GS

vDS
VT vGS = vDS
gm = diD/dvGS|Q; gmb = gm with = -dVT/dvBS|Q; go = diD/dvDS|Q
Clif Fonstad, 10/29/09 Lecture 14 - Slide 3
 Building Blocks for Digital Circuits: inverters

A basic
V DD Performance metrics
Transfer characteristic
inverter v IN vOUT
Pull- Logic levels
Device: on or off Up Lo (0) Hi (1) Noise margins
Switch: open or Hi (1) Lo (0) Power dissipation
closed + Switching speed
+ vOUT Fan-in/Fan-out
vIN
Manufacturability
!
Logic gates V DD
Memory cell

V DD V DD
NOR: Pull-
NAND: Up
vA vB vOUT Pull- Pull- Pull-
Up vA vB vOUT
0 0 1 Up Up
+
0 1 0 0 0 1 +
+
1 0 0 + + 0 1 1 vA vOUT
vOUT
vA vB 1 0 1
1 1 0 +
vB
1 1 0
Flip-flop
Clif Fonstad, 10/29/09 Lecture 14 - Slide 4
!
!
 V DD
Inverter metrics: Transfer characteristic
The transfer characteristic, vOUT vs vIN, is found Pull-
applying the large signal models at this node Up
iPU
Node equation : iPD = iPU
iPD +
# 0* +
% vOUT
vIN
% when v IN < VT ,PD
(
%%K v " V
)
2
2
iPD = $
PD IN T ,PD
V OUT
% when 0 < [v IN " VT ,PD ] < vOUT
% K (v " V
T ,PD " vOUT 2)vOUT
% PD IN
%& when 0 < vOUT < [v IN " VT ,PD ]
iPU : Depends on the specific pull - up device used.

For simplicity: = 1, = 0
* Note: We can say iPD is zero for the
! purpose of calculating a transfer
characteristic. For power we may V IN
want to use:
iPD,off = IS,s"t e
"VT nVt V DD
Clif Fonstad, 10/29/09 Lecture 14 - Slide 5
 Inverter metrics: Transfer characteristic, cont.

V DD # K V 2
2
An example: NMOS % PU T ,PU

% when 0 < VT ,PU < [VDD " vOUT ]

iPU = $
Pull-up: Depletion mode %K PU [ VT ,PU " (VDD " vOUT ) 2](VDD " vOUT )
n-channel MOSFET %
(Note: VT,PU < 0) & when 0 < [VDD " vOUT ] < VT ,PU
# 0
+ %
% when v IN < VT ,PD
Pull-down: Enhancement
PD ( IN T ,PD )
+ ! v OUT %%K v " V 2
2
mode n-channel MOSFET v IN iPD = $
% when 0 < [v IN " VT ,PD ] < vOUT
% K (v " V
T ,PD " vOUT 2)vOUT
% PD IN
Identify the regions %& when 0 < vOUT < [v IN " VT ,PD ]
vOUT vOUT
vOUT = VT,PD
VDD VDD
PD ! PU linear
VDD - vOUT
off PD vOUT
= VDD - |VT,PD| = |VT,PU |
sat.
vIN-VT,PD

PD
PU saturated.
linear

vIN vIN
VT,PD VDD VT,PD VDD
Clif Fonstad, 10/29/09 Lecture 14 - Slide 6
 Inverter metrics: Transfer characteristic, cont.
Combine the plots; write the node equation in each region and solve.
vOUT 0 = K PU [ VT ,PU " (VDD " vOUT ) 2](VDD " vOUT )
VDD
K PD (v IN " VT ,PD ) 2 = K PU [ VT ,PU " (VDD " vOUT ) 2](VDD " vOUT )
2
PD off, PD sat,
PU lin. PU lin.
VDD - |VT,PD!
|
K PD (v IN " VT ,PD ) 2 = K PU VT ,PU
2 2
2
PD sat.,
!
PU sat. K PD (v IN " VT ,PD " vOUT 2)vOUT = K PU VT ,PU
2
2
PD off,
PU sat.
! vOUT
PD lin.,
PU sat.
! VDD
vIN
2
0 = K PU VT ,PU 2 VT,PD VDD
VDD - |VT,PD|
vOUT = VDD
K PD
(VDD " vOUT ) " 2VT ,PU (VDD " vOUT ) + (v IN " VT ,PD ) = 0
2 2
! K PU

(VT ,PD + VT ,PU )

! K PU
v IN =
K PD
! vIN
K
" 2(v IN " VT ,PD )vOUT " PU VT ,PU = 0
2 2
vOUT VT,PD VDD
Clif Fonstad, 10/29/09 K PD Lecture 14 - Slide 7
!
 Inverter metrics: Transfer characteristic, cont.

Is the characteristic really vertical and vOUT indeterminate when both

transistors are in saturation? It is if = 0 (i.e. no Early effect), but we
know this isn't true. We can find the slope when 0 from an LEC
analysis about the bias point vOUT = v IN = K PU K PD (VT ,PD + VT ,PU ) .
V DD id,pu id,pu
gpu dpu d
+ + + pu
! v gs = 0 0 go,pu v ds = -v out
go,pu
- -s -s
spu - pu pu

id,pd
+ gpd d
+ + pd
+ v OUT v gs = v in v ds = v out
v IN gm,pd v in go,pd
spd -- -s
pd

gpd dpd , spu v out gm, pd

Av " =#
+
go,pu
+ v in go, pd + go, pu
v in v out
gm,pd v in go,pd 2K PD ID
- - =#
spd , dpu spd , dpu $PD ID + $PU ID
Clif Fonstad, 10/29/09 This is the slope of the Lecture 14 - Slide 8
"vertical" portion.
 V DD
Inverter metrics:
Logic levels, noise margins Pull- Pull-
Up Up
vOUT1

+ +
Stage 1
+ vOUT1 + vOUT2 = vIN1
vIN1 vIN2
- - - -

vOUT
Stable solution
vIN1 V HI
V DD Tipping point
vIN2 45

V DD Stage 2 Unstable solution

VM
Tipping point
45
Stable
V LO solution

vOUT2
vIN
V LO V 1L V M V 1H V HI

Clif Fonstad, 10/29/09 NML NMH Lecture 14 - Slide 9

 Inverter metrics: Switching times (gate delay)

When the output goes from LO to HI, the load charge store must be
charged through the pull-up device. When the output goes from
HI to LO, it is discharged through the pull-down device.
V DD V DD

Pull- Pull-
iPU Up i
Up PU
iDischarge
+ ON +
OFF LO CL HI CL
+ + to
to LO to HI
HI to LO LO
HI iPD

Charging cycle: iCharge = iPU Discharging cycle: iDischarge = iPD iPU

We can often model CL as a linear capacitor (i.e. a multiple of Cox*) in
which case the charge and discharge cycles are found by solving:
dv 1 dv 1
" Ch arg e : OUT = iPU (vOUT ) " Disch arg e : OUT = [iPD (v IN ,vOUT ) # iPU (vOUT )]
dt CL dt CL
Clif Fonstad, 10/29/09 Lecture 14 - Slide 10

! !
 Inverter metrics: Power
Total Power:
Two components - static and dynamic (switching)
PTotal = PStatic + PDynamic
Static: V DD V DD

Pull-down off: ! Pull- Pull-down on: Pull-

Up Up
iPU iPU

iPD + iPD +
+ vOUT + vOUT
vIN vIN

PStatic,off = IPD,off VDD ( " 0) PStatic,on = IPU ,onVDD

To estimate the total static power we assume the typical pull-down
is off half the time and on half the time.
PStatic,off = ( IPD,off + IPU ,on ) VDD
1 1 1
! PStatic,ave = PStatic,on + !
2 2 2
Clif Fonstad, 10/29/09 Lecture 14 - Slide 11
 Inverter metrics: Power, cont.

Dynamic: V DD V DD

Charging cycle: Pull- Discharging cycle: Pull-

iPU
Up Up i
PU
iDischarge
+ ON +
OFF LO CL HI CL
+ to +
HI to LO to
HI LO to HI LO
iPD

1 2 1 2 1 2
CLVDD Dissipated, CLVDD Stored CLVDD Dissipated
2 2 2
2
Energy dissipated per cycle : CLVDD
PDynamic,ave = f CLVDD
2

! Cycles per second : f !

( PD,off PU ,on ) DD
1
Total: PTotal = I + I V + f C V 2
L DD
2
!
Clif Fonstad, 10/29/09
! Lecture 14 - Slide 12

 V DD V DD
MOS

inverters:
Pull- RL
5 pull-up Up Resistor

choices pull-up

+ +
CL
+ v OUT + v OUT
Generic v IN v IN
inverter

V DD V DD V DD V DD

V GG
(>>V DD )

+ + + + +
+ v OUT + v OUT + v OUT v IN v OUT
v IN v IN v IN

n-channel, e-mode pull-up* n-channel, d-mode Active p-channel

VDD on gate VGG on gate pull-up (NMOS) pull-up (CMOS)**
Clif Fonstad, 10/29/09 Lecture 14 - Slide 13
* Called PMOS when made with p-channel FETs. ** Notice that CMOS has a larger (~3x) input capacitance.
 MOS inverters: Comparing the 5 pull-up choices
Ground rules:
To make the comparison meaningful, we set the following
conditions:
1. We use the same pull-down device with each of the
different pull-ups.
2. We use the same fan out, n, to identical inverters to
have a valid comparison of the amount of charge that
must managed to charge and discharge, and of the
dynamic power dissipation. We also assume the load
capacitance, CL, is linear and n times a single inverter
input capacitance.
3. We use the same VHI and IPU,on so the static power
dissipation is the same.
In this way we can see which pull-up gives us the highest
speed, all else being equal.
Clif Fonstad, 10/29/09 Lecture 14 - Slide 14
 V DD V DD
Switching transients
Pull- iPU Pull-
General approach Up Up i
The load, CL, is a non- PU
iDischarge
linear charge store, but
+ ON +
for MOSFETs it is fairly OFF LO CL HI CL
+ + to
linear and it is useful to HI to LO to
LO to HI
HI LO
think linear: iPD
dvOUT
= iC L (vOUT ) CL Charging cycle: Discharging cycle:
dt iCharge = iPU iDischarge = iPD iPU

Charge i
Charging CL:
The charging

! Bigger current
current for the
CMOS, I ON = 0 faster vOUT change
various MOSFET

pull-up options
n-ch, d-mode
ION
resistor and n-ch, e-mode
w. V GG on gate
n-ch, e-mode
V DD on gate
vOUT
Clif Fonstad, 10/29/09 V DD Lecture 14 - Slide 15
 V DD
Switching transients, cont.
Discharging CL: Pull-
Up i
This depends on the pull-up device,
PU
iDischarge
as well as the pull-down

ON +
The discharging current for the
HI CL
+ to
various pull-up options
LO to HI LO
iPD
i i PD = i Discharge + iPU
Discharging cycle:
iDischarge = iPD iPU

The discharge
n-ch, d-mode current (iDischarge)
ION is the difference
resistor and n-ch, e-mode
iPU!s w. V GG on gate between the upper
n-ch, e-mode curve (iPD) and the
V DD on gate appropriate lower
vOUT
V DD curve (iPU).
CMOS (i PU = 0)

Which pull-up is best? To see we next look

Clif Fonstad, 10/29/09 at each in turn and then compare them. Lecture 14 - Slide 16
Switching transients, cont.

Charging and discharging: iPU = iCharge

Linear resistor pull-up
V DD
ION
iCharge v OUT
RL V DD

+ iPD = iDischarge + iPU

+ v OUT
v IN iDischarge
ION
v OUT
Simple
Least costly with discrete components V DD
but integrated resistors consume lots
of space. Charge >> Discharge
Clif Fonstad, 10/29/09 Lecture 14 - Slide 17
Switching transients, cont.

Charging and discharging: iPU = iCharge

Saturated E-mode pull-up
V DD
ION
iCharge v OUT
V DD
iPD = iDischarge + iPU
+
+ v OUT
v IN ION iDischarge

v OUT
No added cost in adding more MOSFETs V DD
Very compact
No added wiring
Slower than linear resistors
Charge >>> Discharge
Clif Fonstad, 10/29/09 Lecture 14 - Slide 18
Switching transients, cont.

Charging and discharging: iPU = iCharge

Linear E-mode pull-up
V DD
ION
iCharge v OUT
V GG V DD
(>>V DD)

+ iPD = iDischarge + iPU

+ v OUT
v IN iDischarge
ION
v OUT
Still compact

Need to wire VGG to each gate

V DD
Need second supply

Not faster than linear resistor

Charge >> Discharge
Clif Fonstad, 10/29/09 Lecture 14 - Slide 19
Switching transients, cont.

Charging and discharging: iPU = iCharge

D-mode pull-up ("NMOS")
V DD
ION
iCharge v OUT
V DD

+ iPD = iDischarge + iPU

+ v OUT
v IN iDischarge
ION
v OUT
Compact
Symmetrical charge/discharge V DD
Fastest possible
Must make E- and D-mode on safe wafer Charge Discharge
Clif Fonstad, 10/29/09 Lecture 14 - Slide 20
Switching transients, cont.
Charging and discharging: iPU = iCharge
Active complementary pull-up
("CMOS")
V DD
iCharge
v OUT
ION
V DD
ION = 0
+ + iPD = iDischarge + iPU
v IN v OUT
iDischarge
ION v OUT
Symmetrical charge/discharge

Almost as fast, or even faster than, n-MOS*

V DD
MInimal static power dissipation (ION 0)

Must make n- and p-channel on same wafer Charge Discharge

Clif Fonstad, 10/29/09 * The input capacitance is 3x larger, but the interconnect capacitance Lecture 14 - Slide 21
is the same, so it depends on which of the two is dominant.
 Switching transients: summary of charge/discharge currents
V DD V DD iPU = iCharge iPD = iDischarge + iPU
Resistor and E- RL V GG
mode pull-up (>>V DD ) iDischarge
ION ION
+ +
(VGG on gate) + v OUT iCharge v OUT v OUT
+ v OUT
v IN v IN
V DD V DD
V DD iPU = iCharge iPD = iDischarge + iPU

E-mode pull-up

(VDD on gate)
ION ION iDischarge
+
+
v IN
v OUT iCharge v OUT v OUT

V DD V DD
V DD iPU = iCharge iPD = iDischarge + iPU

D-mode pull-up
iDischarge
(called "NMOS")
+
ION ION
+ v OUT
iCharge v OUT v OUT
v IN

V DD V DD
V DD iPU = iCharge iPD = iDischarge + iPU

CMOS
iCharge iDischarge
+ +
v IN v OUT v OUT I v OUT
ION ON
V DD V DD
Clif Fonstad, 10/29/09 ION = 0 Lecture 14 - Slide 22
Comparisons made with same pull-down MOSFET, VHI, and ION.
 MOS Technology: An abbreviated history
p-MOS:
In the beginning (mid-60s) there were only metal-gate p-channel e-
mode MOSFETs; n-channel MOSFETs came out d-mode. p-MOS
logic relied on saturated and linear e-mode pull-ups.
n-MOS:
With the development of <100> substrates, e-beam deposition, self-
aligned poly-Si gates, and ion implantation, initially to improve p-
MOS, it became possible to also reliably fabricate e-mode n-chan-
nel FETs. NMOS, with d-mode pull-ups, then took off (ca 1970).
CMOS:
It was clear for many years that CMOS inverters were superior, but
fabricating them reliably in high density and at low cost was a big
challenge. Eventually manufacturers learned how to make n- and
p-channel MOSFETS together in close proximity and economically
(ca 1980); CMOS then soon became the dominant IC technology
because of its superior low power and high speed.
For the past decade the industry has been fixated on systematically
making FETs smaller, circuits more dense, and wafers larger.*
Clif Fonstad, 10/29/09 Lecture 14 - Slide 23
* And with good reason; more next week in Lecture 17.
 6.012 - Microelectronic Devices and Circuits
Lecture 14 - Digital Circuits: Inverter Basics - Summary

Digital building blocks - inverters

A generic inverter: Switch = pull-down device, Load = pull-up device
MOS inverter options - Pull-down: n-channel, e-mode (faster than p-channel)
Pull-up: 1. resistor; 2. n-channel, e-mode w. and w.o. gate bias;
3. n-channel, d-mode (NMOS); 4. p-channel, e-mode (CMOS)
Digital inverter performance metrics
Transfer characteristic

Logic levels: VHI, VLO

Noise margins: NMHI (high), and NMLO (low)

Design variables: choice of pull-up device

pull-up and pull-down thresholds

device sizes (absolute and relative)

Power dissipation: stand-by power and switching dissipation

Switching speed: capacitive load

charge and discharge currents critical

Fan-out, fan-in: minimal issue in MOS; more so with BJT logic
Manufacturability: small, fast, low-power, reliable, and cheap
Comparing the MOS options
And the winner is.CMOS
Clif Fonstad, 10/29/09 Lecture 14 - Slide 24
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6.012 Microelectronic Devices and Circuits

Fall 2009

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