IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO.
1, FEBRUARY 2006
Adaptive Two-Loop Voltage-Mode Control of
DCDC Switching Converters
Emilio Figueres, Associate Member, IEEE, Gabriel Garcer, Member, IEEE, Jos M. Benavent,
Marcos Pascual, Member, IEEE, and Juan A. Martnez
AbstractA new two-loop control scheme for voltage-mode
control (VMC) of dcdc switching converters is presented. The
proposed method adds a high-gain robust loop with two con-
trollers to the conventional VMC loop, achieving an analog adap-
tive loop in which the equivalent voltage regulator varies
with the changing power stage parameters given as follows:
1) input voltage; 2) load; and 3) component tolerances. The loop
significantly improves the disturbance rejection of the control
system, i.e., closed-loop output impedance and audiosusceptibil-
ity while preserving the stability and the loop gain crossover
frequency to a significant extent. Both the small-signal analysis
and the experimental results carried out on a buck converter
demonstrate the superiority of the proposed scheme with respect
to the conventional single loop.
Index TermsPulsewidth-modulation (PWM) dcdc convert-
ers, reference-model-based control, robust control.
N OMENCLATURE
VMC Voltage-mode control.
A2LVMC Adaptive two-loop voltage-mode control.
fs , Ts , s Switching frequency, switching period,
switching angular frequency.
Se Slope of the pulsewidth modulator (PWM)
ramp.
Vpp Peak-to-peak voltage of the PWM ramp.
Fm Gain of the PWM modulator.
Gain of the output voltage sensor.
Vi , Vo Steady-state input and output voltage.
D Steady-state duty cycle.
Io Steady-state output current.
vc , vc Small-signal control voltage, ripple at the
control voltage.
d Small-signal duty cycle.
vo , iL
vi , io
Small-signal output voltage, inductor current.
Small-signal input voltage, load current dis-
turbance.
VOD(s) Small-signal transfer function of the power
stage in VMC.
VOC(s) Small-signal transfer function of the power
stage in VMC including the PWM modulator.
A(s), Zo (s) Open-loop audiosusceptibility, output im-
pedance.
Manuscript received August 21, 2002; revised July 29, 2005. Abstract
published on the Internet November 25, 2005.
The authors are with the Departamento de Ingeniera Electrnica,
Universidad Politcnica de Valencia, Valencia 46022, Spain (e-mail:
efiguere@eln.upv.es).
Digital Object Identifier 10.1109/TIE.2005.862254
0278-0046/$20.00 2006 IEEE
239
Acl (s), Zocl (s) Closed-loop audiosusceptibility, output im-
pedance.
Gv (s) Transfer function of the voltage regulator in
conventional VMC.
Tv (s) Voltage loop gain in conventional VMC.
G1 (s) Transfer function of the inner loop-shaping
regulator in A2LVMC.
G2 (s) Transfer function of the inner loop reference
model controller in A2LVMC.
Gv-A2L (s) Transfer function of the outer voltage regula-
tor in A2LVMC.
VOCref (s) Transfer function of the VMC reference
power stage for the design of the A2LVMC
control loop.
VOU(s) Equivalent power stage seen by the outer
voltage regulator in A2LVMC.
Ta (s) Loop gain of the inner adaptive loop in
A2LVMC.
Tv-A2L (s) Outer voltage loop gain in A2LVMC.
fC Crossover frequency of the loop gain.
fC1 , fC2 Crossover frequencies of the voltage loop
gain in conventional VMC with two different
voltage regulators.
fCa Crossover frequency of the inner adaptive
loop gain in A2LVMC.
fCv-A2L Crossover frequency of the outer voltage loop
gain in A2LVMC.
I. I NTRODUCTION
O NE of the most extended control methods of dcdc
switching converters is VMC [1], in which there is a
single feedback loop. Although other control schemes like
current-mode controls [2], [3] present several advantages with
respect to VMC, the voltage mode scheme remains useful when
the sensitivity to the current loop noise is not desired, when
there is a wide input voltage variation or when multiple outputs
are needed with a relatively good cross-regulation [4].
Since the small-signal linear model of VMC depends on
the input voltage, the load, and the passive elements of the
power stage, the small-signal transfer functions and properties
derived from the model, like loop gain, closed-loop output im-
pedance, and closed-loop audiosusceptibility also do. The loop
performance and loop stability will be consequently affected
by those variations, and the designer must choose conservative
specifications as design objectives.
240 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 1, FEBRUARY 2006
The purpose of this paper is to present a significant ro-
bustness improvement over conventional single-loop VMC of
dcdc converters. The proposed adaptive two-loop VMC
(A2LVMC) follows a reference-model-based control scheme,
consisting of the addition of a high-gain robust loop with
adaptive nature to the conventional single loop. A2LVMC
has been derived from a similar scheme successfully applied
to average current-mode control in [5] [three-controller robust
average current-mode control (3CRACC)] and to voltage mode
in [6] [two-controller robust VMC (2CRVMC)]. A2LVMC
overcomes some limitations of 3CRACC and 2CRVMC, giving
more degrees of freedom than those schemes for the design
of the robust loop, presenting less noise problems, and being
more robust and stable. The proposed scheme uses two control
loops and three controllersan inner adaptive loop with two
controllers and an outer voltage loop with one controller.
A small-signal study of A2LVMC is carried out in this paper,
showing the following facts.
1) Unlike conventional VMC, A2LVMC significantly pre-
serves the loop bandwidth and stability margins with a
large variation of the input voltage, the load, and the
tolerances of the passive components of the power stage.
2) A2LVMC improves the closed-loop disturbance rejection
properties, i.e., closed-loop output impedance and audio-
susceptibility, in more than 2030 dB with respect to
conventional VMC.
3) The proposed scheme can achieve that the power stage
seen by the voltage regulator of the outer loop becomes
a first-order system like current-mode controls do [2], [3].
Loop shaping is, therefore, simplified with respect to
conventional VMC, in which the power stage to be com-
pensated is a second-order transfer function.
An analytical study of the loop sensitivity to the variation of
the power stage elements both with conventional VMC and with
A2LVMC has been performed by means of the Monte Carlo
analysis of PSPICE.
In order to validate the concept, experimental measurements
of the converter small signal properties and of the large signal
output voltage response to load steps have been carried out on
a Buck converter prototype 5 V5 A, 50 kHz.
II. D ESCRIPTION OF THE A2LVMC
A. Conventional VMC
Fig. 1 shows the well-known implementation of the con-
ventional VMC loop around a Buck converter. Fig. 2 shows
a widely accepted linear small-signal circuit in continuous
conduction mode (CCM) derived from [7] and [8]. A similar
equivalent circuit exists for discontinuous conduction mode
(DCM) [8]. Those models are valid from dc up to fs /2. Line
and load disturbances are also considered in the model.
Table I summarizes the expressions of all the transfer func-
tions of interest for a Buck converter working in CCM, whose
derivation is shown in Appendix A. As shown by the equiv-
alent control block diagram of VMC in Fig. 3(a), the voltage
regulator Gv (s) must compensate a second-order transfer func-
tion VOC(s) = Fm VOD(s) in order to achieve a loop gain
Fig. 1. Conventional VMC of a Buck converter.
Tv (s) = VOC(s) Gv (s). Fig. 3(b) shows the asymptotic
magnitude Bode plot of Tv (s) after the compensation proce-
dure, which is described in Appendix B.
B. Antecedents of A2LVMC
Fig. 4(a) shows the 2CRVMC scheme introduced in [6]. A
similar loop was applied to average current-mode control in [5].
As explained in [6], the transfer function of the reference
model controller G2 (s) is the inverse one of a desired refer-
ence power stage VOCref (s) = Fm VODref (s), i.e., G2 (s) =
1/VOCref (s). Therefore, the output of G2 (s), vc-est (s), is an
estimation of the control voltage vc (s), which would be present
at the input of the PWM modulator if the actual power stage
were the reference one and without disturbances. In Fig. 4(a),
it can be noticed that if Fm (VOD(s) = Fm VODref (s)
and io = vi = 0, then vo = Fm VODref (s) vc (s), so that
vc-est (s) = G2 (s) vo (s) = vc (s). The estimated control volt-
age is subtracted from the actual one to provide an estimation
error (s), which is multiplied by the robust performance
weighting factor Wr , a gain that can be adjusted between
zero and one. This signal is added to the output of the regulator
Gvr (s), reinforcing its action, and achieving that the equivalent
power stage VOU(s, Wr ) seen by Gvr (s) is very similar to
VOCref (s) in a certain low-frequency range, in spite of changes
in the load, input voltage, and tolerances in the power stage
passive components (L, C, Rc , . . .).
In Fig. 4(b), an equivalent scheme has been derived in order
to show that 2CRVMC may be interpreted as a two-loop control
scheme with an outer (and main) voltage loop Tv (s, Wr ) and an
inner robust loop with adaptive effects Ta (s). The condition
for being VOU(s, Wr ) VOCref (s) is met in the frequency
range where |Ta (j)|  1. If this range includes from dc to the
desired crossover frequency of Tv (s, Wr ), the design of Gvr (s)
is made easy, because it has to compensate an almost-fixed
transfer function VOU(s, Wr ) VOCref (s). That is called the
robustness condition, and it is fulfilled for high values of
Wr (Wr 1).
As it can be deduced from Fig. 4(b), the main limitation of
this scheme is the amplification of the output voltage switching
FIGUERES et al.: ADAPTIVE TWO-LOOP VOLTAGE-MODE CONTROL OF DCDC SWITCHING CONVERTERS 241

Fig. 2. Small-signal circuit of VMC in CCM.

TABLE I
SUMMARY OF THE TRANSFER FUNCTIONS OF A VMC-CONTROLLED BUCK CONVERTER

noise by Wr G2 (s) and by the equivalent gain 1/(1 Wr ).
A risk of instability in the large signal sense may appear if
too much switching noise is present at the input of the PWM
modulator vc , specially if its ripple vc is comparable to the
peak-to-peak voltage of the PWM ramp Vpp .
It is difficult to fulfil the robustness condition and to
simultaneously limit the switching noise at the control voltage,
because the designer only has the gain Wr (0 < Wr < 1) as
a degree of freedom. Fig. 4(c) shows the proposed A2LVMC,
in which the adaptive loop has been built in a similar way to
that in Fig. 4(b), but the degrees of freedom in the loop shaping
of Ta (s) have been increased by adding a high-gain regulator
G1 (s) with some poles and zeroes into the loop. Note that
no comparison between the actual and the estimated control
242
Fig. 3. Conventional VMC. (a) Simplified scheme. (b) Asymptotic magnitude Bode plot of Tv (s) after compensation by means of Gv (s).
voltage is carried out in A2LVMC, because the loop has been
derived from the scheme of Fig. 4(b) by substituting the gain
1/(1 Wr ) by the controller G1 (s). As a result, A2LVMC is
superior to 2CRVMC, because the designer has more degrees
of freedom to simultaneously fulfil the robustness condition
and to limit the switching noise at the control voltage.
C. Description of A2LVMC
As explained in the previous paragraph, the adaptive loop
Ta (s) of A2LVMC contains two regulators, namely: 1) a loop-
shaping regulator G1 (s); and 2) a reference model controller
G2 (s). The general expression of the reference model controller
is given by (1), where VOCref (s) = bref /(1 + s/aref ) is a
reference VMC power stage transfer function. The pole at p3
limits the gain of G2 (s) at the switching frequency (p3 <
s ). It will be shown in the next paragraphs that if a certain
robustness condition is fulfilled, the equivalent power stage
VOU(s) seen by the voltage regulator will be very similar
to 1/G2(s) = VOCref (s) (1 + s/p3 ) in a certain frequency
range. Although the power stage with VMC is second order
in CCM, it will be also shown that the designer can choose
VOCref (s) as a first-order transfer function. This choice does
not compromise the fulfillment of the robustness condition
and provides two benefits.
1) The loop shaping of the main voltage loop Tv-A2L (s) is
simplified with respect to conventional VMC, because the
equivalent power stage seen by the voltage regulator
Gv-A2L (s) is essentially first order.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 1, FEBRUARY 2006
2) Conditions about noise in the control voltage are eas-
ier to satisfy than in the case of choosing a second-
order reference model. Because of the derivative nature
of G2 (s), the switching noise amplification would be
excessive if VOCref (s) were chosen as a second-order
system.
Note that the zero at p3 in 1/G2 (s) VOU(s) is easy
to cancel out in the outer loop Tv-A2L (s) by including a
pole at the same frequency in Gv-A2L (s). Thus, the power
stage to be compensated will be close to a first-order transfer
function VOCref (s) like current-mode controls do [2], [3].
The loop shaping of Tv-A2L (s) is then simplified with re-
spect to VMC, because the power stage to be compensated,
VOU(s) VOCref (s) (1 + s/p3 ), is essentially first order.
The achieved robustness to parameter variation may be very
high, because VOCref (s) does not depend on the actual power
stage elements variation. The regulator G1 (s) is for the ad-
equate loop shaping of Ta (s), giving high gain at low fre-
quency to improve the overall disturbance rejection, Zocl (s)
and Acl (s) as will be shown further. The adaptive loop gain
Ta (s) is expressed by (2) as it can be easily derived from
Fig. 4(c)


s
1 1 + aref
G2 (s) =
=
 (1)
VOCref (s) 1 + s
bref 1 + sp3
p3
Ta (s) = G1 (s) G2 (s) VOC(s). (2)
FIGUERES et al.: ADAPTIVE TWO-LOOP VOLTAGE-MODE CONTROL OF DCDC SWITCHING CONVERTERS 243

Fig. 4. Evolution from 2CRVMC to A2LVMC. (a) 2CRVMC scheme. (b) Equivalent 2CRVMC scheme. (c) Proposed A2LVMC.

D. Robustness Condition
From Fig. 4(c), it can be observed that the modified power
stage VOU(s) seen by Gv-A2L (s) is different from the VMC
power stage, VOC(s). VOU(s) is shaped by G1 (s) and G2 (s),
following (3). If condition (4) holds in a certain frequency
range, in this range, VOU(s) will be very similar to 1/G2 (s) =
VOCref (s) (1 + s/p3 ), being VOU(s) almost independent
on the changing power stage parameters (Vi , R, and component
244 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 1, FEBRUARY 2006

tolerances). Equation (4) is the robust performance condition

of the proposed loop

vo (s) 
VOU(s) =
(s) vi=io=0
u
G1 (s) VOC(s)
=
1 + G1 (s) G2 (s) VOC(s)
G1 (s) VOC(s)
= (3)
1 + Ta (s)
1
If |Ta (j)| 1 VOU(s)
 G2 (s) 
s
= VOCref (s) 1 + . (4)
p3

The loop shaping of Ta (s) is carried out by a proper design

of G1 (s) and G2 (s). For fulfillment of the robust performance
condition, it is desired to obtain a crossover frequency of
Ta (s), fCa , as high as possible, so that |Ta (j)| is high enough
at the desired crossover frequency fCv-A2L of Tv-A2L (s). In
this way, VOU(s) will be very similar near fCv-A2L to a fixed
transfer function expressed by (4), and its compensation by
means of Gv-A2L (s) will be easy in spite of parameter varia-
tions in VOC(s). The upper limit on fCa is imposed by two
factors, namely: 1) the switching noise at the control voltage
vc ; and 2) the stability of Ta (s). A compromise solution
between noise and robust performance is to choose fCa
2 fCv-A2L 4 fCv-A2L , being fCa < fs /3 as always.
The proposed high-gain regulator G1 (s) looks like (5). The
poles p1 , p2 , and p3 of G1 (s) and G2 (s) are located for
proper switching noise attenuation as


Ka 1 + sz1
G1 (s) =

.
1 + sp1 1 + sp2
The choice of VOCref (s) depends on the dominant poles
of the actual power stage VOC(s). For stability reasons, it is
recommended to place the pole aref of VOCref (s) below the
resonance frequency n = 1/(LC)1/2 of the power stage. The
dc gain of VOCref (s) may been chosen as: bref = Fm Vi-min ,
i.e., equal to the minimum dc gain of VOC(s). Equation (6)
summarizes the choice of VOCref (s) as
bref
VOCref (s) = s aref n
1 + aref
1 An approximated expression of Tv-A2L (s) from dc to fCv-A2L
= , bref Fm Vi- min . (6)
LC
For the shaping of Ta (s), the stability worst case takes place
when the input voltage is maximum (Vi = Vi- max ). In those
conditions, the highest possible dc gain of VOC(s) results,
achieving fCa its highest value (see Table I). That situation
represents the stability worst case of Ta (s). Thus, the tuning
of G1 (s) and G2 (s) must be done for this worst case.
According to (2), the adaptive loop Ta (s), i.e., G1 (s) and
G2 (s), may be tuned by means of conventional loop-shaping
techniques in order to obtain fCa 2 fCv-A2L 4 fCv-A2L
with acceptable phase and gain margins, PM and GM, re-
Fig. 5. Asymptotic magnitude Bode plots explaining the loop shaping in
A2LVMC. (a) Ta (s). (b) Tv-A2L (s).
spectively. For stability reasons in the large signal sense, the
attenuation of the switching noise in the control voltage is also
a factor to take into account. The switching frequency ripple
Vo in the converter output voltage achieves its highest value
for the maximum input voltage. Vo is amplified by G2 (s)
and by G1 (s), so that vc Vo |G1 (js ) G2 (js )|. A
good criterion is to limit |G1 (js ) G2 (js )|, so that vc <
(5) Vpp /10. This limitation must be checked in the design stage of
G1 (s) and G2 (s), determining the maximum attainable value
of fCa .
Fig. 5(a) shows the asymptotic magnitude Bode plots of
the loop shaping of Ta (s) by means of G1 (s), G2 (s), and
VOCref (s).
E. Design of the Voltage Regulator Gv-A2L (s)
Gv-A2L (s) is designed following (7) for the cascade com-
pensation of VOU(s). The compensation is easy, because
VOU(s) suffers from little variation with the varying power
stage parameters up to the desired fCv-A2L if fCa > fCv-A2L .
is shown by (8). Gv-A2L (s) contains a pole at p3 to cancel
out the zero of VOU(s) that appears in (4). Fig. 5(b) shows
the asymptotic magnitude Bode plots of the loop shaping of
Tv-A2L (s) by means of Gv-A2L (s), given as


iv 1 + szv
Gv-A2L (s) =
 (7)
s 1 + sp3
Tv-A2L (s) = Gv-A2L (s) VOU(s)
 
bref s
Gv-A2L (s) s 1+ . (8)
1 + aref p3
FIGUERES et al.: ADAPTIVE TWO-LOOP VOLTAGE-MODE CONTROL OF DCDC SWITCHING CONVERTERS 245


F. Design Procedure for the A2LVMC Regulators vo (s) 
Acl (s) =
The following design procedure for the loop shaping of Ta (s)
and Tv-A2L (s) is proposed, as illustrated by the asymptotic
Bode plots of Fig. 5.
1) Choose fCv-A2L fs /10 and fCa 2 fCv-A2L to 3
fCv-A2L .
2) Choose VOCref (s) according to (6).
3) Choose p1 = aref to cancel out the fixed zero of G2 (s)
at aref .
4) Choose a high-frequency pole p2 S /2 to filter the
switching noise in Ta (s).
5) Choose p3 to cancel out the equivalent series resistance
(ESR) zero of the VMC power stage VOC(s), i.e., p3 =
ESR = 1/Rc C.
6) Choose z1 Ca in order to provide enough phase
lead to Ta (s) at the desired fCa , so that a phase margin
of Ta (s) higher than 50 results after adjusting Ka .
Note that the slope of |Ta (j)| (decibel) should be
20 dB/dec at the desired fCa .
7) Adjust the gain Ka for the desired crossover frequency
fCa , verifying that at the desired fCv-A2L , the gain of
Ta (s) is at least 6 dB in order to satisfy the robustness
condition.
8) Check the ripple condition for vc : |G1 (js )
(G2 (js )| Vpp /(10 Vo- max ).
9) Choose zv aref in order to provide enough phase lead
to Tv-A2L (s) at the desired fCv-A2L .
10) Adjust the gain iv for the desired crossover frequency,
fCv-A2L .
Note that VOC(s) depends on the input voltage Vi , as shown
in Table I. Therefore, if a high fCa is desired, the worst stability
case of Ta (s), which takes place for high values of Vi , must
be studied. On the other hand, the value of fCv-A2L that will
be chosen for the loop shaping of Tv-A2L (s) is defined by the
frequencies at which |Ta (j)| 6 dB.
G. Improvement of the Disturbance Rejection
Transfer Functions
From Fig. 4(c), the expressions of the closed-loop output
impedance (9) and audiosusceptibility (10) are derived. It can
be noticed that if G1 (s) = 1 and G2 (s) = 0 (i.e., Ta (s) = 0),
both expressions agree with their counterparts in conventional
VMC (Table I). One of the improvements of both trans-
fer functions is the introduction of the summing term Ta (s)
in the respective denominators. Another improvement is the
denominator term G1 (s) Gv-A2L (s) VOC(s), containing
the product of two regulators with high gain at low frequency.
Both terms decrease the low-frequency gain of Zocl (s) and
Acl (s). Therefore, in the range of frequencies where the ro-
bustness condition (|Ta (j)|  1) is fulfilled, the closed-loop
disturbance rejection improves, because the associated transfer
functions become smaller

vo (s) 
Zocl (s) =
io (s) 
vi (s) io =0;vc =0
A(s)
= . (10)
1 + Ta (s) + G1 (s)Gv-A2L (s)VOC(s)
H. Adaptive Loop Interpretation
By substituting (3) into (8), an additional expression (11)
of Tv-A2L (s) results, where the transfer function Ga (s) (12)
appears in series with the VMC power stage transfer function
VOC(s). Ga (s) may be interpreted as an equivalent adaptive
controller, which varies with the power stage transfer function
VOC(s). It is easy to notice that if |VOC(j)| increases,
|Ga (j)| decreases, and vice versa, keeping the outer voltage
loop crossover frequency and stability near the desired values
by means of simple analog regulators G1 (s) and G2 (s). Fig. 6
illustrates the adaptive interpretation of A2LVMC
Tv-A2L (s)
= Gv-A2L (s) VOU(s)
G1 (s)
= Gv-A2L (s) VOC(s)
1 + G1 (s) G2 (s) VOC(s)
= Ga (s) VOC(s) (11)
Ga (s)
G1 (s)
= Gv-A2L (s) . (12)
1 + G1 (s) G2 (s) VOC(s)
III. R ESULTS
A. Description of the Prototype
A2LVMC has been applied to a Buck converter operating
from an input voltage Vi = 1530 V (25 V nominal), giving a
regulated output voltage of Vo = 5 V and a maximum current of
5 A. The switching frequency is fs = 50 kHz and the nominal
values of the output filter elements are given as follows: L =
100 H; C = 940 F; and Rc = 35 m. Other values of
interest are given as follows: Vpp = 1.8 V; Fm = 0.556 V1 ;
and = 0.56. A converter prototype (Fig. 7) with those val-
ues has been built around a commercial PWM integrated cir-
cuit (UC1825) and some operational amplifiers. The dynamic
characteristics of both conventional VMC and A2LVMC have
been measured with different values of the input voltage and
the load.
In order to properly compare the performance of both
control schemes, the following design issues have been es-
tablished:
1) It is chosen: fCv-A2L fs /10 = 5 kHz. The loop shap-
ing of Ta (s) is carried out to fulfil the robustness condi-
tion (4) from dc to fCv-A2L .
2) For conventional VMC, two different regulators Gv1 (s)
and Gv2 (s) have been chosen for cascade compensation
of the nominal power stage VOC(s). With the slow
v vc =0
i =0; controller Gv1 (s), the resulting loop gain Tv1 (s) presents
Zo (s) a crossover frequency fC1 equal to the crossover fre-
= (9)
1 + Ta (s) + G1 (s)Gv-A2L (s)VOC(s) quency fCv-A2L , i.e., fC1 fCv-A2L 5 kHz. With
246 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 1, FEBRUARY 2006

Fig. 6. Adaptive interpretation of A2LVMC.

Fig. 7. Schematics of A2LVMC.

the fast controller Gv2 (s), the resulting loop gain B. Adaptive Loop Design
Tv2 (s) presents a crossover frequency similar to fCa
VOCref (s) has been chosen according to (6), following (13).
in the stability worst case (Vi- max ), i.e., fC2 fCa
Equations (14) and (15) give the expressions of the chosen
12 kHz.
regulators G1 (s) and G2 (s). The design of the regulators
A comparative study of the crossover frequency sensitivity (13)(15) has been carried out following steps 1) to 8) of the
of conventional VMC with Gv1 (s) and A2LVMC has been design procedure explained in Section II-F
carried out. In this case, it would not be correct to perform
a comparative analysis of the disturbance rejection properties
of both schemes, because A2LVMC has an inner loop Ta (s) 8
VOCref (s) = s (13)
with a higher crossover frequency fCa = 12 kHz. In order to 1+
properly study the disturbance rejection, it is more convenient
2400
 
600 1 + 9000
s
to compare loops with similar maximum crossover frequencies, G1 (s) =     (14)
so that Gv2 (s) will be considered in this case.
s
1 + 200 1 + 140s000
FIGUERES et al.: ADAPTIVE TWO-LOOP VOLTAGE-MODE CONTROL OF DCDC SWITCHING CONVERTERS 247

with the chosen regulators is vc = 180 mV at 30 V (10% of

Vpp = 1.8 V).
Fig. 9 shows the experimental measurement of the actual
power stage VOC(s) and of the modified one VOU(s) for some
values of the input voltage. As expected, VOU(s) looks like
the inverse transfer function of the reference model controller
G2 (s) in the range of frequencies where the robustness condi-
tion is fulfilled (up to fCv-A2L = 5 kHz), with a low dispersion
in the curves in spite of the large input voltage variation. At high
frequencies, the dispersion of the curves increases, because the
robustness condition is not satisfied.
On the other hand, VOC(s) presents higher sensitivity than
VOU(s) to the input voltage variation. Note that VOU(s) is
easier to stabilize than VOC(s), because its phase in the range
below 10 kHz is more positive (first order) in all the cases.

C. Shaping of the Voltage Loop

The voltage regulator with the proposed loop Gv-A2L (s) (16)
has been designed for cascade compensation of VOU(s),
achieving a crossover frequency fCv-A2L = 5 kHz with
PM = 65 . The design of Gv-A2L (s) (16) has been carried out
following steps 9) and 10) of the design procedure explained
in Section II-F


 
iv 1 + szv 3600 1 + 1600s
Gv-A2L (s) =
 =   . (16)
s 1+ s s 1 + 27 s000
p3

Equations (17) and (18) show the expressions of the cho-

sen voltage controllers for conventional VMC, Gv1 (s) and
Gv2 (s), respectively. Both controllers have been designed for
cascade compensation of VOC(s) at Vi = 25 V. As explained
in Section III-A, Gv1 (s) achieves a crossover frequency of
its loop gain Tv1 (s) (19) of fC1 = 5 kHz at 25 V (similar
Fig. 8. Experimental measurements (decibel, degrees) of the loop gain to fCv-A2L ), while Gv2 (s) achieves fC2 = 12 kHz at 30 V
Ta (j). (similar to fCa at 30 V) for its corresponding loop gain
Tv2 (s) (20). The design of Gv1 (s) and Gv2 (s) for the loop
shaping of Tv1 (s) and Tv2 (s) has been carried out following
1 1
G2 (s) = the compensation procedure of conventional VMC explained
VOCref (s) 1 + sp3 in Appendix B
1+ s    
=  2400s  . (15) 2000 1 + 1800s
1 + 2400
s
8 1 + 27 000 Gv1 (s) =     (17)
s 1 + 48 s000 1 + 160s000
Fig. 8 shows the experimental measurements of the loop gain    
18 000 1 + 9000s
1 + 2400
s
Ta (j) (decibel, degrees) with nominal and extreme values of Gv2 (s) =     (18)
s 1 + 48 s000 1 + 160s000
the input voltage. A +180 additional phase shift appears in
the phase plots of the loop gain due to the inverting operational Tv1 (s) = Gv1 (s) VOC(s) (19)
amplifiers used to build up the loop, so that the phase margin
can be directly read from those plots, being always higher Tv2 (s) = Gv2 (s) VOC(s). (20)
than 50 .
Ta (s) has been designed with fCa- max 12 kHz = 2.4 Figs. 10 and 11 show the experimental Bode plots of
fCv-A2L , PMmin = 50 , GM > 15 dB in the stability worst Tv1 (s) and of Tv-A2L (s) for different line and load condi-
case (Vi = Vi- max = 30 V). At the desired fCv-A2L = tions. In CCM (Fig. 10), the crossover frequency of the con-
5 kHz, the lowest gain of Ta (j) is in that case: ventional loop ranges from fC1 3.2 kHz to fC1 6 kHz,
|Ta (j) at 15 V|5 kHz 6 dB, which represents the worst case while A2LVMC presents no significant variation of fCv-A2L
of robustness condition fulfilment. It is worth pointing out that 5 kHz, maintaining a proper stability in all cases. In DCM
the maximum switching frequency noise at the control voltage (Fig. 11), the crossover frequency with VMC decreases to about
248
Fig. 9. Experimental measurements of the actual and the modified power stage. (a) VOC(s) (VMC). (b) VOU(s) (A2LVMC).
fC1 100200 Hz, while it remains in the range fCv-A2L
23 kHz with A2LVMC, showing the lower sensitivity to line
and load changes of A2LVMC compared to VMC.
In order to study the sensitivity of both VMC and of
A2LVMC not only with respect to the input voltage and to the
load variations, but also taking into account the tolerances of the
passive components of the power stage (L, C, and Rc ), a Monte
Carlo analysis has been performed by means of PSPICE. The
following tolerances have been considered:
L = 100 H 20% (80 H < L < 120 H)
C = 940 F 20% (752 F < C < 1128 F)
Rc = 35 m 50% (17 m < Rc < 53 m)
R = 15 (CCM)
Vi = 1530 V.
The Monte Carlo analysis has been carried out with a uni-
form distribution of the tolerances and 20 simulation runs.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 1, FEBRUARY 2006
The results appear in Fig. 12, in which the loop gain [module
(decibel) and phase (degrees)] with both VMC and Tv1 (s), and
A2LVMC and Tv-A2L (s), has been represented. The crossover
frequency with conventional VMC ranges from 2.6 to 9.2 kHz,
while A2LVMC decreases drastically the dispersion of the
crossover frequency, which, in this case, ranges from 4.2 to
5.4 kHz. A satisfactory stability is guaranteed under the con-
sidered tolerances with both VMC and A2LVMC. Note the low
dispersion of the curves at low frequencies with A2LVMC, be-
cause the adaptive loop gain is high in that range of frequencies,
and the degree of robustness condition fulfillment increases.
Similar results have been obtained in DCM.
Fig. 13 shows the gain Bode plots of the measured closed-
loop output impedance with conventional VMC and with the
proposed A2LVMC. Zocl1 (s) and Zocl2 (s) denote the closed-
loop output impedance of conventional VMC with slow
(fC1 = 5 kHz) and fast (fC2 = 12 kHz) controllers, respec-
tively. Zocl-A2L (s) denotes the closed-loop output impedance
of A2LVMC. It can be noticed the significant improvement
of the output impedance (27 dB at 100 Hz, 12 dB at 1 kHz)
FIGUERES et al.: ADAPTIVE TWO-LOOP VOLTAGE-MODE CONTROL OF DCDC SWITCHING CONVERTERS 249

Fig. 10. Experimental measurements of the loop gain (CCM, R = 1 ). (a) Tv1 (j) (VMC). (b) Tv-A2L (j) (A2LVMC).

achieved by A2LVMC with respect to conventional VMC with The shaping of the voltage loop is then simplified, because the
fast controller in the range of frequencies where the robust- power stage to be compensated is first order.
ness condition is fulfilled. Similar conclusions apply for the The proposed control scheme must fulfil certain robustness
audiosusceptibility. conditions and noise limitations, which have been highlighted
Fig. 14 shows the large signal output voltage response to in this paper.
load steps from 2 to 4 A (CCM) with the conventional and
with the proposed loop. The fastest response is obtained with A PPENDIX A
A2LVMC, even if the conventional loop is designed with a very D ERIVATION OF THE T RANSFER F UNCTIONS OF
high crossover frequency. VMC IN T ABLE I
From Fig. 2, by making vi = io = 0, the expression (21) of
IV. C ONCLUSION the output voltage results, where H(s) is the transfer function of
A new VMC scheme of dcdc converters has been presented the output LC filter, which can be simplified taking into account
in this paper. It has been shown that the proposed two-loop that Rc  R
scheme preserves the loop bandwidth and stability margins over
a large variation of the input voltage and the load, increasing the
vo = d Vi H(s) (21a)
converter disturbance rejection properties (closed-loop output
impedance and audiosusceptibility) with respect to the conven- 1 + s Rc C
H(s)  
tional single loop. LC R+R
R
c
s2+ L +R C s+1
R c
Moreover, A2LVMC achieves that the equivalent power
1 + s Rc C
stage seen by the voltage regulator of the outer loop becomes L  . (21b)
a first-order system in CCM, like current-mode controls do. LC s2 + R + Rc C s + 1
250 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 1, FEBRUARY 2006

Fig. 11. Experimental measurements of the loop gain (DCM, R = 30 ). (a) Tv1 (j) (VMC). (b) Tv-A2L (j) (A2LVMC).

The transfer function VOD(s) in Table I can be derived from into account that Rc  R. The expression (24) of Zo (s) results
(21) resulting in (22). The expression of VOC(s) shown in directly from (23)
Table I is derived directly from (22), taking into account that
d = Fm vc , and, thus, VOC(s) = Fm VOD(s)    
1
vo = io L s// Rc + //R
C s
 1 + s Rc C
= io L s L 
vo (s)  LC R+Rc
s2 + R + Rc C + 1
VOD(s)  R

d(s) = io L s H(s)
i =io =0
v

= Vi H(s) 1 + s Rc C
io L s L  (23)
1 + s Rc C LC s2 + R + Rc C + 1
= Vi L  
LC R+Rc
s + R
2 + Rc C s + 1 vo (s) 
Zo (s)
io (s) 
R
1 + s Rc C v
i =
vc =d=0
Vi L  . (22) = L s H(s)
LC s2 + R + Rc C s + 1
1 + s Rc C
=L s L 
LC R+R
R
c
+ R + Rc C s + 1
s2
1 + s Rc C
From Fig. 2, by making vi = vc = d = 0, the expression (23) L s L  . (24)
of the output voltage results, which can be simplified taking LC s2 + R + Rc C s + 1
FIGUERES et al.: ADAPTIVE TWO-LOOP VOLTAGE-MODE CONTROL OF DCDC SWITCHING CONVERTERS 251

Fig. 13. Experimental closed-loop output impedance (gain, decibel) with both
VMC and A2LVMC (Vi = 25 V; R = 2 ).

Fig. 12. Results of the Monte Carlo analysis (CCM). (a) VMC loop gain,
Tv1 (j). (b) A2LVMC loop gain, Tv-A2L (j).

From Fig. 2, by making io = vc = d = 0, the expression (25)

of the output voltage results, which can be simplified taking
into account that Rc  R. The expression (26) of A(s) results
directly from (25)

vo = vi D H(s)
1 + s Rc C
= vi D L 
LC R+R
R
c
s2 + R + Rc C + 1
1 + s Rc C Fig. 14. Response of the output voltage to load steps from 2 to 4 A
vi D L  (25) (Vi = 25 V). (a) VMC with slow controller. (b) VMC with fast controller.
LC s + R
2 + Rc C + 1
 (c) A2LVMC.
vo (s) 
A(s)
vi (s) io =
vc =d=0 sated by means a voltage regulator Gv (s) with two zeroes, two
1+sRc C poles, and an integrator, as shown in Table I. The following
= D H(s) = D L 
LC R+R R
c
s + R
2 + Rc C s + 1 design procedure is proposed.
1 + s Rc C
D L  . (26) 1) Choose the crossover angular frequency C of Tv (s)
LC s + R
2 + Rc C s + 1 between S /5 and S /10. The compensation is made
easy if C is well higher than
the resonance frequency of
the output LC filter, n = 1/ LC, i.e., C > 10 n .
A PPENDIX B
2) Choose the first pole pv1 of Gv (s) to cancel the ESR
C OMPENSATION P ROCEDURE IN C ONVENTIONAL VMC
zero of VOC(s), i.e., pv1 = 1/(Rc C).
Fig. 3(b) shows the asymptotic Bode plot (gain, decibel) of 3) Choose the second pole pv2 to filter the switching noise
the loop gain Tv (s) = Gv (s) VOC(s) properly compen- in the loop pv2 S /2.
252 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 1, FEBRUARY 2006
4) Choose the first zero zv1 below n in order to provide
phase lead near the crossover frequency.
5) Adjust the integrator gain iv and the second zero zv2
in order to obtain a minimum phase margin of 50 at the
desired crossover frequency C .
6) Check the noise in the control signals and the stability of
the loop with variations of Vi and R, redesigning Gv (s)
if necessary.
A PPENDIX C
D ERIVATION OF THE D ISTURBANCE R EJECTION
T RANSFER F UNCTIONS IN A2LVMC
From Fig. 4(c), by making vi = 0, the expression (27) of
the output voltage results. Taking into account that the control
voltage in Fig. 4(c) can be calculated following (28), and
substituting (28) into (27), the expression (29) of vo (s) as
a function of io (s) results. From (29), the expression (30)
of the closed-loop output impedance results. The closed-loop
audiosusceptibility, Acl (s), shown in (10), is derived in an
analogous way from Fig. 4(c), by making io = 0 instead of
making vi = 0
vo (s)
vc (s)Fm VOD(s)
= io (s)Zo (s)+
= io (s)Zo (s)+
vc (s)VOC(s) (27)
vc (s)
= Gv-A2L (s)G1 (s)
vo (s)G1 (s)G2 (s)
vo (s)
vo (s)( Gv-A2L (s)G1 (s)+G1 (s)G2 (s))
= (28)
vo (s)[1+( Gv-A2L (s)G1 (s)+G1 (s)G2 (s))VOC(s)]
= io (s)Zo (s) (29)
Zocl (s)

vo (s) 
io (s) 
v
i =0
Zo (s)
=
1+( Gv-A2L (s)G1 (s)+G1 (s)G2 (s))VOC(s) converter modeling and control, robust control of switching converters, soft-
Zo (s)
= . (30)
1+Ta (s)+ Gv-A2L (s)G1 (s)VOC(s)
R EFERENCES
[1] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics. Con-
verters, Applications and Design. New York: Wiley, 1995.
[2] W. Tang, R. Ridley, and F. C. Lee, Small signal modelling of average
current-mode control, in IEEE Applied Power Electronics Conf. (APEC),
Boston, MA, 1992, pp. 747755.
[3] R. Ridley, A new, continuous time model for current mode control, IEEE
Trans. Power Electron., vol. 6, no. 2, pp. 271280, Apr. 1991.
[4] R. Mammano, Switching power supply topology. Voltage mode vs. current
mode, in Unitrode Applications Handbook, DN-62. Merrimack, NH:
Unitrode Corp., Apr. 1997.
[5] G. Garcer, E. Figueres, and A. Mochol, Novel three-controller average
current mode control of dcdc PWM converters with improved robustness
and dynamic response, IEEE Trans. Power Electron., vol. 15, no. 3,
pp. 516528, May 2000.
[6] E. Figueres, G. Garcer, M. Pascual, and D. Cerver, Two controller robust
voltage mode control of dcdc switching converters, in Proc. IEEE Int.
Symp. Industrial Electronics (ISIE), LAquila, Italy, 2002, pp. 10251030.
[7] R. D. Middlebrook and S. Ck, A general unified approach to mod-
elling switching converter power stages, in Proc. IEEE Power Electronics
Specialists Conf. (PESC) Conf. Rec., Cleveland, OH, 1976, pp. 1834.
[8] V. Vorperian, Simplified analysis of PWM converters using the model
of the PWM switch: Parts I and II, IEEE Trans. Aerosp. Electron. Syst.,
vol. 26, no. 3, pp. 490505, May 1990.
Emilio Figueres (S98A00) received the M.Sc.
degree from the Ecole National Superieure
dElectrotechnique, dElectronique, dInformatique
et dHydraulique de Toulouse (ENSEEIHT),
Toulouse, France, and the Dr. Ingeniero Industrial
(Ph.D.) degree from the Polytechnic University
of Valencia, Valencia, Spain, in 1995 and 2001,
respectively.
He has collaborated with several industrial
companies in the following fields: design of power
supplies for particle accelerator superconducting
magnets (GH Group and JEMA); induction heating (GH Group); motor drives
and active filters for power factor correction (Power Electronics S.L.); and
power supplies for audio systems (DAS Audio and VMB). By the end of 1996,
he joined the Electronics Engineering Department of the UPV, where he is
currently an Associate Professor. Since 2004, he has been the Deputy Director
for R&D activities in the Electronics Department of the UPV. His main interest
fields are modeling and control of power converters, robust control, and power
factor correction techniques.
Dr. Figueres is a member of the IEEE Power Electronics Society and of the
IEEE Industrial Electronics Society.
Gabriel Garcer (S97A98M04) was born in
Valencia, Spain, in 1968. He received the Ingeniero
de Telecomunicacin (M.Sc.) and Dr. Ingeniero de
Telecomunicacin (Ph.D.) degrees from the Poly-
technic University of Valencia, Valencia, Spain, in
1993 and 1998, respectively.
From 1993 to 1995, he was with the R&D De-
partment of the company GH ELIN International,
involved in the design of high-current switch-mode
power supplies for particle accelerator superconduct-
ing magnets at CERN. By the end of 1995, he
joined the Electronics Engineering Department of the Polytechnic University
of Valencia, where he is currently an Associate Professor and the Head of the
Industrial Electronic Systems Group (GSEI). His main research fields are power
switching energy conversion, and power factor correction circuits.
Dr. Garcer is a member of the Spanish Association of Telecommunica-
tions Engineers. Since 2004, he has been an Associate Editor of the IEEE
TRANSACTIONS ON INDUSTRIAL ELECTRONICS.
Jos M. Benavent was born in Valencia, Spain, in
1968. He received the Ingeniero Tcnico Industrial
(B.S.) degree from the Polytechnic University of
Valencia, Valencia, Spain, in 1991, and the Elec-
tronic Engineer (M.Sc.) degree from the University
of Valencia , Valencia, Spain, in 2001. He is currently
working toward the Ph.D. degree at the Polytechnic
University of Valencia.
From 1993 to 1996, he was with the R&D De-
partment of the company GH ELIN International,
involved in the design of high-current switch-mode
power supplies. By the end of 1996, he joined the Electronics Engineering
Department of the Polytechnic University of Valencia, where he is currently
an Assistant Professor. His main research fields are power converter modeling
and control, robust control of dcdc converters, and power factor correction
circuits.
FIGUERES et al.: ADAPTIVE TWO-LOOP VOLTAGE-MODE CONTROL OF DCDC SWITCHING CONVERTERS
Marcos Pascual (S01A03M04) was born in
Alcoy, Spain, in 1972. He received the B.S. and
M.Sc. degrees from the Polytechnic University of
Valencia, Valencia, Spain, in 1994 and 1998, re-
spectively. He is currently working toward the Ph.D.
degree at the Polytechnic University of Valencia.
In 1998, he joined the Electronics Engineering
Department of the Polytechnic University of Valen-
cia, where he is currently an Assistant Professor. His
research interests include modeling and control of
dcdc and resonant power converters.
253
Juan A. Martnez was born in Alcoy, Spain, in
1957. He received the B.S. and M.Sc. degrees from
the Polytechnic University of Valencia, Valencia,
Spain, in 1977 and 1985, respectively. He is currently
working toward the Ph.D. degree at the Polytechnic
University of Valencia.
In 1986, he joined the Electronics Engineering De-
partment of the Polytechnic University of Valencia,
where he is currently an Assistant Professor. His
research interests include modeling and control of
dcdc converters.