A 6 Bit Multiplier for a DSP SOC

Senior Design Project

Advisor: Dr. David Parent
Group Members: Steve Wong
Jeremiah Martin

1
 Table of Contents

Section Page

Backgournd.2

Design Flow3

DSP System Theory4

6 Bit Multiplier8

6 Bit Full Adder..10

6 Bit Delay..12

Design Implementation15

System in Padframe.32

Chip Description..33

Testing Procedures...34

Improvements...42

Appendix...44

2
 Background

Multipliers are one of the most important elements in digital filters such as Finite Impulse
Response (FIR) and Infinite Impulse Response (IIR) Filters. These filters are used in a
wide variety of Digital Signal Processing (DSP) applications such as A/D converters,
signal modulators, audio signal processing, multimedia, and process control just to name
a few.

The significance of Multipliers in DSP applications is one of the motivations in designing

a 6-bit multiplier for a DSP System On a Chip (SOC). The multiplier is designed within
a simple feedback system that consists of an adder, and a delay that has a 6-bit coefficient
multiplied to the feedback. The system and its individual components will be discussed
in detail in a later chapter.

Incorporating the multiplier in a simple feedback system gives a setup for ease of testing
multiplier design functionality and can be applied as a filter element for other DSP
systems. With a defined input and coefficient applied to the system, it can create output
waveforms that can be easily analyzed. Varying the coefficient with a given input signal,
the multiplier can produce different output signals. In addition, the feedback system can
be coupled to other 6-bit systems (A/D converter and PLL)that can act as an IIR filter.

Finally, designing a 6-bit multiplier can serve as a basis for IC design students to work
with as a tool in their understanding of digital design. It is also a stepping-stone for
students in designing other CMOS projects using the AMI06 technology and to
encourage them to make improvements in the design.

3
Design Flow

In designing the 6-bit Multiplier for a DSP on SOC, it was important to follow a design
flow to successfully complete the project. The very first step needed was to learn system
theory and to understand each component in the system. With a deeper knowledge of the
theory behind the workings of a multiplier and the system that is required to test its
functionality, the design and testing just fell into place.

There are four main blocks in the design flow - the Initial Design, Design and Layout in
Cadence, Testing, and Documentation. Within the design and layout in Cadence, another
design flow was followed. This is the protocol that was followed to successfully send the
finished layout to MOSIS for fabrication.

Schematic
Capture

Initial Design

Testbench

Design and
Layout in
CADENCE Layout

Testing Circuit
DRC LVS
Extraction

Post
Verificatio
Extraction
n
Simulation
Documentaion

Padframe

Figure 1. Project Design Flow

4
DSP System Design Theory

The system design configuration used for testing the multiplier functionality is also a
filter system with a feedback from the output. As shown in Figure 2, the system consists
of an Adder, a Delay (Z-1), and a Multiplier. The feedback system has a 6-bit input X(n),
a 6-bit coefficient that is less than 1 (a) to the multiplier, and a 7-bit output Y(n)
including the Carry-Out (Co) from the multiplier.

X(n) + Y(n)

x Z-1

a
X(n) - input
Y(n) - output
a - coefficient
Z-1 - delay

Figure 2. DSP system block diagram

System Theory

The system generates an output or a difference equation of:

Y (n) = az 1Y (n) + X (n) Difference Equation (1)

By algebraic manipulation, the difference equation (1) can be transformed to get the
transfer function

1
H ( z) = Transfer Function (2)
1 az 1

The transfer function indicates that the system is a Low-pass filter

5
To further understand how the multiplier should work with the system and why the
coefficient has to have a value less than 1,an impulse response needs to be introduced to
the input of the system. This discussion will be referred to in later chapter on the testing
of the multiplier.

The difference function (1) is a function of time, where n is time.

Time (n) Input Output

0 d(0) d(0)
1 0 a1d(0)
2 0 a2d(0)
3 0 a3d(0)
n 0 and(0) 0

Table 1. Impulse Response, Input and Output relationship with coefficient greater than 1

As shown in Table 1, the impulse response should yield an output of zero over a discrete
time interval because the multiplier coefficient will be less than one. If the multiplier a
were to be a value greater than one, for the general case, an d(0), the output will become
unstable and unbounded over time. It will approach infinity and will do nothing to test
the multiplier design.

Since we are applying an impulse in the input, for any value less than one in the
coefficient, the output should approach to zero. By examining the feedback system
below (Figure 2) of coefficient a = 0.5 [Refer to the Appendix for binary equivalent of
the coefficient (B5-B0)], we can see what is happening in each block.

In the initial stage (Figure 3a), input is zero, then every block will register zero. As the
input hits the impulse (Figure 3b), the adder adds the value of the input (111111) to the
previous product of the multiplier (000000), which it ouputs 111111. The output is then
carried to the delay and is multiplied by the coefficient (100000) outputting a product of
011111.

When the input hits the end of the impulse (Figure 3c), which is zero, the adder adds the
value of the input and the previous product of the multiplier, [(000000) + (011111)] =
011111. The added value is then carried to the output and the delay (Figure 3d). The
delay (011111) and the coefficient (100000) are multiplied again resulting in a product of
001111).

6
000000 000000 000000 111111 111111 111111
X(n) + Y(n) X(n) + Y(n)

000000 011111
111111
x Z-1 x Z-1

a = 100000 a = 100000

Figure 3a. Initial stage of system Figure 3b. Second Iteration

000000 011111 011111 000000 001111 001111

X(n) + Y(n) X(n) + Y(n)

001111 000111

011111 001111
x Z-1 x Z-1

a = 100000 a = 100000

Figure 3c. Third Iteration Figure 3d. Fourth Iteration

Time Input Output (S5S4S3S2S1S0) Output (S5S4S3S2S1S0) Output (S5S4S3S2S1S0)

(n) (A5A4A3A2A1A0) Coefficient = 0.5 Coefficient = 0.25 Coefficient = 0.125
0 000000 000000 000000 000000
1 111111 111111 111111 111111
2 000000 011111 001111 000111
3 000000 001111 001111 000111
4 000000 000111 000011 000111
5 000000 000011 000011 000000
6 000000 000001 000000 000000
7 000000 000000 000000 000000

Table 2. Impulse Response, in a 6 bit input with a 0.5 coefficient

7
From this moment on, the input will be zero, which contributes nothing to the system. So
for every time the signal goes through the multiplier, with a coefficient of 0.5, it shifts
one bit to the right as seen in Table 2.

From the analysis of the system, having an impulse signal applied to the input of the
system produces an output waveform that can be easily analyzed to see if the multiplier
does indeed work. This is also true by using a different value for the coefficient, as seen
in Table 2. Notice that having a coefficient of 0.25, 2 bits are shifted, and a coefficient of
0.125 shifts 3 bits.

The analysis done above did not put the overflow in consideration. In the initial
multiplication of the impulse signal, a carry-out will occur since all of the input bits are
all 1. The carry-out will cause some glitches, which will be pointed out during the testing
section.

8
6-bit Multiplier

Multiplication is just a series of repeated addition that are shifted. Consider the following
binary multiplication of a two 6-bit integer value.

N
111001 (57) Multiplicand
X
110011 (51) Multiplier
111001
111001
000000
N
000000
111001
111001
101101011011 (2907)

For every bit, starting with the least significant bit (LSB) and ending with the most
significant bit (MSB), the multiplier is multiplied with the multiplicand. Every product is
aligned and shifted to the left according to the position of the multiplier bit. The six
products are then added together to get the final product.

It is evident that when the multiplier bit is 1, the corresponding product is the shifted
copy of the multiplicand. And when the multiplier bit is 0, then the product is 0. Thus,
every multiplication bit is just an AND operation.

For an N-bit wide multiplicand and Multiplier (an N x N multiplication), the product will
have a 2N-bit wide product. The result of our desired 6 X 6 multiplication has a 12-bit
product.

9
A simple 6-Bit Unsigned Binary Multiplication

By applying the same concept of multiplication to a 6-bit input A5A4A3A2A1A0

(multiplicand) with a 6-bit input coefficient B5B4B3B2B1B0 (multiplier),

A5 A4 A3 A2 A1 A0
x B5 B4 B3 B2 B1 B0
A5B0 A4B0 A3B0 A2B0 A1B0 A0B0
A5B1 A4B1 A3B1 A2B1 A1B1 A0B1
A5B2 A4B2 A3B2 A2B2 A1B2 A0B2
A5B3 A4B3 A3B3 A2B3 A1B3 A0B3
A5B4 A4B4 A3B4 A2B4 A1B4 A0B4
A5B5 A4B5 A3B5 A2B5 A1B5 A0B5
S5 S4 S3 S2 S1 S0 . [ DO NOT CARE !!!!! ]

a 6-Bit Multiplier will return 12-bits. Because the multiplier coefficient is less than one,
only 6-bits are needed, and the remaining 6-bits are ignored. This is done in order to
have 6-bit feedback adding with the 6-bit input. Because of the feedback, only 6-bits are
allowed or else the system will become unstable and continually output larger bit sizes.
So outputs S5S4S3S2S1S0 will be hardwired to the 6-bit adder.

Now that the basis of multiplication of an N x N bit binary number is set, the design of
the 6-bit multiplier can now be started. In order to design a multiplier, a combinational
circuit has to be constructed for the necessary operation of each product and the final
addition.

10
6-Bit Full Adder

The full adder is one of the most important components used not only in the design of the
6-bit Full Adder in the DSP system, but also in the multiplier design. The full adder
design discussed is implemented for both the 6-bit Adder and the 6-bit Multiplier.

Full Adder Design

Let us start by looking at the truth table of the Full Adder shown in Table 3. The three
inputs A, B and Cin generate the Sum (S) and Carry-out (Co). By creating the Karnough
map from the Full Adder truth table we get the expressions for Co and S.

INPUT1 (A) INPUT2 (B) CARRY IN SUM OUT (S) CARRY OUT
(Cin) (Co)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Table 3. Truth Table for Full Adder

AB AB
Cin 00 01 11 10 Cin 00 01 11 10

0 0 0 1 0 0 0 1 0 1

1 0 1 1 1 1 1 0 1 0

Co = AB + BCin + ACin S=A B C

Figure 4. K-maps for Full Adder

11
The Co expression is easily obtained through the K-map.

Co = AB + BCin + ACin Carry-out Expression (3)

The expression for S may look simple, but in terms of constructing with CMOS
transistors, it may prove to be difficult. Instead, by looking at the truth table, the output S
is simply the inverse of Co except for the cases where ABCin = 000 and ABCin = 111.
The new output expression becomes

S = ABCin + Co(A + B + Cin) Sum Out Equation (4)

Though this method may slow down the adder because S has to wait for Co to compute, it
is significantly easier to implement. Both expressions are now composed of AND, OR
and INV gates.

A
B
Cin

Co S

Figure 5. Full Adder Schematic

To make a 6-bit Full Adder, 6 Full Adders are connected in series. The Full Adder
schematic is shown in later the later section.

12
6-Bit Delay

From the DSP system, the previous output, must be multiplied by a coefficient and then
added with the current input value in order to generate the new output value. To obtain
the previous output, the value must be held or delayed, so that it can be accessed at a later
given time.

The significance of the D-Flip Flop is its ability to hold and store values for an indefinite
amount of time. This hold time is governed by an input CLOCK signal. The length of
the hold time is one complete clock cycle. The shortest hold time is the time the DFF
needs in order to have a stable output. The DFF is triggered on the rising edge of the
clock, becoming active once with every clock cycle. The DFF must be equipped with a
reset function. The reset function is used to clear out any value held within the DFF,
setting the output to 0. Because the DFF can hold values, it acts as a delay in the DSP
system. Whenever the input D is HIGH, the output Q will follow the input.

Deciding not to reinvent the DFF, the DFF designed by Dr. Parent from his Spring 2003
Electrical Engineering 166, Design of CMOS Digital Integrated Circuits shown in Figure
5a, was used for the basis of the DFF in the project.

NPRE

D
Q

NCLK CLK

NQ
ND

NCLR

Figure 6a. Dr. Parents DFF Design

VDD

D
Q

NCLK CLK

NQ
ND

VDD

Figure 6b. Dr. Parents DFF (Modified)

13
The DFF was slightly modified as illustrated in Figure 6b, taking a well thought out
design into a more simplistic approach. Unfortunately, these modifications created flaws
to the design of the DFF. The reset function of the DFF was no longer active.

Each DFF held 1-bit of the 6-bit output. As shown in Figure 7, six DFF were used to
hold the 6-bit output.

Q0 Q1 Q2 Q3 Q4 Q5

D0 D1 D2 D3 D4 D5

DFF DFF DFF DFF DFF DFF

CLK

Figure 7. 6-bit DFF Schematic

The clock skew has to be considered in the design of the DFF. If there is clock skewing
occurring, the DFF will be triggering at different clock edge, which results in timing
problem for each bit. This will cause a glitch or an operation that will cause the
multiplier to output a wrong product from the feedback. The solution to this is equal
paths and spacing of the clock connection and minimize corners to get equal time in
receiving the clock signal for each DFF.

14
Design Specification

Process AMI06 (.5 technology)

Frequency = 200 MHz
VDD 5V
Inputs 1 6 Bit (A5A4A3A2A1A0)
1 6 Bit Coefficient (B5B4B3B2B1B0)
1 CLK
Outputs 1 6 Bit (S5S4S3S2S1S0)
1 Carry-out (Co)

The process that was used is the AMI06 .5micron technology. This is the technology
required for MOSIS to fabricate the chip. The frequency requirement was 200MHz.,
which was the required frequency in EE166 class. But when the system layout was
padframed, because of the super buffers in the pins, the system was limited to perform at
less than 50 MHz. The VDD was set at 5 V.

There are two sets of 6-bit inputs. One set is the 6-bit input signal (A5A4A3A2A1A0),
which is the impulse signal during testbenches in Cadence and actual testing of the chip.
The other set is the 6-bit coefficient (B5B4B3B2B1B0) that is less than one. And of course
the clock (CLK).

The output consists of a 6-bit (S5S4S3S2S1S0) and a Carry-out (Co) to indicate if there is
an overflow in the multiplication. The Co helps in determining and is a good indicator if
the multiplier is functioning properly when testing.

15
Design Implementation

Since the most important aim in the project was to design a Multiplier that is functional
and that can be tested easily, the width and length consideration was not principal. The
minimum width and length were used in designing the Multiplier and the other
components in the DSP system.

In this section, each components schematic and layout are shown. The components are
then put together to form the DSP system. The simulation of different coefficient values
is then pointed out and discussed.

16
6-Bit Full Adder

Full Adder Schematic

The Full adder schematic in Figure 8 was modeled from Figure 5 in the design theory
section. It consists of 28 transistors having 3m for all the widths and 600nm for the
lengths. Inputs are A, B, and C as the Carry-in. Outputs are the Carry_out and the Sum.

The full adder is a fundamental part of the design of the whole system. Not only this
design is used for the 6-bit full adder, but it is also a major component of the 6-bit
multiplier.

Figure 8. Full Adder Schematic

17
6-Bit Full Adder

The 6-bit Full Adder was designed by connecting six full adders together, as shown in
Figure 9. The first full adder to the most left is where the least significant bit of both the
input signal A0 and the coefficient B0 are added with the carry-in grounded. The
following bits are then added with individual full adders.

The full adders are cascaded by connecting the carry-out of one full adder to the carry-in
of another full adder. For every bit of the output signal, a full adder is assigned,
corresponding to the order of the inputs. The outputs most significant bit (S5) is the last
full adder on the right and the least significant bit (S0) is the last full adder on the left.

Figure 9. 6-Bit Full Adder Schematic

18
6-Bit Full Adder Layout

The layout of the 6-Bit Full Adder was approached exactly the way the schematic design
was approached. It was efficient to layout one full adder and copy it five times and
cascade it with the proper routing of the connections. The most significant bit for the
inputs and output is on the far right and the least significant bits are on the far left.

The layout used the conventional way, as taught in EE166, of setting the Vdd on the top
and Gnd on the bottom of the layout. Three metal layers were used to route the
connections together, using metal3 as the input and output connection from the full
adders.

Figure 10. 6-bit Full Adder Extracted Layout

19
D-Flip Flop (Delay)

DFF Schematic

As mentioned in the design theory section, the design of the DFF was based on Dr.
Parents design from EE166 Digital CMOS design class of Spring 2003. It was modified
where the reset was taken out. This caused some minor problem in the project, which
will be discussed in the improvement section.

Figure 11 shows the DFF schematic. The schematic has a simple master and slave
section that consists of four nand2s and four nand3s.

Figure 11. DFF Schematic

The nand2schematic is shown in Figure 12a and the nand3 is shown in Figure 12b.
Making it easy for the design, the widths for the nand2 and the nand3 are also 3m and
the lengths are also 600nm similar to the adder.

20
Figure 12a. Nand2 Schematic of DFF

Figure 12b. Nand3 Schematic of DFF

21
6-Bit DFF Schematic

To make a 6-bit Delay, 6 DFF are connected together with a common CLK as seen in
Figure 13. The inputs least significant bit is D0 and the most significant bit is D5. The
outputs most significant bit is Q5 and the least significant bit is Q0.

The input signal D5 D0 are from the output of the 6-bit adder and the output Q5 Q0
are going to the multiplier, which are multiplied to the coefficient.

Figure 13. 6-Bit Delay Schematic

22
6-Bit DFF Layout

The whole layout was started with designing one DFF and copying that design five times
to create the 6-bit DFF in Figure 14. It was planned ahead of time to connect the 6 DFF
in a row to match up with the layout of the adder and the multiplier. The layout uses 3
metals with metal 3 as the input and output metal this is the same metal used in the
input and output of the adder and the multiplier.

In the layout, clock skew must be kept to a minimum. Because the design was to be
compact, clock is laid out as a bus, where each DFF was spaced out equally and the clock
signal branched out to each DFF clock input. To eliminate clock skewing, the metal
paths to the input clock of each DFF where the same exact path, take the same exact
corner, all from one clock source.

Figure 14. 6-Bit Delay Extracted Layout

23
6-Bit Multiplier

6-Bit Multiplier Schematic

As mentioned in the Design Theory section, every multiplication bit will be an AND
operation, which is referred to as a partial product. The partial products are then summed
by using Adders in each column. Any carries must be propagated from right to left
across the column.

In keeping the design simple for a multiplier, a ripple carry array adder system is used.
The sum and carry-out of each full adder is carried on to the next fuller adder. As a result
30 Full Adders and 36 AND gates were implemented (See Figure 15 for the Multiplier
Schematic)

The full adder used is the same full adder used for the 6-bit full adder. And the and2 gate
used is the same and2 gate used for the DFF.

It was explained in the design theory section of the multiplier that a 6-bit by 6-bit
multiplication will result in a 12-bit product. Since our coefficient is less than 1, we only
care about the sic most significant bits. In the schematic, the right most bits
(S5S4S3S2S1S0) are the only ones used in the system.

24
Full Adder

And2

Output Bits used

Figure 15. 6-Bit Multiplier Schematic

25
6-Bit Multiplier Layout

The layout of the 6-bit multiplier was setup, as shown in Figure 16, considering the other
components that will be connected. The coefficients (B5-B0) are on the right side. The
inputs (from the Delay) and outputs to the adders are on the bottom.

Figure 16. Extracted Layout of the

26
DSP System

With the schematic and layout done for each component, the system is ready to be put
together. The system schematic is shown in Figure 17. The schematic creates pins for
each inputs and outputs of the system, which was put together to create a symbol for the
system for simulation.

Figure 17. System Schematic Pin assignment

27
 System Layout

The layout of the system is very compact. Metal3 connects all of the components
together with the multiplier on the top, in the middle is the delay, and the bottom is the
adder as indicated in Figure 18.

Multiplier

Delay

Adder

Figure 18. Extracted System Layout

28
DSP System Testbench

With the layout in place, testing the system is imperative to determine if the design is
Padframe worthy. To test the system, a symbol is created and voltages and loads are
connected to the proper inputs and outputs.

Testing at 0.5 Coefficient

A 50 fF of load is attached to each output. A voltage is applied to four of the least

significant bit to avoid carry out in the multiplier. Coefficient is set at 0.5 making the
most significant bit (B5) to be at 1 and the rest at 0 (See Appendix for binary value of
coefficient).

Figure 19. Testbench at 0.5 Coefficient

29
Waveform Simulation At 0.5 Coefficient

The impulse signal applied to the input (A3-A0) caused output (S3-S0) to go high on the
next positive clock edge. As soon as the signal goes through the delay, the multiplier
multiplies the 001111 signal that the delay sent to the coefficient (100000). As discussed
in the Design System Theory section, a 0.5 coefficient will shift every bit once, for every
clock cycle, until the final feedback all goes to zero. This is illustrated in Figure 18
below.

Notice that the carry-out (Co) stays low because there is no overflow due to the 2 MSB of
the input to be zero.

Figure 20. Simulated Waveform at 0.5 coefficient with an impulse signal for the input

30
Testing at 0.25 Coefficient

To test the system with a coefficient of 0.25, pin B4 should be high and the rest is set to
low (Refer to Appendix for the coefficient value). The rest of the configuration is similar
to the previous testbench illustrated in Figure 17.

With a coefficient of 0.25, the 2 most significant bits are shifted or turns zero every clock
cycle. S5 and S4 are always zero, because the impulse signal is only applied to A3 A0.
Since there is no over-flow, the carry out (Co) is always zero.

Figure 21. Simulated Waveform at 0.25 coefficient with an impulse signal for the input

31
Testing at 0.125 Coefficient

To test the system with a coefficient of 0.125, pin B3 should be high and the rest is set to
low (Refer to Appendix For the coefficient value). The rest of the configuration is
similar to the previous testbench illustrated in Figure 17.

With a coefficient of 0.25, the 3 most significant bits are shifted or turns zero every clock
cycle. Again S5 and S4 are always zero, due to the impulse signal applied applied to A3
A0.

Similarly from the previous simulations, no over-flow, and the carry out (Co) is always
zero.

Figure 22. Simulated Waveform at 0.25 coefficient with an impulse signal for the input

32
System In Padframe

The system itself is in the center of the padframe occupying only a fourth of the space.
As shown in Figure 23, inputs and output of the system are connected to the pin outs of
the padframe. Only 22 of the pins are used in the padframe.

Figure 23. System in Padframe

33
Chip Description

The Actual Chip Has 40 pins as seen in Figure 24.

Bit 1(MSB) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6(LSB)

Input A5 A4 A3 A2 A1 A0
Coefficient B5 B4 B3 B2 B1 B0
Output S5 S4 S3 S2 S1 S0

B5 1 40
VDD = 5VDC
B4 2 39 VDD CLK: clock set @ 50MHz
B3 3 38 GND: ground
B2 4 37 A0

B1 5 36 A1
INPUTS
B0 6 35 A2 Input Signal: A5-A0
7 34 A3 Coefficient (B5 B0): is less than 1
8 33 A4

9 32 A5
OUTPUT
10 31
Output Signal: S5-S0
11 30 S0 Co: Carry-out
12 29 S1

13 28 S2
Pin 7-19, 21, 23, 31, 38, and 40 are
14 27 S3
not connected (NC)
15 26 S4

16 25 S5
17 24 Co

18 23

19 22 GND

CLK 20 21

Figure 24. Pin Assignment

34
Testing Procedure

The testing uses the Agilent 1627G Logic Analyzer. It is strongly suggested to go
through the Training Guide (Training Kit for Agilent Technologies 1670G Series Logic
Analyzers) before proceeding to the actual testing.

To begin testing the Multiplier in the DSP system, it is important to properly setup the
connection of the chip. The easiest way to test is by setting the chip on a breadboard. By
using a breadboard, it can avoid damage to the chip and one can easily manage the many
connections of the chip to the logic analyzer.

The following procedure will direct you on how the setup should be and what to use to
successfully connect the chip to the logic analyzer.

Chip Setup

Materials needed are: (1) Breadboard with 5V-DC

(1) Dip-switch
(1) Digital Multi-Meter (DMM)
A roll of wire

1. Obtain a breadboard with a 5V-DC properly connected and distributed through

the board. Use a DMM to test for proper voltage and distribution.

2. Put the chip near the center of the breadboard to give space for connections.

3. Determine the pins of the chip by referring to Figure 24. of chip description.

4. Setup the dip-switch on the breadboard, and connect the coefficient input (B5-B0)
from the chip to the Dip-switch. The dip-switch will vary the coefficient easier
during testing.

5. Check and test the dip-switch by using a DMM.

6. Cut and strip wires long enough for inputs and outputs to use for connection to the
logic analyzer Pods. (It will be very useful if you use different color wires, or
label them to manage the different connections)

7. Connect the VDD of the chip to the 5VDC of the breadboard.

35
 8. Make sure to not connect the GND connection of the chip to the ground of the
breadboard. The GND connection of the chip will be connected to the ground of
the Input Pod of the logic analyzer (This will be shown in the Logic Analyzer
Setup).

Logic Analyzer Setup

This will setup the proper configuration of the Agilent 1627G Logic Analyzer for use in
testing the 6-bit Multiplier in a DSP system. The terms and navigation through the
system are not described in detail, and it is assumed that the person testing went through
the Training Guide.

The logic analyzer will use two Pods. Output Pod labeled Pod1, with 7 pins, which
generates the clock and the input signal to the chip. And the Input Pod, also labeled Pod 1
with 15 pins, which will read the output from the chip.

The input pod will be connected to the output pod to check if the configuration of the
Logic Analyzer is properly generating the proper input signal.

Configuring Output Pod (Pod 1)

1. Turn on Logic Analyzer

2. From Analyzer, choose Patt Gen
3. Choose Clock Source Internal
4. Choose Pod B1 for your input pod and clear out Pod B3.
5. Activate all pins by putting asterisks.
6. From Patt Gen Format, switch to Patt Gen Sequence
7. If Base is not in Binary change it to Binary.
8. Configure signal by changing the least significant bit to intervals of 0 and 1.

Configuring Input Pod (Pod 1)

1. From Patt Gen, choose Analyzer

2. From Format Machine 1, choose Configuration
3. In Machine 1, choose timing for Type:
4. From Configuration, change to Format Machine 1
5. Activate 0 15 pins by putting asterisks on Pod A1 make sure it is on TTL.

Checking the Logic Analyzer Setup

1. Connect Output Pod (Pod 1 7pins) to Input Pod (Pod 1-15pins) for testing.
2. From Format Machine 1, go to Waveform Machine 1.

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 3. In the left-hand side bar, click and select Sequential.
4. You need to turn on both simulation from Patt Gen and Analyzer
a. From Patt Gen/Patt Gen Sequence Run (Repetative).
b. From Analyzer/Waveform Machine 1 Run (Repetative).

5. The waveform of the clock should appear. If no clock waveform is generated, see
Trouble Shooting in Appendix.

Actual Testing

With the chip properly setup on the breadboard and the logic analyzer configured and
prepared, testing can now proceed. There are three important configurations to correctly
test the Multiplier functionality. First, the appropriate input signal from the logic
analyzer needs to be programmed correctly. As discussed in the earlier chapter, the input
signal should be an impulse function to test the functionality of the multiplier. Second,
we need to configure the waveform buses on the waveform screen. Finally, the
connection of the input pod and the output pod should be appropriately connected to the
chip.

Programming the Input Signal

1. From Analyzer, choose Patt Gen

2. From Patt Gen Format, switch to Patt Gen Sequence

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3. If Base is not in Binary change it to Binary.
4. Change the LSB of line 5 from 0 to 1. This will act as the clock signal.
5. Copy lines 3 and 4, and insert 9 copies of the copied lines after line 4.
6. In the fifth line, type in the binary signal 0011110. This will start the impulse signal
on the 4 LSB of the input signal with the two MSB at 00.
(note: the two MSB is set at 00 to avoid overflow.)
7. Now you have the impulse response and the clock are completely setup.

Configuring Waveform Machine

1. From Patt Gen, choose Analyzer

2. From Format Machine 1, choose Waveform Machine 1

3&4

3. Click on the Bus assignments on the left hand side and double click on it.
4. Insert Bus1 0-13. It should add all bus assignment form Bus 0 13.
5. It is very important to know which Bus is which when analyzing the generated
waveform. The suggested bus assignment in Table 5 will help in connecting the
input Pod to the designated input and outputs from the chip and will assist in the
reading of the waveform.

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 Bus # from Assignment Output Pod Pin # Input Pod Pin #
Analyzer
- GND Gnd -
Bus1 0 CLK 0 0
Bus1 1 S0 output - 1
Bus1 2 S1 output - 2
Bus1 3 S2 output - 3
Bus1 4 S3 output - 4
Bus1 5 S4 output - 5
Bus1 6 S5 output - 6
Bus1 7 A5 input 1 7
Bus1 8 A4 input 2 8
Bus1 9 A3 input 3 9
Bus1 10 A2 input 4 10
Bus1 11 A1 input 5 11
Bus1 12 A0 input 6 12
Bus1 13 Co output - 13

Table 5. Bus and Pin Assignments (Logic Analyzer to Chip)

Logic Analyzer to Chip Connection

1. Connect output Pod 1 of logic analyzer to the inputs of the chip (A5 A0) including
CLK and GRD (Refer to Table 5 and Figure 24).
2. Connect input Pod 1 of logic analyzer to the outputs of the chip (S5 S0) including
Co (Refer to Table 5 and Figure 24).
3. Set coefficient (a) to 0.5 by switching the dip-switch to its proper position. See
Table of coefficient values in Appendix.

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Testing with 0.5 Coefficient

1. Run from both Patt Gen and Analyzer to display input and output waveform.
a. From Patt Gen/Patt Gen Sequence Run (Repetitive).
b. From Analyzer/Waveform Machine 1 Run (Repetitive).

An impulse with a 0.25 coefficient applied to the DSP system should generate a
waveform similar to Figure 25.

2. Stop the simulation in both Patt Gen and Analyzer by clicking Stop.

CLK
S0
S1
S2
S3
S4
S5
Co
A5
A4
A3
A2
A1
A0

Figure 25. Testing - Impulse response with coefficient set to 0.5

40
Testing with 0.25 Coefficient

1. Set the coefficient to 0.25 by switching the dip-switch to its proper position. See
Table of coefficient values in Appendix.

2. Run from both Patt Gen and Analyzer to display input and output waveform.
a. From Patt Gen/Patt Gen Sequence Run (Repetitive).
b. From Analyzer/Waveform Machine 1 Run (Repetitive).

A 0.125 coefficient should generate a waveform similar to Figure 26.

3. Stop the simulation in Patt Gen and Analyzer by clicking Stop.

CLK
S0
S1
S2
S3
S4
S5
Co
A5
A4
A3
A2
A1
A0

Figure 26. Testing Impulse response with coefficient set to 0.25

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Testing with 0.125 Coefficient

1. Set the coefficient to 0.125 by switching the dip-switch to its proper position. See
Table of coefficient values in Appendix.

2. Run from both Patt Gen and Analyzer to display input and output waveform.
a. From Patt Gen/Patt Gen Sequence Run (Repetitive).
b. From Analyzer/Waveform Machine 1 Run (Repetitive).

A 0.125 coefficient should generate a waveform similar to Figure 27.

2. Stop the simulation in Patt Gen and Analyzer by clicking on Stop.

CLK
S0
S1
S2
S3
S4
S5
Co
A5
A4
A3
A2
A1
A0

Figure 27. Testing Impulse response with coefficient 0.125

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Improvements

Increase Transistor Widths

The design of the whole system was made simple by using lengths at 3m and 900nm
for all components. This is not an ideal way if you want to design an optimum DSP
filter system. Considering delays of each component of the system, and their response
to each others signal, it is important to have the right widths for the specific
components to properly process the signal.

Design System to Operate Faster

Since the design of the system only used a fourth of the real estate of the padframe, the
system could have been designed bigger, which would have resulted in a faster system.
Relating to the improvement of increasing the width, we could have increased the
performance of the system in the best possible way by calculation and simulation on
PSPICE.

Put Double Contacts for Reliability

The system was laid out with only one contact on the metal3 connection between
components. From the beginning that was questionable. Fortunately, the chip worked.
For future design, it is strongly suggested that double contacts in the connection should
be applied to ensure reliability of the layout.

Minimize Metal Routing

As discussed in the improvement of making the system more reliable, related to this is
the use of less metal routing. Three metals were used in all component design. If we
use only two metals, the manufacturability of the chip will increase as well.

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 Appendix

Coefficient Values in Binary

B5(2^-1) B4(2^-2) B3(2^-3) B2(2^-4) B1(2^-5) B0(2^-6) Value

0 0 0 0 0 0 0.000000
0 0 0 0 0 1 0.015625
0 0 0 0 1 0 0.031250
0 0 0 0 1 1 0.046875
0 0 0 1 0 0 0.062500
0 0 0 1 0 1 0.078125
0 0 0 1 1 0 0.093750
0 0 0 1 1 1 0.109375
0 0 1 0 0 0 0.125000
0 0 1 0 0 1 0.140625
0 0 1 0 1 0 0.156250
0 0 1 0 1 1 0.171875
0 0 1 1 0 0 0.187500
0 0 1 1 0 1 0.203125
0 0 1 1 1 0 0.218750
0 0 1 1 1 1 0.234375
0 1 0 0 0 0 0.250000
0 1 0 0 0 1 0.265625
0 1 0 0 1 0 0.281250
0 1 0 0 1 1 0.296875
0 1 0 1 0 0 0.312500
0 1 0 1 0 1 0.328125
0 1 0 1 1 0 0.343750
0 1 0 1 1 1 0.359375
0 1 1 0 0 0 0.375000
0 1 1 0 0 1 0.390625
0 1 1 0 1 0 0.406250
0 1 1 0 1 1 0.421875
0 1 1 1 0 0 0.437500
0 1 1 1 0 1 0.453125
0 1 1 1 1 0 0.468750
0 1 1 1 1 1 0.484375
1 0 0 0 0 0 0.500000
1 0 0 0 0 1 0.515625
1 0 0 0 1 0 0.531250
1 0 0 0 1 1 0.546875
1 0 0 1 0 0 0.562500
1 0 0 1 0 1 0.578125
1 0 0 1 1 0 0.593750
1 0 0 1 1 1 0.609375

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1 0 1 0 0 0 0.625000
1 0 1 0 0 1 0.640625
1 0 1 0 1 0 0.656250
1 0 1 0 1 1 0.671875
1 0 1 1 0 0 0.687500
1 0 1 1 0 1 0.703125
1 0 1 1 1 0 0.718750
1 0 1 1 1 1 0.734375
1 1 0 0 0 0 0.750000
1 1 0 0 0 1 0.765625
1 1 0 0 1 0 0.781250
1 1 0 0 1 1 0.796875
1 1 0 1 0 0 0.843750
1 1 0 1 0 1 0.828125
1 1 0 1 1 0 0.843750
1 1 0 1 1 1 0.859375
1 1 1 0 0 0 0.875000
1 1 1 0 0 1 0.890625
1 1 1 0 1 0 0.906250
1 1 1 0 1 1 0.921875
1 1 1 1 0 0 0.937500
1 1 1 1 0 1 0.953125
1 1 1 1 1 0 0.968750
1 1 1 1 1 1 0.984375

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Troubleshooting in Testing the Chip

These are suggestion in solving any problems encountered in using the Agilent Logic
Analyzer and testing the 6-bit Multiplier on a DSP SOC.

If there are no signal being generated by the logic analyzer during Logic Analyzer setup

1. Make sure that output pod is connected at the back of the Logic Analyzer.
2. Make sure that the pod from the output to the input pod connections is correct.
3. Make sure that the card adapter connected to the pod is correct.
4. Make sure that the wires used are properly connected to the pins.
5. If all else failed, turn the Logic Analyzer off a couple of minutes, and turn it back
on.

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