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5-V Low Drop Voltage Regulator TLE 4262

Bipolar IC

Features
Output voltage tolerance 2 %
Low-drop voltage
Very low standby current consumption
Overtemperature protection
Reverse polarity protection
Short-circuit proof
Settable reset threshold P-DSO-20-6
Wide temperature range
Suitable for use in automotive electronics

Type Ordering Code Package


TLE 4262 G Q67006-A9068 P-DSO-20-6 (SMD)
TLE 4262 GM Q67006-A9356 P-DSO-14-4 (SMD)
New type
P-DSO-14-4

Functional Description
TLE 4262 G is a 5-V low-drop voltage regulator in a P-DSO-20-6 SMD package. The
maximum input voltage is 45 V. The maximum output current is more than 200 mA. The
IC is short-circuit proof and incorporates temperature protection that disables the IC at
overtemperature.
The IC regulates an input voltage VI in the range of 6 V < VI < 45 V to VQrated = 5.0 V. A
reset signal is generated for an output voltage of VQ < 4.5 V. This voltage threshold can
be decreased to 3.5 V by external connection. The reset delay can be set externally with
a capacitor. The IC can be switched off via the inhibit input, which causes the current
consumption to drop from 720 A to < 50 A.

Semiconductor Group 1 1998-11-01


TLE 4262

Dimensioning Information on External Components


The input capacitor CI is necessary for compensating line influences. Using a resistor of
approx. 1 in series with CI, the oscillating circuit consisting of input inductivity and input
capacitance can be damped. The output capacitor is necessary for the stability of the
regulating circuit. Stability is guaranteed at values 22 F and an ESR of 3 within
the operating temperature range. For small tolerances of the reset delay, the spread of
the capacitance of the dalay capacitor and its temperature coefficient should be noted.

Pin Configuration
(top view)

TLE 4262 G TLE 4262 GM

INH 1 14 V
QRES 2 13 N.C.
GND 3 12 GND
GND 4 11 GND
GND 5 10 GND
DRES 6 9 N.C.
SRES 7 8 VQ
AEP02588

Semiconductor Group 2 1998-11-01


TLE 4262

Pin Definitions and Functions

Pin Symbol Function

1 INH Inhibit; TTL-compatible, low-active input

2 QRES Reset output; open-collector output internally connected to


the output via a resistor of 30 k.

4-7, 14-17 GND Ground

9 DRES Reset delay; connected to ground by a capacitor

10 SRES Reset threshold; for setting the switching threshold connect


by a voltage divider from output to ground. If this input is
connected to GND, reset is triggered at an output voltage of
4.5 V.

11 VQ 5-V output voltage; block to ground by a 22F capacitor.

20 VI Input voltage; block to ground directly at the IC by a ceramic


capacitor.

3, 8, 12, N.C. Not connected


13, 18, 19

Semiconductor Group 3 1998-11-01


TLE 4262

Circuit Description
The control amplifier compares a reference voltage, which is kept highly accurate by
resistance adjustment, to a voltage that is proportional to the output voltage and drives
the base of the series transistor via a buffer. Saturation control as a function of the load
current prevents any over-saturation of the power element. If the externally scaled down
output voltage at the reset threshold input drops below 1.35 V, the external reset delay
capacitor is discharged by the reset generator. If the voltage on the capacitor reaches
the lower threshold VST, a reset signal is issued on the reset output and not cancelled
again until the upper threshold VdT is exceeded. If the reset threshold input is connected
to GND, reset is triggered at an output voltage of 4.5 V. The IC can be switched at the
TTL-compatible, low-active inhibit input. It also incorporates a number of internal circuits
for protection against:
Overload
Overtemperature
Reverse polarity

Block Diagram

Semiconductor Group 4 1998-11-01


TLE 4262

Absolute Maximum Ratings


Parameter Symbol Limit Values Unit Remarks

min. max.

Input

Input voltage VI 42 45 V
Input current II internally limited

Reset Output

Voltage VR 0.3 42 V
Current IR internally limited

Reset Input

Reset threshold VRE 0.3 6 V

Reset Delay

Voltage Vd 0.3 42 V
Current Id internally limited

Output

Voltage VQ 5.25 VI V
Current IQ internally limited

Inhibit

Voltage Ve 42 45 V

Ground

Current IGND 0.5 A

Semiconductor Group 5 1998-11-01


TLE 4262

Absolute Maximum Ratings (contd)


Parameter Symbol Limit Values Unit Remarks

min. max.

Temperature

Junction temperature Tj 150 C


Storage temperature Tstg 50 150 C

Operating Range

*)
Input voltage VI 5.2 45 V

Junction temperature Tj 40 150 C

Thermal resistance
junction-ambient Rth JA 70 K/W soldered
junction-case Rth JC 25 K/W

*) Corresponds with characteristics of drop voltage, output current and power


description (see diagrams).

Semiconductor Group 6 1998-11-01


TLE 4262

Characteristics
VI = 13.5 V; Tj = 25 C; Ve > 3.5 V; (unless specified otherwise)
Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Normal Operation

Output voltage VQ 4.9 5.00 5.10 V 5 mA IQ 150 mA;


6 V VI 28 V;
40 C Tj 125 C

Output voltage VQ 4.95 5.00 5.05 V 6 V VI 32 V;


IQ = 100 mA
Tj > 100 C
Output current limiting IQ 200 250 mA

Current consumption; Iq 50 A Ve < 0.8 V


Iq = Ii IQ
Iq 720 A IQ = 0 mA
Iq 10 15 mA IQ = 150 mA
Iq 15 20 mA IQ = 150 mA; Vi = 4.5 V
Drop voltage VDr 0.35 0.6 V IQ = 150 mA *)
Load regulation VQ 25 mV IQ = 5 mA to 150 mA
Supply-voltage VQ 15 25 mV VI = 6 V to 28 V;
regulation IQ = 150 mA
Ripple rejection SVR 54 dB fr = 100 Hz;
Vr = 0.5 Vpp

Reset Generator

Switching threshold VRT 4.2 4.5 4.8 V VRE = 0 V


Switching voltage VRE 1.28 1.35 1.42 V VQ > 3.5 V
Saturation voltage VR 0.10 0.40 V IR = 1 mA

*)
Drop voltage VI 4.5 V; drop voltage = VI VQ (below regulating range)

Note: The reset output is low within the range VQ = 1 V to VRT.

Semiconductor Group 7 1998-11-01


TLE 4262

Characteristics (contd)
VI = 13.5 V; Tj = 25 C; Ve > 3.5 V; (unless specified otherwise)
Parameter Symbol Limit Values Unit Test Condition

min. typ. max.


Saturation voltage VC 50 100 mV VQ < VRT
Charge current Id 7 10 14 A

Delay switching VdT 1.5 1.7 2.1 V


threshold
Switching threshold VST 0.2 0.35 0.55 V

Delay time tD 17 ms Cd = 100 nF


Delay time tt 2 s Cd = 100 nF

Inhibit

Switch-ON voltage Ve ON 3.5 V IC turned on

Switch-OFF voltage Ve OFF 0.8 V IC turned off

Input current Ie 5 10 15 A Ve = 5 V

Note: The reset output is low within the range VQ = 1 V to VRT.

Semiconductor Group 8 1998-11-01


TLE 4262

Input 20 11
Output
6 V...45 V
470 nF
1 9
KL15 22 F 100 k
TLE 4262G
100 nF
Reset 2 10
to MC
56 k
4

AES01084

Application Circuit

20

11 Q

1000 F 470 nF 22 F
TLE 4262G 5.6 k
e 1
2 R
V + Vr VQ
9 4 10
d
VR
V
Ve GND V cd
Cd
100 nF

V Dr = V - V Q *)
Vr
SVR = 20 log
V Q
*) Below Regulating Range AES01082

Test Circuit

Semiconductor Group 9 1998-11-01


TLE 4262

<tt

V Q V RT

dV d
=
V dT dt C d
Vcd
V ST
td tt

VR

Power-on-Reset Over- Voltage Drop Undervoltage Secondary Load


temperature at Input Spike Bounce AET01085

Time Response

Semiconductor Group 10 1998-11-01


TLE 4262 G

Charge Current versus Switching Voltage VdT and VST


Temperature versus Temperature

AED01086 AED01087
16 3.2
A V
d 14 V 2.8
V = 13.5 V
12 2.4
d
V dT , V cd
10 2.0
V = 13.5 V
8 V cd = 1.5 V
1.6

6 1.2

4 0.8
V ST
2 0.4

0 0
-40 0 40 80 120 C 160 -40 0 40 80 120 C 160
Tj Tj

Reset Switching Threshold Current Consumption of Inhibit


versus Temperature versus Temperature
Output Current
AED01088 AED01089
1.6 12
V A
V RE 1.4 e
10

1.2
8
1.0 Ve = 5 V

6
0.8

0.6 4

0.4
2
0.2
0
0 -40 0 40 80 120 C 160
-40 0 40 80 120 C 160 Tj
Tj

Semiconductor Group 11 1998-11-01


TLE 4262 G

Output Voltage versus Output Current versus


Temperature Input Voltage

AED01090 AED01091
5.2 300
V mA
VQ Q T j = 25 C
5.1 250

5.0 200
Ve = 13.5 V

4.9 150

4.8 100

4.7 50

4.6 0
-40 0 40 80 120 C 160 0 10 20 30 40 V 50
Tj V

Input Response Load Response

AED01092 AED01093
2 295
V t r = t f ~_ 1 s mA
V 1 Q 150

0 5

40 200
mV mV
V Q 20 V Q 100
C Q = 22 F C Q = 22 F
0 0

-20 -100

-40 -200
-10 0 10 20 30 40 s 50 -10 0 10 20 30 40 s 50
t t

Semiconductor Group 12 1998-11-01


TLE 4262

Drop Voltage versus Current Consumption versus


Output Current Output Current

AED01094 AED01095
800 32
mV mA
V Dr 700 q 28

600 24

500 20
T j = 125 C V = 13.5 V
400 25 C 16

300 12

200 8

100 4

0 0
0 50 100 150 200 mA 300 0 50 100 150 200 mA 300
Q Q

Current Consumption versus Output Voltage versus


Input Voltage Input Voltage
AED01096 AED01097
30 12
mA V
q VQ
25 10

20 8
R L = 25

15 6
R L = 25

10 4

5
2

0
0 10 20 30 40 V 50 0
0 2 4 6 8 V 10
V
V

Semiconductor Group 13 1998-11-01


TLE 4262

Package Outlines

P-DSO-20-6
(Plastic Dual Small Outline)

0.35 x 45

2.65 max
2.45 -0.2
7.6 -0.2 1)

0.2 -0.1

9
0.23 +0.0

x
8 ma
1.27 0.4 +0.8
0.35 +0.15 2) 0.1 10.3 0.3
0.2 24x

20 11

GPS05094

1 12.8 1) 10
-0.2

Index Marking

1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side

Weight approx. 0.6 g

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book Package Information.
SMD = Surface Mounted Device Dimensions in mm

Semiconductor Group 14 1998-11-01


TLE 4262

P-DSO-14-4
(Plastic Dual Small Outline)

0.35 x 45

1.75 max
4 -0.2 1)

1.45 -0.2

0.19 +0.06
0.2 -0.1

8 max.
1.27
0.1 0.4 +0.8
0.35 +0.15 2)
0.2 14x
6 0.2
14 8

1 7
8.75 -0.21)

Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.05 max. per side GPS05093

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book Package Information.
SMD = Surface Mounted Device Dimensions in mm

Semiconductor Group 15 1998-11-01


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