UNIVERSITY

(Karunya Institute of Technology & Sciences)

(Declared as Deemed-to-be University under Sec.3 of the UGC Act, 1956)

Reg.No. _____________
End Semester Examination April/May - 2017

Code : 12EC205 Duration : 3 hrs

Sub. Name : DIGITAL ELECTRONICS Max. marks : 100

Q.
No. Questions Marks

PART-A(10X1=10 MARKS)
1. Simplify A+A'B. 1
2. Convert (1101101)2 number into its decimal equivalent. 1
3. Write the truth table and draw the circuit of a half subtractor. 1
4. Define Encoder. 1
5. Identify the difference between Synchronous and Asynchronous design. 1
6. Construct the characteristic equation of RS flip flop. 1
7. Distinguish the main difference between combinational and sequential circuits? 1
8. If the present state of a 4-bit binary down counter is1100 then the next count will be------- 1
9. Identify the differene between PLA and PAL. 1
10. Define Shift Register. 1

PART B(5 X 3= 15 MARKS)

11. Express the Boolean function F= A + BC in a sum of minterms. 3
12. Design 4 X1 multiplexer. 3
13. With characteristics table outline the logic diagram of D Flip-flop using NAND gates. 3
14. Differentiate Mealy & Moore model sequential circuits. 3
15. Compare speed, Power dissipation, Fanin ,Fanout of DTL and RTL circuits. 3

PART C(5 X 15= 75 MARKS)

16. a. Estimate the minimal sum of products for the Boolean expression 15

f = m (0, 1, 3, 4, 5, 7, 10, 13, 14, 15) using Quine McClausky method.

(OR)
17. a. Simplify the Boolean function by using Karnaugh map. 10
F(w,x,y,z) = (0,1,2,4,5,6,8,9,12,13,14)
b. Implement EX-OR gate using NAND gates. 5
18. a. With neat logic diagram design 1-to-4 Demultiplexer. 10
b. Sketch the circuit diagram and truth table of full adder. 5
(OR)
19. a. Implement the following function with a 8:1 multiplexer. 9
F(W,X,Y,Z) =m(0,1,3,5,8,9,15)
b. Design single-bit magnitude comparator 6
20. a. Draw and explain the working of a master slave J-K Flip flop using a NAND gate. 10

b. Realize Y=A + BCD using NAND gates. 5

(OR)
21. a. Implement the following two flip-flop input functions 10

JA=BCx + BCx and KA= B + y

b. Describe in detail about Parallel in Serial out shift register 5
22. a. Design BCD Synchronous Counter by using T Flip-flop with necessary diagrams. 15
 (OR)
23. a. Design Mod 10 synchronous counter using JK flip-flop. 15
24. a. Decribe about PLA with neat block diagram and Implement the following two 15
functions using PLA
F1= A B + AC + ABC ; F2= AC + BC
(OR)
25. a. Implement the following functions using PAL 10
F(A,B,C,D)= (1,2,5,8,10,11,15)

b. Explain about CMOS logic and also illustrate in detail about CMOS NAND with 5
neat diagrams.

ALL THE BEST