GBC 011 E0 0 Zxg10-Bsc (v2) Description-99

GBC_011_E0_0 ZXG10-BSC(V2) Description
Course Objectives:
Grasp ZXG10-BSC(V2) Hardware structure
State function of ZXG10-BSC(V2) Cabinet, subracks and

Boards
Understand board indicator and jumper

Contents
1 Cabinet.............................................................................................................................................................. 1
1.1 Type-A Cabinet Composition................................................................................................................. 1
1.2 Power Box............................................................................................................................................... 2
1.3 Subracks.................................................................................................................................................. 5
1.4 Fan Box................................................................................................................................................... 5
2 Subracks............................................................................................................................................................ 7
2.1 Overview................................................................................................................................................. 7
2.1.1 Structure....................................................................................................................................... 8
2.1.2 Backplane..................................................................................................................................... 8
2.2 BCTL Subrack........................................................................................................................................ 9
2.2.1 Subrack Configuration................................................................................................................. 9
2.2.2 BCTL-RMU Subrack Configuration........................................................................................... 9
2.2.3 BCTL-SCU Subrack Configuration........................................................................................... 10
2.2.4 Functions and Principles............................................................................................................ 12
2.2.5 External Interfaces..................................................................................................................... 13
2.2.6 DIP Switches and Jumpers on the Backplane............................................................................ 14
2.3 BNET Subrack...................................................................................................................................... 15
2.3.1 Subrack Configuration............................................................................................................... 15
2.4 BATC Subrack...................................................................................................................................... 20
i
2.4.3 TCU Functions........................................................................................................................... 21
2.4.4 AIU Functions............................................................................................................................ 22
2.5 BBIU Subrack....................................................................................................................................... 23
2.6 BSMU Subrack..................................................................................................................................... 27
2.6.2 NSMU Subrack Configuration................................................................................................... 27
2.6.3 FSMU Subrack Configuration................................................................................................... 27
3 Boards and Modules...................................................................................................................................... 33
3.1 Overview............................................................................................................................................... 33
3.2 MP B0111..............................................................................................................................................34
3.2.1 Panel Description....................................................................................................................... 34
3.2.2 Jumpers and DIP Switches......................................................................................................... 35
3.2.3 Index and Hot-Plugging/Unplugging......................................................................................... 37
3.3 SMEM................................................................................................................................................... 37
ii
3.4 COMM/ECOM..................................................................................................................................... 39
3.5 PEPD..................................................................................................................................................... 45
3.6 MON..................................................................................................................................................... 46
3.7 PCOM................................................................................................................................................... 48
3.8 SYCK.................................................................................................................................................... 49
3.9 BOSN.................................................................................................................................................... 52
3.10 DSNI................................................................................................................................................... 55
3.10.1 Functions and Principles.......................................................................................................... 56
3.10.2 Panel Description..................................................................................................................... 60
3.10.3 Jumpers and DIP Switches....................................................................................................... 61
3.11 GPP......................................................................................................................................................61
3.11.2 Panel Description......................................................................................................................63
3.12 AIPP.................................................................................................................................................... 64
iii
3.13 BIPP.................................................................................................................................................... 65
3.14 FSPP.................................................................................................................................................... 67
3.15 GIPP.................................................................................................................................................... 68
3.16 NSPP................................................................................................................................................... 69
3.17 TCPP................................................................................................................................................... 71
3.18 DRT/EDRT.......................................................................................................................................... 72
3.19 COMI.................................................................................................................................................. 74
3.20 TIC...................................................................................................................................................... 76
3.20.3 Jumpers and DIP Switches....................................................................................................... 79
3.21 POWB................................................................................................................................................. 82
3.22 POWI...................................................................................................................................................84
3.23 POWT1............................................................................................................................................... 84
iv
3.24 POWT................................................................................................................................................. 86
4 Alarm Box....................................................................................................................................................... 89
4.1 Functions and Principles....................................................................................................................... 89
4.2 Panel Description.................................................................................................................................. 90
4.3 Index and Hot-Plugging/Unplugging................................................................................................... 91
4.4 Precautions............................................................................................................................................ 91
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1 Cabinet
1.1 Type-A Cabinet Composition

Type-A cabinet include racks, front and back doors, sideboards, standard subracks (six),
power P plug-in box (one) and air filter.
Fig 1.1 1 shows the type-A cabinet composition.
4
8
9
10
5
11
12
1. Chute 2. Side top panel 3. Top panel 4. Side door
5. Busbar 6. Left door 7. Right door 8. Leading-out hole
9. Rack 10. Power P plug-in box 11. Standard subrack 12. Air filter
Fig 1.1 1 Type-A Cabinet Composition
Type-A cabinet design features are as follows:
Double door structure facilitates door opening and closing;
Sideboard mount mode facilitates assembly and disassembly.
1
Each cabinet can be configured with six standard subracks and one power P plug-in box.
The power P plug-in box is mounted on the top, and the air filter is mounted at the bottom
of the cabinet.
1.2 Power Box

Power P (POWP) is located in the power P plug-in box on top of the cabinet.
The power P main functions include:
Lead the primary power supply in the cabinet and distribute the power to the
standard subracks at various layers.
Directly supply power to the fans.
Provide over-voltage or under-voltage alarm for -48 V power supply.
Perform lightning protection for power supply system.
There are antistatic wrist strap sockets on the power P plug-in box body that serve to
connect antistatic wrist straps to prevent the equipment from electrostatic impact.
There are three kinds of grounds on the cabinet: protection ground (PGND), working
ground (GND) and -48 V GND, described as follows:
Protection grounds in standard subracks at various layers are connected to busbar

through the power socket on the backplane. The busbar is connected to the cabinet
at the bottom.
Power grounds in standard subracks at various layers are connected to busbar

through the power socket on the backplane. The busbar is connected to the power
ground provided by power P on the top of cabinet.
Working ground is also connected to the busbar.
This cabinet supports two kinds of power P plug-in boxes: One is the single-input power P
plug-in box with a filter, and the other is the dual-input power P plug-in box with a filter.
Fig 1.2 1 shows the single-input power P panel with a filter.
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1 Cabinet
POWER(P)
DISTRIBUTION UNIT
FAN POWER UNDER- OVER- ANTI-STATIC

VOLTAGE VOLTAGE SOCKET
1 2
Fig 1.2 1 Single-Input Power P Panel
Indicator
Antistatic wrist strap socket
Fig 1.2 2 shows the single-input power P plug-in box structure with filter.
1 2 3
4 5 6 7
1. EMI filter 2. Lightning arrester 3. Three-core round aerial plug-in unit
4. Box body 5. POWT1 board 6. Fan 7. Circuit breaker
Fig 1.2 2 Single-Input Power P Plug-in Box Structure
The -48 V power supply (primary power) input from the power distributing cabinet is led
to the busbars on both sides through the Electronic Messages Interexchange (EMI) filter
and diode to supply standard subracks in the cabinet.
The air switch of power on the panel, control the -48 V power from the power distribution
box. The Power Test1 (POWT1) board monitors the -48 V power input alarms and the
fans, provides power and monitors the fan speed.
3
Fig 1.2 3 shows the dual-input power P panel with a filter.
ON ON
OFF OFF
LEFT UNDER- OVER- FAN RIGHT UNDER- OVER- ANTI-STATIC
POWER VOLTAGE VOLTAGE POWER VOLTAGE VOLTAGE SOCKET
POWER (P) DISTRIBUTION UNIT
1 2
1. Indicator 2. Antistatic wrist strap socket
Fig 1.2 3 Dual-Input Power P Panel
Fig 1.2 4 shows the dual-input power P plug-in box structure with a filter.
1 2 3
4 5 6 7
1. Lightning arrester 2. EMI filter 3. Three-core round aerial plug-in unit
4. Box body 5. POWT board 7. Fan 8. Circuit breaker
Fig 1.2 4 Dual-Input Power P Plug-in Box Structure
The dual -48 V power supply (primary power) input from the power distributing cabinet is
led to the busbars on both sides through the EMI filter and diode to supply standard
subracks in the cabinet.
The air switch of power on the panel, control the -48 V power from the power distribution
box. The Power Test (POWT) board serves to monitor the fan speed and detect the dual-
input power, -48 V power P output voltage, power supply, under-voltage, and air-cooled
system operation in real time.
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1 Cabinet
1.3 Subracks
ZXG10-BSC (V2.95) has seven kinds of subracks designed for different functions.
Different combinations of these subracks implement BSC system functions.
The following lines briefly describe these subracks:
Control layer subrack (BCTL):
BCTL subracks are of two types: the System Control Unit (BCTL-SCU) subrack
and the Radio Management Unit (BCTL-RMU) subrack.
Network layer subrack: Backplane of the Network layer (BNET).
A interface, transcoding, and rate adaptation layer subrack: Backplane of A

interface and Transcoder layer (BATC).
Abis interface subrack: Backplane of Abis Interface Unit (BBIU).
Sub-multiplexing interface subrack: Backplane of Sub-multiplexing Unit (BSMU).
BSMU subracks include the Near Sub-multiplexing Unit (NSMU) subrack and Far
Sub-multiplexing Unit (FSMU) subrack.
Packet control unit subrack: Backplane of Packet Control Unit (BPCU).
Gb interface unit subrack: Backplane of Gb Interface Unit (BGIU).
For details on subracks, refer to subracks.
1.4 Fan Box

Fan box is located in the power P plug-in box on top of the cabinet, as shown in Fig 1.2 2.
Each power P plug-in box is configured with five fans, which compose a fan box.
After passing through the air filter, the cold air enters the cabinet from the lowest layer. In
the cabinet, the space between subracks and the boards in subracks forms a duct and the
space between the front and back doors and panels and backplanes forms an air intake
duct naturally. The heat exchange occurs to the cold air when it passes through six layers
of calorific subracks, the cold air becomes hot when it reaches the plug-in box on the top
of the cabinet. The fans eject hot air out of the cabinet. This forms an air cooling
circulation, which guarantees the normal operation of components and devices in the
cabinet.
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2 Subracks
2.1 Overview
ZXG10-BSC (V2.95) has seven different functional subracks designed for different
functions. Different subrack combinations implement BSC system functions.
Following is a brief description of subrack types and functions
Control layer subrack (BCTL):
BCTL subracks are of two types: the BCTL-SCU subrack and the BCTL-RMU
subrack
BCTL-SCU subrack bears System Control Unit (SCU), where the system kernel
software is located. It implements the system control functions.
BCTL-RMU bears the radio Resources Management Unit (RMU) and implements
the radio resources management functions.
Network switching layer subrack (BNET):
BNET subrack bears the Network Switching Unit (NSU) and implements 32K
32K 2-bit circuit-switching network and clock functions.
A interface and transcoding unit subrack (BATC):
BATC subrack bears the A-Interface Unit (AIU) and the transcoding and Rate
Adaptation Unit (TCU). It implements A-interface, transcoding and rate adaptation
functions.
Abis interface unit subrack (BBIU):
BBIU subrack bears the Abis Interface Unit (BIU) and implements the Abis
interface function.
Sub-multiplexing interface unit subrack (BSMU):
SMU is designed to save the transmission equipment cost. It implements sub-

multiplexing functions. The NSMU subrack performs near SMU functions and
FSMU performs far SMU functions.
7
Packet control unit subrack (BPCU):
BPCU subrack bears the Packet Control Unit (PCU) and implements GPRS
functions.
Gb interface unit subrack (BGIU):
BGIU subrack bears the Gb Interface Unit (GIU) and provides the Gb interface
functions.
2.1.1 Structure
The basic structure of above seven subrack types is the same as shown in Fig. 2.2 1.
These subracks differ in the inserted boards, backplanes, and slot labels.
790
9
2 31
279.5
3
5 25
1.Back aluminum beam 2.Front aluminum beam 3. Backplane 4.Side board 5.Guide rail
Fig. 2.1 1 Subrack Structure
2.1.2 Backplane
Backplane is fixed to the subrack through 18 M4 screws and serves to implement electric
connection.
The backplane is configured with many sockets, through which the boards are connected
to the backplane, and thus all boards in the standard subrack are connected to be an
integrated system through the backplane. In addition, the busbar can be connected to the
whole subrack through the backplane, thus providing the power to various units.
All backplanes are of the same outline dimensions, that is 260 mm (H) 722 mm (W)
2.4 mm (D).
There is a one-to-one relationship between backplanes and functional subracks, as shown

8
1 Cabinet
in.
Table 2.1 1 Relationship Between Backplanes and Functional Subracks
Backplane Functional Subrack

BBIU: AIU backplane BBIU subrack
BCTL: Control layer backplane BCTL subrack
BNET: Network switching layer backplane BNET subrack
BATC: A-interface and transcoder backplane BATC subrack
BSMU: SMU backplane BSMU subrack
BPCU: PCU backplane BPCU subrack
BGIU: GIU backplane BGIU subrack
2.2 BCTL Subrack

System kernel software resides on the BCTL subrack. BCTL subracks are of two types:
BCTL-SCU subrack and BCTL-RMU subrack
The BCTL-SCU subrack implements the MPPP and MPMP communications and
processes MTP2 signaling. BCTL-SCU receives instructions on system configuration and
upgrade from OMCR through the Ethernet and report the system status to the OMCR,
thus implementing the system control functions.
The BCTL-RMU subrack implements MPMP communication and LAPD processing, as

well as radio resource management functions.
2.2.1 Subrack Configuration
Following is a description of two types of BCTL subrack configuration.
2.2.2 BCTL-RMU Subrack Configuration
The BCTL-RMU occupies one subrack position on the control layer backplane. Fig. 2.2
1 shows the board configuration in the BCTL-RMU subrack.
1 2 3 ... 27
E/ E/ E/ E/ E/ E/ E/ E/ E/ E/ E/ E/ E/ E/
P S C C C C C C C C C C C C C C P
O M M M O O O O O O O O O O O O O O O
W E P P M M M M M M M M M M M M M M W
B M M M M M M M M M M M M M M M B
9
Fig. 2.2 1 BCTL-RMU Subrack Full Configuration Diagram
Note
The E/COMM in Fig. 2.2 1 indicates that both COMM and ECOM can be inserted into
this slot.
The following boards are configured in BCTL-RMU subrack:
Main Processor (MP)
COMM/ECOM
Shared Memory (SMEM) board
Power B (POWB)
MP is the Network Service (NS) board and is connected to OMCR through Ethernet. Two
MPs work in the active and standby mode. They control the COMM/ECOM board
through the AT bus on the backplane, and exchange data through the SMEM board.
COMM/ECOM is the assistant processing board of the MP. It implements MPMP

communication and LAPD processing functions. It communicates with MP through the
AT bus and is connected to the Communication Interface (COMI) board through the 2
Mbps HW cable. The COMM/ECOM located in slot 13 and 14 implements the MPMP
communication functions, while the COMM/ECOM in slots 15 to 26 implements the
LAPD processing functions.
Two power boards (POWB) supply power to all boards at this layer.
2.2.3 BCTL-SCU Subrack Configuration
The BCTL-SCU occupies one subrack position on the control layer backplane. Fig. 2.2 1
shows the board configuration in the BCTL-SCU subrack.
1 2 3 ... 27
E/ E/ E/ E/ E/ E/ E/ E/ E/ E/ E/ E/
P S C C C C C C C C C C C C P M P
O M M M O O O O O O O O O O O O E O
M O
W E P P M M M M M M M M M M M P W
B M M M M M M M M M M M M M D N B
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1 Cabinet
Fig 2.2 1 BCTL-SCU Subrack Full Configuration
Note
The E/COMM in Fig. 2.2 2 indicates both the COMM and ECOM can be inserted into
this slot.
The following boards are configured in the BCTL-SCU subrack:
MP
COMM/ECOM
SMEM Board
Peripheral Environment & Power Detect Board (PEPD)
Monitoring Board (MON)
Packet Communication Board (PCOM)
POWB
MP is the NS board. Two MPs work in the active and standby mode. They control the
COMM/ECOM, PEPD, MON, and PCOM boards through the AT bus on the backplane,
and exchange data through the SMEM board.
COMM/ECOM is the assistant processing board of the MP. It implements MPMP and
MPPP communication and MTP2 signaling processing functions. It communicates with
the MP through the AT bus and is connected to the network layer through the 2 Mbps HW
cable. The COMM/ECOM located in slot 13 and 14 implements the MPMP, the
COMM/ECOM in slots from 15 to 20 implements the MPPP communications, and the
COMM/ECOM in slots 21 and 22 COMM/ECOM implements MTP2 processing function.
Slots 23 and 24 are standby slots.
MON monitors the board status such as the power supply and clock boards through the
485 cable and reports to MP through the AT bus.
PEPD monitors the equipment room environment through some sensor interfaces.
To connect the subrack to Cell Broadcast Center (CBC), the COMM/ECOM board can be
replaced in slot 23 with the PCOM board to provide the X.25 protocol function.
11
Two power boards (POWB) supply power to all boards at this layer.
2.2.4 Functions and Principles
BCTL layers external communication interfaces include the 2 Mbps HW cables, RS485
asynchronous serial buses and Ethernet interfaces. Fig. 2.2 2 shows the BCTL subrack
block diagram.
Ethernet
Control layer bus 1
M P0
SM EM
Control layer bus

M P1 2
Ethernet COM M COM M ... PE PD MON

O M C-R ... ... ...
Temperature and
smoke sensor
humidity sensor
Infrared and
4 H W 4 H W 8 R S 485 b u ses
Connections Connections
Fig. 2.2 2 BCTL Subrack Block Diagram
The active and standby MPs are connected to the COMM/ECOM, MON, PEPD, and
PCOM boards through the independent AT bus on the backplane and exchange data
through the SMEM board. The COMM/ECOM board is responsible for processing the
HDLC, LAPD (RMU) and MTP2 (SCU) data links. The MON board monitors the board
status such as the power supply and clock boards through the 485 bus and reports to MP
through the AT bus. PEPD monitors the equipment room through external sensor
interfaces (smoke & temperature) and reports the results to MP. MP is connected to
OMCR through the Ethernet. It receives configuration data from the OMCR and reports
various alarms to the OMCR.
The SMEM, MON, PEPD and PCOM boards are hot pluggable. MP is not hot pluggable.
Before plugging/unplugging an MP, set the power switch on the MP panel to OFF.
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1 Cabinet
2.2.5 External Interfaces
Table 2.2 1 lists the BCTL subrack external interfaces.
Table 2.2 1 BCTL Subrack External Interfaces
Interface ID Function Connection Relation

X1_485IN Power monitoring socket of the 485 bus Connects the upper subrack
X1_485OUT Power monitoring socket of the 485 bus Connects the lower subrack
X43_485IN Power monitoring socket of the 485 bus Connects the upper subrack
X43_485OUT Power monitoring socket of the 485 bus Connects the lower subrack
X10_COMM1D1 2 Mbps HW interface Connects DSNI
X38, X46 Power supply socket Connects the busbar
Connects the -48 V power
X34_PEPDD1 Power interface
supply
X34_PEPDD2 Sensor interface Connects external sensors
X36_MOND1 Interface 485 Connects the 485 bus
13

X36_MOND2 Interface 485 Connects the 485 bus
X801~X806 Ethernet RJ45 interface Connects external Ethernet
Connects external Ethernet
X6_MP_2D1 Ethernet interface (through HUB or directly to
OMCR)
OMCR)
OMCR)
OMCR)
2.2.6 DIP Switches and Jumpers on the Backplane
Fig. 2.2 3 shows the jumper layout on the BCTL subrack backplane.
X X5 74 7 X 3 9X 6 0
X X5 84 5 X 4 0X 6 1
Fig. 2.2 3 Jumper Layout on the BTCL Subrack Backplane
Jumpers X39 and X47 on the backplane select the subrack layer (bottom to top) in the
rack. Jumpers X40 and X45 select whether the POWB board of this subrack is located at
the farthest end of 485 monitoring. Table 2.2 2 shows jumper switch meanings.
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1 Cabinet
Table 2.2 2 BCTL Jumper Switch Meanings
Jumper Position
Status Meaning
(top to bottom)
X39, X47 (1~6) OFF OFF OFF OFF OFF ON First subrack
X39, X47 (1~6) OFF OFF OFF OFF ON OFF Second subrack
X39, X47 (1~6) OFF OFF OFF ON OFF OFF Third subrack
X39, X47 (1~6) OFF OFF ON OFF OFF OFF Fourth subrack
X39, X47 (1~6) OFF ON OFF OFF OFF OFF Fifth subrack
X39, X47 (1~6) ON OFF OFF OFF OFF OFF Sixth subrack
POWB board closest to the jumper is
X45, X40 OFF not located at the farthest end of 485
monitoring.
X45, X40 ON located at the farthest end of 485
monitoring.
Note
OFF: Jumper not inserted ON: Jumper inserted
2.3 BNET Subrack

BNET subrack is the SCMs network switching layer. It implements the voice services,
data services and communication timeslots switching function, and provides clock signals
for the whole system.
The following boards are configured in the BNET subrack:
Clock Interface Board (CKI)
Synchronous Clock Board (SYCK)
Bit-Oriented Switching Network (BOSN)
Digital Switching Network Interface Board (DSNI)
Power B Board (POWB)
Fig 2.3 1 shows a fully configured BNET subrack.
15
1 2 3 ... 27
P S S B B D D D D D D D D D D P
C
O Y Y O O S S S S S S S S S S O
K
W C C S S N N N N N N N N N N W
I
B K K N N I I I I I I I I I I B
Fig 2.3 1 BNET Subrack Full Configuration
BNET subrack takes up one subrack position. Both the CKI and SYCK boards are the
clock synchronization units. One CKI board is used to access the external clock
synchronization reference (BITS or E8K). Two SYCK boards work in the active and
standby mode. SYCK serves to synchronize the external clock reference and then provide
clocks for the subracks at this layer and the whole system. If this module does not use
BITS clock, it is not necessary to configure CKI. The SYCK can directly synchronize the
external E8K clock.
Two BOSN boards in the active and standby mode are configured in the BNET subrack.
The BOSN board is the 32 K 32 K 2-bit switching network board. It provides 64 pairs
of bi-directional 8 Mbps HW single-polarity signals.
Two MP-level DSNIs are configured in the BNET subrack. Each MP-level DSNI converts
two 8 Mbps HW signals into sixteen 2 Mbps HW Low Voltage Differential Signals
(LVDS). MP-level DSNI is interconnected to control layer subrack through the cable, and
clock for the control layer subrack is provided by the MP-level DSNI through the same
cable. Two MP-level DSNIs provide up to thirty-two 2 Mbps HWs. The MP-level DSNIs
are located in slots 13 and 14, and the PP-level DSNIs are located in slots 14 to 22. BNET
subrack is configured with up to five active/standby PP-level DSNI pairs. Each DSNI pair
is connected to the BOSN through 16 single-polarity 8 Mbps HW cables and converts the
single-polarity signals into LVDSs for connection with the BATC, BBIU and BPCU units.
The subrack is configured with two POWB boards, which are located at fixed positions.
The CKI, SYCK, BOSN and DSNI are hot pluggable.
Fig 2.3 2 shows the BNET subrack block diagram. Digital switching network has the
following four primary functions.
Semi-permanently connects the communication timeslots of various external
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1 Cabinet
interface units to the COMM board of SCM Main Processing Unit (MPU) to
establish communication with the MP. It semi-permanently connects the
communication timeslots of RMM to the COMM board of SCM MPU to establish
MP-MP communication. As the RMM implements BTS radio resource
management by BSC independently, BOSN switches the communication
information between MP-PP, MTP2 and MP-MP.
BOSN switches the BSS traffic in the subscribers voice and data channels to the
MSC and Serving GPRS Support Node (SGSN). It supports n 16 kbps timeslot
switching and uses the fixed time delay-switching mode.
DSNI provides cable drive for BOSN HWs. It is connected to the BATC, BBIU,
and BPCU and provides clock signals to them. All MPMP, MPPP, and MTP2 are
semi-permanently connected to the MP-level DSNI through BOSN for code rate
conversion and cable driving, then connected to the control layer subrack. In this
way, message internetworking between various units is fulfilled and the MP-level
DSNI also provide clock signals to the control layer subrack.
CKI provides the external clock reference interface, BITS. The SYCK provides
clock signals for all boards in the BNET subrack and all other system units through
the DSNI.
Control
s helf
2 Mbps HW & clock
DSNI- M P DSNI- M P
8 M H z/8 kH z
clo ck 8 M bps H W
External clock 1 6 M H z/8 kH z
reference 8 kHz clock clo ck
CK I SYCK BDOSSNN
reference
8 M H z/8 kH z 8 M bps H W
clo ck
DSNI- P P DSNI- P P DSNI- P P DSNI- P P DSNI- P P

B N ET
8 Mbps HW & clock

? ?/ ?
B B IU , B A TC,
B P?C? U,
? ?e tc .
Fig 2.3 2 BNET Subrack Structural Diagram
17
The MP through the COMM/ECOM (MPPP board) implements T net connection control.
The COMM/ECOM board is connected to T net through the 256 kbps link and MP sends
connection messages to COMM/ECOM. COMM/ECOM forwards these messages to the
active and standby switching networks through the 256 kbps (4 64 kbps) super channel
HDLC link, ensuring that the connections in the active switching network are exactly
same as those in the standby switching network, as shown in Fig 2.3 3.
256 k b p s Switching
MP C O M M /E C O M ne tw ork
256 k b p s
256 k b p s
MP C O M M /E C O M Switching
ne tw ork
256 k b p s
Fig 2.3 3 T Net Connection Control Structure
Table 2.3 1 lists the BNET subrack external interfaces.
Table 2.3 1 BNET Subrack External Interfaces

Power monitoring socket of the 485
X1_485_IN Connects the upper subrack
bus
X1_485_OUT Connects the lower subrack
bus
X44~X55 BITS interface Connects external BITS clock reference
X2_E8K E8K clock reference interface Connects TIC
X3_E8K E8K clock reference interface Connects TIC
Connects BRMT, BRMI, BFBI or
X25_CLK0~3 Clock output interface
BSNM
HDLC communication interface of
X27_COMM0~1 Connects the control layer subrack
BOSN board
HDLC communication interface of
X28_COMM0~1 Connects the control layer subrack
BOSN board
Inter/intra-module communication
MPC0~31 Connects the control layer subrack
interface
Connects units such as the trunk and
SPC15~58 HW and clock interface
subscriber
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1 Cabinet

X18_RS485 Connects the control layer subrack
bus
bus
bus
Fig 2.3 4 shows the jumper layout on the BNET subrack backplane.
X 57 X 60
X 58 X 61
Fig 2.3 4 Jumper Layout on the BNET Subrack Backplane
Jumpers X57 and X60 on the BNET backplane select the subrack layer (bottom to top) in
the rack. Jumpers X58 and X61 select whether the POWB board of this subrack is located
at the farthest end of 485 monitoring.
Table 2.3 2 shows jumper switch meanings.
Table 2.3 2 BNET Jumper Switch Meanings
Jumper Position
Status Meaning
(top to bottom)
POWB board closest to the jumper
X58, X61 OFF
is not located at the farthest end of 4
19
Jumper Position
Status Meaning
(top to bottom)
85 monitoring.
POWB board closest to the jumper
X58, X61 ON is located at the farthest end of 485
monitoring.
Note
2.4 BATC Subrack

The BATC subrack carries the TCU and AIU. TCU provides transcoding and rate
adaptation functions, and the AIU completes the A interface physical connection.
Fig 2.4 1 shows the BATC subrack configuration.
1 2 3 ... 27
P T T E/ E/ E/ E/ E/ E/ E/ E/ A A P
T T T T T T T T
O C C D D D D D D D D I I O
I I I I I I I I
W P P R R R R R R R R P P W
C C C C C C C C
B P P T T T T T T T T P P B
Fig 2.4 1 BATC Subrack Full Configuration
The following boards are configured in BATC subrack:
Transcoder Unit Peripheral Processor (TCPP)
Dual-Rate Transcoder/Enhanced Dual-Rate Transcoder (DRT/EDRT)
A Interface Peripheral Processor (AIPP)
Trunk Interface Circuit (TIC)
Power Board (POWB)
BATC subrack is configured with two mandatory POWB boards, two mandatory TCPP
boards, two mandatory AIPP boards, up to eight DRT boards or EDRT boards that can
20
1 Cabinet
coexist, and up to eight TIC boards. Each TIC board provides up to four E1 trunk circuits.
Each DRT board process up to 126 channels Frame Relay (FR), or 32 channels EFR. Each
EDRT (C62) board process up to 126 channels FR, or 126 channels EFR. Each EDRT
(C64) board processes up to 126 channels FR, 126 channels EFR, or 126 channels HR.
The TCU and AIU are connected in series between the T net and A interface. One TCU is
connected to one AIU in series, with the physical structure shown in Fig 2.4 2.
BOSN
DSNI
2 x 8 M bps
TCU 1 x 8 M bps A IU
4 E1
( E) D R T T IC
1 1
TCP P A IP P

( E) D R T
T IC
1 x 8 M bps n 1 x 8 M bps n
n 8
A in terface
Fig 2.4 2 AIU and TCU Structure Connected in Series
2.4.3 TCU Functions
TCU implements transcoding and rate adaptation functions. Transcoding and rate
adaptation refer to the conversion between GSM radio interface voice codes and the
PSTN A-law PCM voice codes, and rate adaptation between two different voice codes
(including rate adaptation of data services).
TCPP manages TCU and is in turn controlled and managed by the SCU through the
HDLC channel. HDLC channels physical carrier is the 8 Mbps HW cable connecting the
TCU and T net. The active and standby TCPPs communicate with SCU through two 64
kbps HDLC channels. The TCPP software is downloaded from MP through the HDLC
channel.
21
DRT board or the EDRT board implements transcoding and rate adaptation functions.
Active TCPP manages the DRT/EDRT through the point-to-point HDLC link. Each
DRT/EDRT board communicates with the active TCPP through two load-sharing 64 kbps
HDLC channels. The DRT and EDRT software is downloaded from TCPP through the
HDLC channel.
2.4.4 AIU Functions
AIPP controls the AIU module. SCU manages and controls the AIPP through the HDLC
channels. HDLC channels physical carrier is the 8 Mbps HW cable connecting the AIU
and T net (forwarded through the 8 Mbps HW cable between the TCPP and AIPP). The
active and standby AIPPs communicate with the SCU through two 64 kbps HDLC
channels. AIPP software is downloaded from MP through the HDLC channel.
Active AIPP manages other boards such as TIC through the RS485 bus. RS485 addresses
of various boards are equal to board addresses (ranging from 0 to 7) in the subrack. TIC
software cannot be downloaded online.
Fig 2.4 3 shows the jumper layout on the BATC subrack backplane.
X
X 51 72 6 XX1620 3
X 58
X 127 XX1621 4
Fig 2.4 3 Jumper Layout on the BATC Subrack Backplane
rack. Jumpers X127 and X124 select whether the POWB board of this subrack is located
at the farthest end of 485 monitoring. Table 2.4 1 shows jumper switch meanings.
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1 Cabinet
Table 2.4 1 BATC Jumper Switch Meanings
Jumper Position (top

Status Meaning
to bottom)
OFF OFF OFF OFF OFF
X123, X126 (1~6) First subrack
ON
OFF OFF OFF OFF ON
X123, X126 (1~6) Second subrack
OFF
OFF OFF OFF ON OFF
X123, X126 (1~6) Third subrack
OFF
OFF OFF ON OFF OFF
X123, X126 (1~6) Fourth subrack
OFF
OFF ON OFF OFF OFF
X123, X126 (1~6) Fifth subrack
OFF
ON OFF OFF OFF OFF
X123, X126 (1~6) Sixth subrack
OFF
X127, X124 OFF not located at the farthest end of 485
monitoring.
X127, X124 ON located at the farthest end of 485
monitoring.
Note
OFF: Jumpers not inserted ON: Jumpers inserted
2.5 BBIU Subrack

The BBIU subrack carries BIU, which provides the Abis interface physical layer functions
through digital trunk interface.
One BBIU subrack carries two BIUs, one of which is connected to the BNET layer
through the cable. The two BIUs of one BBIU subrack correspond to one RMU and
support up to 256 TRXs. For a certain practical redundancy, one RMUs default maximum
configuration is 240 TRX.
Fig 2.5 1 shows the BBIU subrack board configuration.
23
1 2 3 ... 27
P B B C C B B P
T T T T T T T T T T T T
O I I O O I I O
I I I I I I I I I I I I
W P P M M P P W
C C C C C C C C C C C C
B P P I I P P B
Fig 2.5 1 BBIU Subrack Full Configuration
The following boards are configured in the BBIU subrack:
Abis Interface Peripheral Processor (BIPP)
Communication Interface Board (COMI)
TIC
POWB
The BIU comprises two mandatory BIPP boards and up to six TIC boards at most, each of
which may take four E1 trunk circuits.
For the whole BBIU subrack, two COMI and two POWB boards must be provided.
Fig 2.5 2 shows the BIU block diagram.
C as caded
B IP P A bis
interface
B IU
T IC 1
.
CO M M I B IP P
8 M bps .
2 x 8 M bps .
n
1 6 x 2 M bps 2 x 8 M bps T IC
D SN I n 6
M PM P LA P D
S
M M M
P E P
M
RM U
Fig 2.5 2 BIU Block Diagram
24
1 Cabinet
The BIU is connected to RMU through the 2 Mbps HW to form the radio resource
management module.
BIPP manages the base station interface unit. The SCU through HDLC channels controls
and manages the BIPP. It works in the active/standby mode. The hardware it uses is the
General Peripheral Processor (GPP) board.
The COMI implements HW connection between the BIU and Radio Resource Unit
(RRU). TIC implements E1 interface physical layer functions.
Of all the parallel and cascaded BIUs in one RMM, two BIUs in subracks at the same
layer share one COMI (active/standby) pair. The communication links in the cascaded
BIPPs are collected to these two COMIs through certain physical connection.
The 2 Mbps HW connections between the BIU and RRU carry two different
communication channels: communication connection between the MPMP-RMU and SCU,
and communication connection between the LAPD-RMU and BTS.
Table 2.5 1 lists the BBIU subrack external interfaces.
Table 2.5 1 BBIU Subrack External Interfaces

Power monitoring socket of the
485 bus
485 bus
X15_CNT0,X23_CNT1 HW and clock interface Connects the network switching unit
TICL (0-5)IN (0-3) 75-ohm E1 input signals Connects BTS
TICL (0-5)OUT (0-3) 75-ohm E1 output signals Connects BTS
TICR (0-5)IN (0-3) 75-ohm E1 input signals Connects BTS
TICR (0-5)OUT (0-3) 75-ohm E1 output signals Connects BTS
X9_CNC0-15 2 Mbps HW and clock interface Connects BCTL-RMU and COMM
485 bus
485 bus
25
Fig 2.5 3 shows the jumper layout on the BBIU subrack backplane.
XX547 5 X
X 6401
X 58 X
X 46 X 6412
Fig 2.5 3 Jumper Layout on the BBIU Subrack Backplane
rack. Jumpers X42 and X46 select whether the POWB board of this subrack is located at
the farthest end of 485 monitoring.
Table 2.5 2 BBIU Jumper Switch Meanings
Jumper Position
Status Meaning
(top to bottom)
POWB board closest to the jumper is not
X42, X46 OFF
located at the farthest end of 485 monitoring.
POWB board closest to the jumper is located
X42, X46 ON
at the farthest end of 485 monitoring.
Note
Note: OFF: Jumper not inserted ON: Jumper inserted
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2.6 BSMU Subrack

There are two types of BSMU subracks: NSMU and FSMU. NSMU is the BSMU subrack
that provides the near SMU functions and FSMU is the one that provides the far SMU
functions.
This section describes configuration of both the BSMU subrack types.
2.6.2 NSMU Subrack Configuration
Fig 2.6 1 shows the NSMU subrack configuration.
1 2 3 ... 27
P N N P
T T T T T T T T
O S S O
I I I I I I I I
W P P W
C C C C C C C C
B P P B
Fig 2.6 1 NSMU Subrack Full Configuration
The following boards are configured in the NSMU subrack:
Near Sub-multiplexing Peripheral Processor (NSPP)
TIC
POWB
The NSMU subrack is configured with two mandatory POWB boards, two mandatory
NSPP boards, and up to eight TIC boards.
2.6.3 FSMU Subrack Configuration
Fig 2.6 2 shows the FSMU subrack configuration.
1 2 3 ... 27
P S S F F P
C T T T T T T T T
O Y Y S S O
K I I I I I I I I
W C C P P W
I C C C C C C C C
B K K P P B
Fig 2.6 2 FSMU Subrack Full Configuration
27
The following boards are configured in the FSMU subrack:
Far Sub-multiplexing Peripheral Processor (FSPP)
TIC
CKI
SYCK
POWB
The FSMU subrack is configured with two mandatory POWB boards, one optional CKI
board, two mandatory SYCK boards, two mandatory FSPP boards, and up to eight TIC
boards.
The SMU implements the BSC far-end interface physical layer functions. As an optional
unit in the ZXG10-BSC (V2.95), the SMU is adopted only when TC is configured at the
far end.
According to its location in relation to the T net in the ZXG10-BSC (V2.95), the SMU
falls into two types; near-end SMU and far-end SMU, namely NSMU and FSMU, as
shown in Fig 2.6 3.
SYCK
4 x E 1
T IC T IC F a r- end
8 M bps 1 TC P P
1 . 1
T IC T IC 2 x 8 M bps
n x 8 M bps 2 .
NSPP 2 FSPP .
...
T net
...
F a r- end
8 M bps TC P P
T IC T IC n/ 2
n n n 8
Fig 2.6 3 SMU Basic Structure
Fig 2.6 4 shows the possible SMU physical locations.
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1 Cabinet
B IU T CU
SMU
B IU T net TCU /Far-en d
B IU T CU
Fig 2.6 4 SMU Physical Locations
The SMU trunk transmission is conducted between the NSMU and FSMU, so there is
one-to-one mapping between NSMU and FSMU E1 interfaces.
The FSPP and NSPP, controlling the FSMU and NSMU respectively, use GPP as
their hardware and implement functions through the backplane configuration and
the corresponding software use.
The TIC is consistent with the A-interface and Abis interface in design.
FSMU is configured with the clock module SYCK. Besides the BITS clock, the
SYCK reference clock comes from the device to which FSMU is connected. When
the FSMU is connected to TCU, the reference clock comes from the AIU (two
AIUs at most). That is, the clock is provided by AIPP, extracted from the A
interface E1 cable connected to it.
FSPP manages FSMU and the BATC layer attached to it in the 485 mode. That is, it
adopts the RS485 mode to manage the CKI, SYCK and TIC at this layer. It also
manages the POWB at the BATC layer.
Table 2.6 1 lists the BSMU subrack external interfaces.
Table 2.6 1 BSMU Subrack External Interfaces

X1_485_IN Power monitoring socket of the 485 bus Connects the upper subrack
X1_485_OUT Power monitoring socket of the 485 bus Connects the lower subrack
29

8 kHz reference clock extracted from the
X3_E8K Connects AIPP or NSPP
E1 cable
X4_2MHZ 2 MHz clock Connects the 2 MHz clock
X4_5MHZ 5 MHz clock Connects the 5 MHz clock
X4_2MBIT BITS clock Connects the BITS clock
Input to the CKI for extraction of the 8 kHz
X1425-148,X139, X61-64 75-ohm E1 input signals
reference clock signals
X5_E8K Connects AIPP or NSPP
E1 cable
X9_8KREF Connects CKI or SYCK
E1 cable
X9_HW0-1 HW and clock interface Connects NSPP
For NSPP, X10_HW2-3~6-7 is to connect the
X10_HW2-3~8-9 HW and clock interface network switching unit; for FSPP, X10_HW2-3~8-9
is to connect TCPP.
TIC (0-7)IN (0-3) 75-ohm E1 input signals Connects BTS
TIC (0-7)OUT (0-3) 75-ohm E1 output signals Connects BTS
X9_CNC0-15 2 Mbps HW and clock interface Connects BCTL-RMU and COMM
X29_485_IN Power monitoring socket of the 485 bus Connects the upper subrack
X29_485_OUT Power monitoring socket of the 485 bus Connects the lower subrack
Fig 2.6 5 shows jumper layout on the BSMU subrack backplane.
X1 3 4 X1 2 9
X1 3 7 X1 4 0 X1 3 2
X1 3 5 X1 3 0
X1 5 0 X1 4 9
X1 3 8 X1 4 1 X1 3 3
Fig 2.6 5 Jumper Layout on the BSMU Subrack Backplane
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rack.
Jumpers X135 and X130 select whether the POWB board of this subrack is located at the
farthest end of 485 monitoring.
Jumpers X150 and X149 serve to connect the 485 of this backplane when the subrack
serves as the NSPP.
Jumpers X137
X137, X138 X132, and X133 serve to manage POWBs at this layer and other
X138, X132
layers when the subrack serves as the FSPP.
Jumpers X140 and X141 serve to set the subrack function as the NSPP or FSPP.
Table 2.6 2 BSMU Jumper Switch Meanings
Jumper Position (top to bottom) Status Meaning

POWB board closest to the jumper is not
X130, X135 OFF
X130, X135 ON (It is available only when the subrack
serves as the NSPP. If it serves as the FSPP,
it can only be set to OFF.)
X150, X149 OFF FSPP
X150, X149 ON NSPP
X132, X133, X137, X138 OFF NSPP
X132, X133, X137, X138 ON FSPP
X140, X141 X140 = OFF, X141 = OFF NSPP
X140, X141 X140 = ON, X141 = OFF FSPP
Note
31
32
3 Boards and Modules
3.1 Overview
A board is an integrated circuit board that can be plugged in the subrack slot, perform a
certain function and has panels.
The ZXG10-BSC (V2.95) comprises the boards shown in Table 3.1 1.
Table 3.1 1 Boards Abbreviations and Names
Name Abbreviation Name Abbreviation

A-Interface Peripheral Processor AIPP Enhanced Dual-Rate Transcoder EDRT
Abis Interface Peripheral Processor BIPP Power Test Board POWT
Gb Interface Peripheral Processor GIPP Monitoring Board MON
Transcoder Unit Peripheral
TCPP Main Processor MP
Processor
Near Sub-multiplexing Peripheral
NSPP Packet Communication Board PCOM
Processor
Far Sub-multiplexing Peripheral
FSPP Power B POWB
Processor
General Peripheral Processor GPP Power Isolation Board POWI
Bit-Oriented Switching Network BOSN Packet Unit Controller PUC
Communication Board COMM Shared Memory Board SMEM
Communication Interface Board COMI Synchronous Clock Board SYCK
Name Abbreviation Name Abbreviation
Clock Interface Board CKI Trunk Interface Circuit TIC
BSSGP RLC/MAC Protocol
Dual-Rate Transcoder DRT BRP
Processor
Digital Switching Network
DSNI Frame Relay Protocol Processor FRP
Interface Board
Enhanced BSSGP RLC/MAC
Enhanced Communication Board ECOM EBRP
Protocol Processor
100 Mbps Ethernet Switching Enhanced Frame Relay Protocol
HMS EFRP
board, Processor
Peripheral Environment & Power
PEPD -
Detect Board
33
3.2 MP B0111
MP is the core of various modules in ZXG10-BSC (V2.95) and is located at the control
layer. There are two MPs in the active/standby mode at this layer. Currently, the MP in the
ZXG10-BSC (V2.95) may be either MP B0111, described in this section or MP B09908,
described in Section.
3.2.1 Panel Description
Fig 3.2 1 shows the MP panel. Table 3.2 1 describes panel indicators and buttons.
ON/OFF
RST
SW
R UN
MST
RES
FAU
MP
Fig 3.2 1 MP B0111 Panel
Table 3.2 1 MP B0111 Panel Indicators and Buttons
Indicator Color Description Status
One second ON and one second OFF: Board runs normally
ON: No software runs on the board or the board runs

RUN Green Running indicator
abnormally
OFF: Fault occurrence
OFF: MP runs normally

FAU Red Status or fault indicator
ON: Fault occurred on the MP
ON: Board in active state
MST Green Active indicator
OFF: Board in standby state
RES Green Standby indicator ON: Board is in standby state
Changeover button, only
SW - When SW is pressed, FAU blinks once
functions with active board
Lockless button: Reset
RST - Press this button to reset the board
switch
ON/OFF - Power switch Press this button to power ON or OFF the board
34
1 Cabinet
Note
When the delay function is set in closing the file and the reset or power-off button is
pressed, the board is reset or powered off after indicators RUN, FAU and RES blink for
several seconds (20 seconds at most).
Tips
A small cover with the keyboard and display interfaces is located under the panel for
debugging. Normally, the cover is closed.
3.2.2 Jumpers and DIP Switches
Fig 3.2 2 shows jumpers and DIP switches layout on MP B0111.
X1
X5
3
X1 2
3 1
2
1
X8
3
2
1
X2 SW 1
8
7
6
5
4
3
2
ON
2 4
1 3
X 11
Fig 3.2 2 Jumpers and DIP Switches Layout on MP B0111
3.2.2.1 Jumpers
There are four jumper pairs on the MP:
X1: It serves to enable the built-in CGA display adapter. By default, the CGA is
enabled, and the jumper is inserted on position 1 and 2. Jumper insertion on
position 3 and 4, selects the automatic mode. CGA enables on the MP startup if the
display is connected, and CGA is disabled if the display is not connected.
35
X5: It serves to clear the Complementary Metal-Oxide-Semiconductor

(CMOS).Normal is the default selection and jumper is inserted on position 1 and 2.
Power must be switched off when the CMOS is cleared. MP is restarted after the
jumper insertion on position 2 and 3 for three to five seconds and then back to
position 1 and 2.
X8: It serves to select the board type. To select the MP, the jumper must be inserted
on position 2 and 3 or no jumper is used. Jumper insertion on position 1 and 2,
selects the MRBH board.
X11: Protection ground jumper, no jumper is used by default. For the old backplane
that is not connected to the protection ground at the MP position, the jumper may
be inserted on position 1 and 2 or 3 and 4.
3.2.2.2 DIP Switch
An MP only has one DIP switch, called SW1

SW1, located at the lower right corner of the MP
board. It is an 8-bit DIP switch. ON indicates the bit 0, while OFF indicates the bit 1.
This switch has four functions through different combinations.
Module number
The DIP switch uses the binary coding mode. First bit of the switch is the Least
Significant Bit (LSB), while eighth bit is the Most Significant Bit (MSB). The binary
numbers that the switch can indicate, ranges between (0000001)2 to (1111111)2. That is,
the module numbers range from 1 to 127.
Initialization
Set the 8-bit DIP switch to (10000001)2 and then start the MP. MP will format the hard
disk and load the initial software version. The whole process takes approximately five
minutes to complete. Upon completion, power off the MP and set the switch to the
original module number.
Caution
If the hard disk is formatted, all data in disk C will be lost and no prompt is available at all.
It is necessary to reconfigure the office numbers.
Hardware watchdog
Set the eighth bit of the DIP switch to ON to enable the hardware watchdog (in case the
software does not run properly, MP resets) and OFF to disable the watchdog, for
36
1 Cabinet
debugging.
Caution
When the MP is the module 1, the eighth bit cannot be set to OFF, because the debugging
mode is unavailable to module 1 and the hardware watchdog of module 1 is always
enabled. If the eighth bit is set to OFF in this case, the initialization function is selected
which formats the hard disk.
POST CARD
Set all the lower seven bits of the DIP switch to 0, to display the POST CARD in the
BOOT process. A combination of four indicators and four switches on the panel displays
the POST CARD.
After the switch is set, the first and second functions are only effective when the MP
restarts, while the third and fourth functions are effective immediately.
3.2.3 Index and Hot-Plugging/Unplugging
The MP consumes a relatively high amount of power and is fed with -48V power. The
power supply is switched on or off by pressing the red button on the panel. The MP board
is not hot pluggable. To unplug the MP board, first power it off.
3.3 SMEM
To change over the active/standby MPs, SMEM board provides active/standby MPs with
simultaneously accessible 8 KB dual-port RAM and shared 2 MB RAM (SMEM). The
SMEM board uses parity check codes to ensure data correctness. MP uses the SMEM
board as the message exchange channel and for data backup.
At the same moment, only one MP can access the 2 MB SMEM, and the SMEM board
hardware serves to decide which MP can access it. The SMEM can only be accessed by
MPs that have acquired SMEM control right. The control right is withdrawn instantly
upon access completion. If one MP attempts to access the SMEM in case the other MP has
acquired control right, it receives BUSY signal.
The active/standby MPs access the 8 KB dual-port RAM at the same time. When the two
MPs access the same address unit simultaneously, the SMEM board arbitrate through the
BUSY signal.
37
The active/standby MP "mailbox" is established on SMEM through the 8 KB dual-port

RAM. When MP A sends a mail to MP Bs "mailbox", it sends an interrupt to MP B.
When MP B checks the mail, it resets the interrupt signal.
Fig 3.3 1 shows the SMEM board organizational diagram.
M PO bus 1 2
D ata D ata
buffer buffer
D ual -port 2MB

RAM E PL D RAM
M P1 b u s
D ata D ata
buffer buffer
Fig 3.3 1 SMEM Organizational Diagram
The SMEM board uses Erasable Programmable Logic Device (EPLD) to implement main
functions such as various control and logic circuit arbitration. MP0 and MP1 reach the
dual-port RAM through a level-1 buffer. Here the address and control buffer works in the
through and transparent mode, while EPLD controls the data buffer. MP0 and MP1 can
access the RAM simultaneously. Level-2 buffers (including address, control, and data) are
the time-division multiplexed 2 MB shared RAM switches and EPLD controls the
sequence.
Fig 3.3 2 shows the SMEM panel. Table 3.1 1 describes the panel indicators.
SMEM
RU N
Fig 3.3 2 SMEM Panel
38
1 Cabinet
Table 3.3 1 SMEM Panel Indicators
Legend Indicator Description Status
HL1
HL2 Indicate the running status of
RUN: HL1 ON: Normal running
the board.
3.4 COMM/ECOM
As an auxiliary processor of the MP, COMM/ECOM fulfills MP-MP communication,
MP-PP communication, and data link layer functions of the A interface and Abis interface.
Corresponding to the different data link control procedures, COMM/ECOM may be called
LAPD board (LAPD protocol), MPPP board (HDLC protocol), MPMP board (HDLC
protocol) and SS7 board (MTP2 in CCS7), which is categorized according to the software.
The MPMP, MPPP and SS7 boards work in the load-sharing mode, improving
communication reliability.
In case the PEPD board is configured, BSC control layer is configured with 12
COMM/ECOM boards, each of which can simultaneously process up to thirty-two 64
kbps channels and support the 256 kbps and 512 kbps super channels. The physical layer
is the 2 Mbps HW cable. Each logical link may randomly select 1 to 32 Time Slots (TS)
from the four HW cables leading out of the COMM/ECOM, and the total TS number
cannot exceed 32.
COMM/ECOM board hardware structure is the same for LAPD, HDLC or MTP2.
Respective software implements these functions on the board.
The communication board and the active/standby MPs are connected through the data bus.
As the active/standby MPs adopt the dual-bus (ISA) structure, communication board is
connected to the active/standby MPs through two dual-port RAMs and then the backplane
serial port buses. The active/standby MPs place the data to be transferred on the dual-port
39
RAM connected to their own buses in a certain format. The communication board CPU
judges whether it is from the active MP, and then send the active MPs message to the data
layer protocol controller in the required frame format. For data reception, the CPU places
the correct messages that have been checked by the data layer protocol controller on the
two dual-port RAMs, and the MP receives the corresponding information. In case of error
in the message, the MP waits for resending.
Both the communication board and active/standby MPs can send interrupt signals. When
one party writes data to the other partys mailbox, it sends an interrupt to the other party
until it reads the data.
The CPU exchanges control commands, status information and data sent and received
with the data layer protocol controller through a dual-port RAM. The switching circuit
switches 32 TSs of one HW cable of the protocol controller to four 2 Mbps HW cables for
differential output to meet the communication demands. Each communication board can
select and process up to 32 TSs from the four 2 Mbps HW cables.
Communication board uses Programmable Logic Device (PLD) to generate all logical
signals on the board and system clock that is the 4 MHz/8 kHz clock with difference drive.
Fig 3.4 1 shows the COMM/ECOM board organizational structure. CPU exchanges data
with the active/standby MPs through the dual-port RAM. Simultaneously, it processes
data (data link layer protocol) through another dual-port RAM. As the 2 Mbps HW cables
of COMM/ECOM are connected to subracks at different layers and uses differential drive
to improve transmission reliability. The COMM/ECOM data synchronization clock comes
from the DSNI board. After processing, the clock is provided to corresponding functional
units.
40
1 Cabinet
Clock regulation 4 MHz

processing 8 kH z
Differential transceiving
Logic control
0 0
Switching circuit
2 M bps H W
drive isolation
D ata layer
control 1 1 2 M bps H W
protocol 2 2
2 M bps H W
3 3
2 M bps H W
D ual- port
RAM
Parity
check
D ual -port
B uffer M P0
RAM
C PU
D ual -port B uffer M P1
RAM
Fig 3.4 1 COMM/ECOM Organizational Diagram
The COMM/ECOM has the following four communication functions:
MPU in the module manages various functional units, implementing O&M of the
boards, while the COMM/ECOM implements data link layer functions.
RMM and SCM communicate in real time to implement their service functions.
The MPMP board implements communication between the SCM MP and RMM
MP. The physical layer is the same as that mentioned above.
BSC communicates with the BTS for BTS management. The Base station Interface
Equipment (BIE) separates the communication messages from the BTS
transparently and connects to the COMM/ECOM directly. The physical layer is the
same as mentioned above.
Because the protocols for the A interface and the Abis interface are different,
COMM helps the MP to implement conversion between the LAPD and Message
Transfer Part (MTP) protocol. The BSC external interface unit separates the
communication messages transparently and connects to the COMM/ECOM
directly. The physical layer is the same as mentioned above.
3.4.1.1 Communication Between COMM/ECOM and PP
Communication process between COMM/ECOM and various PPs is as follows: PP

provides a communication channel for maintenance of this board. The active and standby
PPs take a 64 kbps TS as the channel for communicating with the MP. For the SCM, this
41
timeslot passes through the PP-level DSNI board and then semi-permanent connection of
the switching network, and finally is connected to the COMM/ECOM through the MP-
level DSNI. For the RMU, TS provided by the PP is transferred to the COMM/ECOM
through the COMI. Fig 3.4 2 shows the communication mode.
64 kbps
PP C O M M /E C O M
64 kbps
64 kbps
PP C O M M /E C O M
64 kbps
Fig 3.4 2 Communication Between COMM/ECOM and PP
Here, both the PP and COMM/ECOM work in the active and standby mode, with 1+1
backup and reliable communication. Each communication board communicates with the
PP through one 64 kbps channel.
With the same mechanism at the physical layer, communication between the MSC, BTS
and BSC is the same as that mentioned above.
3.4.1.2 Communication Between COMM /ECOM and MP
COMM/ECOM is connected to the active and standby MPs by routing on the background.
They are cross connected through buses on the backplane. 1 + 1 backup mode ensures
reliable communication. Fig 3.4 3 shows communication connection between the
COMM/ECOM and MP.
CO M M /ECO M CO M M /ECO M
Control layer
backplane bus 2
Control layer
backplane bus 1
M P0 M P1
Fig 3.4 3 Communication Between COMM/ECOM and MP
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3.4.1.3 Inter-Module Communication
For inter-module communication, MPMP adopts the 512 kbps communication channel in
the active and standby mode. Fig 3.4 4 shows communication connection between
modules.
512 k b p s
MP M PM P M PM P MP
512 k b p s
MP M PM P M PM P MP
Fig 3.4 4 Inter-Module Communication Connection
3.4.1.4 Communication with T Net
Communication between the T net and MP is very special: The MP is connected to the
BOSN through two 256 kbps links leading out of the COMM/ECOM, and then controls
TSs through the CPU on T net. Fig 3.4 5 shows communication connection with the T net.
256 k b p s
MP C O M M /E C O M BOSN
256 k b p s
256 k b p s
MP C O M M /E C O M BOSN
256 k b p s
Fig 3.4 5 Communication Connection Between COMM/ECOM and T Net
The four 8 Mbps links (HW0 to HW3) leading out of the BOSN active/standby switching
planes, are dedicatedly used for communication switching between various physical
entities and MP. The T net has either a permanent, or dynamic connection to other TSs.
Fig 3.4 6 shows the COMM/ECOM panel.
43
RUN
ECOM
FAU
RST
COMM
RUN
RST
FAU
Fig 3.4 6 COMM/ECOM Panel
Indicator meanings vary with the functionality that the COMM/ECOM provides. Table
3.4 1 describes the COMM/ECOM panel indicators and switches.
Table 3.4 1 COMM/ECOM Panel Indicators and Switches
Indicator
Board Legend Description Status
or Switch
Blink slowly: Normal running
Indicate the running
HL1 RUN: HL1 ON, together with FAU indicator: Fault occurred on
status of the board.
HL2 the board
COMM/
ECOM OFF: Normal
Indicate the failure
(MPPP) FAU: HL2 ON, together with RUN indicator: Fault occurred on
(MPMP) SW1 the board
Lockless button reset
RST: SW1 Press this switch to reset the board
switch
Indicate the running Blink quickly: SS7 link is normal

HL1
RUN: HL1
status of the board. Blink slowly: SS7 link is obstructed
HL2
COMM/ OFF: Normal
ECOM FAU: HL2
status of the board. Blink slowly: Fault occurred on the board
(MTP)
SW1
Lockless button reset
switch

HL1 RUN: HL1 Blink slowly, together with the FAU indicator: Fault
HL2
occurred on the board
COMM/
OFF: Normal
ECOM Indicate the failure
FAU: HL2 Blink slowly together with the RUN indicator: Fault
(LAPD) SW1 status of the board.
occurred on the board
Lockless button:
Reset switch
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3.5 PEPD
PEPD monitors the BSC external environment, and report anything abnormal to the MP
for processing.
The PEPD monitors the switch equipment room environment, such as the temperature,
humidity, smoke and infrared, and reports any abnormity to the MP through indicators in
time.
PEPD board is mandatory for BCTL-SCU subrack while optional for BCTL-RMU
subrack and is located in slot 25 at the BSC control layer. Fig 3.5 1 shows the PEPD
organizational structure.
Temperatur
Isolated e and
MP0 and humidity
Buffer Dual-port magnified
RAM sensor
CPU
Infrared
Buffer Dual-port Isolated and smoke
MP1 RAM sensor
Fig 3.5 1 PEPD Organizational Diagram
Table 3.5 1 shows the PEPD panel. Fig 3.5 1 describes the panel indicators and switches.
RUN
PEPD
FAU
RST
Fig 3.5 2 PEPD Panel
Table 3.5 1 PEPD Panel Indicators and Switches
Indicator or
Legend Description Status
Switch
HL1
RUN: HL1
status of the board. Blink quickly: Sensor is warming
HL2
45
SW1
Indicator or
Switch
up
ON or OFF: Abnormal running
Off: Normal
Indicate the failure status
FAU: HL2
of the board. ON: Fault occurred on the board

switch
3.6 MON
The MON board monitors all boards that the PP does not manage, such as the power board,
clock board and switching network drive board, reports abnormity to the MP.
There is only one MON board, which is located in slot 26 at the control layer. It provides
10 asynchronous serial ports (eight RS485 interfaces and two RS232 interfaces).
RS485 interfaces are applied for long-distance communication. The asynchronous

communication link at each serial port is in the half-duplex bus mode. It can be configured
with many communication nodes (boards). It fulfills communication in the master and
slave mode under the MON board control. The MON board actively sends the query
signals, and the queried board sends message in response to it and data information. Then
the MON board processes and judges the received data, and report alarms, if any
abnormity, to the MP.
RS232 bus is the standby bus for subscriber expansion.
Fig 3.6 1 shows the MON board organizational diagram.
Data transmission between the MON board and the active/standby MPs is similar to that
of the COMM/ECOM board. They can send the interrupt signals mutually.
Communication between the MON and other boards are fulfilled as follows: The CPU
sends control information (polling) to each board through the multi-serial port controller
and the RS485 transceiver through the RS485 bus. The boards send information data to
the CPU through RS485 transceiver and multi-serial port controller for check bit
46
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generation, and then sent to the MP. When the serial port controller transceives data, it
generates interrupt signals to notify CPU to act accordingly.
transceiver (8)
Memory
RS485
Dual-
MP0 Buffer port
RAM
Multi-
CPU serial-port
Dual- controller
transceiver
MP1 Buffer port
RS485
RAM
(2)
Parity EPLD chip
check section control
Fig 3.6 1 MON Organizational Diagram
Fig 3.6 2 shows the MON board panel. Table 3.6 1 describes the panel indicators and
switches.
RUN
MON
RST
FAU
Fig 3.6 2 MON Panel
Table 3.6 1 MON Panel Indicators and Switches
Indicator or
Switch
HL1 RUN: HL1 Blink quickly: Sensor is warming up
HL2 ON or OFF: Abnormal running state
Indicate the failure status OFF: Normal
FAU: HL2
of the board. ON: Fault occurs on the board
SW1
switch
47
3.7 PCOM
PCOM board is located at the SCU control layer in the rack. To connect the board to CBC,
replace the COMM/ECOM in slot 23 with the PCOM board.
The PCOM provides the following functions:
Communicate with the MP through the dual-port RAM (with parity check).
Provide one V.35 (or V.24) interface for connection to the X.25 network.
Processes X.25 packet protocol.
PCOM board comprises four parts: the CPU core system, dual-port RAM used for
communication with MP, interface circuit, and EPLD.
CPU is the core system of PCOM board. It completes the X.25 packet protocol processing
and provides external communication interfaces for the baseband MODEM. Fig 3.7 1
shows the PCOM board organizational structure. Multi-mode
transceiver
V.35 or
Core system of CPU
serial
V .24 Baseband
M ODEM
Dua l-
MP0 B uffe r port
RAM
MP1 Dua l-
B uffe r port X .25
RAM EPLD
P a rity
c he c k
Fig 3.7 1 PCOM Board Organizational Structure
The PCOM board and the active/standby MPs are connected through the data bus. Due to
the dual-bus (ISA) structure, the PCOM board is connected to the active/standby MPs
through two dual-port RAMs.
EPLD provides the various control signals and clock signals for the PCOM.
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Fig 3.7 2 shows the PCOM board panel. Table 3.7 1 describes the panel indicators and
switches.
PCOM
RUN
R ST
R X1
R X2
FAU
TX1
TX2
Fig 3.7 2 PCOM Panel
Table 3.7 1 PCOM Panel Indicators and Switches
Indicator or
Switch
HL1
HL2 RUN: HL1 ON: Abnormal running state
HL3 OFF: Abnormal running state
HL4
Indicate the failure OFF: Normal
HL5 FAU: HL2
HL6 status of the board. ON: Fault occurred on the board
SW1
TX1: HL3 Unavailable at present N/A
RX1: HL4 Unavailable at present N/A
Indicator for the
Blinking: PCOM send data to
TX2: HL5 baseband MODEM
the Baseband MODEM
interface
Indicator for the
Blinking: PCOM receive data
RX2: HL6 baseband MODEM
from the Baseband MODEM
interface
Lockless button: Reset Press this switch to reset the
RST: SW1
switch board
3.8 SYCK
SYCK is the clock synchronization board, completes synchronization with the upper-level
office clock or BITS equipment in case that the CKI is available, and provides clock
signals for various units of this system.
49
Fig 3.8 1 shows the SYCK board organizational diagram. SYCK has the clock receiving
circuit, and can receive four channels of 8 kHz clock reference signals from the AIPP,
NSPP and FSPP. In this way, when the clock references such as the BITS are unavailable,
CKI may not be employed. SYCK fulfills synchronization with the received clocks and
provides required clock signals to various units of this module through the clock
processing circuit.
Clock output
C lo ck
processing
circuit
M onitoring
interface
Frequency
16 M H z
divider
MON
CPU D/A OCXO
8 kH z
F IF O Phase data
8 kH z
Phase comparator
selection circuit
CKI
Reference
receiving
circuit
Clock
Fig 3.8 1 SYCK Organizational Diagram
Fig 3.8 2 shows the SYCK board panel. Table 3.8 1 describes the panel indicators and
switches.
CATCH
MANEN
MANSL
TRACK
REF I
HOL D
FREE
R UN
MST
FAU
R ES
SYCK
R ST
MANI
SW
Fig 3.8 2 SYCK Panel
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1 Cabinet
Table 3.8 1 SYCK Panel Indicators and Switches
Indicator or
Switch
ON: Normal running
Indicate the running status of the
HL1 RUN: HL1 Blinking: OCXO crystal oscillator is
board.
HL2 warming up
HL3
OFF: Normal
HL4 FAU: HL2 Indicate the failure status of the board.
HL5 ON: Fault occurred on the board
HL6 Indicate the active/standby status of ON: Board in active state
HL7 MST: HL3
the board. OFF: Board in non-active state
HL8
Indicate the active/standby status of ON: Board in standby state
HL9 RES: HL4
HL10 the board. OFF: Board in non-standby state
HL11 Indicate the fast capture mode of the ON: Board works in the fast capture mode
HL12 CATCH: HL5
board. OFF: Board works in non-fast capture mode
SW1
SW2 Indicate the tracing mode of the ON: Board works in the tracing mode
TRACK: HL6
SW3 board. OFF: Board works in non-tracing mode
SW4 ON: Board works in the hold mode
HOLD: HL7 Indicate the hold mode of the board.
OFF: Board works in non-hold mode
Indicate the free running mode of the ON: Board works in the free running mode
FREE: HL8
board. OFF: Board works in non-free running mode
Indicate the clock reference source of
When HL9~11 is:
the board. HL9~11 constitutes the
000: No reference
REFI: three-bit binary digital indicator, with
001~100: Clock reference of the local board
HL9~11 HL9 indicating the MSB and HL11
is selected 101: Clock reference sent by the
indicating the LSB. ON indicates 1,
CKI is selected
while OFF indicates 0.
ON: Manual clock reference selection is
Indicate the Enabled status of manual enabled
MANI: HL12
clock reference selection. OFF: Manual clock reference selection is
disabled
MANSL: Press this switch to select the clock reference
Lockless button: Selection switch
SW1 manually.
ON: Manual selection is enabled
MANEN: Press this switch to turn on/off the indicator,
Lockless button: Enabled switch
SW2 indicating enabled status of manual clock
reference selection.
51
Indicator or
Switch
Press this button to change over the
SW: SW3 Lockless button: Changeover switch
active/standby status of the board.
RST: SW4 Lockless button: Reset switch Press this switch to reset the board.
3.9 BOSN
The switching network designed for ZXG10-BSC (V2.95) is a single-T nonblocking 2-bit
time-division switching network, called BOSN (T net in short). The T net, with a 32 k 32
k capacity, works in the dual-input/single-output (dual planes) active/standby mode.
The MP through COMM/ECOM (MPPP board) implements T net connection control. The
COMM/ECOM board is connected to T net through the 256 kbps link and MP sends
connection messages to COMM/ECOM. COMM/ECOM forwards the messages to active
and standby switching networks through the 256 kbps (4 64 kbps) super channel HDLC
link, ensuring that the connections in the active switching network are the same as that in
the standby switching network.
Fig 3.9 1 shows the T net connection control.
256 k b p s Switching
MP COM M
netw ork
256 k b p s
256 k b p s
COM M Switching
MP netw ork
256 k b p s
Fig 3.9 1 T Net Connection Control Structure
Fig 3.9 2 shows the BOSN general physical position in the ZXG10-BSC (V2.95).
52
1 Cabinet
PP-level DSNI
59 x 8 M bps E x tern al in terface
u n it o r R M M
59 x 8 M bps
BO SN
D ig ital
4x8 Mbps
s w itch in g
n etw o rk
MP-level DSNI
32 k x 32 k 16 x 2 M bps
HWs
C O M M( S C M )
2 M bps
H W
CO M M CO M M M P U of S CM
( H D C L) ( H D L C)
M P0 M P1
Fig 3.9 2 BOSN Physical Position
The digital switching network has the following three functions.
Perform the voice channel switching connection of subscribers in the local BSS to
MSC.
Semi-permanently connects the communication TSs of various external interface

units to the COMM/ECOM of the SCM MPU to establish communication with MP.
It also semi-permanently connects the RMM communication TS to the
COMM/ECOM of the SCM MPU to establish MP-MP communication. As RMM
independently implements the BTS radio resource management, the information
switched by BOSN mainly contains MP-PP, MTP and MP-MP communication
information.
Support n 16 kbps TS switching. Using the fixed delay-switching mode, that is,
data of a frame (a frame is 125 microseconds long) is still in the same frame after
passing through the digital switching network, maintaining frame integrity.
The BOSN implements input/output information switching by adopting the write-in-

sequence and read control mode.
53
Fig 3.9 3 shows the BOSN organizational diagram.
1 6 MHz
Clock processing circuit SY CK
8k H z
4 MHz 8 kH z 16 M H z 8 kH z
COM M0
H W 0
interface
Concentrator EPLD H W 1
Bus
COM M1 TS H W 2
selection
switching .
control
circuit
Chip
HDLC control circuit .
protocol 64
32 k x 32 k
isolation
.
Drive
H W 62
Alarm
Shared H W 63
m em ory
FE frame
adjustment
A ctive/ standby
CPU changeover
Fig 3.9 3 BOSN Organizational Diagram
The BOSN includes the TS switching network, core CPU, clock processing circuit, alarm
circuit, and active/standby control circuit.
BOSN provides four of 64 HWs for COMM/ECOM as the communication links between
external units and the MP.
Fig 3.9 4 shows the BOSN panel. Table 3.9 1 describes the panel indicators and switches.
EXCH
RUN
R ES
R ST
FAU
BOSN
MST
Fig 3.9 4 BOSN Panel
54
1 Cabinet
Table 3.9 1 BOSN Panel Indicators and Switches
Indicator or
Switch
HL1 Blink slowly: Normal running

HL2 Indicate the running Blink quickly: Data loading synchronization
HL3 RUN: HL1
HL4 ON or OFF: Abnormal running state
SW1 OFF: Normal

SW2
ON: Fault occurred on the board
FAU: HL2
status of the board. Blink slowly: Communication between this
board and the upper-level board is interrupted
Indicate the ON: Board in active state

MST: HL3 active/standby status
OFF: Board in non-active state
of the board.
Indicate the ON: Board in standby state
RES: HL4 active/standby status
OFF: Board in non-standby state
of the board.
Lockless button: Press this switch to changeover the

EXCH: SW1
Changeover switch active/standby status of the board.
Lockless button:
RST: SW2 Press this switch to reset the board.
Reset switch
3.10 DSNI
DSNI board drives the 64 HWs output from the BOSN. There are two types of DSNI
boards:
MP-level interface board
It is to convert external information into the 8 Mbps stream or 2 Mbps stream in

MP-level message channels, and distribute the 4 MHz and 8 kHz clock signals to
the communication board.
PP-level interface board
It is to convert the drive modes of two types of 8 Mbps HW cables, enhancing anti-
interference. In addition, it provides the 8 MHz and 8 kHz clock signals for the
various layer PPs and RMMs.
55
Fig 3.10 1 shows the DSNI board physical position in ZXG10-BSC (V2.95).
Control layer
1 6 x 2 M bps
D S N I( M P)
4 x 8 M bps
S w itching
netw ork
5 9 x 8 M bps
D S N I(P P )
Base station S M U or TC
interface unit
PCU
Fig 3.10 1 DSNI Board Physical Position
Ten DSNI boards in total are available, of which two MP-level DSNIs fulfill load sharing
through data configuration, and eight PP-level DSNIs work in the active/standby mode.
Table 3.10 1 describes the connection relationship between the T net and the DSNI.
Table 3.10 1 Connection Relationship between T Network HW Cables and DSNI
BOSN DSNI (MP) DSNI (PP)

HW1, 2 The first DSNI board -
HW3, 4 The second DSNI board -
HW5~20 - The third and the fourth DSNI boards
HW21~36 - The fifth and the sixth DSNI boards
HW37~52 - The seventh and the eighth DSNI boards
HW53~63 - The ninth and the tenth DSNI boards
Jumpers on the boards help distinguish between the MP-level and PP-level DSNI boards.
The following lines illustrate their principles.
56
1 Cabinet
3.10.1.1 MP-Level Interface Board
MP-level DSNI board organizational diagram is shown in Fig 3.10 2.
8 MHz C lo ck 4 MHz
frequency 4 MHz and 8 kH z (1 6 channels)
COM M
SYCK division
distribution 8 MHz and 8 kH z (4 channels )
8 kH z 8 kH z
8 MHz 8 kH z
8 x 2 M bps
2 x 8 M bps Code rate
tran s fo rm
H W 0
Code rate
tran s fo rm H W 1
.
Differential drive
8 x 2 M bps
2 x 8 Mbps .
.
Single-end drive
isolation circuit
2 x 8 M bps 8 MHz 8 kH z
Code rate 8 x 2 M bps H W 14
tran s fo rm
H W 15
Code rate
tran s fo rm 8 x 2 M bps
A ctive /
sta ndby
changeover
Board position
identification
CPU
R S 485 MON
Fig 3.10 2 MP-Level DSNI Board Organizational Diagram
The MP-level DSNI board establishes communication link between MP and the T net. The
2 Mbps differential signals from COMM/ECOM and the 8 Mbps single-polarity signals
from T net are respectively converted into the 8 Mbps signals and 2 Mbps differential
signals through different rate information switching, and then output to the T net and
COMM/ECOM.
After the system clock from the SYCK board passes through the clock processing circuit
of MP-level DSNI, the working frequency required by this board is generated, and
provide 4 MHz/8 kHz differential clock signals for the COMM/ECOM.
CPU controls the DSNI board and communicates with MP through the RS485 bus. It
constantly monitors both the transcoders working status and the clock. If any fault is
found, it generates alarm information, sends it to MP and executes commands that the MP
sends back. Simultaneously, panel indicates the fault.
57
MP-level DSNI board external physical connections are shown in Fig 3.10 3.
H W 0 (T S 0~T S 1 5 )
0 # cab le
H W 1 (T S 0~T S 1 5 )
.
D SN I0 .
H W 1 .
H W 14 (T S 0~T S 1 5 )
7 # cab le
H W 2
H W 15 (T S 0~T S 1 5 )
BO SN
H W 0 (T S 0~T S 1 5 )
8 # cab le
H W 3
H W 1 (T S 0~T S 1 5 )
.
H W 4 .
D SN I1
.
H W 14 ( T S 0~T S 1 5 ) 1 5 # cab le
H W 15 (T S 0~T S 1 5 )
Fig 3.10 3 MP-Level DSNI Board External Physical Connections
The two MP-level DSNI boards work in the load-sharing mode. All TSs of the 8 Mbps
HW cables from T net are connected to the first 16 TSs of the 2 Mbps HW output from
DSNI board. Therefore, 128 TSs of one 8 Mbps HW can be connected to eight 2 Mbps
HW cables. Each cable contains two 2 Mbps HW wires. Take 8 Mbps HW1 as an example:
TSs 0 to 15 are connected to the TSs 0 to 15 of 2 Mbps HW0, TSs 16 to 31 are connected
to the TSs 0 to 15 of 2 Mbps HW1, TSs 96 to 111 are connected to the TSs 0 to 15 of 2
Mbps HW6, and TSs 112 to 127 are connected to the TSs 0 to 15 of 2 Mbps HW7.
3.10.1.2 PP-Level Interface Board
PP-level DSNI board organizational diagram is shown in Fig 3.10 4.
The PP-level DSNI board establishes communication links between various external
interface units and the T net. The 16 channels of 8 Mbps single-polarity signals from the T
net and the 16 channels of 8 Mbps differential signals from the external interface unit (PP)
are respectively converted into 16 channels of differential signals and 16 channels of
single-polarity signals by the local board drive circuits, and then sent to various external
interface units and the T net. The system clock from SYCK board is re-driven and
reallocated by the clock processing circuit of this board, and then output to various
external interface units in differential output mode.
58
1 Cabinet
1 6 x 8 M bps H W 0
Differential
. H W 1
drive
.
.
drive circuit
Single-end
1 6 x 8 M bps H W 14
H W 15
identification
A ctive /standby
position
Board
changeover
CPU
R S485 MON
8 MHz
8 MHz
interface unit
External
SY CK Clock frequency
division 8 M H z, 8 k H z
distribution 8 kH z
8 kH z
Fig 3.10 4 PP-Level DSNI Board Organizational Diagram
PP-level interface board working mode: The T net and PP-level DSNI are interconnected
in active/standby mode. According to location correspondence principle, the T net
active/standby signals are directly connected to the PP-level DSNI boards, as shown in
Fig 3.10 5.
16
A ctive T Active D SN I
n et
16 16 External
16 interface units
Standby T Standby
n et 16 D SN I
Fig 3.10 5 PP-Level DSNI Board External Physical Connections
During the active/standby changeover, there are the following three cases.
In the absence of standby DSNI board, the DSNI does not change over during the T
net active/standby changeover.
With the standby DSNI interface board, the DSNI board changes over along with
the T net active/standby changeover.
After the DSNI board is unplugged, the active/standby DSNI boards automatically
change over but the T net does not.
59
Once the MP finds that the DSNI drive board works abnormally, it will force the
active/standby DSNI to change over. Both manual active/standby changeover and
automatic changeover in case of fault are available on DSNI board to make it more
reliable.
If a fault occurs on the standby DSNI board, MON board obtains the information and
notifies the MP to lock the other DSNI board as the active one.
Fig 3.10 6 shows the DSNI board panel. Table 3.10 2 describes panel indicators and
switches.
EXCH
RUN
RES
RST
FAU
DSNI
MST
Fig 3.10 6 DSNI Panel
Table 3.10 2 DSNI Panel Indicators and Switches
Indicator or
Switch
HL1
HL2 Indicate the running Blink quickly: Communication
RUN: HL1
HL3 status of the board. between this board and the MP is
HL4 interrupted
OFF: Normal
SW1
SW2 ON: Fault occurred on the board
FAU: HL2 Blink slowly: Communication
between this board and the upper-
level board is interrupted
Indicate the ON: Board in active state
MST: HL3 active/standby status of
OFF: Board in non-active state
the board.
Indicate the ON: Board in standby mode
RES: HL4 active/standby status of
OFF: Board in non-standby mode
the board.
Lockless button: Press this switch to change over the
EXCH: SW1
Changeover switch active/standby status of the board.
RST: SW2 Lockless button: Reset s Press this switch to reset the board.
60
1 Cabinet
Indicator or
Switch
witch
Fig 3.10 7 shows the DSNI board jumper layout.
1 2 3 X1
X 4 :A
X 4 :B
X3
1
2
3
X2
Fig 3.10 7 DSNI board Jumper Layout
The DSNI board has three jumpers in total, X3 X4A, and X4B
X3, X4A X4B. Table 3.10 3 shows the
jumper settings.
Table 3.10 3 DSNI Jumper Settings
Jumper Description
Used for selecting DSNI configuration. When pins 1 and 2 are connected, the
board is set to MP-level DSNI and connected to COMM/ECOM; when pins 2
X3, X4A, X4B
and 3 are connected, the board is set to PP-level DSNI and connected to PP
board.
3.11 GPP
The ZXG10-BSC (V2.95) system, with a multi-module structure, provides a large
capacity TRX and GPRS services. The RMM processes LAPD channel. At the Abis
interface, A-interface, TC unit, and the Gb interface, GPP carries out the local integrated
61
management and therefore reduces service channel consumption and the number of MP-
PP communication channels.
BIPP implements centralized management on the Abis interface, which also concentrates
the LAPD channels switched by the BTS and sends the channels to RMU for processing
through COMI. Therefore, the switching network receives mostly service channels, fully
utilizing switching network resources.
AIPP implements centralized management on the A interface, TCPP on the TC, and GIPP
on the Gb interface.
Considering different networking modes, when the TCU or BIU is configured at the
remote end, SMU is added especially as the digital trunk to reduce the subscribers
transmission cost.
Since the BIPP, TCPP, AIPP, NSPP, FSPP and GIPP boards are of the same concentrated
management roles and have similar functions, hardware of all these six boards are
implemented by one kind of board: the GPP board. Downloading different programs to
the FLASH, implements the functions of these six boards. Respective sections describe
each boards specific functions while the panel, jumpers, indices and precautions are the
same for each board.
Fig 3.11 1 shows the GPP board organizational diagram. CPU is the core of GPP. It
controls the GPP switching circuit and communicates with other boards through HDLC
and RS485. In the circuit switching part, GPP provides 10 differential signal channels and
10 single-polarity signal channels. The switching circuit, switch the services to the
corresponding 20 HW channels. Simultaneously, GPP provides the
multiplexing/demultiplexing circuits (used when the GPP functions as the TCPP) for TS
integration and division processing.
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1 Cabinet
Differential drive
Differential drive
10 channels of differential 10 10 10 channels of differential
signals from the backplane channels channels signals out of the backplane
10 10
Drive
10 channels of single- polarity
Drive
channels channels 10 channels of single- polarity
signals out of the backplane signals out of the backplane
Switching circuit
1 x 8 M bps 2 1 x 8 M bps
D emultiple
xing
M ultipl
e xing
D emultip 8 8 M ultipl
lexing channels channels
e xing
HDLC
Debugging port of the local board CPU R S 485 (connected to the backplane )
Fig 3.11 1 GPP Board Organizational Diagram
The ZXG10-BSC (V2.95) system supports half-rate voice and data services, called the
half-rate mode, increasing the systems existing spectrum efficiency by one time to that of
full-rate services. Half-rate services require 8 kbps mode that is, BSC should use 1 bit
switching. Therefore, one uplink 2 bit TS is divided into two 1-bit TSs, while the two
downlink 1 bit TSs are combined into one 2 bit TS on the BIPP. The multiplexing and
demultiplexing modules implement these functions. Fig 3.11 1 shows these signals in
bold.
Fig 3.11 2 shows the GPP panel. Table 3.11 1 describes the panel indicators.
63
EXCH
MST
RUN
RES
RST
GPP
FAU
Fig 3.11 2 GPP Panel
Table 3.11 1 GPP Panel Indicators

Indicate whether the board Blinking: Board runs normally
RUN Green
is running normally. ON: Board runs abnormally
Indicate whether the board ON: Board in active state
MST Green
is active. OFF: Board in standby mode
Indicate whether the board ON: Board in standby mode
RES Green
is standby OFF: Board in active state
Indicate whether there is a OFF: Board working normally
FAU Red
fault on the board. ON: Fault occurred on the board
3.12 AIPP
AIPP is located in the AIU connecting the MSC and BSC. One AIU comprises two AIPPs
in the active/standby mode and eight TICs used for the A interface.
Fig 3.12 1 shows the AIPP organizational diagram.
8 channels of signle- 8 8 8 channels of differential

polarity signals channels signals connected to
Differential
connected to 8 TICs channels EDRT/DRT

Switching circuit
drive
Drive
Drive
TCPP
2
Opposite board
Fig 3.12 1 AIPP Organizational Diagram
Below are the AIPP board functions:
Provides eight 8 Mbps differential HW input/output channels, which are

respectively connected to eight (E)DRTs.
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1 Cabinet
Provides eight 8 Mbps single-polarity HW input/output channels, which are

respectively connected to eight TIC boards.
Provides one 8 Mbps single-polarity HW input/output, which is connected to the

TCPP, and two MP-PP communication channels (two 64 kbps HDLCs) for the
local board maintenance and management on eight TIC boards.
Provides one 8 Mbps single-polarity HW input/output channel, which is connected

to the other AIPP, and one HDLC as the communication channel between the active
and standby NSPPs in one unit.
QUICC Multi-channel Controller (QMC) of the CPU processes two HDLCs for
MP-PP communication and one HDLC for active/standby board communication.
Provide clock signals to eight TIC boards in this unit.
Manage the eight TICs through RS485 bus.
Receives eight 8 kHz synchronous reference clock signal channels from the eight
TICs, and selects and sends two of them to the SYCK or CKI.
Support the active/standby changeover function and active/standby mode.
3.13 BIPP
BIPP refers to the Abis interface peripheral processor. Applied in the Abis interface, the
BIPP manages and controls boards such as the TIC, POWERB and COMI. BIPP is located
in the BIU connecting the BTS and BSC. One BIU comprises two BIPPs in the mutual
active and standby mode, two COMIs, and six TICs.
Fig 3.13 1 shows the BIPP organizational diagram.
65
0, 1 ( 2 channels) Abis interface

differential input
1 2 - 1 7 ( 6 channels) single polarity
6 T IC s
0, 1 ( 2 channels) 1 0 - 1 1 ( 2 channels) single polarity
differential output
T net 2 COM Is
2- 9 ( 8 channels) differential
Switching chip
Multiplexing
SM B or cascaded BIPP
1 x 8 M bps
1 9 single polarity
Opposite board
1 x 8 Mbps
Demultiplexing
Fig 3.13 1 BIPP Organizational Diagram
The BIPP provides the following functions and interfaces:
Provides two 8 Mbps differential HW input/output channels, which are connected

to the T net.
Provides six 8 Mbps single-polarity HW input/output channels, which are

respectively connected to six TICs.
Provides two 8 Mbps single-polarity HW input/output channels, which are

respectively connected to two COMIs.
Provides eight 8 Mbps differential HW input/output channels, that are connected

with cascading BIPP.

to the other BIPP in this unit, and one HDLC as the communication channel
between the active and standby BIPPs in one unit.
Two MP-PP communication channels (two 64 kbps HDLCs) of the two 8 Mbps
HWs connected to the T net are used for the local board maintenance and
management on the six TIC boards and two COMIs.
QMC of the CPU processes two HDLCs for MP-PP communication and one
HDLC for active/standby board communication.
Provide clock signals to six TICs and two COMIs.
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1 Cabinet
Manage the six TICs and two COMIs through RS485 bus.
In case the HR is supported, the demultiplexing and BIPP multiplexing modules

functions to separate one uplink 2 bit TS into two 1 bit TSs, and combine two
downlink 1 bit TSs into one 2 bit TS.
3.14 FSPP
The Far Subchannel Multiplexing Peripheral Processor (FSPP) is a sub-multiplexing
peripheral processor located in the SMU.
Fig 3.14 1 shows the FSPP hardware interface diagram.
Differential
Connected to 8 single-polarity 4 TCPPs
Drive
drive
Switching circuit
signal channels
8 channels 8 channels 8 channels or B IP P s
8 T IC s
19 Opposite
Drive
b o ard
Fig 3.14 1 FSPP Hardware Interface Diagram
FSPP has the following interface functions:

respectively connected to eight TIC boards.
Provides eight 8 Mbps differential HW input/output channels, which are connected

to four TCPPs or four BIPPs.
Provides one channel of 8 Mbps HW single-polarity input/output, which is

connected to the other FSPP, and one HDLC as the communication channel
between the active and standby FSPPs in one unit.
67
Two MP-PP communication channels (two 64 kbps HDLCs) of the first two (10,
11) 8 Mbps HWs connected to the NSPP are used for the local board maintenance
and management on the eight TIC boards.
Provide clock signals to eight TIC boards in this unit and to the four TCPPs or four
BIPPs connected to it.
When the SMU is between the T net and TCU, the FSPP receives eight 8 kHz
synchronous reference clock signal channels from the eight TICs, and selects and
sends two of them to the SYCK or CKI.
3.15 GIPP
The GIPP refers to the Gb interface peripheral processor. GIPP functions in the BSC
(V1.2) differ from that in the BSC (V2.0), so the GIPPs in these two systems are calked
the GIPP_1 and GIPP_2 respectively. The GIPP is located in the GIU (GPRS Interface
Unit) and works in the active/standby mode.
Fig 3.15 1 shows the GIPP organizational diagram.
Connected to Connected
Differential drive
8 single-polarity
Drive
10
Switching circuit
8 TICs 8 channels 2 channels to T net

signal channels channels
Opposite 19 Connected
Drive
boa r d 8 channels to 8 A U Cs
Fig 3.15 1 GIPP Organizational Diagram
The GIPP has the following functions.
Provides two 8 Mbps differential HW input/output channels, which are connected

to the T net. The GIPP_2 fixedly processes one of HWs according to the left and
right board positions, with HW0 outputting from the left board, and HW1 from the
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1 Cabinet
right board.

respectively connected to eight TICs.

respectively connected to eight AUCs.
Provides one 8 Mbps HW single-polarity input/output channel, which is connected

to the other GIPP in this unit, and one HDLC as the communication channel
between the active and standby GIPPs in one unit.
Two MP-PP communication channels (two 64 kbps HDLCs) of one channel of 8

Mbps HW connected to the T net serves for the local board maintenance and
management on the eight TIC boards.
One 8 Mbps HW channel connected to the T net functions to forward signaling

between the MP and AUC in the RMM. The GIPP_2 forwards the signaling
between the MP and AUC in the RMM in the load-sharing mode. The number of
channels processed by each GIPP is designed according to the system: 8 + 2 8 =
24 (twenty-four 128 kbps HDLCs).
QMC of the CPU processes two HDLCs for the MP-PP communication, 24
HDLCs for signaling forwarding between the MP and AUC and one HDLC for the
active/standby board communication. Therefore, the QMC of the CPU on GIPP_2
must process 27 HDLCs.
Provide clock signals for the eight TICs in this unit.
3.16 NSPP
The Near Subchannel Multiplexing Peripheral Processor (NSPP) is located in the SMU.
At the T net side, one SMU comprises two NSPPs in the mutual active and standby mode
and eight TICs for digital trunk.
Functions and Principles Fig 3.16 1 shows the NSPP hardware interface diagram.
69
8 channels of single-
polarity signals 8 8 8 channelsED RT/
Differential
connected to the TIC channels channels DRT
Drive
drive
Switching circuit
TCPP
Drive
2
O pposite board
Fig 3.16 1 NSPP Hardware Interface Diagram
NSPP has the following functions.
Provides eight 8 Mbps differential HW input/output channels, which are connected

to the T net.

respectively connected to eight TICs.

to the other NSPP, and one HDLC as the communication channel between the
active and standby NSPPs in one unit.
Two MP-PP communication channels (two 64 kbps HDLCs) of the first two (0, 1)
8 Mbps HWs connected to the T net are used for the local board maintenance and
management on the eight TIC boards.
Provide clock signals to eight TIC boards in this unit.
When the SMU is between the T net and TCU, the NSPP receives eight channels of
8 kHz synchronous reference clock signals from the eight TICs, and selects and
sends two of them to the SYCK or CKI of the BSC.
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3.17 TCPP
Fig 3.17 1 shows the TCPP organizational diagram.
TCPP has the following interface functions:
TCPP provides two 8 Mbps differential HW input/output channels, which are

connected to the T net.
Separates the uplink signals from the T net: The communication information is
separated transparently and sent to CPU for processing. Traffic Channel (TCH)
channel is separated to a demultiplexing unit and each multiplexed service TS is
divided into four demultiplexed service TSs. The circuit-switching chip connects
demultiplexed TSs and communication information from CPU to the
corresponding EDRT or DRT board.
2 differential signal 8 differential signal channels

Differential drive
channels connected to T net 8 channels connected to EDRT/D R T
Differential
2 drive
Switching circuit
2 A IP P
Drive
Opposite board
2
Dem ulti 8 8
ple xing channels channels M ultiplexing
Fig 3.17 1 TCPP Organizational Diagram
Separates the downlink signals from the EDRT or DRT: The communication
information is separated transparently, and sent to CPU for processing. The circuit-
switching chip connects the TCH channel to a multiplexing unit. Every four non-
multiplexed service TSs are multiplexed into one service TS, and then the circuit
switching chip connects the multiplexed TSs and the communication information
from the CPU to the T net.

respectively connected to eight (E)DRTs.
71

to the AIPP and functions to transparently connect the management by the MP on
the AIUs connected to the MP.

to the other TCPP in this unit, and one HDLC as the communication channel
between the active and standby TCPPs in one unit.
Two MP-PP communication channels (two 64 kbps HDLCs) of the two 8 Mbps
HWs connected to the T net are used for the local board maintenance and
management on the eight (E)DRT boards. One 64 kbps communication channel is
provided from the 8 Mbps HWs connected to each (E)DRT board for management
on the (E)DRT board.
QMC of the CPU processes two HDLCs for the MP-PP communication, eight
HDLCs for management on the (E)DRT and one HDLC for the active/standby
board communication. Therefore, on the TCPP board, the QMC of the CPU
processes 11 HDLCs.
Provide clock signals for the eight (E)DRT boards in this unit and AIPP board
connected to the AIU.
3.18 DRT/EDRT
The DRT/EDRT fulfills conversion between voice codes at the GSM radio interface and
the PSTN A-law PCM voice codes in the BSC, and implements rate adaptation (including
data services rate adaptation) between them.
DRT: Dual-rate transcoder, realizing the transcoding service processing. It can process
126 FRs or 32 EFRs at most.
EDRT (C62): Enhanced dual-rate transcoder, an enhanced version of the DRT board. It
can process 126 FRs or 126 EFRs at most.
EDRT (C64): Enhanced dual-rate transcoder, an enhanced version of the DRT board. It
can process 126 FRs, 126 EFRs or 126 HRs at most.
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1 Cabinet
The board has the following functions.
Performs the transcoding and rate adaptation function: It converts the 260-bit
vocoder block into one hundred and sixty 8-bit A-law PCM sample signals, and
vice versa. Performs framing and vocoder block synchronization, detect voice
activation, regulate the block phase in the downlink direction to minimize delay,
send alarms to BSC by passing through BTS through in-band signaling, processes
data blocks in compliance with the protocol standard rate adaptation and re-
assorting them following the A interface requirements.
Provide physical-layer functions of the digital trunk interface.
Separates signals, SS7 links pass transparently, and the service channels pass
through the DSP for processing.
Has the HDLC channels communicating directly with the, facilitating O & M
Center.
Fig 3.18 1 shows the DRT/EDRT board organizational diagram. DRT uses eight DSPs,
EDRT (C62) uses six, and EDRT (C64) uses two. In the given figure, n = 8, 6, 2
respectively.
The DRT/EDRT comprises the DSP, CPU, and switching circuits. The DSP is responsible
for mass calculations, implementing the conversion between radio service channels and
ground service channels. It is the core of the DRT/EDRT board.
HDLC
Switching circuit
DS P n
. . A
.. ..
CPU
D S P4
DSP 3 A b is
HP I DSP 2
DSP 1
Fig 3.18 1 DRT/EDRT Board Organizational Diagram
Except the board name, DRT and EDRT panel is the same, as shown in Fig 3.18 2. Fig
3.18 1 describes the DRT/EDRT panel indicators and switches.
73
(E)DRT
I DL E
RUN
RS T
FA U
Fig 3.18 2 DRT and EDRT Panel
Table 3.18 1 DRT/EDRT Panel Indicators and Switches
Indicator or
Switch
HL1
HL2 Indicate the running Blink quickly: Communication failure with MP
RUN: HL1
HL3 status of the board.
ON or OFF: Abnormal running state
OFF: Normal
SW1
Indicate the failure Flash slowly: Communication between this
FAU: HL2
status of the board. board and the upper-level board is interrupted
Indicate whether ON: None of the DSPs is processing the speech

there is speech channels
IDLE: HL3
channel processing in
OFF: Speech channel processing in progress
progress on this board.
Lockless button:
Reset switch
3.19 COMI
HW connection between the BIU and RRU uses COMI. COMI can distribute four
message HWs sent from BIPPs in two BIUs to 16 communication boards at most. It
implements the conversion of 8 Mbps stream and 2 Mbps stream for message channels,
and the distribution of 4 MHz and 8 kHz clock supplied to the communication boards.
74
1 Cabinet
Fig 3.19 1 shows the COMI board organizational diagram.
D rive 2 Mbps and 8 Mbps Differential

Code stream transform dr ive
16 pairs of 2 Mbps
4 pairs of 8 Mbps
H Ws
HWs
Clock drive E PL D Clock drive

Input clock 4 MH z,
8 kH z
485 Board position

communication
CPU identification
Fig 3.19 1 COMI Board Organizational Diagram
The COMI establishes communication links between up to two BIUs and RMU. The 8
Mbps HW from the BIPP and the 2 Mbps HW from the COMM/ECOM are connected to
COMM/ECOM and BIPP after rate conversion. Circuit switching chips perform
information exchange. The 8 MHz and 8 kHz clock signals from the clock board are
allocated to six 8 MHz and 8 kHz clock signal channels. Four of them are sent to the
switching chip. EPLD logically combines one of them to generate the 4 MHz and 8 kHz
signals, from which the clock driver generates 16 clock signal channels. Then, the
differential drive chip changes these signals into differential signals and send them to
related communication boards. The last channel is sent to clock test chip for clock test.
Fig 3.19 2 shows the COMI panel. Table 3.19 1 describes the panel indicators and
switches.
EXCH
RUN
RES
MST
RST
FAU
COMI
Fig 3.19 2 COMI Panel
75
Table 3.19 1 COMI Panel Indicators and Switches
Indicator or
Switch
HL1 blinks slowly while HL2 is
HL1
OFF: Normal running
HL2 Indicate the running
HL3 RUN: HL1 HL1 blinks quickly while HL2 is
HL4 OFF: Waiting for data
synchronization
SW 1 Indicate the failure OFF: Normal
SW 2 FAU: HL2
status of the board. ON: Clock is lost
Indicate the active ON: Board in active state
MST: HL3
status of the board. OFF: Board in standby mode
Indicate the standby ON: Board in standby mode
RES: HL4
status of the board. OFF: Board in active state
EXCH: Active/Standby Press this switch to change the
SW1 changeover switch active/standby status.
Lockless button:
Reset switch
3.20 TIC
The TIC board implements signal transmission between the ZXG10-BSC and BTS, SGSN,
and MSC.
76
1 Cabinet
Fig 3.20 1 shows the TIC board organizational diagram.
To
G PP E1 interface
Isolation
dr ive circuit0
E1 interface
circuit1
E1 interface
circuit2
From
G PP E1 interface
Isolation circuit3
receiving
E 1 interface unit
CPU
8 M H z , 8 kH z, 2M H z
Clock 8 kHz square wave

R S 485 Alarm processing unit
indication 8 MHz and 8 kH z
clocks
G PP
Fig 3.20 1 TIC Board Organizational Diagram
As a transmission interface board, TIC has the following functions:
Transcoding
Signals transmitted outside the BSC are High-density Bipolar Order 3 (HDB3)
code, and uses Non-Return-to-Zero (NRZ) coding for switching connection inside
the BSC. The digital trunk interface unit converts the incoming HDB3 codes into
NRZ codes and NRZ codes from the office into HDB3 codes and sends them out of
the office.
Clock extraction
TIC extracts clocks from the input data stream as the reference clock of input data
stream and external reference clock source of the local system clock.
Frame synchronization
At the receiving end, it obtains the frame alignment signals from the input PCM
77
stream, and generates TS pulses for various channels at the receiving end to align
them with the frame TS pulses at the transmitting end beginning with TS0.
Therefore, the respective channels receive the signals sent from different channels
correctly, realizing frame synchronization.
Control, detection and alarm
Control function covers interface circuits initialization and reset commands

execution. Detection involves bit error rate, trunk signal loss and out of frame
(OOF) etc. The fault information detected is sent to the local O & M equipment in a
certain mode and through a certain channel. Then fault indication is displayed on
the unit circuit board and related alarm information is sent to the opposite end
office.
Converts the 8 Mbps PCM stream inside the ZXG10-BSC (V2.95) system into E1
stream for long-distance transmission and converts the E1 stream sent by the
remote end into the 8 Mbps PCM stream inside the ZXG10-BSC (V2.95) system.
Provide RS485 asynchronous serial interface for communication with the GPP
board.
Fig 3.20 2 shows the TIC board panel. Table 3.20 1 describes the panel indicators and
switches.
RU N
FAU
E1-1
E1-2
E1-3
E1-4
RST
TIC
Fig 3.20 2 TIC Panel
Table 3.20 1 TIC Panel Indicators and Switches
Indicator or
Switch
HL1
Indicate the Blink slowly: Normal running
RUN: HL1
HL2 running status of th Blink quickly: Communication failure with
HL3
HL4 78
HL5
HL6
SW1
1 Cabinet
Indicator or
Switch
MP
e board.
ON or OFF: Abnormal running state
OFF: Normal
Blink slowly: Communication between this
FAU: HL2 board and the upper-level board is
interrupted
Indicate the status Blink quickly: Normal running
E1-1: HL3 of the first E1 port ON: Alarm occurrence
on the board. OFF: E1 port is not initialized
E1-2: HL4 of the second E1 ON: Alarm occurrence
port on the board. OFF: E1 port is not initialized
E1-3: HL5 of the third E1 port ON: Alarm occurrence
on the board. OFF: E1 port is not initialized
E1-4: HL6 of the fourth E1 ON: Alarm occurrence
port on the board. OFF: E1 port is not initialized
Lockless button:
Reset switch
At present, three TIC versions are involved in the ZXG10-BSC (V2.95).
TIC000304
TIC000905
TIC031100
Fig 3.20 3 shows the DIP switches layout on TIC000304/TIC000905.
79
X1
S4
on
12 34
S5
on
12 34
S3
on
X2
12 34 S6
on
12 34
S2 S7
on on
12 34 12 34
Fig 3.20 3 DIP Switches Layout on TIC000304/TIC000905
TIC000304/TIC000905 has six DIP switches in total, S2 to S7 used for matched

impedance configuration and line frame format. Table 3.20 2 describes the DIP switches
on TIC000304/TIC000905.
Table 3.20 2 DIP Switches Description on TIC000304/TIC000905
Impedance Matching Configuration

Line Impedance
DIP Switch
75 ohms 120 ohms
on 75 A X X on 75 A X X
Software-related
S2 off 120 B X X off 120 B X X
configuration 1XXX 0XXX
4-line E1 impedance on 75 75 75 75 on 75 75 75 75
S3 off 120 120 120 120 off 120 120 120 120
matching
1111 0000
on 75 75 75 75 on 75 75 75 75
Line 1 of E1 S4 off 120 120 120 120 off 120 120 120 120
1111 0000
on 75 75 75 75 on 75 75 75 75
Line 2 of E1 S5 off 120 120 120 120 off 120 120 120 120
1111 0000
on 75 75 75 75 on 75 75 75 75
Line 3 of E1 S6 off 120 120 120 120 off 120 120 120 120
1111 0000
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1 Cabinet
on 75 75 75 75 on 75 75 75 75
Line 4 of E1 S7 off 120 120 120 120 off 120 120 120 120
1111 0000
Line Frame Format Configuration
Software-related configuration Description
TIC Position
S2
on 75 A X X There is no E1 frame format on
At the Gb interface off 120 B X X the line. It works in transparent
X0XX
mode.
on 75 A X X
At non-Gb interface off 120 B X X Transmit in the E1 frame format.
X1XX
Note: 1 = ON; 0 = OFF
Fig 3.20 4 shows the DIP switches layout on TIC031100. Table 3.20 3 gives a
description of the DIP switches.
X1
12 3 4
S2
on
X2
12 3 4
S5
on
Fig 3.20 4 DIP Switches Layout on TIC031100
81
Table 3.20 3 DIP Switches Description on TIC031100
Impedance Matching Configuration

Line Impedance
DIP switch
75 120
4-line E1 on 75 75 75 75 on 75 75 75 75
impedance S2, S5 off 120 120 120 120 off 120 120 120 120
1111 0000
matching
Note: 1 = ON; 0 = OFF
3.21 POWB
POWB is the concentrated power supply of the control layer, network layer and trunk
layer, with 30 A, +5 V load current. The POWB has a relatively large supply range, and
work reliably between +5 V, 3 A to +5 V, 27 A.
Table 3.21 1 shows the POWB board organizational diagram.
Control w ire
Monitoring circuit
Primary power
-48 V input +5 V
Input filter Soft start circuit -4 8 /5 V, 30 A F ilter
Fig 3.21 1 POWB Board Organizational Diagram
The POWB comprises three parts, switching, monitoring and power supply.
The -48 feed circuit includes capacitor load and high-power Metallic Oxide
Semiconductor Field Effect Transistor (MOSFET). Resistor-Capacitor (RC) charging
circuit controls MOSFET grid potential, and the drain-source channel width. With
increase in charging grid-source voltage, the channel becomes wide, which increases input
current and slows the process. Another MOSFET circuit function is to control the output
switch of -48V feed circuit. As the right and left power boards are installed in parallel,
each power boards output voltage channel needs to be isolated with the isolation diode.
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1 Cabinet
After the delayed start through the power MOSFET and p-type filtering, -48V voltage is
sent to the DC-DC circuit. Over/under-voltage detection circuit is employed, If the
detected voltage exceeds the nominal value by 20%, over-voltage occurs; if the detected
voltage is below this nominal value by 20%, under-voltage occurs. In case a serious short-
circuit occurs to a subscriber board, and the circuit is so overloaded that it exceeds the
power modules rated value, under-voltage occurs on the output. POWB core is 150 W
synchronous-rectification DC-DC conversion circuits. An independent fly back DC-DC
conversion circuit supplies Monitor circuit to ensure its priority in power supply. Manual
panel switch and software controls the power switch. Power is switched off manually or
by software, while both the software and switch must be turned on to switch on the power.
Ripple is removed by a large-capacity electrolytic capacitor, while the noise transmission

between the primary power supply and secondary power is removed by a common mode
suppression inductance. From the system viewpoint, as the filter capacitors of backplane
and boards can suppress ripple and high-frequency noise, the ripple and high-frequency
noise tested from the cabinet is very low.
Fig 3.21 2 shows the POWB panel. Table 3.21 1 describes panel indicators.
OFF
ON
POWER B
RUN
FAU
Fig 3.21 2 POWB Panel
Table 3.21 1 POWB Panel Indicators
On: Normal running

Normal running
RUN Green
indicator Flash at 0.5Hz: Cabinet is powered on, but the
power board switch is turned off
OFF: Normal
FAU Red Fault status indicator
83
3.22 POWI
POWI is the P power isolation board. It takes -48 V as input and after it is isolated by the
isolation diode, outputs the same -48 V.
Fig 3.22 1 shows the POWI board block diagram.
-48V V IN -48V VOUT

Isolation diode
Input reverse
connection
protection
-48V GND
Fig 3.22 1 POWI Board Block Diagram
-48 V is input into the POWI, and output as -48 V after it is isolated by the isolation diode
for supplying power to the POWT.
3.23 POWT1
POWT1 is a single-input power detection board, comprising the -48 V power input
indication, over-/under-voltage detection, fan power supply, and circuit detection and
protection. It can monitor the -48V output voltage of the P power and system operation
status in real time (including power supply, under/over-voltage, and air-cooled system
working).
Fig 3.23 1 shows the POWT1 block diagram.
84
1 Cabinet
-48 V power display Air

cooled system monitoring A/D converter -4 8 /5 V
-4 8 V power supply
Overvoltage and
undervoltage test
485 b u s
LCD display CPU R S 485
Fig 3.23 1 POWT1 Block Diagram
To detect in real time the -48V output voltage of the P power supply and the system
operation status (including the power supply status, over-/under-voltage, and air cooled
system working). The detection board circuit adopts the single-chip microcomputer
system to convert the analog voltage into 12-bit serial digital signals through the A/D
converter and input these signals into the CPUs I/O port for operation processing. It also
inputs the system working status signals into the CPU I/O port through the optical coupler
and gating diode to detect in real time the system operation status. The P power detection
signals pass through the 485 bus at the 485 port. Connecting the resistor and the
luminotron in series, displays the -48 V P power working voltage indicators. Software
detects the over/under-voltage. Fan detection is carried out by connecting the diode in
series with fan, and then the comparison circuit checks whether the fan is short-circuited
by detecting voltage drop on the diode. Air-cooled system indicator output displays air-
cooled system detection and controlled by CPU.
Fig 3.23 2 shows the POWT1 panel. Table 3.23 1 describes panel indicators.
FA N PO W ER U N D ER - O V ER -
V O LTA G E V O LTA G E
Fig 3.23 2 POWT1 Panel
85
Table 3.23 1 POWT1 Panel Indicators

Air cooled system
FAN Green ON: Cooling system functions normally
indicator
ON: -48 V input power exists
POWER Green Power indicator
OFF: -48 V input power does not exist
Under-voltage ON: Under-voltage (less than or equal to 40
UNDER-VOLTAGE Red
indicator 1 V) on -48 V power
Over-voltage ON: Over-voltage (more than or equal to 57
OVER-VOLTAGE Red
indicator 1 V) on -48 V power
3.24 POWT
POWT board is a dual-input power detection board. It includes dual-input -48 V power
indications, over/under-voltage detection, fan power supply, circuit detection and
protection. It monitors the -48 V output voltage of the P power and system operation
status in real time (including power supply, under/over-voltage, and air-cooled system
working status).
Fig 3.24 1 shows the POWT board block diagram.
D ual-channel -48 V A/ D
power display Air cooled -4 8 /5 V
converter D ual-channel -4 8 V
system monitoring
power supply
Overvoltage and
undervoltage test
485 b u s
LCD display CPU R S 485
Fig 3.24 1 POWT Board Block Diagram
POWT board circuit uses single-chip microcomputer system to convert the analog voltage
into 12-bit serial digital signals through the A/D transformer and input these signals into
86
1 Cabinet
the CPU I/O port for operation processing, implementing real-time monitoring on the -48
V output voltage. It also inputs the system working status signals into the CPU I/O port
through the optical coupler and gating diode to detect in real time the system operation
status. The P power detection signals pass through the 485 bus through the 485 port.
Connecting the resistor and the luminotron in series, displays the -48 V working voltage
indication of P power. Over/under-voltage is detected with the resistance divider and
Zener as the comparison reference and displayed in the triode drive mode. Fan detection is
carried out by connecting the diode in series with fan, and then the comparison circuit
checks whether the fan is short-circuited by detecting voltage drop on the diode. Air-
cooled system indicator displays the air-cooled system detection and controlled by CPU.
The lock-bearing 2-core plugs and sockets are used for -48 V power cables of the fans.
Fig 3.24 2 shows the POWT panel. Table 3.24 1 describes panel indicators.
Fig 3.24 2 POWT Panel
Table 3.24 1 POWT Panel Indicators

LEFT POWER Green Left power supply indicator ON: Left -48 V power supply exists
Under-voltage indicator of ON: Under-voltage on the left -48 V power
UNDER-VOLTAGE (LEFT) Red
left power supply supply (less than or equal to 40 1 V)
Over-voltage indicator of left ON: Over-voltage on the left -48 V power
OVER-VOLTAGE (LEFT) Red
power supply supply (more than or equal to 57 1 V)
FAN Green Air cooled system indicator ON: Air cooled system functions normally
RIGHT POWER Green Right power supply indicator ON: Right -48 V power supply exists
Under-voltage indicator of ON: Under-voltage on the right -48 V power
UNDER-VOLTAGE (RIGHT) Red
right power supply supply (less than or equal to 40 1 V)
OVER-VOLTAGE (RIGHT) Red Over-voltage indicator of righ ON: Over-voltage on the right -48 V power sup
87
t power supply ply (more than or equal to 57 1 V)
88
4 Alarm Box
4.1 Functions and Principles

The ZXG10-BSC (V2.95) alarm box is compliant with the Ministry of Posts and
Telecommunications General Technical Specifications for Telephone Switching
Equipment and has the following functions:
Alarm classification
There are two categories of alarms on the exchange according to severity, critical
alarm and non-critical alarm.
Alarm signals
The alarm signals are two types: audible and visual. Audible signals use the DC
ringer, and alarm mode falls into three types: continuous ringing, intermittent
ringing and single ringing. Visual signal indicators use five different colors: blue,
red, green, white and yellow. Alarms are indicated by different indicator color
combinations and ring tones according to fault severity.
Alarm removal
When the maintenance personnel handle the fault, they should cut off the audible
alarm signals. However, visual signals cannot disappear until the fault is removed.
For various switch faults information, received from the main control console
through the Ethernet interface, different level audible and visual alarms are output
according to alarm instructions.
Fig 4.1 1 shows the Alarm box block diagram.
89
B utton
Loudspeaker Loudspeaker
CPLD logic dr ive
implementation
unit Display drive Integrated
CPU of board luminescent light
10 Mbps Ethernet
Ethernet
interface
Fig 4.1 1 Alarm Box Block Diagram
4.2 Panel Description

Fig 4.2 1 shows the Alarm box panel. Table 4.2 1 describes panel indicators and Table
4.2 2 describes panel buttons.
F IR S T L E V E L
SECO ND LEVEL
T H IR D L E V E L
FO U RTH LEVEL
E N V .(T & H )
RST M UTE PW R
Fig 4.2 1 Alarm Box Panel
Table 4.2 1 Alarm Box Panel Indicators
Normal
Status
FIRST LEVEL Red Level-1 alarm ON: Occurrence of level-1 alarm OFF
90
1 Cabinet
Normal
Status
indicator
SECOND Level-2 alarm
Blue ON: Occurrence of level-2 alarm OFF
LEVEL indicator
Level-3 alarm
THIRD LEVEL Green ON: Occurrence of level-3 alarm OFF
indicator
FOURTH Level-4 alarm
White ON: Occurrence of level-4 alarm OFF
LEVEL indicator
Level-5 alarm
ENV. (T & H) Yellow ON: Occurrence of level-5 alarm OFF
indicator
ON: Mute
MUTE (side) Red Mute indicator OFF: Audible alarm can be OFF
generated
Blinking @ 1 Hz: Ethernet
Red/Gre communication is normal
PWR (side) Running indicator Blink @ 1 Hz
en
ON: Communication is interrupted
Table 4.2 2 Alarm Box Panel Buttons
Button Meaning Description

RST Reset button Serves to reset and restart a board.
MUTE Mute button Serve to enable/disable audible alarms.
PWR Power switch Press it to switch on the power.
4.3 Index and Hot-Plugging/Unplugging

The Ethernet interface is hot pluggable while -48 V power cable is not.
4.4 Precautions
Alarm box is a chassis device, the -48 V power shall observe the power ON/OFF
sequence and must first be powered OFF before the -48V power cable is unplugged.
91

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GBC_011_E0_0 ZXG10-BSC(V2) Description

State function of ZXG10-BSC(V2) Cabinet, subracks and

Understand board indicator and jumper

1.1 Type-A Cabinet Composition................................................................................................................. 1

1.2 Power Box............................................................................................................................................... 2

1.4 Fan Box................................................................................................................................................... 5

2.2 BCTL Subrack........................................................................................................................................ 9

2.2.1 Subrack Configuration................................................................................................................. 9

2.2.2 BCTL-RMU Subrack Configuration........................................................................................... 9

2.2.3 BCTL-SCU Subrack Configuration........................................................................................... 10

2.2.4 Functions and Principles............................................................................................................ 12

2.2.5 External Interfaces..................................................................................................................... 13

2.2.6 DIP Switches and Jumpers on the Backplane............................................................................ 14

2.3 BNET Subrack...................................................................................................................................... 15

2.3.1 Subrack Configuration............................................................................................................... 15

2.3.2 Functions and Principles............................................................................................................ 16

2.3.3 External Interfaces..................................................................................................................... 18

2.3.4 DIP Switches and Jumpers on the Backplane............................................................................ 19

2.4 BATC Subrack...................................................................................................................................... 20

2.4.2 Functions and Principles............................................................................................................ 21

2.4.3 TCU Functions........................................................................................................................... 21

2.4.4 AIU Functions............................................................................................................................ 22

2.4.5 DIP Switches and Jumpers on the Backplane............................................................................ 22

2.5 BBIU Subrack....................................................................................................................................... 23

2.5.1 Subrack Configuration............................................................................................................... 23

2.5.2 Functions and Principles............................................................................................................ 24

2.5.3 External Interfaces..................................................................................................................... 25

2.5.4 DIP Switches and Jumpers on the Backplane............................................................................ 26

2.6 BSMU Subrack..................................................................................................................................... 27

2.6.1 Subrack Configuration............................................................................................................... 27

2.6.2 NSMU Subrack Configuration................................................................................................... 27

2.6.3 FSMU Subrack Configuration................................................................................................... 27

2.6.4 Functions and Principles............................................................................................................ 28

2.6.5 External Interfaces..................................................................................................................... 29

2.6.6 DIP Switches and Jumpers on the Backplane............................................................................ 30

3 Boards and Modules...................................................................................................................................... 33

3.2.1 Panel Description....................................................................................................................... 34

3.2.2 Jumpers and DIP Switches......................................................................................................... 35

3.2.3 Index and Hot-Plugging/Unplugging......................................................................................... 37

3.3.1 Functions and Principles............................................................................................................ 38

3.3.2 Panel Description....................................................................................................................... 38

3.4.1 Functions and Principles............................................................................................................ 39

3.4.2 Panel Description....................................................................................................................... 43

3.5.1 Functions and Principles............................................................................................................ 45

3.5.2 Panel Description....................................................................................................................... 45

3.6.1 Functions and Principles............................................................................................................ 46

3.6.2 Panel Description....................................................................................................................... 47

3.7.1 Functions and Principles............................................................................................................ 48

3.7.2 Panel Description....................................................................................................................... 49

3.8.1 Functions and Principles............................................................................................................ 50

3.8.2 Panel Description....................................................................................................................... 50

3.9.1 Functions and Principles............................................................................................................ 52

3.9.2 Panel Description....................................................................................................................... 54

3.10.1 Functions and Principles.......................................................................................................... 56

3.10.2 Panel Description..................................................................................................................... 60

3.10.3 Jumpers and DIP Switches....................................................................................................... 61

3.11.1 Functions and Principles.......................................................................................................... 62

3.11.2 Panel Description......................................................................................................................63

3.13.1 Functions and Principles.......................................................................................................... 65

3.14.1 Functions and Principles.......................................................................................................... 67

3.15.1 Functions and Principles.......................................................................................................... 68

3.17.1 Functions and Principles.......................................................................................................... 71

3.18.1 Functions and Principles.......................................................................................................... 73