Escolar Documentos
Profissional Documentos
Cultura Documentos
V * denotes the infinite set of all the words build from the 2.2 Definitions related to sequential circuits
concatenation (juxtaposition) of elements of V , including We call Boolean or binary variable, any numeric variable
empty string denoted . We call formal language (or in the set: B {0,1} . The set B is associated with two
simply language, if there is no confusion), every part of binary logic operators: AND (also called conjunction) and
V*. OR (also called disjunction) and one unary operator: NOT
(called complement), noted respectively: , , . These
Formal languages, generated by grammars and recognized three logic operators allow expressing all the other logic
by automata, exist in several types and are classified operators. AND and OR operators are implemented with
according to the generation technique (Noam Chomsky's AND and OR gates respectively and NOT is implemented
classification [7]) or the recognition technique. In this with an inverter or NOT gate.
paper, we are only interested in regular languages, which
are generated by regular grammars and recognized by We call logic function, a function on logic variables,
finite-state automata (or finite-state machines). associated by logic operators and possibly of other logic
Formally, a finite-state automaton is a 5-tuple: functions. A logic equation is an equation of logic
A VT , Q, q0 , F , , such that: functions and binary variables. Logic functions can be
implemented with electronic circuits, called
VT denotes the final vocabulary; i.e. the vocabulary
combinatorial circuits.
used to write the words recognized by the finite-state
machine. We call final symbol, any element of VT ; We call monomial, the conjunction of possibly
Q denotes the set of states; i.e. a vocabulary such that: individually complemented logic variables. A canonical
monomial is a monomial comprising the totality of the
VT Q ; logic variables used in a given logic function. For
q0 Q denotes the initial state; that is the state in example, if x, y, z are Boolean variables, then xy, yz,
which the automaton is set to start the recognition of a x yz, xy z are four monomials; among which
new word;
F Q denotes the set of final states, provided that a
x yz, xy z are two canonical monomials. When a function
is expressed as a disjunction of canonical monomials, it is
final state (or accepting state) is a state in which the
said to be in disjunctive canonical form, or quite simply
automaton ends the recognition of any word of the
in the canonical or normal form, if there is no ambiguity.
related regular language;
Notice that each logic function admits a unique canonical
: Q VT Q is the transition function; i.e. a form.
mapping of a set of states and a set of final symbols onto
the original set of states. It is a mathematical model of the The value computed by a logic function must be stored in
automaton behavior, specifying which state the machine an elementary memory called latch or flip-flop, which can
will go to after the recognition of an input final symbol. store only one binary digit (i.e. bit). There are several
The interpretation of (q, a) q ' is that automaton A in types of latches: D, RS, JK, T and so on. A latch can be
state q with a as input final symbol will go in state q ' synchronized with a clock intended to allow the latch to
after processing input atomic data a . The function change its state. The content of a latch is available
through its output q (often referred to as Q in the
admits an extension denoted: : Q VT* Q , such
literature). A combinatorial circuit, provided with a
that: memory is called sequential circuit. In a sequential
circuit, the memory output can be used as an input of the
(q, ax) (q, a), x same circuit. Both combinatorial and sequential circuits
(q, a, x) Q VT VT* ,
are called logic circuits.
(q, ) q
A sequential circuit is formally defined as a quintuplet
Behavior of an automaton: The automaton A switches
C Z , I , Y , , such that:
from a state to another, as it recognizes each input final
symbol from the input stream of the word to be Z denotes the set of states encoded in a set of latches;
recognized. I refers to the set of input boolean variables; it can be
regarded as a register containing the input value;
Y denotes a set of circuit output values;
is the transition function which determines circuit Unfortunately, this practice is not use, because the world
behavior; i.e. a combinatorial function which of the finite-state machines (theory of the languages) and
determines the circuit next state from the input that of sequential circuits (computers architecture) cohabit
variables and the latches output values. The transition while being unaware of.
function can incorporate a component called input-
function, devoted to filtering input values; Since sequential circuit designers are unwilling to use the
denotes the output function which uses the inputs languages theory powerful tools in order to simplify their
variables and the latches outputs to determine the finite-state machines, therefore pending sequential
output value of the sequential circuit. circuits, a solution would be to let them design their
sequential circuits, then to provide them with a method to
3 PROBLEM PRESENTATION calculate the associated minimal automaton. The interest
of this approach is obvious: the reduction of sequential
It is established that any sequential circuit is the circuit complexity, by exploiting the simplification
implementation of a finite state automaton [1] [3] [4] [11] potential offered by the minimal finite-state automata.
[14] [17] [18] [19] [22] and that all the equivalent finite- However, there is no procedure to calculate the minimal
state automata admit one and only one minimal finite- finite-state automaton associated with a sequential circuit;
state automaton [4] [5] [6] [7] [13] [20] [22] [29]. This so it is the aim of this contribution to provide such a
automaton is minimal in term of possible states and procedure. Once a sequential circuit designed or specified,
transitions [12] [13]. This implies that any sequential our method consists in disassembling this circuit in order
circuit admits a unique minimal finite-state automaton. to deduce an associated finite-state machine, then to
calculate the single minimal automaton associated with
Finite state machines can be represented graphically for this circuits.
an efficient visualization or design. Then, the
visualization can be converted in a simulator using
hardware description languages. So, the designer requires 4 MINIMAL FINITE AUTOMATON ASSOCIATED
a tool to convert the visualized design to hardware
WITH A SEQUENTIAL CIRCUIT
description language code in order to simulate and
implement it. Procedures to covert state diagrams to Let C Z , I , Y , , denote a sequential circuit. We
hardware description language code are addressed by need to deduce from C , a related finite-state automaton
many references [1] [3] [8] [30] [9] [10] [19] [23] [25]
[26] [30]. AC VT , Q, q0 , F , , from which we can calculate
the single minimal finite-state automaton AC [ ]
Most circuit conception platforms represent finite state
machines graphically for efficient visualization and associated with C . Reconstituting the minimal finite-state
design; this visualization in then converted in a simulator machine AC [ ] from the sequential circuit C amounts
using hardware description languages, using appropriate previously to deduce from the
tools. The procedure is addressed by many existing tools
quintuplet Z , I , Y , , a finite automaton
[15] [23] [26] [30]. ,
AC VT , Q, q0 , F , implemented as C. Once the
Despite implementing a sequential circuit from its finite- finite-state automatonAC is available, the next step will
state automaton, it is better to substitute this one by the
associated minimal finite-state automaton; because the consist in applying to AC the adequate algorithm in
latter offers a minimal number of states and transitions, order to calculate its unique minimal automaton, which is
and the language theory guarantees that it is equivalent to to be the minimal automaton AC [ ] of the sequential
the automaton of departure [12] [13], since they recognize
both the same regular language. From then on, the circuit C . It is the purpose of this section to show how
sequential circuit can be implemented from the minimal AC and AC [ ] can be computed, provided C .
automaton, with a minimal complexity.
First, we propose an algorithm to disassemble a
But, given a sequential circuit, how can we compute its
combinatorial circuit, in order to rebuild its unique
related minimal finite-state automaton? Ideally to do so,
disjunctive canonical function. Second, using this
prior to conceive a sequential circuit, one must initially
algorithm, we propose another algorithm to calculate a
design the associated finite-state machine, then calculates
finite-state automaton associated with a sequential circuit.
its related minimal automaton, and finally implements
Third, we propose a version of the minimal automaton
this last as a sequential circuit using a well-known
algorithm adapted to the case of sequential circuit.
procedures [1] [3] [4] [8] [9] [10] [17] [18] [19] [22].
1. Remove from ES ;
2. Transform using AND, OR and NOT
n
Illustrative example: Let A, B, C be 3 Boolean variables
operators, such that: i , where
i 1 and S a logic function such that:
i is a function or a monomial, and n is S A (B C) C
the number of i ;
Our aim is to find the canonical form of S using the
3. Insert each i in ES . Naturally, duplicates above procedures 1 and 2. With procedure 1, we recognize
are removed from ES . that C , the last term of S , is already a monomial. So, at
the thirst step of procedure 1 we have:
The transformations suggested in step 2 can be made ES {A ( B C ), C} . The following are the next
using the same rules as those of logical equation
steps of procedure 1 to transform the function
simplification, in particular Morgan's laws [4] [14] [17]
[24]. Procedure 1 ends, because any function can be A ( B C ) in a disjunction of monomials:
decomposed using only AND, OR and NOT operators. At
the end of procedure 1, the set ES consists of k ' ES { A ( B C ), C} { AB C ), C}
monomials i such that: { A( BC BC ), C}
ES {1 , 2 ,..., k ' }
k' (1)
{ A( BC ( BC ), C} { A( B C B C ), C}
S
i 1
i
{ A( B C B C ), C}
A BC BC , C
Let us note that the equality (1) was obtained by replacing
every function i by its disjunctive form. The next step ABC ABC , C ABC , ABC , C
consists in normalizing S using the following procedure
2. Three monomials were obtained: ( ABC , ABC , C ), two
Procedure 2: Calculation of the normal disjunctive form of which are canonical ( ABC , ABC ). It thus remains to
of a combinatorial function transform the monomial C into a set of canonical
Let VS {v1 , v2 ,..., v j } be the set of j Boolean monomials. To do so, we apply procedure 2, introducing
successively the variables A and B :
variables constituting ES monomials.
C AC AC ABC ABC ABC ABC
While ( ES / is not a canonical monomial)
do
So, we add the four monomials sequential circuit is reduced to the outputs of the flip-flops
( ABC , ABC , ABC , ABC ) to ES : encoding the sequential circuit states; because, as well as
the input function, the output function is not taken into
ES ABC , ABC , ABC , ABC , ABC account in reducing a sequential circuit transition
function.
We can now deduce the canonical form of S :
S ABC ABC ABC ABC ABC .
Each boolean function i operates on a couple of vectors E Si applying the previous procedures 1 and 2, in
order to disassemble the transition function i and
(Q , I ) such that (see fig. 1): Q (q1 , q2 ,..., qn ) is the
to build its canonical monomials merging all the
vector of the output of the n latches encoding each
variables of Q and I . For each latch Li , we get:
sequential circuit state; and I (i1 , i2 ,..., im ) is the vector
of m circuit input variables. In the following, we suppose
that Q , which means that the output function of the
Si
E M , M ,...M
1 2 ki prefixes; that is, the vectors of the input variables, and
S E , the set of suffixes of the canonical monomials ( the
and
4.2.4 Determination of the final state set F monomial set of a latch Li ), then monomial aq sets latch
In principle in sequential circuits, each state eventually Li to 1; elsewhere is sets Li to 0. Gathering the values set
produces an output value, because these circuits are
seldom used to implement sequences or word recognition by aq on each latch, we obtain a vector of bits which
automats. In this case we can consider that: F Q . corresponds to the code of the state q ' successor of state
However, a sequential circuit can be associated with a q with input data a . That is:
special output function , proceeding with input (q, a ) q ' (q, a ) q '.
variables and the output of the flip-flops. This necessitates
In fact, q ' corresponds to the right part of the truth table
disassembling to obtain E a set of canonical
for the line of the monomial aq . The following algorithm
monomials from which to deduce F: formalizes that process.
F q Q / v I , vq E Procedure 6: Determine the initial state
Vector q ;
In the following, without losing the generality, we assume
that F Q . ; // Empty set
For-all aq E do:
4.2.5 Determination of transition function For-all (i 1 n ) do:
In this section, we focus on , the fifth element of the If aq E Si
finite-state automaton quintuplet :
AC VT , Q, q0 , F , , associated with the sequential Then q[i ] 1;
circuit C Z , I , Y , , . Else q[i ] 0;
Insert ( a , q , q ) in .
We have to calculate from the sequential circuit
transition function; that is, we must determine the set of 4.2.6 Minimal finite automaton associated with a
triplets: (a, q, q ') VT Q Q / (q, a) q '; which sequential circuit
means: ( q, a) q '. In other words, if the circuit is in At this level, we assume that the finite automaton obtained
the state q and it receives as input the data a , then it in the preceding step is deterministic. If this is not the
switches into the state q ' . case, it is appropriate to apply known algorithms to make
it deterministic [11] [20] [21] [22].
At this step, we assume that, using above procedure 3,
The algorithm for computing a minimal finite automaton
the sequential circuit transition function has been already
associated with a deterministic finite automaton is well
decomposed in set of canonical monomials E . We know known in the literature [5] [6] [20] [21] [27] [28] [29]. We
that each of these monomials consists in the conjunction have adapted this algorithm to the specific case of a
of an element of VT (let us denote it a ) and an element of sequential circuit. But let us first present some theoretical
rudiments.
Q (let us denote it q ). Every canonical monomial
aq I Q (c.f. procedure 4) imposes on the circuit a 1. Let A VT , Q, q0 , F , be a determinist finite-
new transition, that is to say a new state q ' . We thus state automaton. We call family of the words
have for each canonical monomial two elements ( a and recognized from state q Q , the set Lq such that:
q ) of the triplet (a, q, q ') . We must now determine the Lq x VT* / ( q, x ) F .
third element: q ' . To do so, we must determine the state
In fact, this is the set of words recognized by the (q, q ') X 2 / a VT , (q, a) (q ', a)
automaton: Aq VT , Q, q, F , , q Q. q X //remove q from X Insert X ' in
q X ' //insert q into X'
2. Let A VT , Q, q0 , F , be a determinist finite- Qi 1 .
state automaton. We call equivalence or congruence 3. Repeat (2) until the sequence is stationed at a term k
of Nerode [13] [20], the relation defined by: such that : Qk 1 Qk .
(q, q ') Q 2 , ( q) q ' Lq Lq ' . 4. If k is the term at which the sequence (2) is
stationary then Qk is the Nerode partition, of which
The relation is an equivalence relation on Q , whose Q[ ] is the quotient set [13] [20].
equivalence classes are denoted by Q[ ] . For any To build Q[ ] from Qk , we keep one state q[ ] from
state q Q , we denote [ q ] , the equivalence class of each equivalence class [ q ] and suppress all the
q for the relation . We denote q q '[ ] to signify that others states of [ q ] . This state is the quotient of
q is equivalent to q ' modulo . that class. This is to say :
Q[ ] q[ ] Q / q[ ] [ q ] .
The equivalence of Nerode makes it possible in fact to
determine groups (classes) of states, as in each group, the q0[ ] is the quotient the of class of q0 .
automata Aq associated with the states q Q recognize F[ ] is the set of quotient of the final state classes:
the same language Lq . In other words, two states are F[ ] q[ ] F / q[ ] [ q ] .
equivalent, if the sequences recognized from one are the
same as those recognized from the other. That is to say, The transition function [ ] is constructed by
formally: removing all the states and transitions from
2
(q, q ') Q , q q '[ ] except quotient of classes, as
( q, q ' , a ) Q 2 VT , [ ] (q[ ] , a) q[' ]
x VT* , (q, x) (q ', x).
follows: (q , x ) q ' .
Procedure 7: Determine the minimal finite automaton
associated with a sequential circuit Comments: The calculation of the automaton is carried
Let AC VT , Q, q0 , F , denote a determinist finite- out in two steps. The first one consists in building the
state automaton calculated from sequential circuit classes of equivalence Qk , where k is the term at which
C Z , I , Y , , using the above procedures 3 to 6. the sequence 3-4 is stationary, and then in deducing
The minimal finite-state automaton Q[ ] . To do so:
AC [ ] VT , Q[ ] , q0[ ] , F[ ] , [ ] , associated with We start Q1 with two classes: F and M Q F .
C , is processed as follows: Note that often M Q F in sequential circuits, in
Q[ ] denoting the quotient set of the equivalence
which case: M Q F .
classes of the relation on Q , is calculated as
follows: To obtain Qi 1 , we proceed in a refinement of each
1. Q1 F , Q F ; // Even if we assume that of the equivalence classes of Qi : if two states of the
VT I , I AC I , I T , q1 , q2 , q3 , q4 , q5 , q1 ,
Q {Q1Q2Q3 , Q1Q2Q3 , Q1Q2Q3 , q1 , q2 , q3 , q4 , q5 ,
with given by the above table.
Q1Q2Q3 , Q1Q2 Q3 }
For sake of simplicity, we rename Q elements:
3. Minimal finite-state automaton AC [ ] associated with
Q q1 , q2 , q3 , q4 , q5
C using procedure 7:
Determining the initial state q0 with procedure 5. Determining the partition of Nerode: lets calculate
According to figure 3, the initial configuration of the the sequence (Q ) .
3 latches is (RESET, RESET, SET); which gives Q1 {q1 , q2 , q3 , q4 , q5 }
vector (001) which is the code of state Q1Q2Q3 ,
Q2 {q1},{q2 , q3 , q4 , q5 }
renamed as q1 . Definitely, q1 is the initial state of
our finite-state automaton AC .
Q3 {q1},{q2 , q3},{q4 , q5 }
Determining the set of final states F . Since we have Q4 {q1},{q2 , q3 },{q4 , q5 }
no precision on the nature of the automaton, we The sequence (Q ) is stationary at step 3, so: Qk Q3 .
abstract the set of final states: F Q.
Determining Q[ ] the state set of AC [ ] : the quotient
Calculation of the finite-state automaton transition
function applying procedure 6: set of Q3 is q1 , q2 , q4 . Therefore:
Q[ ] q1 , q2 , q4
Determining q0[ ] the initial state of AC [ ] : q1 the
initial state of AC is a singleton in its class, so:
Table 1: Transition function
q0[ ] q1 .
I Determining F[ ] the set state of final states of
Q \ VT I
Q1Q2Q3 Q1Q2Q3 Q1Q2Q3 AC [ ] : since F Q according to our assumption,
[15] KAESLIN H.: Digital integrated circuits design, [27] WATSON B. W., DACIUK J.: An efficient DFA
from VLSI architectures to CMOS fabrication, minimization algorithm, Natural Language
Cambridge University Press, Engineering, pages 4964, 2003.
http://books.google.ga/books?id=gdRStcYgf2oC&pg [28] WEATHERSPOON H.: State and Finite State
=PA787&dq=medvedev+fsm&hl=fr#v=onepage&q= Machines, CS 3410, Spring 2013, Computer Science,
medvedev%20fsm&f=false Cornell University
[16] MEALY G.H.: A method for synthesizing sequential [29] WRIGHT D.R. : Finite State Machines, CSC216,
circuits, The Bell System Technical Journal, 34, 5, (Summer 2005),
pp. 1045-1079, September 1955. http://www4.ncsu.edu/~drwrigh3/docs/courses/csc21
[17] MIT Open Course Ware: Introduction to Electrical 6/fsm-notes.pdf
Engineering and Computer Science, chap 4, April [30] ZIMMER P.: Fizzim an open-source fsm design
25, 2011, 6.01SC, environment, 2015, Available:
https://www.google.fr/url?sa=t&rct=j&q=&esrc=s&s http://www.fizzim.com/
ource=web&cd=13&ved=0ahUKEwi4t8u9habRAhXI
NhoKHTC0CZM4ChAWCCQwAg&url=https%3A AUTHOR
%2F%2Focw.mit.edu%2Fcourses%2Felectrical- Born in 1958 in Gabon, Pierre MOUKELI
engineering-and-computer-science%2F6-01sc- MBINDZOUKOU received a doctorate in
introduction-to-electrical-engineering-and-computer- computer science in 1992 from Claude
science-i-spring-2011%2Funit-1-software- Bernard University, Lyon France. From
engineering%2Fstate- 1988 to 1992, he was a researcher-student
machines%2FMIT6_01SCS11_chap04.pdf&usg=AF member of LIP (Laboratoire de
QjCNFIgVLi1nzzhRGo-QcR-D8YG4pxTQ&cad=rja lInformatique du Paralllisme) at ENS-Lyon (Ecole
[18] MOORE E. F.: Gedanken-experiments on sequential Normale Suprieure de Lyon). Back to Gabon, he joined
machines, pp 129-153 in Shannon and McCarthy the African Institute of Computer Science (IAI), an inter-
(eds.), Automata Studies, Annals of Mathematics African engineer-degree school, where he is teacher and a
Studies, Number 34, Princeton University Press, researcher at the LAIMA (Laboratoire Africain
1956. dInformatique et de Mathmatiques Appliques IAI).
[19] PATT Y. N., PATEL S. J.: Introduction to He is also a teacher at INPTIC (National Institute of Post
Computing Systems, from bits and gates to C and and Information and Communication Technologies) at
beyond, McGraw Hill International Editions, 2001 Libreville Gabon. Since 2009, Pierre MOUKELI is
[20] PERRIN D.: Finite automata, in J. van Leeuwen, Adviser in Computer Science of the President of the
editor, Handbook of Theoretical Computer Science, Republic of Gabon; and since January 2017, he helds these
volume B, chapter 1, pages 157. Elsevier, 1990 positions with the post of Director of Education of the
[21] STERN J.: Fondements mathmatiques de African Institute of Computer Science (IAI). Among other
linformatique, McGraw-Hill, 1990. activities, he is a consultant and auditor with public and
[22] STRAUBING H.: Finite Automata, Formal Logic private Gabonese companies. His research topics include
and Circuits Complexity, Progress in theoretical parallel computing, operating system, language theory,
computer science. Birkhauser, 1994. document processing and e-Government.
[23] TCHOUMATCHENKO V. P.: Web Based Tool for
State Machines Design, ANNUAL JOURNAL OF
ELECTRONICS, 2015, ISSN 1314-0078, PP 69-71
[24] TEMAN O.: Architecture des Ordinateurs,
http://pages.saclay.inria.fr/olivier.temam/teaching/x/t
exts/text_01_05.pdf
[25] UMA R.: Qualitative Analysis of Hardware
Description Languages: VHDL and Verilog (IJCSIS)
International Journal of Computer Science and
Information Security, Vol. 9, No. 4, pp-127-135,
April 2011.
[26] UMA R., DHAVACHELVAN P.: Synthesis
optimization for finite state machine design in
FPGAS, International Journal of VLSI design &
Communication Systems (VLSICS) Vol.3, No.6,
December 2012, DOI : 10.5121/vlsic.2012.3607 79