Special Subject Book January 2000

Thermal Resistance
Theory and Practice

http://www.infineon.com

SMD Packages

Never stop thinking

Edition January 2000
Published by
Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 Mnchen
Infineon Technologies AG 1999
All Rights Reserved.

Attention please!
The information herein is given to describe
certain components and shall not be
considered as warranted characteristics.
Terms of delivery and rights to technical
change reserved.
We hereby disclaim any and all warranties,
including but not limited to warranties of
non-infringement, regarding circuits,
descriptions and charts stated herein.
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manufacturer.

Information
For further information on technology,
delivery terms and conditions and prices
please contact your nearest Infineon
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Infineon Technologies Representatives
worldwide (see address list).

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Due to technical requirements components
may contain dangerous substances.
For information on the types in question
please contact your nearest Infineon
Technologies Office.
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of Infineon Technologies, if a failure of such
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body, or to support and/or maintain and
sustain and/or protect human life. If they
fail, it is reasonable to assume that the
health of the user or other persons may be
endangered.
Thermal Resistance - Theory and Practice

Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

SMD-Package Properties for Power Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Using a Printed Circuit Board as a Heat Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Static Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Dynamic Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Finite Element Method (FEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Determining the Static Heat Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Measuring the Rthj-a in the Real Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Determining the Dynamic Heat Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Package and Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Michael Lenz
Gnther Striedl
Ulrich Frhler

Infineon Technologies AG 3
 Thermal Resistance - Theory and Practice

Introduction
Power-SMD applications or
whats the size of the heat sink ?

More and more frequently,

modern SMD-component users
(Surface Mounted Devices) ask
the question, Whats the size of
the heat sink ?
The reason: The trend from
through-hole packages to
low-cost SMD-applications is
marked by the improvement of
chip technologies.
Silicon instead of heat sink is
therefore possible in many cases.
The printed circuit board (PCB)
itself becomes the heat sink. As
many applications today use
PCBs assembled with SMD-
technology, the emphasis is on
Power-ICs in SMD packages
mounted on single-sided PCBs
laminated on one side.
Pricing pressure demands simple
processes and lowest-cost
solutions. This report describes a
solution.

4 Infineon Technologies AG
 SMD-Package Properties for
Power Applications
There are two basic groups of
packages:
Heat Sink packages are the first
group.The heat sink (chip carrier -
lead frame) is soldered directly to
the PCB. The thermal resistance
of this packages between chip
and heat sink is called Rthj-c
(junction-case) and has low
values.
Thermal Enhanced Leadframes
constitute the second group of
packages. Metal bridges are
connected between the chip
carrier (lead frame) and the pins.
From the outside, this package
looks identical to standard
components because the plastic
molding compound conceals
these details. Figure 1 shows
both types of packages with the
examples P-TO252-3-1 (D-Pack)
and P-DSO-14-4 (3 center pins
each per side of the cooling path).
The internal structure is described
in more detail in this report and
can be seen in Figure 11.

Footprint / Dimensions
5.8 Package e A L B
P-DSO-14-4 1.27 5.69 1.31 0.65
L
6.4
10.6

2.2

1.2
B

5.76 A
+0.15
6.5 -0.10
2.3 +0.05
-0.10
A 0.35 x 45
1.75 max.

5.4 0.1 B 0.9 +0.08

1.45 -0.2

-0.04
4 -0.2 1)
0.19 +0.06
1 0.1

0.2 -0.1
0.8 0.15
(4.17)
6.22 -0.2

8 max.
9.9 0.5

1.27
0.51 min

0.1 0.4 +0.8

0.35 +0.15 2)
0.2 14x
0.15 max 0...0.15 6 0.2
per side 3x
0.75 0.1 0.5 +0.08
-0.04 14 8
2.28 10.1
4.57
0.25 M A B 0.1 1 7
8.75 -0.21)
All metal surfaces thin plated,
except area of cut. Index Marking

P-TO252-3-1 P-DSO-14-4
Dimensions in mm

Figure 1 Heat Sink - vs. Thermal Enhanced Package Types

Infineon Technologies AG 5
 Thermal Resistance - Theory and Practice

Using a printed circuit board

Package Heat Sink / Pin
as a heat sink ?
How do I calculate that ? P-DSO-8-1
How big does my heat sink P-DSO-14-4 Pin 3-5; 10-12
need to be ? P-DSO-16-1
Which size do we need ?
P-DSO-20-1
In earlier fabrications, a solid heat P-DSO-20-6 Pin 4-7; 14-17
sink was either screwed or P-DSO-24-3 Pin 5-8; 17-20
clamped to the power package. It P-DSO-28-6 Pin 6-9; 20-23
was easy to calculate the thermal
P-DSO-20-10 Tab
resistance from the geometry of
the heat sink. P-DSO-36-10 Tab
In SMD-technology, this SCT-595-5-1 Pin 2; 5
calculation is much more difficult SOT-223-4-2 Tab or Pin 4
because the heat path must be
P-TO252-3-1 (D-Pack) Tab
evaluated: chip (junction) - lead
P-TO263-5-1 Tab
frame - case or pin - footprint -
PCB materials (basic material,
Table 1 The Most Important
thickness of the laminate) - PCB SMD-Packages
volume - surroundings.
As the layout of the PCB is a main
contributor to the result, a new
technique must be applied. The
Appendix proivdes thermal data for
all packages listed in Table 1.

Let us start with some

theoretical considerations:

Static Properties

To facilitate discussion of the

static properties of a Power IC
(PIC), the internal structure of a
PIC and its method of mounting
on a PCB or heat sink is
illustrated in Figure 2. The PIC
consists of a chip mounted on a
chip carrier or lead frame, and
held by solder or bonding
adhesive. The lead frame consists
of a high-conductivity material
such as copper, and can have a

6 Infineon Technologies AG
 thickness of several millimeters.
The associated static equivalent
circuit is shown in Figure 3. The
following analogies with electrical
Molding compound quantities have been used:
(Molding)
C The power dissipation PV
Chip (Die)
occurring close to the chip
Chip adhesive / Lot surface is symbolized by a
(Die bond)
current source.
Chip carrier
(Leadframe)
Solder
C The thermal resistances are
represented by ohmic
Heat sink or PCB resistors. The resistance
(Heat sink) network is essentially a serial
connection to the ambient
temperature. As a first
approximation, the parallel-
connected thermal resistance
of the molding (broken lines)
can be neglected in power
Figure 2 Internal Structure of packages.
a PIC and Method of
Mounting on C The ambient temperature is
a Heat Sink represented by a voltage
source.
In accordance with the analogy,
the thermal current PV = Q/t can
now be calculated from the
thermic Ohms law
V = I R as Tj - Ta = PV Rthj-a.
Rth
Molding For the purpose of discussing the
Rth Rth Rth Rth Rth application as a whole, the
function PV = (Ta) is of practical
Die Die Lead- Solder Heat
bond frame sink
interest. One obtains:
PV = - Ta / Rthj-a + Tj / Rthj-a.
PV Tj Rthj-c Tc Rth = Ta This is a descending straight line
Application
of gradient -1 / Rthj-a with its zero
at Tj.

Rthj-a

Figure 3 Static Equivalent

Circuit for the
Structure
shown in Figure 2

Infineon Technologies AG 7
 Thermal Resistance - Theory and Practice

In Figure 4, this function is

shown for the P-DSO-14-4 Pack-
age (Thermal Enhanced Power
Package) mounted on the PV

standard application board. From W

Tj 150
this function, the user can derive 1.63 PVO = = W 1.63 W
Rthj-a 92
the permissible power dissipation
directly for any ambient
Parameter: Tjmax = 150 C
temperature. At Ta = 85 C, for 1.08 Rthj-a = 92 K/W
example, the permissible PV = 1 W
Tamax = 85 C
dissipation is approxi-mately
T = 92 C
0.7 W. The exact value can be 0.54
calculated from the equation
Tamax
PV = (Tj - Tamax) / Rthj-a = Tj
65 K / 92 K/W = 0.7 W.
0 Ta
It should be noted that in the data 0 50 100 150 C
sheets of the PICs the power
dissipation is given as a function
of the package (case) tempera-
Figure 4 Permissible Power Dissipation of the
ture TC, because the application- P-DSO-14-4 Package Mounted on a
specific thermal resistances are PCB with 300 mm Cooling Area, as
not known to the manufacturer. a Function of Ambient Temperature
This function, like the previous
one, is a descending straight line.
The slope now has the value
1 / Rthj-c. The zero remains at Tj.
As an example, this function is
PV
presented in Figure 5 for the
W
P-TO252-3-1 Package.
The new P-TO252-3-1 package 30
has a thermal resistance of max.
4 K/W and is unique in the small
size of its base area when com- 20 Rthj-c = 4 K/W
pared with packages of equivalent
performance (PCB board area). At
approximately 30 C, the permis- 10
sible power dissipation is 30 W.
Higher power dissipation is
0 TC
prevented by intervention of the 0 50 100 150 C
chip-internal current limiters. For
this reason, the value for power
dissipation at lower temperatures
remains constant. Figure 5 Permissible Power Dissipation of
the P-TO252-3-1 as a Function of
the Package (Case) Temperature

8 Infineon Technologies AG
Dynamic Properties
As mentioned earlier, the thermal
behavior of PICs changes when
dynamic phenomena are
considered (pulse power
operation). This behavior can be
described in terms of thermal
capacity Cth, which is directly
proportional to the relevant
volume V (in cm), to the density
(in g/cm) of the material and to
a proportionality factor of the
specific heat c in Ws/g K.
The applicable equation is:
Cth = c V = m c
This means: The thermal capacity
of a body of mass m = V
needed to heat the body by 1 C.
To calculate the temperature
change T it is necessary to use
the quantity-of-charge equation
for a capacitance C.
The equation is:
VC=It=Q
By analogy, the quantity-of-heat
equation is:
T Cth = P t = Q
This means: Just as the current
I = Q/t represents a transport of
charge per unit of time, the
power dissipation P represents
the transport of thermal energy
per unit of time. Consequently:
T = P t
Cth
The equivalent circuit of the
P-TO263-7-3 power package, with
the thermal capacities added, is
shown in Figure 6. The thermal
capacities calculated from the
material and the volume are
shown in parallel with the thermal
resistances.
When calculating the components
of a network it is necessary to
know the thickness d, the cross-
sectional area A and the thermal
conductivity L in W/m K, in order
to obtain the appropriate thermal
resistance Rth. The formula is:
d K
Rth =
LA []
W

corresponds to the quantity of heat

Die Heat sink

RthD RthHS

0.48 K/W 0.24 K/W

PV CthD 3 mWs/K CthHS 300 mWs/K = Tcase

D = 1.5 ms HS = 70 ms

Figure 6 Thermal Equivalent

Circuit of the
P-TO263-7-3 Package
(Simplified)

Infineon Technologies AG 9
 Thermal Resistance - Theory and Practice

10 0.2 4.4 Footprint

9.8 0.15 1.270.1
8.5 1) 0.1
1 0.3

0.05
B

0.47
A

8.42
10.8

0.8
2.4
1.3 0.3
8 1)
9.25 0.2
(15)

9.4 4.6
2.7 0.3
4.7 0.5

16.15

0...0.15
7x0.6 0.1 0.1 1)
Typical
0.5 0.1
6x1.27 All metal surfaces tin plated, except area of cut.
0.25 M A B
8 max.

Figure 7 Outline Drawing of the P-TO263-7-3 Power Package

To calculate the thermal capacity The thermal capacity Cth is Table 2 lists all the important
Cth, it is necessary to know the calculated from: parametric data of the
volume V = d A, the specific Cth = m c (Ws/T). P-TO263-7-3 package.
weight in g/cm3 and the speci- The package dimensions are
fic thermal capacity c in Ws/g K. shown in Figure 7.

Parameters for the Chip Symbol Value Dimension

Area AD 5 mm
Thickness dD 360 m
Thermal conductivity of silicon LSi 150 W/m K
Thermal resistance of chip RthD 0.48 K/W
Specific weight of silicon Si 2.33 g/cm
Mass of chip mD 4.2 mg
Spec, thermal capacity of Si cSi approx. 0.7 Ws/g K
Thermal capacity of chip CthD approx. 3 mWs/K
Thermal time constant of chip D approx. 1.5 ms
Parameters for the Heat Slug Symbol Value Dimension
Area (effective area of 64 mm) AHS 14 mm
Thickness dHS 1.27 mm
Thermal conductivity of cooper LCu 384 W/m K
Thermal resistance of heat slug RthHS 0.24 K/W
Specific weight of cooper Cu 8.93 g/cm
Mass of heat slug mHS 0.8 g
Spec, thermal capacity of Cu cCu 0.385 Ws/g K
Thermal capacity of heat slug CthHS 310 mWs/K
Thermal time constant of heat slug HS 70 ms

Table 2 Parametric Data of the P-TO263-7-3

10 Infineon Technologies AG
The die bond and molding
components have been omitted
from this discussion because they
do not significantly influence the
calculation of Rthj-c.
For reference, these data are
listed here:
C RthDB = 0.01 to 0.1 K/W;
C CthDB = 0.1 to 0.5 mWs/K;
C DB = 1 to 50 ms;
C RthM = 100 K/W;
C CthM = 0.64 Ws/K and
C M = 64 s.
(Die Bond = index: DB;
molding = index: M)
PV
tp
Tj
Tmin
Figure 8 Chip Temperature Tj
vs. Time, for Periodic
Pulse Operation
The time constance of the die
bond is smaller than that of the
chip by two orders of magnitude
and can, thus, be neglected.
The thermal resistance RthM of
the molding is even three orders
of magnitude bigger than that of
the chip and that of the heat slug,
and, being in parallel, can be
neglected also.
Pulse operation and the associat-
ed chip temperature responses
also deserve examination.
In accordance with the analogy to
electrical systems, the chip tem-
perature response can be viewed
like a voltage increase across an
T
Tmax
Tavg
RC section which is being fed by
a current pulse generator.
The following relationship applies:
V(t) = R I (1 - et/R C)
and for the increase in tempera-
ture:
T(t) = Rth P (1 - et/R C )
th th
This heating-up and cooling-down
process is presented qualitatively
in Figure 8 (valid for tp >> 2 ms
only).
The chip temperature goes up
and down between Tmin and Tmax.
The variation depends on the
magnitude of the power pulse
and its duty cycle.
t
t
Infineon Technologies AG 11
 Thermal Resistance - Theory and Practice

This junction temperature medium-power package

transients can be represented in P-DSO-14-4 for three different
the form of a function if the cooling areas on the PCB.
dynamic thermal impedance This function clearly shows the
Zth = (Tmax - Tmin) / PV regions of dominance of the
is shown versus pulse width tp for various time constants of the
different duty cycles (duty cycle = chip, the lead frame, and the
DC = tp/T) (Figure 9). PCB.
A special case of this representa- The chip time constant tD lies in
tion is the dynamic thermal the millisecond range, whereas
impedance in single-pulse the lead frame dominates in the
operation (DC = 0). Figure 10 range of several 100 ms and the
shows the thermal impedance in PCB in the 100-second range.
single-pulse operation for the

10 0 120

K/W K/W
Zthj-c Zthj-a Footprint
100

10 -1

80
300 mm 2
D=
-2 0.50
10 60
0.20 600 mm 2
0.10
0.05
0.02 40
-3 single pulse 0.01
10

20

10 -4 0 -3 -2
10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 s 10 0 10 10 10-1 100 101 102 s 103
tp tp

Figure 9 Dynamic Thermal Figure 10 Thermal Impedance of the

Impedance Zthj-c of a P-DSO-14-4 Package for
P-TO263-7-3 Package Single-Pulse Operation

12 Infineon Technologies AG
 Finite Element Method (FEM)
The steps of the Finite Element
Method (FEM) are explained
below and one example is
provided per group.
P-TO252-3-1
Figure 11 FEM Model of Heat Sink and
Thermal Enhanced Package
The geometric data of the
package is entered into the FEM
model to calculate the thermal
resistance. This avoids time-
consuming measurements.
Figure 11 shows an implemented
model.
P-DSO-14-4
Infineon Technologies AG 13
 Thermal Resistance - Theory and Practice

The temperatures of the

individual components (chip, die-
pad, molding compound, and
leadframe) can be viewed
individually or in combination
(Figure 12).

Chip with two active areas (dice only) Mold compound without cooling P-TO252-3-1 without mold compound
tab,chip and lead frame with PV = 3 W for determining the Rthj-c

Chip and lead frame of the Lead frame of the SCT595-5-1 on a SOT223-4-2 on a PCB with 6 cm
SOT223-4-2 package on a PCB PCB with heat sink heat sink; Rthj-a ~ 70 K/W is calculated
with heat sink at PV = 0.5 W

Figure 12 FEM Analysis Possibilities

14 Infineon Technologies AG
 Three different PCBs have been
created for each package model.
They differ in the size of the
copper laminated area A (heat
sink) which is linked to the heat
dissipating parts of the case (die-
pad in the P-TO252-3-1 or center
pins in the P-DSO-14) (Figure 13).

P-DSO-14-4 P-DSO-14-4 P-DSO-14-4

-16-1
1 0.375 2 3
6 cm 3 cm 0.375 Footprint only
a/2
a/2
0.67
a

1 1 1

Application-Board for Rth Measurement Rth-P-DSO-14-4 LP 1.0

P-TO252-3-1 P-TO252-3-1 P-TO252-3-1

a
1 2 3
6 cm 3 cm a Footprint only

a/2 a/2

I Q I Q I Q
1 1 1

Application-Board for Rth Measurement Rth-P-TO252-3-1 LP 1.1

Figure 13 PCB-Layout for FEM-Simulation

P-DSO-14-4 and P-TO252-3-1

Infineon Technologies AG 15
 Thermal Resistance - Theory and Practice

Determining the Static Heat
Resistance
The FEM simulation calculates
the thermal static resistance Rthj-a
(junction-ambient) and the Rthj-c
(junction-case) for packages with
enhanced die-pad or Rthj-pin
(junction to a defined pin) for
thermal enhanced P-DSO
packages without die-pad. This
value depends only slightly on the
active chip area. It is sufficient to
simulate just one medium-sized
chip (>2 mm).
If the static thermal resistance
Rthj-a is applied versus the PCB
heat sink area, a very important
function is obtained for the
application of the component. By
estimating the heat sink area in a
real application, the user can
easily determine the expected
Rthj-a, especially as the simulated
values are calculated in still air.
Therefore, they represent the
worst case. In real applications
the values for the heat resistance
are much lower. At an air stream
of 500 lin ft/min (linear feet per
minute) the Rthj-a of the
P-DSO-14-4 for example is up to
15 % lower (Figure 15).

P-DSO-14-4 P-TO252-3-1
120 160
K/W 112 K/W 143.9
Rthj-a Rthj-pin = 31.7 K/W Rthj-a Rthj-c = 1.8 K/W
100
92 120
90
80 100
78
70
80
60 78
60
50
54.7
40 40
0 100 200 300 400 500 mm 2 600 0 100 200 300 400 500 mm 2 600
A A

Figure 14 Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A at zero airflow

P-DSO-14-4 P-TO252-3-1
120 160
K/W Footprint only K/W
Rthj-a 110 A = 300 mm 2 Rthj-a 140
A = 600 mm 2
100 120
Footprint only
90 100
A = 300 mm 2
A = 600 mm 2
80 80

70 60

60 40
0 100 200 300 400 m/min 600 0 50 100 150 m/min 200
Airspeed Airspeed

Figure 15 Thermal Resistance Junction to Ambient Rthj-a vs.

Airspeed for the P-DSO-14-4 and P-TO252-3-1 Packages

16 Infineon Technologies AG
Measuring the Rthj-a in a
Real Application:
Using the measurement described
below the real thermal resistance
can be determined.
To determine the actual Rthj-a the
temperature difference between
chip temperature Tj and ambient
temperature Ta is required. The
Tj - Ta
equation Rthj-a = applies.
PV
The power loss PV and the ambient
temperature Ta can be determined
easily in a temperature chamber or
calculated.
To measure the chip temperature
(Tj) requires a little trick:
A temperature sensor is required
on the chip which can also be read
during operation. In many products
a substrate diode can be used at
an output (Status, Reset, etc.) to
measure the chip temperature.
To do this, the forward voltage VF
of the diode is measured at load
independent current as a
calibration curve. Due to the
characteristic temperature behavior
of the forward voltage - it has a
negative temperature coefficient of
approx. -2 mV/K - the relevant chip
temperature can be determined.
The calibration curve is measured
in the temperature chamber with
airflow. The power loss should be
kept as low as possible to ensure
the chip temperature remains
equal to the ambient temperature.
For the voltage regulator
TLE 4269 GM (P-DSO-14-4 Package)
a calibration curve (measured at
the diode at the reset output, pin 7).
RO is illustrated in Figure 16.
Figure 17 shows the
corresponding measuring circuit.

700
mV
VF 600
500

400

300

200

100

0
0 50 100 C 150
T

Figure 16 Calibration Curve TLE 4269 GM for IRO = -500 A

(current drawn from Pin 7; RO)

Infineon Technologies AG 17
 Thermal Resistance - Theory and Practice

The Rthj-a of any application can be forward voltage VF of the diode.

determined by measuring the
forward voltage of an output with
substrate diode during operation
(Figure 17).
When the switch S1 is closed and
the output voltage VQ = 5 V, the
output current is 5 A.
35
The power loss PV = (VI - VQ) IQ
in the chip of the voltage
regulator is now 1 W. Now,
change the ambient temperature
Ta and measure the respective
The appropriate Tj for every VF
value can be read from the
calibration curve VF = (Tj).
The exact heat resistance of the
real application is calculated with
this values in the formula
Tj - Ta
Rthj-a =
PV
Parameters such as air flow can
be changed without affecting the
measuring accuracy.

TLE 4269 GM

I 13 TPower 9 Q

RPU
20 k
IF ~ 500 A
TRO 7 RO
VI = 12 V CI
10 F Substrat RF RL
diode 100 k 35
of TRO
VF ~ 0.7 V
P-DSO-14-4 VB CQ
3-5; 10-12 50 V S1 22 F
+

1. Measurement of function VF = f (Ta): 2. Measurement of thermal resistance junction to ambient Rthj-a:

S1 open; we get IQ = 0 mA S1 closed; we get IQ = VQ / RQ
and PV = VI * II ~ 0 mW and PV = (VI - VQ) * IQ ~ 1 W PV = Power losses
Ta ~ Tj Tj then can be found by measuring VF at given Ta from function VF vs. Ta Ta = Ambient temperature
then we get Rthj-a = (Ta - Tj) / 1 W Tj = Junction temperature

Figure 17 Measuring Circuit

with TLE 4269GM

18 Infineon Technologies AG
Determining the Dynamic
Heat Resistance
The FEM analysis is used also for
dynamic processes.
As described above, the dynamic
thermal impedance is defined as
the ratio of the temperature
difference T = Tj - Ta (chip tem-
perature - start temperature) after
the time tp to the power loss.
If a transient FEM simulation is
performed, it is easy to obtain the
graph Zthj-a = (tp) (dynamic
thermal impedance as a function
of the pulse width tp).
For the P-TO252-3-1 (D-Pack) and
the P-DSO-14-4 the thermal
impedances for the above-
mentioned PCB configurations are
specified (Figure 18).
The peak temperatures can be
calculated easily from these
curves:
P-TO252-3-1 (D-Pack)
3 cm heat sink
Power loss PV = 10 W
Pulse width tp = 200 ms
Ambient temperature
Ta = 85 C.
From the middle curve (Figure 18),
the Zthj-a of approximately 3.5 K/W
at tp = 200 ms gives a tempera-
ture rise T = PV x Zthj-a of 35 K
and finally a peak temperature
Tjmax of 85 C+35 C = 120 C.

P-DSO-14-4 P-TO252-3-1
120 160
K/W K/W
Zthj-a 100 Zthj-a
Footprint 120
80 300 mm 2
600 mm 2 100
60 80
Footprint
60 300 mm 2
40 600 mm 2
40
20
20
0 -3 0 -3
10 10-2 10-1 100 101 102 s 103 10 10-2 10-1 100 101 102 s 103
tp
tp

Figure 18 Thermal Impedance

Junction to Ambient
Zthj-a vs. Single
Pulse Time tp

Infineon Technologies AG 19
 Thermal Resistance - Theory and Practice
Summary
For each case listed in Table 1,
a Package and Thermal
Information data sheet is
provided in the appendix.Each
data sheet shows the footprint
and case dimensions. The various
versions of the PCBs used for the
simulation are shown. It shows
the heat distribution diagrams and
the result diagrams of the FEM
simulation. The left side shows
the diagram of the static thermal
resistance Rthj-a depending on the
PCB heat sink area A. It includes
the related thermal resistance
Rthj-c (junction-case) or Rthj-pin.
20 Infineon Technologies AG
On the right side is the diagram
for the dynamic heat resistance
Zthj-a, with three graphs for the
various PCB heat sinks depending
on the single pulse duration tp.
This information is a valuable aid
for SMD Power applications. It is
intentionally limited to PCBs
laminated on one side because it
represents the cost optimum. For
double sided PCBs or multilayers
a simple attempt with
conductance cross sections can
be made to determine the change
in the PCB thermal resistance
(compare thermal data sheet of
P-DSO-20-10 with P-DSO-36-10 in
the appendix).
The PCBs are usually installed in
closed plastic cases. The most
favorable heat path then usually
forms at plug contacts to the
cables because a supply wire
with an adequate cross section is
ideal as a heat conductor.
The future of chip placement
requires mechatronic solutions
where the PCB can be replaced
by chip-connector-supply wire
configurations.
Package and Thermal Information

Appendix
P-DSO-8-1 22

P-DSO-14-4 23

P-DSO-16-1 24

P-DSO-20-1 25

P-DSO-20-6 26

P-DSO-24-3 27

P-DSO-28-6 28

P-DSO-20-10 29

P-DSO-36-10 30

SCT595-5-1 31

SOT223-4-2 32

P-TO252-3-1 33

P-TO263-5-1 34

Infineon Technologies AG 21
 P-DSO-8-1
Footprint/Dimensions
0.35 x 45

1.75 max.
1.45 -0.2
4 -0.21)

0.19 +0.06
0.2 -0.1
Package e A L B

8 max.
P-DSO-8-1 1.27 5.69 1.31 0.65
0.4 +0.8
L 1.27 0.1 6 0.2
0.35 +0.15 2)
0.2 8x
e 8 5
B

A
1 4
Reflow soldering 5 -0.21)
Index Marking Dimensions in mm

PC-Board Application-Boards for Rth - Measurement

P-DSO-8-1 P-DSO-8-1 P-DSO-8-1
a/2
1 2 3
6 cm 3 cm a/2 Footprint only
a

a
0.375

0.375
0.67

0.67

1 1 1

FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn
A = 600 mm; a = 17.32 mm A = 300 mm; a = 12.247 mm Footprint only

Finite Element Method FEM Simulation (chip area 2 mm; Pv = 0.5 W; zero airflow)

A = 600 mm; Ta = 298 K; Tmax = 369 K A = 300 mm; Ta = 298 K; Tmax = 380 K Footprint only; Ta = 298 K; Tmax = 390 K

Diagrams
Thermal Resistance Junction to Ambient Rthj-a vs. Thermal Impedance Junction to Ambient Zthj-a vs.
PCB Heat Sink Area A (zero airflow) Single Pulse Time tp (zero airflow)
190 200
K/W 185 Rthj-pin2 = 71.8 K/W K/W
Rthj-a Zthj-a Footprint
170 160 300 mm 2
164 600 mm 2
160 140
120
150
100
140 142 80
130 60
120 40
110 20
100 0 -3
0 100 200 300 400 500 mm 2 600 10 10-2 10-1 100 101 102 s 103
A tp

22
22 Infineon Technologies
Infineon Technologies AG AG
 Package and Thermal Information
P-DSO-14-4
Footprint/Dimensions
0.35 x 45

1.75 max.
1.45 -0.2
1)

0.19 +0.06
4 -0.2

0.2 -0.1
Package e A L B

8 max.
P-DSO-14-4 1.27 5.69 1.31 0.65
1.27
L
0.1 0.4 +0.8
0.35 +0.15 2)
0.2 14x GND GND
6 0.2
14 8
e
B

A
1 7
8.75 -0.21)
Reflow soldering
Index Marking Dimensions in mm

Application-Boards for Rth - Measurement PC-Board

P-DSO-14-4 P-DSO-14-4 P-DSO-14-4
-16-1
1 0.375 2 3
6 cm 3 cm 0.375 Footprint only
a/2
a/2
0.67
a

1 1 1

FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn
A = 600 mm; a = 17.32 mm A = 300 mm; a = 12.247 mm Footprint only

FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow) Finite Element Method

A = 600 mm; Ta = 298.1 K; Tmax = 377.7 K A = 300 mm; Ta = 298 K; Tmax = 389.8 K Footprint only; Ta = 298 K; Tmax = 410.1 K

Diagrams
Thermal Resistance Junction to Ambient Rthj-a vs. Thermal Impedance Junction to Ambient Zthj-a vs.
PCB Heat Sink Area A (zero airflow) Single Pulse Time tp (zero airflow)
120 120
K/W 112 K/W
Rthj-a Rthj-pin4 = 31.7 K/W Zthj-a 100
100 Footprint
92 80 300 mm 2
90 600 mm 2
80 60
78
70
40
60
20
50
40 0 -3
0 100 200 300 400 500 mm 2 600 10 10-2 10-1 100 101 102 s 103
A tp

Infineon Technologies
Infineon Technologies AG
AG 23
23
 P-DSO-16-1
Footprint/Dimensions
0.35 x 45

1.75 max.
1.45 -0.2
4 -0.2 1)

0.19 +0.06
0.2 -0.1
Package e A L B

8 max.
P-DSO-16-1 1.27 5.69 1.31 0.65 1.27
L 0.1
0.35 +0.15 2) 0.4 +0.8
0.2 16x
6 0.2
e 16 9
B

A
1 8
10 -0.21)
Reflow soldering
Index Marking Dimensions in mm

PC-Board Application-Board for Rth - Measurement

P-DSO-14-4
-16-1
3
Footprint only

FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn

Footprint only

Finite Element Method FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow)

Footprint only; Ta = 298 K; Tmax = 419.1 K

Diagrams
Thermal Resistance Junction to Ambient Rthj-a vs. Thermal Impedance Junction to Ambient Zthj-a vs.
PCB Heat Sink Area A (zero airflow) Single Pulse Time tp (zero airflow)
130 140
121 K/W
Rthj-a K/W Rthj-pin4 = 48.2 K/W Zthj-a Footprint
110
100
100
90 80
80 60
70
40
60
50 20

40 0 -3
0 100 200 300 400 500 mm 2 600 10 10-2 10-1 100 101 102 s 103
A tp

24
24 Infineon Technologies
Infineon Technologies AG AG
Package and Thermal Information
P-DSO-20-1
0.35 x 45 Footprint/Dimensions

2.65 max.
2.45 -0.2
7.6 -0.21)

0.2 -0.1

9
0.23 +0.0
Package e A L B

8max.
P-DSO-20-1 1.27 9.73 1.67 0.65 1.27 0.4 +0.8
L 0.35 +0.15 2) 0.1 10.3 0.3
0.2 20x
20 11
e
B

A
1 12.8 1) 10
-0.2
Reflow soldering
Index Marking Dimensions in mm

Application-Board for Rth - Measurement PC-Board

P-DSO-20-1
-20-6
-24-3
3 -28-6
Footprint only

FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn

Footprint only

FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow) Finite Element Method

Footprint only; Ta = 298 K; Tmax = 407 K

Diagrams
Thermal Resistance Junction to Ambient Rthj-a vs. Thermal Impedance Junction to Ambient Zthj-a vs.
PCB Heat Sink Area A (zero airflow) Single Pulse Time tp (zero airflow)
120 120
K/W 109 Rthj-pin5 = 43.6 K/W K/W
Rthj-a Zthj-a
100 Footprint
80
90
80 60
70
40
60
20
50
40 0 -3
0 100 200 300 400 500 mm 2 600 10 10-2 10-1 100 101 102 s 103
A tp

Infineon Technologies
Infineon Technologies AG
AG 25
25
 P-DSO-20-6
Footprint/Dimensions 0.35 x 45

2.65 max.
2.45 -0.2
7.6 -0.21)

0.2 -0.1

9
0.23 +0.0
Package e A L B

8max.
P-DSO-20-6 1.27 9.73 1.67 0.65 1.27 0.4 +0.8
L 0.35 +0.15 2) 0.1 10.3 0.3
0.2 20x
GND GND
20 11
e
B

A
1 12.8 1) 10
-0.2
Reflow soldering
Index Marking Dimensions in mm

PC-Board Application-Boards for Rth - Measurement

P-DSO-20-6 P-DSO-20-6 P-DSO-20-1
-24-3 -24-3 -20-6
-28-6 -28-6 -24-3
1 a 2 3 -28-6
6 cm 0.375 3 cm 0.375 Footprint only
0.3

0.3
a/2
a/2

1 1 1

FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn
A = 600 mm; a = 17.32 mm A = 300 mm; a = 12.247 mm Footprint only

Finite Element Method FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow)

A = 600 mm; Ta = 298 K; Tmax = 372 K A = 300 mm; Ta = 298 K; Tmax = 379 K Footprint only; Ta = 298 K; Tmax = 397 K

Diagrams
Thermal Resistance Junction to Ambient Rthj-a vs. Thermal Impedance Junction to Ambient Zthj-a vs.
PCB Heat Sink Area A (zero airflow) Single Pulse Time tp (zero airflow)
110 120
K/W 100 Rthj-pin5 = 22.9 K/W K/W
Rthj-a Zthj-a
90 Footprint
81 80 300 mm 2
80 600 mm 2
60
74
70
40
60

50 20

40 0 -3
0 100 200 300 400 500 mm 2 600 10 10-2 10-1 100 101 102 s 103
A tp

26 Infineon Technologies AG
 Package and Thermal Information
P-DSO-24-3
0.35 x 45 Footprint/Dimensions

2.65 max.
2.45 -0.2
7.6 -0.21)

0.2 -0.1

+0.09
0.23
Package e A L B

8max.
P-DSO-24-3 1.27 9.73 1.67 0.65 1.27 0.4 +0.8
L 0.35 +0.15 2) 0.1 10.3 0.3
0.2 24x
GND GND
24 13
e
B

A
1 12
Reflow soldering 15.6 -0.4 1)
Index Marking Dimensions in mm

Application-Boards for Rth - Measurement PC-Board

P-DSO-20-6 P-DSO-20-6 P-DSO-20-1
-24-3 -24-3 -20-6
-28-6 -28-6 -24-3
1 a 2 3 -28-6
6 cm 0.375 3 cm 0.375 Footprint only
0.3

0.3
a/2
a/2

1 1 1

FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn
A = 600 mm; a = 17.32 mm A = 300 mm; a = 12.247 mm Footprint only

FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow) Finite Element Method

A = 600 mm; Ta = 298 K; Tmax = 358 K A = 300 mm; Ta = 298 K; Tmax = 365 K Footprint only; Ta = 298 K; Tmax = 374 K

Diagrams
Thermal Resistance Junction to Ambient Rthj-a vs. Thermal Impedance Junction to Ambient Zthj-a vs.
PCB Heat Sink Area A (zero airflow) Single Pulse Time tp (zero airflow)
80 90
K/W 76.4 K/W
75 Rthj-pin6 = 20.5 K/W
Rthj-a Zthj-a
70 70
67.4 Footprint
60 300 mm 2
65 600 mm 2
60.5 50
60
40
55
30
50 20
45 10
40 0 -3
0 100 200 300 400 500 mm 2 600 10 10-2 10-1 100 101 102 s 103
A tp

Infineon Technologies AG 27
 P-DSO-28-6
Footprint/Dimensions 0.35 x 45

2.65 max.
2.45 -0.2
7.6 -0.21)

0.2 -0.1

+0.09
0.23
Package e A L B

8max.
P-DSO-28-6 1.27 9.73 1.67 0.65 1.27 0.4 +0.8
L 0.35 +0.15 2) 0.1 10.3 0.3
0.2 28x
GND GND
28 15
e
B

A
1 14
Reflow soldering 18.1 -0.4 1)

Index Marking Dimensions in mm

PC-Board Application-Boards for Rth - Measurement

P-DSO-20-6 P-DSO-20-6 P-DSO-20-1
-24-3 -24-3 -20-6
-28-6 -28-6 -24-3
1 a 2 3 -28-6
6 cm 0.375 3 cm 0.375 Footprint only
0.3

0.3
a/2
a/2

1 1 1

FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn
A = 600 mm; a = 17.32 mm A = 300 mm; a = 12.247 mm Footprint only

Finite Element Method FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow)

A = 600 mm; Ta = 298 K; Tmax = 349 K A = 300 mm; Ta = 298 K; Tmax = 354 K Footprint only; Ta = 298 K; Tmax = 359 K

Diagrams
Thermal Resistance Junction to Ambient Rthj-a vs. Thermal Impedance Junction to Ambient Zthj-a vs.
PCB Heat Sink Area A (zero airflow) Single Pulse Time tp (zero airflow)
65 70
K/W 61.4 Rthj-pin7 = 20.1 K/W K/W
Rthj-a Zthj-a
60 Footprint
56 50 300 mm 2
600 mm 2
55 40
51
50 30

20
45
10

40 0 -3
0 100 200 300 400 500 mm 2 600 10 10-2 10-1 100 101 102 s 103
A tp

28 Infineon Technologies AG
 Package and Thermal Information
P-DSO-20-10
Footprint/Dimensions

3.5 max.
11 0.15 1)

3.25 0.1
B

0 +0.15
1.2 -0.3

-0.027
2.8

+0.0
0.25
1.3

5 3
Package e A L B
15.74 0.1
P-DSO-20-10 1.27 13.48 1.83 0.68
(Heatsink) 0.1 6.3 Heatsink
1.27
L 0.95 0.15
0.4 +0.13
0.25 M A 20x 14.2 0.3
0.25 M B GND
20 11
e
B

A
1 10
Index
Reflow soldering Marking 1 x 45
15.9 0.15 1) Dimensions in mm
A

Application-Boards for Rth - Measurement PC-Board

P-DSO-20-10 P-DSO-20-10 P-DSO-20-10

a 0.375
1 2 a 3
a/2

6 cm 3 cm Footprint only
a/2
0.375
0.3

0.3

1 1 1

FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn
A = 600 mm; a = 17.32 mm A = 300 mm; a = 12.247 mm Footprint only

FEM Simulation (chip area 2 mm; Pv = 3 W; zero airflow) Finite Element Method

A = 600 mm; Ta = 298 K; Tmax = 406 K A = 300 mm; Ta = 298 K; Tmax = 421 K Footprint only; Ta = 298 K; Tmax = 463 K

Diagrams
Thermal Resistance Junction to Ambient Rthj-a vs. Thermal Impedance Junction to Ambient Zthj-a vs.
PCB Heat Sink Area A (zero airflow) Single Pulse Time tp (zero airflow)
60 60
K/W 55 K/W
Rthj-a 55 Rthj-c = 2.4 K/W Zthj-a 50
Footprint
50 40 300mm 2
600 mm 2
45 30
41
40 20
36
35 10

30 0 -3
0 100 200 300 400 500 mm 2 600 10 10-2 10-1 100 101 102 s 103
A tp

Infineon Technologies AG 29
 P-DSO-36-10
Footprint/Dimensions 11 0.15 1)

3.5 max.
3.25 0.1
B
1.1 0.1

-0.027
0 +0.1
2.8

0.25+0.0
1.3

5 3
Package e A L B
15.74 0.1
P-DSO-36-10 0.65 13.48 1.83 0.45 (Heatsink)
0.65 0.1 6.3 Heatsink
L 0.95 0.15
0.25 +0.13
0.25 M A 36x GND
14.2 0.3
0.25 B
36 19
e
B

A 1 18
Index
Reflow soldering Marking 1 x 45
15.9 0.15 1) Dimensions in mm
A

PC-Board Application-Boards for Rth - Measurement

P-DSO-36-10 P-DSO-36-10

FR4; 47 x 50 x 1.5 mm; 70 Cu FR4; 47 x 50 x 1.5 mm; 70 Cu

A = 600 mm; 24.5 x 24.5 mm A = 300 mm; 16 x 19 mm

Finite Element Method FEM Simulation (chip area 2 mm; Pv = 3.5 W; zero airflow)

A = 600 mm; Ta = 298 K; Tmax = 398 K A = 300 mm; Ta = 298 K; Tmax = 427 K

Diagrams
Thermal Resistance Junction to Ambient Rthj-a vs. Thermal Impedance Junction to Ambient Zthj-a vs.
PCB Heat Sink Area A (zero airflow) Single Pulse Time tp (zero airflow)
60 60
K/W Rthj-c = 2 K/W K/W
Rthj-a Zthj-a 50
50
40
45
300 mm 2
40 30 600 mm 2
36.8
35
20
30
28.6 10
25
20 0 -3
0 100 200 300 400 500 mm 2 600 10 10-2 10-1 100 101 102 s 103
A tp

30
30 Infineon Technologies
Infineon Technologies AG AG
 Package and Thermal Information
SCT595-5-1
Footprint/Dimensions
2.9 0.2
1.4 B
(2.2)
1.2 +0.1
-0.05
1.1 max
(0.3) 0.1 max
A GND
+0.2
2.9
1.9

5 4
acc. to

2.6 max

1.6 0.1
DIN 6784

10max

10max
0.5 1 2 3
0.3 +0.1
-0.05 GND
0.8 0.15 +0.1
-0.06
0.6 +0.1
-0.05
0.95 0.25 M B
0.95 0.20 M A
Reflow soldering 1.9
Dimensions in mm

Application-Boards for Rth - Measurement PC-Board

SCT595 SCT595 SCT595

1 2 3
6 cm a 3 cm Footprint only
0.375 a
0.375
0.3

0.3
a/2
a/2

GND

GND
GND
INH

INH

INH
I Q I Q I Q
1 1 1

FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn
A = 600 mm; a = 17.32 mm A = 300 mm; a = 12.247 mm Footprint only

FEM Simulation (chip area 2 mm; Pv = 0.2 W; zero airflow) Finite Element Method

A = 600 mm; Ta = 298 K; Tmax = 315 K A = 300 mm; Ta = 298 K; Tmax = 318 K Footprint only; Ta = 298 K; Tmax = 334 K

Diagrams
Thermal Resistance Junction to Ambient Rthj-a vs. Thermal Impedance Junction to Ambient Zthj-a vs.
PCB Heat Sink Area A (zero airflow) Single Pulse Time tp (zero airflow)
200 200
K/W 178.7 Rthj-pin5 = 25.9 K/W K/W
Rthj-a Zthj-a
160
140 Footprint
160 300 mm 2
120 600 mm 2
140 100
80
120 60
98.5 40
100
87 20
80 0 -3
0 100 200 300 400 500 mm 2 600 10 10-2 10-1 100 101 102 s 103
A tp

Infineon Technologies
Infineon Technologies AG
AG 31
31
 SOT223-4-2
Footprint/Dimensions
6.50.2 1.6 0.1
B
3 0.1 0.1 max
3.5
B GND
4

15max
1.4

+0.2
acc. to

3.5 0.2
7 0.3
DIN 6784
1.2
4.8

0.5 min
1.1
1 2 3
1.4

0.70.1 2.3 0.280.04

4.6
Reflow soldering
0.25 M A 0.25 M B Dimensions in mm

PC-Board Application-Boards for Rth - Measurement

SOT223 SOT223 SOT223
a/2
1 2 a/2 3
6 cm 3 cm Footprint only
a

0.3 0.3

I Q GND I Q GND I Q GND

1 1 1

FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn
A = 600 mm; a = 24.49 mm A = 300 mm; a = 17.32 mm Footprint only

Finite Element Method FEM Simulation (chip area 2 mm; Pv = 0.5 W; zero airflow)

A = 600 mm; Ta = 298 K; Tmax = 332 K A = 300 mm; Ta = 298 K; Tmax = 339 K Footprint only; Ta = 298 K; Tmax = 380 K

Diagrams
Thermal Resistance Junction to Ambient Rthj-a vs. Thermal Impedance Junction to Ambient Zthj-a vs.
PCB Heat Sink Area A (zero airflow) Single Pulse Time tp (zero airflow)
180 180
K/W 164.3 K/W
Rthj-a Rthj-pin4 = 16.5 K/W Zthj-a
140
140 120 Footprint
300 mm 2
100 600 mm 2
120
80
100 60
81.2 40
80
68 20
60 0 -3
0 100 200 300 400 500 mm 2 600 10 10-2 10-1 100 101 102 s 103
A tp

32
32 Infineon Technologies
Infineon Technologies AG AG
 Package and Thermal Information
P-TO252-3-1
Footprint/Dimensions
6.5 +0.15
-0.10
2.3 +0.05
-0.10
A
5.8 5.4 0.1 B 0.9 +0.08
-0.04

1 0.1

0.8 0.15
(4.17)
6.22 -0.2
GND

9.9 0.5
6.4
10.6

2.2

0.51 min
1 3

1.2 0.15 max 0...0.15

per side 3x
0.75 0.1 0.5 +0.08
-0.04
5.76
2.28 10.1
Reflow soldering 4.57
0.25 M A B 0.1
Dimensions in mm

Application-Boards for Rth - Measurement PC-Board

P-TO252-3-1 P-TO252-3-1 P-TO252-3-1

a
1 2 3
6 cm 3 cm a Footprint only

a/2 a/2

I Q I Q I Q
1 1 1

FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn
A = 600 mm; a = 24.49 mm A = 300 mm; a = 17.32 mm Footprint only

FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow) Finite Element Method

A = 600 mm; Ta = 298 K; Tmax = 353 K A = 300 mm; Ta = 298 K; Tmax = 376 K Footprint only; Ta = 298 K; Tmax = 442 K

Diagrams
Thermal Resistance Junction to Ambient Rthj-a vs. Thermal Impedance Junction to Ambient Zthj-a vs.
PCB Heat Sink Area A (zero airflow) Single Pulse Time tp (zero airflow)
160 160
K/W 143.9 Rthj-c = 1.8 K/W K/W
Rthj-a Zthj-a
120
120
100
100 80
Footprint
60 300 mm 2
80 600 mm 2
78 40
60
20
54.7
40 0 -3
0 100 200 300 400 500 mm 2 600 10 10-2 10-1 100 101 102 s 103
A tp

Infineon Technologies
Infineon Technologies AG
AG 33
33
 P-TO263-5-1
Footprint/Dimensions
4.4 0.1
10 0.2 1.270.1
A B
8.5 1) 0.1 0.1

10.3
0.05
GND
2.4 0.1

9.25 0.2

81)
0.6
1.1
10.8

7.9

(15)

2.7 0.3
4.7 0.5
9.4 4.6 1 5

16.15
5x0.8 0.1 0.5 0.1
4x1.7
Reflow soldering 8max.
0.25 M A B 0.1 B Dimensions in mm

PC-Board Application-Boards for Rth - Measurement

P-TO263-5-1 P-TO263-5-1 P-TO263-5-1

a/2
1 2 3
6 cm 3 cm a/2 Footprint only
a

1 1 1

FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn
A = 600 mm; a = 24.49 mm A = 300 mm; a = 17.32 mm Footprint only

Finite Element Method FEM Simulation (chip area 2 mm; Pv = 3 W; zero airflow)

A = 600 mm; Ta = 298 K; Tmax = 417 K A = 300 mm; Ta = 298 K; Tmax = 455 K Footprint only; Ta = 298 K; Tmax = 533 K

Diagrams
Thermal Resistance Junction to Ambient Rthj-a vs. Thermal Impedance Junction to Ambient Zthj-a vs.
PCB Heat Sink Area A (zero airflow) Single Pulse Time tp (zero airflow)
85 90
K/W 78.4 K/W
Rthj-a Rthj-c = 1.3 K/W Zthj-a
75 70
70 60
65 Footprint
50
60 300 mm 2
40 600 mm 2
55 52.4
50 30
45 20
40 10
39
35 0 -3
0 100 200 300 400 500 mm 2 600 10 10-2 10-1 100 101 102 s 103
A tp

34
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To t a l Q u a l i t y M a n a g e m e n t

Qualitt hat fr uns eine Quality takes on an all-

umfassende Bedeutung. encompassing significance
Wir wollen allen Ihren at Semiconductor Group.
Ansprchen in der For us it means living up
bestmglichen Weise to each and every one of
gerecht werden. Es geht your demands in the best
uns also nicht nur um die possible way. So we are
Produktqualitt unsere not only concerned with
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gelten gleichermaen der our efforts equally at
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Part of this is the very
Dazu gehrt eine bestimmte special attitude of our
Geisteshaltung unserer staff. Total Quality in
Mitarbeiter. Total Quality thought and deed,
im Denken und Handeln towards co-workers,
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Lieferanten und Ihnen, customer. Our guideline is
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Leitlinie ist, jede Aufgabe defects, in an open
mit Null Fehlern zu manner that is
lsen in offener demonstrated beyond
Sichtweise auch ber den your immediate
eigenen Arbeitsplatz workplace, and to
hinaus und uns stndig constantly improve.
zu verbessern. Throughout the
Unternehmensweit corporation we also think
orientieren wir uns dabei in terms of
auch an top (Time Time Optimized Processes
Optimized Processes), um (top), greater speed on
Ihnen durch grere our part to give you that
Schnelligkeit den decisive competitive edge.
entscheidenden Give us the chance to
Wettbewerbsvorsprung prove the best of
zu verschaffen. performance through the
Geben Sie uns die Chance, best of quality you will
hohe Leistung durch be convinced.
umfassende Qualitt zu
beweisen.
Wir werden Sie berzeugen.

Ordering No. B112-H7482-G1-X-7600

Printed in Germany
Published by Infineon Technologies AG TB 01005. NB