Report format Internship with Electronic Faculty Coordinator

Student Name: Jos Mauricio Surez Mejia

Date Since: 31 / 10 / 2016 To: 14 / 11 /2016
Company Name: Infineon Technologies Austria AG

Activity Description Observation

PPLL (Peripheral Phase Locked Loop) Measurement Phase
Noise : This is the first process in order to
verify the normal behavior.
Using the next laboratory instruments: Phase Noise Analyzer,
Clock Generator, Voltage Sources and Multimeter. The phase The Peripheral PLL output (clocks
noise measured is taken (In PPLL block) in each one the different the peripherals in the microcontroller
examples given by design and the manufacturing process (three - HSCT, Multi-ADC) is related with a
of each one). To validate the Phase Noise behavior this different circuit part that the System
measurement is taken in three different PLL Output frequencies PLL.
which are considered the nominal parameter and critical
parameters that the microcontroller may work. Moreover the test Test duration (1 sample): 20 min.
has three different Input Frequencies values also considered Total test duration (12 sample):
nominal and critical voltages. A code described in Matlab is used 1 day.
to acquire the data.

PPLL (Peripheral Phase Locked Loop) Measurement Phase

Noise (Temperature variation): This process is able to start after the
measurement process in normal
In this measurement is executed the same process that PPLL with conditions has finished
an additional instrument; this measurement uses the termostream
instrument to test the microcontroller in three different Test duration (1 sample): 1 H.
temperatures (Cold temperature, Hot temperature and normal Total test duration (12 sample):
temperature). A code described in Matlab is used to acquire the 2 days
data.

SysPLL (System Phase Locked Loop) Measurement Phase

Noise (Temperature variation): The SysPLL output is part of the
clocks that control the system.
Using the next laboratory instruments: Phase Noise Analyzer,
Clock Generator, Voltage Sources and Multimeter. The phase Test duration (1 sample): 1 H.
noise measured is taken (In SysPLL block) in each one the Total test duration (12 sample):
different examples given by design and the manufacturing 2 days
process (three of each one). To validate the Phase Noise
behavior this measurement is taken in three different PLL Output
frequencies which are considered the nominal parameter and
critical parameters that the microcontroller may work. Moreover
the test has three different Input Frequencies values also
considered nominal and critical voltages and uses the
termostream instrument to test the microcontroller in three
different temperatures (Cold temperature, Hot temperature and
Nominal temperature). A code described in Matlab is used to
acquire the data.

PPLL DCRO (Digital Controller Ring Oscillator) Tuning curves

(Temperature variation) Digitally Controlled Oscillator (DCO)
known as Voltage Controlled
Using the next laboratory instruments: Clock Generator, Oscillator (VCO) in the analog PLL.
Frequency counter, Voltage Sources and Multimeter. The DCRO
measured is taken to validate the frequency behavior in which the Test duration (1 sample): 2 H.
test has frequency, voltage and temperature variations. Total test duration (12 sample): 1
week

Contribution to knowledge

PHASE LOCKED LOOP (PLL)

A phase-locked loop is a feedback system combining a voltage controlled oscillator (VCO) and a phase
comparator so connected that the oscillator maintains a constant phase angle relative to a reference signal.
Phase-locked loops can be used, for example, to generate stable output high frequency signals from a fixed
low-frequency signal. Figure 1A shows the basic model for a PLL. The PLL can be analyzed as a negative
feedback system using Laplace Transform theory with a forward gain term, G(s), and a feedback term, H(s),
as shown in Figure 1B. The usual equations for a negative feedback system apply.

Figure 1. Basic PLL (Phase Locked Loop) Model [1]

The basic blocks of the PLL are the Error Detector (composed of a phase frequency detector and a charge
pump), Loop Filter, VCO, and a Feedback Divider. Negative feedback forces the error signal, e(s), to approach
zero at which point the feedback divider output and the reference frequency are in phase and frequency lock,
and Fo = NFREF.
Referring to Figure 1, a system for using a PLL to generate higher frequencies than the input, the VCO
oscillates at an angular frequency of o. A portion of this signal is fed back to the error detector, via a
frequency divider with a ratio 1/N. This divided down frequency is fed to one input of the error detector. The
other input in this example is a fixed reference signal. The error detector compares the signals at both inputs.
When the two signal inputs are equal in phase and frequency, the error will be constant and the loop is said to
be in a locked condition [1]

In these tests the Phase Noise Measurement in where multiple noise sources can do our job a nightmare,
there are multiple kinds of Noises, the most common are:

Power Supply Noise: Switching current through finite supply impedance causes supply voltage drops that vary
with time and physical location.

- Time varying (switching) currents induce variations on the supply voltage.

- Supply noises a circuit see depends on its location in supply distribution network.
- Supply noise can induce variations in a circuit delay (Jitters on clock and data signals).
- Simultaneous switching noise: Finite supply impedance causes significant Simultaneous Switching
Output (SSO) noise. SSO noise is proportional to number of outputs switching, N, and inversely
proportional to signal transition time.

Receiver offset: Caused by random device mismatches.

Crosstalk: One signal (aggressor) interfering with another signal (victim).

- Coupling between on-chip (capacitive) wires.

- Coupling between off-chip (t-line/channel) wires.
- Signal return coupling.

Inter-symbol interference (overlap, temporary widening): Signal dispersion causes signal to interfere with itself.

Random noise: Thermal and shot noise, clock jitter components. [2]

To determinate the noise source classification, is important to know whether noise source is Proportional vs
Independent, Bounded vs Statistical:

PROPORTIONAL INDEPENDENT
BOUNDED

RX Offset
Residual ISI
Rx Sensitivity
Crosstalk
Power Supply Noise
STATISTICAL

Large-Channel
Random Noise
Crosstalk

Figure 2. Noise Source Classification [2]

Although to develop the PPLL DCO test is important to know how this process is and due to some issues
and analog loop filter implementation is undesirable, the striving for a better way to do the test leads to
implement digital PLL, in which this suffer some challenges:

- Digital loop filter: Compact area, insensitive to leakage.

- Phase detect change to Time digital converter (TDC).
- Voltage controller oscillator (VCO) change to Digitally controller oscillator (DCO). [3]

Figure 2. Analog to Digital PLL (Phase Locked Loop) Model [3]

The Digital PLL actually detects the phase difference between the reference oscillator and DCO. Therefore,
the edges of the DCO are aligned to those of references when the PLL has reached the steady state.

A DCO is considerate as a VCO but is synchronized by external frequency reference. The reference is the
reset pulses produced by a digital counter. The counter acts as a frequency divider, this counts pulses from a
high frequency master clock (MHz) and toggling the state of its output when the count reaches some
predetermined value.

Here there is some information about the difference between Peripheral and System PLL.

System PLL

Control the microcontroller clocks

Has: Oscillator Watchdog and Spread Spectrum Frequency Modulation for Electromagnetic
Emission Reduction.

Peripheral PLL

Control the peripheral clocks in the microcontroller.(HSCT, Multi ADC)

Except than the features that are mentioned above, the System and Peripheral PLLs are implemented in the
same way
 Figure 3. Typical connections between the instruments and the board: 1 and 2 Multimeters, 3 - Digital Counter, 4 - Power supply, 5 Phase Noise
Analyzer, 6 Termostream, 7 Clock Generator, 8 - Board

Recommendation:

Check communication between instruments and equipment (Addresses and ports).

As recommendation after Matlab starts introduce the line restoredefaultpath in order to get a good
performance during tests. This because Matlab has some start problems with the search path.
Ensure the limit of current that can generate the power sources (recommended maximum 200 mA)
Sometimes In cases where specific temperature (low) measurements are taken, remember to raise
the temperature to the maximum and then drop to the nominal temperature so that there are no liquid
problems that could affect the card.

Bibliographic References

[1] Analog Devices. (2009). Fundamentals of Phase Locked Loopc (PLLs). Recuperado el 11 de Noviembre de
2016, de Analog Devices: http://www.analog.com/media/en/training-seminars/tutorials/MT-086.pdf

[2] Palermo, Sam. (2015). Electrical & Computer Engineering - Noise Sources . Recuperado el 11 de 11 de
2016, de Texas A&M University:
http://www.ece.tamu.edu/~spalermo/ecen689/lecture9_ee720_noise_sources.pdf

[3] Perrot, M. H. (September 2009). Tutorial on Digital Phase Locked Loops. Abgerufen am 11. November
2016 von CppSim System Simulator: http://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf