Document Type: Tutorial

NI Supported: Yes
Publish Date: Aug 21, 2007

Create a Custom Analog Trigger in LabVIEW FPGA

Overview

This exercise will introduce you to using I/O in LabVIEW FPGA. This application will also show the flexibility of a LabVIEW FPGA system, creating analog input and output nodes and performing
parallel processing for analog triggering. All hardware in this exercise will be emulated in LabVIEW. We will be able to run an FPGA application in LabVIEWs emulation mode.

Configuring the LabVIEW Project

Download the project attached to this tutorial, Custom Analog Trigger.lvproj, and place in in a convenient location, such as the desktop.

1. Launch LabVIEW 8.5 and open the Custom Analog Trigger.lvproj project. This project contains an RT CompactRIO Target and an FPGA Target backplane that is set up for 4 I/O modules.

2. Configure the FPGA Target to run LabVIEW VIs in Emulation mode, which simulates running on an FPGA Target with random numbers for input stimulus.

1. Right-Click on the FPGA Target(cRIO-9103) and select Properties.

2. Select On Use Random Data for Inputs from the Emulator drop down menu.
3. Click OK to apply the emulator settings.
Developing the LabVIEW FPGA Application

Now that you have finished configuring the FPGA target for emulation, you will begin to develop a LabVIEW FPGA application. The application you build will:

Use parallel loops for different rates of analog input and analog output
Access simulated I/O using FPGA I/O Nodes
Use a Single-Cycle Timed Loop (SCTL) to optimize trigger routine speed
Trigger a digital output line of a custom analog input value

The completed application should look like this:

3. In the LabVIEW Project Window, right-click on the FPGA target (cRIO-9103, Emulator) and select New>>VI to start a new LabVIEW FPGA VI (LabVIEW programs are called Virtual Instruments
or VIs). Save this VI as Custom Trigger (FPGA) in the Filename text box to signify that this program will be run on the FPGA.

A common use for LabVIEW FPGA and RIO hardware is custom triggering. In this exercise we will read in data from an analog channel, compare it to a threshold, and write the appropriate value
to a digital channel. If the analog input value exceeds the threshold then an LED on the front panel of the FPGA VI will turn on. If the value is below the threshold then the LED will turn off. We will
begin building the application by reading in the analog channel at a timed interval.

4. First, place a While Loop ( Functions >> Structures) on the block diagram.

5. From the Functions>> FPGA I/O palette place a FPGA I/O Node function inside the While Loop.

6. Using the operate tool, click the FPGA I/O node and select Mod1>>Mod1/AI0.

7. Place a Loop Timer function (Functions >> Time & Dialog) inside the loop. Select sec as the counter units and 32 Bit as the size of the internal counter.

8. Right-click on the input terminal to the Loop Timer Function and create a control. Label the control AI Scan Rate (uS). This control will set the wait time which controls speed of the analog
input.

9. From the Functions>>Structures palette enclose the timing functions inside the loop in a Flat Sequence Structure.

10. Right click on the sequence structure and add a frame after. Expand this frame and place the Analog Input inside.

11. Place an Add function (Funtions >> Numeric) on the block diagram, and wire the AI Ch 0 I/O node to the top input and right-click and create a control labeled Offset on the bottom input.
Right-click on the control and change the Representation to I32.

12. Right click on the output terminal of the Add function and create an indicator. Label the indicator AI Ch 0. You can use the indicator to pass data back to the host and to the trigger detection
loop.

13. Wire a FALSE Boolean Constant (Functions >> Boolean) to the While Loop Condition terminal. The VI should look like this:

Note: On the first execution of the loop timer function, the internal timing value is set but no delay is added to the loop. By placing the loop timing function in the first frame of the flat sequence
structure, we ensure that the correct loop timing occurs on the first iteration of the loop. If no sequence structure were used, the second acquisition would occur immediately after the first since no
delay would be added.

14. Drop down another While Loop that will run parallel to the analog in loop. This loop will be where we perform our custom triggering.

15. Drag out a Timed Loop (Functions >> Structures>>Timed Structures) inside the while loop. This is a single-cycle loop, which means that the code inside it will run in a single cycle of the
onboard clock of the FPGA (40 MHz). Basically we want to check every clock cycle to see if the input is above or below the threshold. If so, we will set the Digital Output to the appropriate value.

16. Create a Local Variable for the AI Ch 0 indicator, place it inside the Timed Loop, and change it to read by right clicking on it.

17. Drop a Greater? function (Functions >> Comparison) on the block diagram, wire the output of the local variable to the top input and create a control labeled Threshold on the bottom input.

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18. Right click the border of the Timed Loop and select Add Shift Register. This register will store the previous value of the threshold. If the analog in value has risen above or dropped below
the threshold value then we will stop the timed loop and update the digital output. Connect the output of the Greater? function to the input of the shift register on the right border of the timed loop.

19. Drop an Exclusive Or function (Functions >> Boolean) on the block diagram inside the Timed Loop, wire the output of the Greater? function to the top terminal and the output of the shift
register on the left hand side of the timed loop to the bottom terminal. Wire the output of the Exclusive Or function to the timed loop condition terminal.

20. Right click the output of the shift register on the right border of the timed loop and create an indicator. Name this indicator Over Threshold.

21. Drop down a FPGA I/O Node (Functions >> FPGA Device I/O) inside the while loop (outside of the timed loop) . Left-click the I/O node and select Chassis I/O>>FPGA LED to access the
FPGA LED on the CompactRIO controller. (This is the output to the LED so that when the threshold is reached, the LED will turn on.) Wire the output from the right shift register to the Digital
Output node.

22. Wire a FALSE Boolean Constant to the Loop Condition terminal of the outer while loop. Because of the single cycle loop, it only takes 25 ns for the trigger to be recognized. Now, the VI
should look like below:

23. Open the VI front panel by clicking Window >> Show Block Diagram or by using the keyboard shortcut <Ctrl+E>. Change the value of AI Scan Rate to 10000 and then right-click on the
control and select Data Operations >> Make Current Value Default . Since the user interface in an FPGA VI is usually only used for passing data to and from an FPGA VI, you may leave the rest
of the front panel as is. In a typical FPGA application, a host VI will eventually be used to display all data. Because you are completing an online evaluation, this exercise will not be able to
communicate with a host VI, so you will need to alter the front panel to make displaying data easier.

24. Right-click on the AI Ch 0 indicator and select Replace >> Graph >> Waveform Chart . A waveform chart will show the time domain history of the input values, so you can see as the input
signal approaches and crosses the threshold value.

25. Right-click on the Offset control and select Replace >> Numeric >> Vertical Pointer Slide. Change the maximum value of the slide scale by double clicking on the 10 and typing in 64767.

26. Increase the Threshold value to 32768. The front panel should look similar to the front panel pictured below.

27. Save the VI and project . Click the Run button to run the VI in emulation mode. In emulation mode, the analog input values are simulated with random numbers. If you were building a VI for
physical hardware and deployment, clicking on the run button would initiate a compile of the LabVIEW code into an FPGA bitfile.

28. Adjust the Offset value and observe the reaction of the system. As you increase the offset slide control, the emulated analog input value will tend to be higher than the threshold, and the Over
Threshold indicator will tend to stay on more.

29. After you have run and tested the code, stop the application. Because this code was written to run indefinitely in FPGA HW, there is no stop button. The only way to stop this code is with the
Abort button. Press the abort button to interrupt and stop the FPGA emulation.

30. When you are finished testing your FPGA application, close the application and close the Project Explorer.

Downloads

custom_analog_trigger.lvproj

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