Analisis Pequeña Señal

GENERALIZATION OF SMALL SIGNAL APPOXIMATION TO MULTITERMINAL DEVICES
IC 4
+
2
IB Use terminal 1 as a reference to define
IA
+ + 3 terminal voltages and currents
VC
VA VB
- -
-
1
ID = - ( IA + IB + IC )

In general:
i A f A v A , v B , vC
i B f B v A , v B , vC Large signal nonlinear device (system)
equations may be dependent on range
iC f C v A , v B , v C of voltages and currents.
Taylor series expansion of iA w.r.t. Q point: VA, VB, VC
f A
i A f A V A , VB , VC v A V A f A vB VB f A vC VC
v A Q
v B Q
v C Q
1 2 f A 2 fA 2 fA
v A V A 2
vB VB 2
vC VC 2
2 v A2 v B2 vC2
Q Q Q
f A
v A V A vB VB
v A v B Q
if |va|, |vb|, |vC| are small enough
i A I A gaa va gab vb gac vc

ia ( t )
where
1 f i A i A
gaa
A gab
gac

raa v A Q
v B Q
vC Q
Small signal analysis for a 4 terminal device
ia ga v a gab v b gac v c
ib gba v a gb v b gbc v c
ic gca v a gcb v b gc v c
ia
+
ia1 ia2 ia3
va ra 1
ga a gabvb gac v c
-
MOST GENERAL SMALL SIGNAL EQUIVALENT CIRCUIT FOR A 4 TERMINAL DEVICE
ia
3 ib 4 ic
2 + + +
va ra g ab v b g ac v c gba va gbcvc rb vb gca va gcb v b rc vc
- - -
Remarks:
- All small signal parameters are Q-point dependent.
- Capacitances between terminals have to be considered for high frequency
analysis.
- BJT and MOS are four terminal devices, only a few parameters have non
negligible values.
- Voltage controlled sources indicate how what happens at one port affects
another port (coupling between ports).
BJT MODELLING
E B C S
n+ n+ p+
p VSS
n-
n+
p-substrate
base cc s
substrate
gate collector substrate
c drain 3 ib 4 ic
ia
2 + + +
c
va ra g ab v b g ac v c gba va gbc vc rb vb gca va gcb v b rc vc
- - -
emitter
source 1
BJT MODELLING: HYBRID MODEL
c
Models leakage current r
rc
rb
b b c
+ c
r c v g m v ro
Substrate
cc s
-
e S
Always connected to signal

ground (DC voltage).
e
VBE
V
i 3 ic I S e VT
1 CE
VA
iC iC Large signal equations
i1 i B or iE forward active mode.

iE iB iC
C: Forward biased base emitter junction:
c je 0 f
c e I c 0.33
1
where
V EB e VT
oe
C: Reversed biased base collector junction:
c 0
c C 0.5
1
where
VBC C
oc
CCS: Reversed biased collector substrate junction:
cCS 0
S
Large area
cCS 0.5 low doping
1
where
VCS S
oS
r: base emitter resistance:
-1 -1
i i
r B VT
C
2.5 K
v BE v BE I CQ
Q Q
ro: output resistance:

-1
i
ro C VA
100 K
vCE I CQ
Q
gm: transconductance:
i I CQ
gm C 40 mA
v BE VT V
cj0, j0, , F are different for each junction, must be known.
r = 5 r0 100 M can be usually neglected.
re 5 strongly geometry dependent
rb 200 strongly geometry dependent
rc 200
Ic dependent
EXAMPLE:
Emitter area 500 m2, High voltage NPN device
VEB0 = 7 V VCB0 = 50 V VCS0 = 70 V

Cje0 = 1 pF C0 = 0.3 pF CCS0 = 3 pF
joe = 0.7 V joc = 0.7 V joS = 0.52 V
e = 0.33 c = 0.5 S = 0.5
SMALL SIGNAL ANALYSIS

- Set all signal sources to zero.
1.- Perform DC Analysis - Determine all DC voltages and currents if possible
using DC equivalent circuits.
Check for |VCE| > 0.2 V I BJTs.
2.- Passivate DC Sources

- Voltage sources
- Current sources
short circuits
open circuits

- Small signal device parameters can only be
determined if DC(Q ) operating point is known.
3.- Replace devices by small - For small frequency analysis do not include parasitic
signal equivalent circuits device capacitances.
-Small signal equivalent circuits do not depend on the
type of transistor (NPN, PNP).
EXAMPLE
+ 15 V
+ 15 V
IBIAS2
5mA 15 K
IB3 0.7 V
15 K
vout IB1
IB1 IB2 vout
IB2
vS Q3 IB1 IB3
Q1 Q2
DC
0.7 V 0.7 V
3 K
3 K
IBIAS1
ro
1mA
- 15 V
- 15 V
- 15 V
- 15 V
Since We have the same VBE for Q1 and Q2:

I BIAS 1
IC1 IC 2 0.5 m A where 1
2
I BIAS 2
IC 3 5 mA

VE 1 VE 2 - 0.7 V
VC 2 15 - 15 k 0.5 mA 7.5 V
VE 3 VC 2 0.7 8.2 V
VC 3 15 3 k 5 mA 0 V
VCE 1 15 - ( - 0.7 ) 15.7 V
VCE 2 8.2 - ( - 0.7 ) 8.9 V
VEC 3 8.2 0 8.2 V
All transistors are in active mode.
Calculation of small signal parameters: = 200, VA= 100 V

I CQ
g m1 g m 2 20 mA
V
VT
I CQ3
g m3 200 mA
V
VT
VT 26 mV
r 1 r 2 200 10 K
I CQ1, 2 0.5 mA
VA 100 V
ro1 ro 2 Q
2 00 K
I C1, 2 0.5 mA
VA 100 V
ro 3 20 K
I CQ3 5 mA
SIMPLIFIED SMALL SIGNAL EQUIVALENT CIRCUITS FOR BJTS
+
b
ib
ie
r v ro b
gmv
ro
-
re
e
ve
r re
gm ie gm
r ( 1) re
SISTEMATIC PROCEDURE TO WRITE NODAL ADMITANCE MATRIX:
4 e3
r gm 3v 3
v ro3
rc2 =15 K 3 b3
rS +
1
c1 c2
c3 5
+ b2
b1
vS +
rc3=3 k
r v g m 1 v 1 ro1 ro2 gm 2v 2 v r
- -
e1 e2
2
4 e3
c v gm 3v 3
cS2 ro3
rc2 =15 K 3
r
b3
rS +
1
c c1 c2
c3 5
+ b2 c
vS b1
r c +
cS3 rc3=3 k
v g m 1 v 1 ro1 ro2 gm 2v 2 v
c c
r
- -
e1 e2
2
MOS TRANSISTOR (ENHANCEMENT)
ID
D
Drain
IG IB
B
Substrate
IS
S
Source
Dependent Independent
i D , i S , iG , i B vG S , v DS , v BS
Large signal equations:
iG 0
iB 0
iS iD Only one equation needed
MOS TRANSISTOR: OPERATION REGIONS
Saturated Mode: i D f1 vGS , v DS , v BS
Cutoff Mode: iD 0
Nonsaturated Mode: i D f 2 vGS , v DS , v BS

or triode
Weak inversion: i D f 3 vGS , v DS , v BS

or Subthreshold
Strong inversion: VGS VT

VGD VT VDS VGS VT
MOS TRANSISTOR:STRUCTURE.
G S
D
n+ n+ p+
p- substrate
Cross-Section of CMOS Technology
VDD
ID RD
Vout
Rs Vin
+ W/L, Cox, Vth, l,

Vs
VGS Ldrain , Lsource
VinQ
-
vinQ v S ( t ) vGS
iD C ox
tox
W
L (vGS vth ) 2
vout v DD - i D RD
Q Q Q Q
Find ID , VGS , Vout = VDS
VDD
ID RD
VinQ Q
VGS
V 2
Vout
C ox W
Rs Vin
IQ
D 2 L
Q
GS
VT
+ W/L, Cox, Vth, l,

Vs
VGS Ldrain , Lsource
VinQ
- Q
VoutMIN = VGS -VT
Q
Vout VDD I DQ RL VGS
Q
- VT
Another AC equivalent circuit
RC
Vout
ie
RS
rO C

Ib gm
VS
Effective collector (drain) resistance

Gain Rule :
Effective emitter (source) resistance
For MOS = 1, ie is , =
Example: Gain stage with MOS transistor and biased with current
source.
n cox 1
25 A V 2 ; l n 0.02 V ; | Vt n | 0.8 V ; VDD 5 V
2
Q
Vout VDD I DQ RL VGS
Q
- VT
Q
if VGS 2.5
V DD Vout
Q
5 2.5
100 k 25 A
Q
I D RL
W 12

L 2
Q
ID
C ox W
2 L
V Q
GS
VT 2
Q
25 A
VT
Q
ID
VGS 0.8V
C ox W 25 A/V
2 12
2 L 2
0.408V 0.8V 1.208V

Example: Gain stage with MOS transistor and biased with current
source.
n cox 1
25 A V 2 ; l n 0.02 V ; | Vt n | 0.8 V ; VDD 5 V
2
1 1
rout 200 k
ln I D
Q
0.0225 A
W

12
gm Q
2 25 10 6
2 I bias
122.55 A / V
L 2
VGS1 Vt 0.408
rout RL ro 66.67 k
Avo g m r
o 100 k 8.1704
Diffusion Capacitance
Channel-stop implant
N A1
Side wall
Source
W
ND
Bottom
xj Side wall
Channel
LS Substrate N A
4m
For 2 m :
12 m 10
CJSW 1.3284 10
4
CJ 3.4239 10
2m
cd c s CJSW 2 Lsource 2 W CJ Lsource W 0.2 pF

RD
Vout
Cgd Id
RS
+
gm Vgs rO Cdb
VS Vin=Vgs Cgs
_
Gs+ -sCgd Gs Vs
+sCgd+sCgs
gm- GD+g0+ 0
-sCgd +sCgd+sCdb
Dynamic Behavior of MOS Transistor
CGS CGD
S D
CSB CGB CDB
B
The Gate Capacitance
Polysilicon gate
Source Drain
W
n+ xd xd n+
Gate-bulk
Ld
overlap
Top view
Gate oxide
tox
n+ L n+
Cross section
Gate Capacitance
Cut-off Resistive Saturation
Most important regions in digital design: saturation and cut-off

Gate Capacitance
Capacitance as a function of VGS Capacitance as a function of the

(with VDS = 0) degree of saturation
Gate Capacitance
3 102 16
10
V GS 9
Gate Capacitance (F)

8
I 7
6
5
4
3
2
2 2 2 1.5 2 1 2 0.5 0 0.5 1 1.5 2
V GS (V)
Parasitic Resistances
MOS TRANSISTOR: LARGE SIGNAL EQUATIONS.
Saturated Mode: i D f1 vGS , v DS , v BS

VGS VT VGD VT or VDS VGS VT
kp W
iD
1
VGS VT 2
2 L 1 ( vGS VT ) - l v DS
25 A/V2 n-channel
kp transconductance parameter ~
10 A/V2 p-channel
Vt Vto 2j f VBS 2j f ~ 0.8 - 1.6 V for l arg e VBS
Body effect parameter: ~ 0 .5 V 1

Fermi level: j f ~ 0 .3 V
Mobility degradation: ~ 0.35 V 1 for L 2 m
Channel length modulation: l ~ 0.3 for L 3 m
For long dimensions ( L > 3 m ) and Low vGS ( | vGS| < 2 V
l is not significant no degradation
kp
iD vGS Vt 2 1 l vDS f vGS , v DS , v BS
2
kp
iD vGS Vt 2 f vGS
2
Used for quick hand calculations: simplified small equivalent circuits.
Used to derive general small equivalent circuits
Condition for small signal approximations
VGS V Q
GS VT
cd b
cg d
g d b
+
+ +
g m v gs
cg s vg s gm v cb s
vd s vb s
ro
-
- -
Transconductance: s
i

Q
W 2 ID
gm D kp V W

V
Q Q Q
VGS 2 ID k
vGS
t p L
VtQ
Q
L GS
Q
Body effect bulk transconductance gain

i D
gmb gm
v BS Q 2
Q
ID k W
p L
Output resistance:
-1
i
ro D 1 VA

v DS l I nQ ID
Q
G
VGS < Vt D
S VDS B
n+ n+ p+
- -
- - -
p- substrate
VDS 0 0 VGS Vt
-No current flows, electrons begin to accumulate under gate.
-Strictly speaking: small current flows (subthreshold or weak inversion

operation.
G
VGS > Vt D
S VDS B
- - - - - - - - -
n+ n+ p+
p- substrate
-Channel is induced for vGS Vt
-The width of the channel is uniform, and is controlled by vGS - Vt.
- For small vDS:
v DS n Cox vGS Vt
1 W
iD v DS
R channel L
G
VGS > Vt D
S VDS B
- - - - - -- - - -
n+ - - - - n+ p+
p- substrate
- vDS > 0 subject to:

vGS > Vt , vGD > Vt
vDS < vGS -Vt (small VDS!)
-Nonuniform channel width, narrower in drain side than in source side:

nonlinear resistive behavior.
i D n Cox
W
vGS v DS /2 - Vt v DS
L Equation for
2 vGS Vt - v DS v DS
k pW triode mode

2L
G
VGS
D
S VDS B
- - --- - - -
n+ - - - n+ p+
p- substrate
- vDS > 0 subject to:
vGS > Vt , vGD < Vt
vDS > vGS -Vt (large VDS!)
-Channel pinch-off: channel width becomes zero on drain size.

- Further increases in vDS once channel pinch-off takes place do not affect.
vGS Vt
k pW
iD
2
2L
REMARKS.
-Large vDS , Drain terminal performs as high

Saturation
vDS > vGS -Vt mode impedance source depending only
on vDS
-Smal vDS , Device acts as a voltage controlled

Triode mode
vDS < vGS -Vt resistor
- Equations are valid for long channel devices !!!!!

MOSFETs Short channel effects
Gate oxide
tox
n+ L n+ xj
Cross section
The behavior of short-channel transistors (sub-micron channel length) deviate

from that of the long-channel transistors.
A MOS transistor is called short channel device if its channel length is of the
same order of magnitude as the depletion region thickness of the source and
drain junctions.
Alternatively, a MOSFET transistor can be defined as a short-channel device if
L
the effective length
eff LD 2 xd
is approximately equal to the source and drain junction depth xj
The short channel effects that arises in this case are attributed to two
physical phenomena:
(i) The limitation imposed on electron drift characteristics in

the channel, and
(ii) the modification of the threshold voltage due to shortening

channel length.
Fundamental scaling limits for conventional MOS devices

Mobility Degradation
Transistors with channel lengths < 1um

High gate voltage
Large electric fields, no longer one-dimensional
Greater channel depth
More electron collisions
Carrier mobility n degraded
Carrier velocity between source & drain saturates
Channels effective sheet resistance goes up
How can we model mobility degradation?
Use finite series source resistance Rsx:
Rsx = (1/Ec) (1/ nCox) (1/W)
where Ec = critical electric field ~ 1.5X1E6 v/m
For 0.8m long transistor with nCox = 90 /V2,

Rsx = 6K/m width - much larger than physical source resistance
Id/Vgs square law no longer true - relationship somewhere between

linear and square law
Threshold Variations
VT VT
Long-channel threshold Low VDS threshold
VDS
L
Threshold as a function of Drain-induced barrier lowering

the length (for lowVDS ) (for lowL)
Velocity Saturation
In long channel devices, the drift velocity of the carriers, vd, is

proportional to the electric field, independent of the value of the field,
Ex. Note that the lateral (horizontal) electric field, along the channel
increases, as the effective channel length decreases.
v DS
vd
Leff
For channel electric field of Ex 105 V/cm, the electron drift velocity in
the channel reaches a saturation value of vd = 105 V/sec. In this case, the
carriers fail to follow the linear model. The critical value of the electric
field at which the carrier velocity saturates, EC, depends on the doping
levels and the vertical electrical field applied (The vertical electric field
is due the voltage applied on the gate of the MOSFET).
E
v d E vd
1 E / Ec
Velocity Saturation
The velocity saturation has very significant implications upon the current-voltage
characteristics of the short-channel MOSFET, especially the n-type
MOSFET. For short-channel, these implications include:
1. Due to carrier velocity saturation, the delivered saturation-mode

current is less than the current value predicted by the conventional
long-channel current equation. The current is no longer a quadratic
function of the gate-to-source voltage,, and it is virtually independent of
the channel length. The saturation current displays a linear
dependence with respect to.
2. The device enters saturation before reaches, i.e., .
3. The actual threshold voltage of the short-channel devices is less than
that of the long-channel devices.
4. In the surface region of the channel, i.e., the region under the gate
oxide, the surface mobility of the carriers is reduced with respect to the
bulk mobility.
Velocity Saturation
u n ( m /s)
usat = 10 5
Constant velocity
Constant mobility (slope = )
x = 1.5
c x (V/m)
-4
x 10
2.5
VGS= 2.5 V
Early Saturation
2
VGS= 2.0 V
1.5
ID (A)
Linear
VGS= 1.5 V
1 Relationship
0.5 VGS= 1.0 V
0
0 0.5 1 1.5 2 2.5
VDS(V)
ID
Long-channel device
VGS = VDD
Short-channel device
VDSAT VGS - VT VDS

ID versus VGS
-4
x 10 -4
6 x 10
2.5
5
2 linear
4 quadratic
1.5
ID (A)
ID (A)
3
1
2
1 0.5
quadratic
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS(V) VGS(V)
Long Channel Short Channel

ID versus VDS
-4 -4
x 10 x 10
6 2.5
VGS= 2.5 V
VGS= 2.5 V
5
2
4 VGS= 2.0 V
Resistive Saturation
VGS= 2.0 V 1.5
ID (A)
ID (A)
3
VDS = VGS - VT 1 VGS= 1.5 V
2
VGS= 1.5 V
0.5 VGS= 1.0 V
1
VGS= 1.0 V
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VDS(V) VDS(V)
Long Channel Short Channel

Hot Carrier Effects
Hot Carrier effects - term used to describe mobility reduction and velocity
saturation (as temp increases, electron mobility decreases)
Hot Carriers can tunnel through gate oxide and cause finite gate currents
Can become trapped in gate oxide causing threshold voltage to gradually change
Can cause impact ionization - avalanche breakdown
Finite Drain to Ground impedance - current flows from drain to bulk
Latch-up may occur due to substrate currents
Lowered Output resistance
Source-drain punch-through - high energy electrons shoot from S to D via
abnormal conduction mechanism not governed by drift equations; unlimited
current flow, transistor may breakdown
Reduced Output Impedance
Widening depletion region at drain end affects drain current

more for short channel devices
Id - Vds characteristic not as flat: output impedance reduced
Phenomenon also known as dibble - DIBL or drain

induced barrier lowering: effective lowering of threshold
voltage as Vds is increased giving greater Id and less output
impedance as channel shortened
Can be a problem! Use cascode configuration
Which are more prone to hot carrier effects: N or P channel

MOSFETs ?
Sub Threshold Operation/Region
weak inversion - sub threshold region
W Cox Cdep
I d I DO e ( qVGS / nkT ) n
L Cox
Cdep also depends on interface state density
-2
10
-4
Linear
10
S is DVGS for ID2/ID1 =10
-6
10 Quadratic
ID (A)
-8
10
10
-10 Exponential
-12 VT Typical values for S:
10
0 0.5 1
VGS(V)
1.5 2 2.5 60 .. 100 mV/decade
Sub-Threshold ID vs VDS
qVGS
qV
DS
I D I 0e nkT 1 e kT 1 l VDS

qAj ni
Io xd
2 o
VGS from 0 to 0.3V
Sub-Threshold ID vs VGS
qVGS
qV
DS
I D I 0e nkT 1 e kT

VDS from 0 to 0.5V

Leakage Currents
Currents at reverse biased pn junctions

Result in static dissipation
Determine max hold time for sample and hold circuit or
dynamic memory cell
Strong function of temperature - doubles for every 11 deg C
rise of temp
qAj ni
Io xd
2 o
SPICE Model Parameters

Short Channel Effects - what happens as L is decreased .
Increased Channel Length Modulation
DIBL (drain induced barrier lowering)

Future Perspectives
25 nm FINFET MOS transistor


Velocity Saturation

v d E

E
vd
1 E / Ec

Velocity Saturation

v d E

E
vd
1 E / Ec

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GENERALIZATION OF SMALL SIGNAL APPOXIMATION TO MULTITERMINAL DEVICES

if |va|, |vb|, |vC| are small enough

i A I A gaa va gab vb gac vc

va ra g ab v b g ac v c gba va gbcvc rb vb gca va gcb v b rc vc

Always connected to signal

C: Reversed biased base collector junction:

CCS: Reversed biased collector substrate junction:

ro: output resistance:

r = 5 r0 100 M can be usually neglected.

re 5 strongly geometry dependent

rb 200 strongly geometry dependent

VEB0 = 7 V VCB0 = 50 V VCS0 = 70 V

2.- Passivate DC Sources

Since We have the same VBE for Q1 and Q2:

Calculation of small signal parameters: = 200, VA= 100 V

Large signal equations:

Saturated Mode: i D f1 vGS , v DS , v BS

Nonsaturated Mode: i D f 2 vGS , v DS , v BS

Weak inversion: i D f 3 vGS , v DS , v BS

Strong inversion: VGS VT

+ W/L, Cox, Vth, l,

+ W/L, Cox, Vth, l,

Effective collector (drain) resistance

0.408V 0.8V 1.208V

cd c s CJSW 2 Lsource 2 W CJ Lsource W 0.2 pF

CSB CGB CDB

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

Capacitance as a function of VGS Capacitance as a function of the

Gate Capacitance (F)

Saturated Mode: i D f1 vGS , v DS , v BS

Vt Vto 2j f VBS 2j f ~ 0.8 - 1.6 V for l arg e VBS

Body effect parameter: ~ 0 .5 V 1

l is not significant no degradation

Used for quick hand calculations: simplified small equivalent circuits.

Used to derive general small equivalent circuits

Condition for small signal approximations

Body effect bulk transconductance gain

-No current flows, electrons begin to accumulate under gate.

-Strictly speaking: small current flows (subthreshold or weak inversion

-Channel is induced for vGS Vt

-The width of the channel is uniform, and is controlled by vGS - Vt.

- For small vDS:

- vDS > 0 subject to:

vDS < vGS -Vt (small VDS!)

-Nonuniform channel width, narrower in drain side than in source side:

vDS > vGS -Vt (large VDS!)

-Channel pinch-off: channel width becomes zero on drain size.

-Large vDS , Drain terminal performs as high

-Smal vDS , Device acts as a voltage controlled

- Equations are valid for long channel devices !!!!!

The behavior of short-channel transistors (sub-micron channel length) deviate

Alternatively, a MOSFET transistor can be defined as a short-channel device if

(i) The limitation imposed on electron drift characteristics in

(ii) the modification of the threshold voltage due to shortening

Fundamental scaling limits for conventional MOS devices

Transistors with channel lengths < 1um

For 0.8m long transistor with nCox = 90 /V2,

Id/Vgs square law no longer true - relationship somewhere between

Long-channel threshold Low VDS threshold

Threshold as a function of Drain-induced barrier lowering

In long channel devices, the drift velocity of the carriers, vd, is

1. Due to carrier velocity saturation, the delivered saturation-mode