ESc201 : Introduction to Electronics

Amplifiers

Shilpi Gupta
Dept. of Electrical Engineering
IIT Kanpur
Feb 15, 2017
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 Announcements

1. Assignment-6 uploaded on the course website.

2. Check your marks for mini-quizzes and labs on Brihaspati. In

case of any discrepancy, please contact Avirup Dasgupta
(avirup@iitk.ac.in)

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Voltage Amplification

3-terminal unilateral linear device

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 I1 I0
+ + (Ideally large)
Vi V0
- - Trans conductance

(Ideally large)

(Ideally small) 4
Voltage Amplifier

RS
v0
+
Ri g m vi
vS vi rO RL
-

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Necessary Condition for Voltage Amplification 6
Voltage Amplification

Trans-conductance >> Output Conductance

Transistor
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Transistor
Trans-resistor

IO
+ +

VIN Vo

- -

Current IO is much more sensitive to VIN than VO

Can be used for voltage amplification

Can be used as a switch
Implement logic

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9
In the ideal case ro is infinite

We would ideally like input resistance Ri to be infinite as well !

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An ideal 3-terminal device for Voltage Amplification

Ideal Transistor Characteristics

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Ideal Transistor (IT)
Making a voltage amplifier with an ideal transistor is straightforward

In practice there is no element which has the characteristics of ideal 12

transistor !
Ideal transistor

Device X

Device Y

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How do we use elements such as X, Y etc to make amplifiers?
Device X

Ideal Characteristics

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How do we
Simple use device
amplifier X towork
will not make! an amplifier?

No Amplification 15
Simple
How doamplifier will not
we use device work
X to ! an amplifier?
make

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When only a part of device characteristics is suitable for amplification, then we
need to push the device into that region by applying suitable bias voltages.
This process is called BIASING

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How should one choose the bias voltage VB ?

1.2V

Quiescent point or Bias point

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 IO

Vin

IO
I0
Q-point
2mA
Vin

1.0V 1.2V
1
V 1V ; g m 0.01 19
Output voltage is distorted !

IO
RL=1k

clipped

Need to choose a proper value of

biasing Voltage

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Unnecessary Power Dissipation
IO VIN vs time
v0
X
+
RL
vi
1.8V - RL=1k

vs
IO vs. time

I0
Q-point
8mA
VO vs. time

Vin
1.0V 1.8V
1
V 1V ; gm 0.01 21
Optimum Biasing ?IO
v0 Vin vs. time
X
+
RL
vi
1.5V -

vs
IO vs. time

I0
Q-point
5mA

Vin
1.0V 1.5V
1 VO vs. time
V 1V ; gm 0.01 22
How do we get rid of unwanted dc voltage at the output ?
IO

IO
v0
X
+
RL
vi
1.5V -

vs

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 IO

dc ac (signal)
IO

Capacitor is chosen large enough so

that at the signal frequency 1/j C24~0.
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AC Analysis

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 v0
X
+ RC
RL
vi
VB -

vs

The addition of biasing network allows element X to

appear as an ideal transistor to the signal source 27
What happens if both dc voltage source and signal source
have one terminal as ground?

v0
X
+ RC
RL
vi
VB -

vs
Shorts the signal source
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 Shorts the signal source

Solution

Gives vS + VB
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Capacitor is chosen large enough so
that at the signal frequency 1/j C ~0.

Note the role of RB 30

 Amplifier Schematic

I1 I0
X
+ +
Vi V0
- -

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