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fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2015.2424246, IEEE Transactions on Power Electronics
1
Electrical and Computer Science Department, Power Electronics and Drives Laboratory
University of Texas at Dallas
Richardson, TX, USA
serkan.dusmez@utdallas.edu; li.xiong@utdallas.edu; bilal.akin@utdallas.edu
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2
0.5 The switches S2-S3, and S1-S4 have 180o phase shift with
D2 D1 respect to each other. The duty cycle of the middle switches
Dr2 Dr1 should be greater than 50% such that they allow a
freewheeling path for the transformer primary side current.
S1 The switching scheme is as follows; S1 is turned on right after
S3 is turned off, and similarly, S4 is turned on when S2 is turned
S2 off. A dead-time should be inserted in between the turning on
S3 instant of S1 and turning off instant of S3, and likewise between
switching of S2 and S4 to avoid short circuit.
S4
vL1 vL1 iL1 B. Operation Principle
iL1 v1 The operation modes of the circuits, which are given in
v1 v1-vdc Fig. 3, are explained in this section. It should be noted that
L1 L1 these operation modes are valid when iL2>iL1. For this case,
vL2 vL2 v1-vdc iL2 iL2,pk is higher than primary side of the transformer at steady-
iL2 v2
state. Under this condition, iL1,pk is smaller than primary side of
v2 v2-vdc the transformer at steady-state. If iL1>iL2, the equivalent circuits
L2 L2 would be different from the one presented here. Basically, the
v2-vdc charging/discharging current of C1 and C2 would be exhanged.
vtr vdc -2Nvo vdc Interval 1 [t<t0]: Before t0, S3 is off and S1 is on. The energy
vtr itr 2N2Lo 2 stored in L2 is released to the load through the primary winding
itr of the transformer. The excess energy is transferred to C1
-vo through conducting the body diode of S1. Thus, S1 can be
vdc
-vo NLo vdc turned on under zero voltage with proper time delay. The
2N -
iLo vLo 2
current of L1 increases linearly under V1. Total current of L2
charges C2. Meanwhile, Vdc/2 is applied to the primary side of
vLo the transformer.
iLo iL1 t V1 / L1
V v t v t / L
iL 2 t
2 C1 C2 2
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3
Fig. 3. Operation intervals of the converter; a) interval 1: t 0<t<t1, b) interval 2: t1<t<t2, c) interval 3: t2<t<t3, d) interval 4: t3<t<t4, e) interval 5: t4<t<t5, f)
interval 6: t5<t<t6, g) interval 7: t6<t<t7, h) interval 8: t7<t<t8, j) interval 8: t8<t<t9.
applied across the primary side of the transformer. The output before, peak current of L1 is smaller than the load current for
inductor voltage is equal to Vo and the output inductor current this case. Thus, C2 discharges over to the load and Vdc/2 is
decreases linearly. applied across the primary side of the transformer. The current
of L2 continues to store energy under the influence of V2.
iL1 t V1 / L1
iL1 t V1 vC1 t vC 2 t / L1
L2
i t 0
iL 2 t
V2 / L2
vC1 t 0
d / dt vC1 t iL1 t / C1
vC 2 t 0 d / dt
i t vCo t / Lo vC 2 t iL1 t / C2 NiLo t / C2
i t
vC 2 t / NLo vCo t / Lo
Lo
vCo t iLo t / Co vCo t / Co Ro Lo
(3) vCo t iLo t / Co vCo t / Co Ro
(5)
Interval 5 [t3<t<t4]: At t=t3, S3 is turned on, while S2 is kept
on. The primary side current continues to freewheel and zero Interval 7 [t5<t<t6]: At t=t5, the energy stored in L1 is
voltage is applied across the primary side; hence, the output completely transferred out. Its current reaches to zero at DCM.
inductor current continuous to decrease under output voltage. The load current is solely supplied by C2.
Meantime, V2 is applied across L2, and current increases iL1 t 0
linearly storing energy in L2.
iL 2 t V2 / L2
iL1 t V1 / L1 vC1 t 0
d / dt
iL 2 t V2 / L2 vC 2 t NiLo t / C2
vC1 t 0 i t v t / NL v t / L
d / dt Lo
C2 o Co o
vC 2 t 0 vCo t iLo t / Co vCo t / Co Ro (6)
i t vCo t / Lo
Lo
vCo t iLo t / Co vCo t / Co Ro (4)
Interval 8 [t6<t<t7]: In this interval, S4 is turned off. The
current in the leakage inductance conducts D8 and the primary
Interval 6 [t4<t<t5]: At t=t4, S2 is turned off. The stored side current freewheels, hence, zero voltage is applied across
energy in L1 is released to the load as well as to C1. As stated the primary side of the transformer. The current of L2
0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2015.2424246, IEEE Transactions on Power Electronics
4
0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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10.1109/TPEL.2015.2424246, IEEE Transactions on Power Electronics
5
vx vx vtr iLx
vtr iLx
ix vx ix vx
vtr vtr
vdc
Vx-
2
Vx- vdc Vx- vdc
(a) (b)
Fig. 4. DCM/CCM boundary cases; a) input inductor current reaches to zero within D2Ts, b) input inductor current reaches to zero within (D2+Drx)Ts,
Vo 2 0.5 Dmin on the chosen parameters and output power, there could be one
Lo (23) more operation mode, which was not shown in Fig. 3. It is yet
2 Px f s necessary to analyze this operation mode in order to define the
where, Px represents the minimum output power at which the CCM/DCM boundary. In such a circumstance, after the
converter is desired to be operated in CCM. When output operation interval 7, the upper inductor would still continue to
inductor operates in CCM mode, D2 can be expressed as in Eq. provide energy to the upper capacitor even after S4 is turned
(24) at steady-state. off under the influence of Vdc/2. The voltage of the primary
NVo side of the transformer remains at zero since D8 conducts.
D2,max (24) Relevant waveforms are illustrated in Fig. 4.
Vdc ,min
To find the boundary operation point, one should consider
where, N represents the turns ratio of the transformer windings. that the inductor current reaches to zero at the end of the
The equivalent duty ratio for DCM mode can be written as switching period. The critical dc link voltage can be found
2 Lo through the expression of the voltage balance equality of the
D2 inductor, as
V
2
(25)
RTs dc 1 1 V
NVo Vx D1 Vdc ,crt Vx D2 dc ,crt Vx 1 D1 D2
2 (26)
Depending on the operation mode, N can be found from
either Eq. (24) or Eq. (25). Once D2,max and Vdc,min are where Vx denote the voltage of the input source that provides
determined, D1 and the limits for D1 can be found using Eq. higher output power. The lowest DC link voltage that should
(21) and (22). be adopted for DCM operation can be expressed as,
2Vx
2) Determination of DCM Boundary and DC Link Voltage: Vdc ,crt (27)
In this paper, the operation principle is based on operating D2 D1 1
input inductors in DCM. This is due to the fact that input For DCM operation, the following condition should be
sources are controlled by D1 and their voltages can be satisfied; Vdc,min>Vdc,crt.
different, only one of the cells would be able to operate in
CCM, while the other one would continue operating in DCM. 3) Determination of L1 and L2: In this paper, the operation
Once one of the input sources transits to CCM, the continuous principle is based on operating input inductors in DCM. For
current forces to apply Vdc to the other input, which keeps the the proposed converter, the duty ratios of S2 and S3 are the
voltage of latter at the same level; hence, latter continues to same, and equal to D1. Hence, the output power of each cell is
provide same amount of power in DCM mode. The rest of the proportional to the square of its input voltage, and inversely
necessary power is supplied from the input source operating in proportional to the inductance. The total power fed by the
CCM. This operation could be considered for applications input sources can be expressed as
where output power of one of the input sources is maximized Vdc D12Ts n
Vn 2
Po L V (28)
dc Vn
to definite value, while the secondary input source provides 2 1 n
rest of the load power demand.
The operation modes shown in Fig. 3 has been given Thus, with proper design of these parameters with respect to
considering that the input inductors are well chosen for DCM behaviors of input source, an autonomous power sharing is
operation under any load, and input inductor currents reach to possible. Based on Eq. (28), there are various possibilities to
zero within D2Ts. In case this interval lasts longer depending determine L. The bottom boundaries for Ln based on Vdc,min and
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6
250
P=1.4
200
P=1.0
L1(H)
150 P=0.7
100
50
80 140 200 240
L2(H)
Fig. 5. Inductance determination based on power sharing when V1=V1,min,
V2=V2,min.
Fig. 7. Power can be drawn from the second input source at Vdc=500V under
DCM mode.
Fig. 6. Power can be drawn from the first input source at Vdc=500V under
DCM mode. Fig. 8. Power can be drawn from both input sources at various DC link
voltages when V1=V1,min, V2=V2,min.
output power are defined as
Vdc D1,max 2Ts n Vn,min 2 L2 combinations can be found. Another criterion in
Pmax
2
L V
1 Vn,min
determining the inductances is the power ratio among the input
n dc ,min
(29) sources at desired input voltages. For this design, the power
The values of the inductances can be determined for rated ratio of the second input source to the first input source at
power, which would fall into the boundary defined above. The maximum output power and minimum input voltages, denoted
determination of inductances depends on the application as P, is evaluated. Based on the chosen P, the values of the
needs. For instance, for PV generation systems, the inductances can be determined as shown in Fig. 5. In this
inductances can be calculated according to the desired load study, P is determined as 0.7, which means that the second
sharing at the maximum power operation point. source provides 500W and the first source provides 700W
C. Design Example under maximum load when V1=V1,min, and V2=V2,min. The
The design procedure for constant power loads with corresponding L1 and L2 values, are selected from Fig. 5;
constant input voltage sources is straight-forward. Thus, this L1=108H, L2=122H.
section illustrates a design procedure for an application with The output power capability of the first and second input
dynamic variables having the parameters of V1,min=110V, sources according to D1 and their respected voltages are
V1,max=130V, V2,min=100V, V2,max=150V, Vo=200V, plotted in Fig. 6 and Fig. 7, respectively. As it can be seen
Ptot,max=1.2kW, fs=50kHz. In typical bridge-type isolated from the figures, the first input source provides 700W, while
converters, the duty ratio of the second stage, D2, is between the second one provides 500W to fulfill the load demand at
0.48 and 0.25. Since there is a limitation on the duty cycles in their respected minimum input voltages. On the other hand, the
the proposed converter, as stated in Eq. (21) and Eq. (22), power ratio becomes 1.23 when the voltages of the input
D1,max can be set to 0.7, where D1 becomes 0.2. In this case, sources reach to highest values. The selection of the power
D2,max is equal to 0.3. Using Eq. (27), the critical dc link ratio is completely dependent on the application needs, and it
voltage, Vdc,crt, is calculated as 500V; thus, Vdc,min is can be modified analogously. The total power supplied from
determined as 500V. From Eq. (24), transformer turns ratio is the input sources as a function of duty ratio and dc link
calculated as 0.75. voltages for V1=V1,min, and V2=V2,min is plotted in Fig. 8. As
Based on the condition given in Eq. (29), all possible L1 and expected, higher dc link voltage results in lower output power
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7
Transformer Primary and Input Inductor Voltages [V] Transformer Primary and Input Inductor Voltages [V]
500 400
vtr vtr
200
0 0
-200
vL2 vL2 -400 vL2 vL2
-500
(a) Time [4s/div] (a) Time [4s/div]
Input Boost Inductor Currents [A] Input Boost Inductor Currents [A]
20 20
15 iL2 15 iL1 iL2
10
iL1
10
5 5
0 0
-5 -5
(b) Time [4s/div] (b) Time [4s/div]
Transformer Primary and Output Inductor Currents [A] Transformer Primary and Output Inductor Currents [A]
15 itr 15
10 itr
5 5
0 iLo iLo
-5 -5
-10
-15 -15
-20
(c) Time [4s/div] (c)
DC Bus Capacitor Voltage Ripples [V] DC Bus Capacitor Voltage Ripples [V]
0.5 0.5
vC1
vC2
vC1 vC2
0 0
(d) Time [4s/div] (d) Time [4s/div]
DC Bus Capacitor Currents [A] DC Bus Capacitor Currents [A]
20 20
10 10
0 0
-10 iC1 -10 iC2
iC2 iC1
-20 -20
-30 -30
(e) Time [4s/div] (e) Time [4s/div]
Fig. 9. Simulation waveforms when V1=V2=150V, L1=200H, L2=100H; a) Fig. 10. Simulation waveforms when V1=150V, V2=50V, L1=L2=100H; a)
Transformers primary winding voltage, and input inductor voltages; b) Input Transformers primary winding voltage, and input inductor voltages; b) Input
boost inductor currents; c) Transformers primary winding current and output boost inductor currents; c) DC bus capacitor voltage ripples; d) DC bus
inductor current; d) DC bus capacitor voltage ripples; e) DC bus capacitor capacitor currents.
currents.
for the same output voltage. This figure is of significant IV. SIMULATION AND EXPERIMENTAL RESULTS
importance to evaluate the converters output power capability The simulations are performed to illustrate the operation of
at different dc link voltages. As it can be seen, the total power the converter with different set of parameters in MATLAB
drawn from the input sources can be adjusted for the given using SimPower Toolbox. The first simulation is conducted for
reference dc link voltage. same input voltage and different inductances, while the second
It should be noted that this part only illustrated a design one aims to illustrate the operation when inductances are the
framework for DCM operation; however, as stated earlier, one same with different voltages. The first set of parameters as
of the input sources can transit to CCM mode and supply the follows; V1=V2=150V, L1=200H, L2=100H,
rest of the demand power, which can be preferred in fuel cell C1=C2=100F, Lo=330H , fsw=50kHz. The results are shown
applications. Another point is that advantages of the proposed in Fig. 9. The second set of parameters are; V1=150V,
converter become more apparent when input voltages and dc V2=50V, L1=L2=100H, C1=C2=100F, Lo=330H,
link voltages are higher. The voltage specifications given for fsw=50kHz.
this design procedure and simulation results given in the In Fig. 9(a), it can be observed that even though same
following section are determined rather low to be suitable with voltage is applied to the inductors, the output power
the designed low voltage proof-of-concept prototype. contribution is different due to the chosen different
inductances. For this case, the output power is 1.6kW and
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8
duty ratio.
10V/div
S1
S2
S3
S4
20s/div
Fig. 12. Experimental waveforms of gate signals when D1=0.6, D2=0.35.
Fig. 11. Photo of the designed prototype.
5A/div
vdc 5A/div vdc
vtr 250V/div vtr iL2
100V/div
iL1
iL2 iL1
10A/div
10A/div
100V/div
5us/div 100V/div
20s/div
Fig. 13. Experimental results of dc link voltage, transformer voltage, input 14. Simulation results of dc link voltage, transformer voltage, input inductor
inductor currents when D1=0.6, D2=0.35, V1=70V and V2=90V. currents when D1=0.6, D2=0.35, V1=70V and V2=90V.
2A/div
iLo vo 25V/div
iLo
100V/div
vo
vtr 5A/div
100V/div
20s/div
vtr 5us/div 100V/div
Fig. 16. Simulation results of output voltage, transformer voltage, output
Fig. 15. Experimental results of output voltage, transformer voltage, output
inductor current when D1=0.6, D2=0.35, V1=70V and V2=90V.
inductor current when D1=0.6, D2=0.35, V1=70V and V2=90V.
S1 10V/div
iL2,pk>iL1,pk. The charging/discharging current of C2 is higher
than that of C1, resulting in asymmetrical voltage ripples S2
across two dc bus capacitors.
The corresponding results for latter simulation are given in S3
Fig. 10. As it can be seen from Fig. 10(a), the applied voltages
are different while the chosen inductances are same. For this
case, iL1,pk>iL2,pk and the capacitor charging currents and
S4
thereby the capacitor voltage ripples are replaced. It is worth 20s/div
mentioning that the feedback voltage signal should be
averaged over the switching period for capacitor voltage Fig. 17. Experimental waveforms of gate signals when D1=0.7, D2=0.25.
balancing.
Due to the asymmetry of the voltage source, the capacitor A low voltage laboratory built prototype has been designed
currents are different, resulting in different capacitor voltage and tested, as shown in Fig. 11, to serve as a proof-of-concept.
ripples. Like in any other multi-level converter, the capacitor The input inductances (L1=L2) are 87H each, dc link
voltages should be balanced. For the proposed converter, this capacitances (C1=C2) are 470F each. The output capacitor
(Co) is 220F and output inductor (Lo) is 200H. The
can be achieved by adding a compensating signal to the duty
secondary side of the transformer has a tapped winding
ratio of S1 and S4, which either extends or shortens its effective
configuration followed by a half-bridge rectifier. The
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9
transformer has 1:1 turns ratio for each secondary winding. in Fig. 17. In Fig. 18 and Fig. 19, both input source voltages
vdc 5A/div
vdc
5A/div
vtr 250V/div vtr
100V/div
iL2
iL1
iL2 iL1 10A/div
10A/div
100V/div
5us/div 100V/div
20s/div
Fig. 18. Experimental results of dc link voltage, transformer voltage, input Fig. 19. Simulation results of dc link voltage, transformer voltage, input
inductor currents when D1=0.7, D2=0.25, V1=70V and V2=70V. inductor currents when D1=0.7, D2=0.25, V1=70V and V2=70V.
0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2015.2424246, IEEE Transactions on Power Electronics
10
0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2015.2424246, IEEE Transactions on Power Electronics
11
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