IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO.
3, AUGUST 2009
A WIP Balancing Procedure for Throughput
Maximization in Semiconductor Fabrication
Jaewoo Chung and Jaejin Jang
AbstractIn a semiconductor fabrication line (fab), high
throughput often guarantees high revenue and profit since rel-
atively constant operating cost is required throughout the year;
however, maintaining high throughput has been a challenging task
due to complicated operational variables in a modern high-end
wafer fabrication line. To deal these variables, the industry has
developed a fab scheduling system consisting of several functional
modules that focus on different areas of decision making. WIP
balancing, which aims to prevent starvation of bottleneck toolsets,
has been an important component for fab scheduling. This re-
search proposes a new WIP balancing concept, which directly
considers load levels of bottleneck toolsets for higher throughput.
Also, an MIP (mixed integer programming) model is developed
for the new WIP balancing. A performance test shows that the
new approach increases throughput, especially when WIP level
and product routing flexibility are low.
Index TermsFabrication, load balancing, mixed integer pro-
gramming, scheduling, semiconductor, WIP balancing.
I. INTRODUCTION
GOOD scheduling system enhances the benefits of
A modern automated semiconductor fabrication lines
(fabs). It increases throughput while reducing work-in-process
(WIP) and enables earlier detection of process failures. With
less operator intervention in a standardized fab control, opera-
tions become more predictable and transparent.
Since a modern high-end wafer fab involves very complicated
operational variables, the fab scheduling system consists of sev-
eral functional modules that focus on different areas of deci-
sion making. Fig. 1 shows a fab scheduling system (left box)
and related fab operating systems (right boxes). This and other
similar structures [1] are being used in industry. While a plan-
ning system makes long-term production plans at an aggregated
level, a scheduling system makes a shorter production schedule
with more frequent updates [1], [2].
In Fig. 1, the WIP balancing module in the scheduling system
determines target production quantity for each layer, defined as
a set of several sequential processing stages such as deposition,
etching, metrology, and litho stage at its end. Based on this quan-
tity, detailed schedules of each lot, toolset, and toolset group are
Manuscript received May 23, 2008; revised February 24, 2009. First pub-
lished July 07, 2009; current version published August 05, 2009.
J. Jang is with the Department of Industrial and Manufacturing Engineering,
University of Wisconsin-Milwaukee, Milwaukee, WI 53211 USA (e-mail:
jang@uwm.edu).
J. Chung was with the School of Industrial Engineering, Purdue University,
West Lafayette, IN 47906 USA. He is now with the School of Business Ad-
ministration, Kyungpook National University, Daegu 702-701, Korea (e-mail:
chung@knu.ac.kr).
Digital Object Identifier 10.1109/TSM.2009.2017666
0894-6507/$26.00 2009 IEEE
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381
made by other modules in the scheduling system. The lot-based
scheduling module in the figure makes very detailed schedules
for both individual lots and toolsets, based on the target produc-
tion quantity. The area scheduling module, which focuses on
specific processing areas such as photolithography (litho), dif-
fusion, etching, and deposition areas, also makes detailed sched-
ules by assigning the target production quantities to toolsets
based on detailed process constraints. While the WIP balancing
module focuses on longer term performance criteria, these de-
tailed scheduling modules focus on short term ones. Sometimes
rescheduling is required when unpredictable disturbances occur
[3][5]. Also, simulation helps fab scheduling by estimating
gaps between scheduling and its implementation. The sched-
uling system guides the lot dispatching system [6][10] and the
automated material handling system (AMHS) at its lower hier-
archy.
WIP balancing has been widely used to achieve high utiliza-
tion of toolsets in a fab [12], [31]. Performance measures in
a fab are very complicated because of such characteristics as
long ramp-up period, frequent product change, high product-
mix, reentrant flow, batch process, setup time and mask allo-
cation. Consequently, fab managers often use indirect perfor-
mance measures to increase operational efficiency. The conven-
tional view regards the uniformity of WIP levels of processing
stages based on flow times as an important criterion because
it potentially increases toolset utilization and decreases waiting
time of wafers in storage. This research proposes a new WIP bal-
ancing concept and a procedure called the toolset available WIP
balancing (TAWB) to foster efficient fab scheduling, specifically
for the litho stage, the bottleneck in most fabs. The new WIP
balancing concept considers two main factors: load levels of
litho toolsets and the target production volumes from the plan-
ning system. In previous studies, the load levels of toolsets were
not considered for WIP balancing; hence, an already overloaded
bottleneck toolset often gets even more wafers. The detailed
method and benefits of TAWB are explained in Section III-B.
TAWB is different from existing WIP balancing methods in
two aspects.
1) New WIP balancing measure: The new measure uses the
routing flexibility of each litho layer (measured by the
number of toolsets that can process the litho layer). It also
uses the current WIP level of an individual litho toolset
while conventional methods use the WIP level of each litho
layer.
2) Relaxing planning requirements: Lee et al. [11] pointed
out that module lines often use a pull system while fab
lines use a push system; as a consequence, a large amount
of WIP often piles up between them. Also, there are bin-
ning, substitution, and product branch-off at the end of the
382
Fig. 1. Fab operating systems.
fab lines (see the last part of this section). Fab lines and
module lines are often located far from each other, some-
times belonging to different companies. All these factors
make the synchronization of fab and module lines diffi-
cult; therefore, following the production guide from plan-
ning too closely can give unnecessarily tight constraints to
scheduling. The method proposed in this paper relaxes re-
quirements from production planning, i.e., the target pro-
duction volume (Fig. 1), to maximize throughput.
In a semiconductor manufacturing system, the front-end (fab)
has more than 400 processing stages and uses more than 85%
of the systems time and resources. In a fab, about
of the lots waiting time and WIP are observed in front of the
bottleneck stage, i.e., litho stage [12]. Each layer on a wafer
requires its own mask (reticle) at this litho stage, and a mask
change requires a non-negligible amount of setup time.
The litho process is so sensitive that one layer can only be
processed by a few dedicated toolsets approved after a series
of tests using send-ahead lots or test wafers. This dedication
limits the wafers routing flexibility. The average up time of a
litho toolset, including its idle time, is more than 90%. A litho
toolset has about of unscheduled down time [13] with
1020 days of MTBF (mean time between failure). Although
this uptime rate is relatively high compared with other indus-
tries, its random disturbance has been regarded as an important
characteristic [14], apparently because of the high standard of
reliability for the expensive toolsets and the low routing flexi-
bility.
The back-end (module line) makes final products. One type
of wafer from the front-end (fab) possibly becomes tens of dif-
ferent semiconductor products, or branches-off, depending on
the attached materials, the required specifications of products
and others. Chips are graded, or binned, by their quality, such as
clock speed. Sometimes higher binned chips are downgraded,
or substituted, to meet the due date of lower binned chips.
Branch-off, binning, and substitution make tight synchroniza-
tion of front-end and back-end production difficult and less
relevant.
Section II reviews previous studies on fab scheduling. In Sec-
tion III, we develop the TAWB procedure and illustrate the use
of the TAWB in an area scheduling module. Section IV com-
pares the new method with two existing methods.
II. PREVIOUS RESEARCH
From the 1980s to the early 1990s a large number of studies
focused on a single operational aspect of fab scheduling (e.g.,
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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 3, AUGUST 2009
lot releasing, due-date scheduling, batch scheduling, WIP bal-
ancing or load balancing). Since the mid 1990s, integrated so-
lution procedures were proposed, often based on hierarchical
approaches.
Lot releasing methods attempted to avoid starvation of bottle-
neck toolsets by using the flow rate of a layer [16], [17]. For load
balancing, mathematical programming and heuristic methods
were frequently used, considering detailed operational aspects
such as the toolset setup time and the number of available masks
[19][22]. Batch processing, which is common at such stages as
diffusion, oxidation, litho and wet bench, was also studied [14],
[23][26]. Look-behind and look-ahead approaches were fre-
quently used to form a batch [16], [25]. Some studies focused on
due-date scheduling for ASIC (application-specific integrated
circuit) manufacturers and foundry companies [27][29].
The integrated approaches focused on multiple performance
measures. Bai et al. [30] recognized the complexity of fab
scheduling and proposed a hierarchical framework. Vargas-Vil-
amil et al. [31] proposed a three-layer hierarchical approach
based on integrated product, optimization and dispatching
steps. Based on the flow rate control procedure, the TB (two
boundary) algorithm was introduced by Lou and Kager [17],
and its robustness was confirmed by Yan et al. [32]. The
TB algorithm tried to make surplus, the difference between
planned and actual production, zero to determine TPQ (target
production quantity) at the end of a shift. Many hierarchical
approaches were developed based on the TB algorithm for
WIP balancing [12], [18], [33][37]. Lee et al. [12] proposed
scheduling methods for lot release, WIP balancing, and load
balancing based on a modified TB method. In industry, gaps
between planning and scheduling were frequently observed,
and some studies proposed daily planning procedure as an in-
termediate decision step of long-term planning and scheduling
[32]. Dabbis et al. [35] proposed a dispatching-based sched-
uling that integrated WIP balancing (global criteria) and several
dispatching criteria (local criteria) using a linear combination
of these criteria.
III. THE NEW WIP BALANCING METHOD: TAWB (TOOLSET
AVAILABLE WIP BALANCING)
In this section, we develop a new WIP balancing method
called TAWB (toolset available WIP balancing) and illustrate
use of the TAWB in an area scheduling module that centers
on the bottleneck stage, photolithography (litho). (See [4], [5],
[12], [27], [36], [37] for other bottleneck scheduling methods.)
The new method in this section also shows by an MIP model
CHUNG AND JANG: A WIP BALANCING PROCEDURE FOR THROUGHPUT MAXIMIZATION IN SEMICONDUCTOR FABRICATION 383

TABLE I
CALCULATING LAYER DEMAND (FOR PRODUCT i)

how the WIP balancing module cooperates with the area sched- TABLE II
uling module to maximize throughput of the current shift and SCHEDULING INPUT DATA FROM MES
the following shifts as well. The higher throughput in the bottle-
neck stage eventually creates higher actual production quantity
(fab-out volume) over the long term. The detailed MIP modeling
may need to adjust to reflect specifics of each fabrication site.
A. Input for the New WIP Balancing Procedure
The new procedure receives input from the planning system
and the manufacturing execution system (MES) (Fig. 1). The
production planning system determines target production
volume for each of the front and back end, product type and
time bucket. The time horizon and time bucket of planning
vary from two months to a year and from a day to a week,
respectively. Based on the target production volume, the WIP
balancing module in the scheduling system determines target
production quantity (TPQ) for each product type and process
stage. Generally, its time horizon is a few months and its time
bucket is a shift.
Tables I and II show an example of input data for WIP bal-
ancing. The weekly target production volume is given for
each week in Tables I and II shows the flow times, current WIP
levels, and toolset dedications for each layer of a product, or a
layer in short, which are available from the manufacturing exe-
cution system (MES).

B. Overview of the TAWB Procedure

This section overviews the detailed WIP balancing processes
presented in Part C and Part D in Section III. Fig. 2 shows a flow
chart of the new WIP balancing procedure, consisting of four
sub-modules (M1 to M4). M1 calculates layer demands, i.e.,
standard production quantities, for layers based on the layers
flow times (times from lot release to fab-out) and target produc-
tion volumes given by product types from the planning system
(Table I). M2 calculates the lateness indices for layers, which in-
dicate urgency for processing, and M3 calculates the upper-limit
production quantity (UPQ), the maximum allowed production
quantity, based on the layer demands from M1 and the current
WIP levels. Finally, M4 determines the target production quan- Fig. 2. Flow chart for the proposed WIP balancing procedure.
tity (TPQ) of each layer using a new MIP model and assigns
available WIP of each layer to litho toolsets based on the late-
ness and UPQ. The new MIP model internally uses the concepts calendar time until the designated fab-out time internally spec-
of LAW (layer available WIP) and TAW (toolset available WIP) ified by the planning system. If the lateness of a layer is larger
to be explained below, for better WIP balancing. M1 and M2 than a certain limit, it is assigned to at least one toolset for pro-
have been used by many other researchers, while M3 and M4 duction in the MIP model (constraint (14) in Part D in Sec-
are new in this research. tion III). In M3, the UPQ is obtained from a modified method
In M2, the lateness index for each layer is the difference be- of the two boundary heuristic [17]. The resultant UPQ in a shift
tween its remaining flow time until fab-out and the remaining can be larger than the production capacity of the litho toolsets;

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384 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 3, AUGUST 2009

2) Input Data:
: Setup time of the litho toolset.
: Flow time of product , layer (including average
waiting time in days).
: Sum of flow time of product from layer to final
layer including the flow time of layer .
: Number of available masks for product , layer .
: Wafer processing time of product , layer on litho
toolset .
: Average wafer processing time of litho toolsets for
product , layer .
: Average wafer processing time on litho toolset .
: Initial processing layer index. If toolset is
Fig. 3. Layer WIP balancing versus toolset WIP balancing. processing product , layer at the beginning of the
current shift, ; otherwise, .
: WIP level of product , layer at the beginning of
TABLE III
CALCULATION OF UPPER-LIMIT PRODUCTION QUANTITY (UPQ) AND TOOLSET the current shift.
AVAILABLE WIP (TAW) (FOR PROJECT i) : Target production volume for week given by the
planning system.
: Layer demand for product , layer .
: Weight value of layers, if is the last layer of
product i; otherwise, .
: Toolset dedication. If product , layer can be
processed at toolset , ; otherwise, .
: Upper-limit production quantity (UPQ) for product
, layer .
: Current lateness (days) of WIP of product , layer
.
3) Decision Variables:
this loosened upper limit of the production quantity gives some
flexibility for determining TPQ and is used to increase actual : Production quantity for product , layer from toolset
production quantity by the MIP model. during the current shift.
Sometimes, starvation can not be avoided even with good : WIP of product , layer at the end of a shift.
WIP balancing from the two boundary method because of the : Production assignment. If , ;
low routing flexibility of wafers, as is illustrated in Fig. 3 and otherwise, .
Table III. UPQ in Table III [and Fig. 3(a)] represents a conven-
tional WIP balancing status based on layers, which we call layer C. Determination of Layer Demand, Layer Lateness, and UPQ
WIP balancing. There are six layers, L1 to L6, in the table. In the
1) Layer Demand Calculation (M1 Module): Layer demand
last row of Table III [and Fig. 3(b)], we have another possible
is the weekly target production volume times the flow time of
WIP balancing status based on toolsets, which we call toolset
the layer divided by 7 if the flow time of the layer is covered by
available WIP balancing. There are also six toolsets, T1 to T6 in
one weekly target production volume:
the table. Although this layer WIP balancing looks good, since
all layers have similar WIP levels, the toolset available WIP bal-
ancing in Fig. 3(b) is poor, since T1, T2, and T6 have much
higher WIP levels than T3 and T4, and the toolsets 3 and 4 can (1)
be idle soon. In Table I, . If the flow time
The new MIP model calculates TPQ to maximize throughput of a layer is covered by two weekly target production volumes,
for the current shift and maintain good toolset available WIP a layer demand is determined based on the proportion of the
balancing to ensure the maximized throughput during the fol- weeks over the layers flow time, i.e.,
lowing shifts. The following notations are used in this model.
1) Data Sets: if or
and (2)
: Set of products.
: Set of layers of product , . where and are the parts of in the 1st and
: Set of litho toolsets. 2nd weeks, respectively. If the flow time of layer 9 has
0.5 days in week 1 and 1.5 days in week 2 in Table I,
: Set of weeks for demands.
. The subscript that

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CHUNG AND JANG: A WIP BALANCING PROCEDURE FOR THROUGHPUT MAXIMIZATION IN SEMICONDUCTOR FABRICATION 385

TABLE IV In Table III, (here, it is assumed that

CALCULATION OF LATENESS AND UPQ (FOR PROJECT i) 800 is the WIP level at the end of the previous shift). The TAW
(toolset available WIP) in formula (5) of a tool set is a sum of
the above average WIP levels ( s) for the tool set.
: Toolset Available WIP for Toolset

(5)

In Table III, . Now, the Toolset

Available WIP Balancing is measured by the deviation of TAW
of each toolset from the average TAW of all toolsets, i.e.,
appears on the right side of (1) and (2) does not appear on the , where AAW is defined by (6).
left side because is a function of and in the if part of the : Average Available WIP for all Litho Toolsets:
equation.
2) Lateness Calculation (M2 Module): This index shows
(6)
how much the layer production is behind schedule. If cumula-
tive demand for a layer is larger than its cumulative WIP, late-
ness is increased by its flow time, . In Table IV, The above indices are used in the MIP model in the next section.
( is less than , so is in- 2) MIP Objective Function: The objective function has two
creased by ). parts: one for the difference between the UPQ and scheduled
3) UPQ Calculation (M3 Module): This procedure uses two quantity (for the throughput maximization of the current shift),
types of demand: rolling and pulling demand for the calcula- and the other, , for WIP balancing at the end of
tion of UPQ. The rolling demand for a layer is the sum of the the current shift (to ensure the high throughput of the following
layer demand from the current layer to the last layer. The pulling shifts). For higher fab-out volume (actual production quantity),
demand is the layer demand during the pulling period, which more weight is given to the last layer of a product (i.e., ,
is assumed to be the preceding two days in this research. The and if ). In (7), is the relative weight of WIP bal-
pulling period (two days) is a parameter that can be changed by ancing, which will be determined empirically reflecting the de-
users. As discussed in Part B in Section III, by using the pulling tailed conditions of each problem (see Part C in Section IV).
demand, the production demand might be loosened; however, The objective function of the MIP model is
the scheduling flexibility increases in the MIP model. Conse-
quently, throughput might be also increased by reducing setup
times of toolsets. (7)
In Table IV, the rolling demand for layer 4 is 3) MIP Constraints:
, and the pulling demand is (layer 3s demand for Production quantity constraint. Production quantity cannot
1.5 days) (layer 2s demand for 0.5 days) exceed the available WIP:
. The UPQ for each
layer is rolling demand plus pulling demand minus the sum of (8)
WIP from its next layer to the last layers:
Toolset setup index. If there is production during a sched-
(3) uled shift (i.e., ), then ; otherwise,
:

where is the pulling demand of product i, layer j. In (9)

Table IV, .
where is a large number.
D. Determination of TPQ: MIP Model Toolset time constraint. The sum of production time and
setup time cannot exceed the production capacity of a
Here, we first introduce a few indices for the TAWB (tool
toolset. Here is the time bucket (e.g., 8 h):
available WIP balancing) procedure.
1) TAWB Measure: For the WIP balancing, we first define
WPT (WIP per toolset) for a layer as its average WIP per toolset
that can process the layer. In formula (4), , WIP of product
i, layer j at the end of a shift, is a decision variable of the MIP
model. (10)
: WIP Level of Product , Layer Per Toolset:
Balance equation for WIP. The WIP at the end of the shift
(4) is the WIP at the beginning of the shift plus assigned quan-
tity of the previous layer minus the assigned quantity at the

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386 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 3, AUGUST 2009

current shift. Also, the WIP of the 1st layer at the beginning of a toolset divided by the batch size . is the
of a shift is the same as the release quantity of the layer: capacity of toolset for the shift.

(18)

2) Small WIP assignment. A layer whose WIP is less than one

(11) lot is not assigned to any toolset:
where is the newly released quantity of product [12],
if (19)
[16].
UPQ constraint. Production quantity of a layer cannot ex-
ceed its UPQ: 3) Large WIP assignment. A layer that has two times higher
WIP than a toolset capacity is assigned to at least one
(12) toolset. This assignment happens in most cases even
without bounding; however, this constraint reduces the
computation time:
Mask constraint. The number of assigned toolsets to a layer
cannot exceed the number of masks for the layer:
if (20)
(13)

Lateness constraint. If lateness of a layer is larger than two

days (can vary depending on a site), at least one toolset is Assumptions and Discussions of the Proposed MIP Model
assigned to the layer: 1) One simplification assumption of the model is that the en-
tire WIP is available at the beginning of each shift, which
if and (14) can give slightly higher TPQ than the true optimum. This
discrepancy can be adjusted by the detailed scheduling
modules explained in Section I.
where is batch size (e.g., number of wafers in a carrier)
2) If a toolset is already broken down or scheduled to be down,
determined externally.
this can be reflected in constraint (10). Unscheduled toolset
Toolset dedication constraint. If a toolset cannot process a
downtime can also be reflected in the constraint based on
layer of a product, the binary variable of the assignment is
historical data if needed.
set at zero:
3) The model assumes that the same types of layers are pro-
cessed together without setups between them. However,
when (15) the number of actual setups cannot be known in advance
because the lot processing sequence is determined by the
Current processing layer constraint. If a toolset is already lot dispatching system after WIP balancing. Based on es-
processing a lot at the end of the last shift, it continues timation, the adjustment of the setup time can be made in
to process the lot at the beginning of the next shift; the the model by changing the term in
corresponding assignment variable is set to unity: constraint (10) to , where re-
flects the estimated number of additional setups.
and 4) Constraint (13) says that the number of assigned toolsets
(16) to a layer cannot exceed the number of masks for the layer
during a shift. Although a mask can be used for multiple
Restrictions on variables: litho toolsets during one shift, when a toolset uses a new
mask, it usually needs a test, which takes much time. If a
layer is relatively easy to process or when a mask was used
(17) by the new toolset recently (e.g., within two to three hours),
the test can be skipped. If it is desired for a layer not to have
this constraint, the (13) for this layer can be removed from
the model.
E. Adding Bounds
5) is used in constraint (18) to reduce the computation
To reduce its computation time, this MIP model bounds the time. Equation (18) does not affect the model solution. If it
range of variables. is not convenient to calculate this average value, the min-
1) The number of scheduled layers. The number of layers for a imum of over all and can be used for conser-
toolset to process during a shift cannot exceed the capacity vatively.

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CHUNG AND JANG: A WIP BALANCING PROCEDURE FOR THROUGHPUT MAXIMIZATION IN SEMICONDUCTOR FABRICATION
TABLE V
TOOLSET FLEXIBILITY AND PART MIX (NUMBER OF AVAILABLE LITHO TOOL SETS/LAYER)
6) While the performance test in the next section assumes four
product types, some fabs in practice produce more than
four product types at a specific scheduling period; however,
the problem size is not increased much by this because,
as the number of product types increases, the production
quantity per product type decreases due to the capacity
of the fab. A product type with less production quantity
has fewer available toolsets; therefore, based on constraint
(15), the number of non-constrained integer variables in
this MIP model remains at a similar level.
IV. PERFORMANCE TEST
A. Test Case
In this section, we compare the TAWB method and other two
ones, the TBH (two boundary and heuristic) method [17] and
the TBMIP (two boundary and MIP) method [29] for fab sched-
uling. These two methods use hierarchical approaches for WIP
balancing and toolset assignment. These two methods also use
the same WIP balancing algorithm, the TB algorithm. For the
toolset assignment, the TBH method uses a heuristic algorithm
while TBMIP uses an MIP model.
The test case is a fab having 35 K WSPM (wafer starts per
month), four product types, and 25 layers for each product type.
There are 50 litho toolsets with two types of wafer processing
time (25 toolsets with 140 s, and another 25 toolsets with 150
s).
One test case runs for 21 shifts (7 days), and the scheduling
result of a shift is used as input for the next shift. A production
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387
quantity in a shift is regarded as an actual production quantity in
the next shift after a disturbance rate is multiplied. The distur-
bance rate, which is from a uniform distribution between 0.73
and 1.21, reflecting real production, makes actual production
quantity be smaller or larger than a scheduled quantity. (Note
that this value can be larger than one.) The test results are the
same as a 3% less production quantities than scheduled quanti-
ties. (The test using other distributions such as a triangular dis-
tribution give similar test results.)
The test also considers the different toolset flexibility and
WIP levels, which are shown in Table V. Each layer can be
processed by a specific set of tools (dedication). In the table,
product type A has higher flexibility on average than the others
because of its larger target production volume given by the fab
planning system shown in Fig. 1. The test uses three WIP levels,
low, medium, and high, which have 1200, 1800, 2400 wafers/per
layer, respectively.
Fig. 4 shows a simplified WIP modeling. A layer consists of
three consecutive WIP stages: W1, W2, and W3. All WIP in the
first and second stages (W1 and W2) move to the next stages
during a shift. The amount of WIP in W3, which wait for litho
machines, is multiplied by the disturbance rate and becomes the
first WIP of the next layer at the next shift. The same number
of wafers as the fab-out volume at the previous shift is newly
released to the fab at the current shift as the WIP of the first layer
for each product. This test realistically assumes 10 min of setup
time for litho toolsets. The weight value of the objective function
of the TAWB model, in (7), is set to 0.01 (more explanation
on value is given in Part C in Section IV).
388
Fig. 4. WIP flows in test model.
Fig. 5. Average throughput rates of different scheduling methods under dif-
ferent flexibility levels.
CPLEX is used to solve the TAWB and TBMIP models. The
parameters in the solver such as EpGap and ObjDif for relative
optimality tolerance [38], and TiLim are carefully tuned for the
computation time. The maximum solution time of TAWB and
the other MIP models is limited to 15 min, which was deter-
mined after referencing a few semiconductor companies. If an
optimal solution is not found within 15 min, the best solution
until that time is used.
B. Performance Comparison
The performance criteria are throughput rate and the lateness
of wafers.
1) Throughput: Fig. 5 compares throughput (number of
wafers produced by litho toolsets in a shift) of three methods
at three different flexibility levels given in Table V and at the
medium WIP level. The largest throughput is observed from the
TAWB method, and the throughput difference between methods
is larger as the flexibility decreases. At a high flexibility level,
the throughput difference between the TAWB and TBMIP
methods is 28 wafers per shift, which increases to 218 and 403
wafers under medium and low flexibility level, respectively.
The change of throughput of each method is larger be-
tween medium and low flexibility levels than between
high and medium flexibility levels, even though the dif-
ference of the number of available toolsets per layer be-
tween high and medium flexibility cases is larger than that
between medium and low flexibility cases. (In Table V,
the average numbers of available toolsets per layer are
, ,
and for low, medium and high
flexibility cases.) It is worth noting that the flexibility of litho
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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 3, AUGUST 2009
Fig. 6. Average throughput rate of different scheduling methods under different
WIP levels.
toolsets will get lower with the recent nano-process technology
because of the tighter process control.
Fig. 6 shows throughput at different WIP levels under the
medium flexibility level. Again, the throughput of the TAWB
method is the highest; in particular, when the WIP level is low,
the difference is larger. At the high WIP level, the average
throughput difference between the TAWB and TBMIP methods
is 334 and increases to 1,531 wafers per shift under the low
WIP level.
The sum of the average assigned quantities of the TAWB
method for 21 shifts is 9876 wafers at the medium WIP and
flexibility levels, while it is 9448 for the TBH, and 9659 for the
TBMIP. Since the capacity of litho toolsets is 9950 wafers per
shift, the TAWB case corresponds to about 0.7% of throughput
loss from setup and starvation time. Among the 0.7%, about
0.3% is used for setup, and 0.4% for idle time. The utilization in
case of the TAWB method is about
4% higher than the TBH method
and 2% higher than the TBMIP method
, which is very significant in practice.
2) Late Quantity: We define the average late quantity as the
quantity for 21 test shifts being delayed for more than two days.
Fig. 7 shows the average late quantity for different methods at
different flexibility levels and at the medium WIP level. The
late quantity of the TBH method is much higher than that of the
other two methods, implying that the TBH method cannot meet
the required target production volume. The late quantity of the
TBMIP method is slightly lower than that of the TAWB method.
The average late quantity of the TAWB method is 1211 wafers,
which is about 3.4% of total WIP (about 36 000 wafers) and
higher than that of the TBMIP method by about 1.7%; however,
it is still low enough when we consider uncertainty in the target
production volume from planning and the characteristics of the
semiconductor production explained in Section I. Note that the
due date is set internally by the back-end, and the increase of
the late quantity from medium flexibility to low flexibility of
TAWB is much smaller than that of TBMIP.
C. Determination of Weights
We tested different G values in (7) to determine the best
weight under various flexibility and WIP levels. Fig. 8 shows
changes of average throughput for 21 shifts with different G
values. High throughput is observed when G is between 0.005
and 0.05 in most cases, the best at 0.01. When the G value
CHUNG AND JANG: A WIP BALANCING PROCEDURE FOR THROUGHPUT MAXIMIZATION IN SEMICONDUCTOR FABRICATION
Fig. 7. Average late quantity of different scheduling methods under different
flexibility levels.
Fig. 8. Weight value test.
gets larger than 0.05, the throughput decreases because toolsets
sometimes do not produce wafers to maintain good WIP bal-
ancing. G was set to 0.01 in the performance test. This value is
expected to be good for most full size fabs, for example the fabs
with 35 WSPM and 50 litho toolsets; however, a simulation
study is recommended reflecting actual fab conditions for the
determination of the best G value.
D. Computational Issues
The MIP model of the TAWB method has 5000 binary integer
variables, and the sparseness is about 0.0001206 under medium
flexibility and WIP levels. The effect of the bounding constraints
in the TAWB model on computation time and optimality gap
is examined. Here, gap is defined as (best integerbest LP
node)/best integer [38]. Without bounding constraints, the av-
erage gap for 21 shifts is 0.23%, and the average computation
time is 6.97 min. The average gap decreases to 0.18% and av-
erage computation time to 4.52 min with constraints. Optimal
solutions are often found (about a 20% was solved optimally
and 50% was solved within a 2% gap) before the 15-min limit
with bounding. Stronger bounding would be possible consid-
ering specifics of each fab.
V. CONCLUSION
Semiconductor fab scheduling has been regarded as one of
the most difficult problems in production systems control. Fab
scheduling begins with information from the planning system.
While planning cannot develop very precise production deci-
sions due to the complexity and uncertainty in a fab, most ex-
isting WIP balancing methods try to follow due-date targets
from planning too tight. The new scheduling approach, TAWB,
introduces a new concept of toolset available WIP balancing
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389
(TAWB) and relaxes the requirement from planning by using
the UPQ (upper-limit production quantity). Although the TAWB
method considers only the bottleneck stage, scheduling of other
stages such as diffusion, implantation, deposition, and etching
can be determined by targeting meeting the litho stage sched-
ules. The target production quantity calculated in this research
can guide detailed scheduling in the scheduling system shown
in Fig. 1.
In the future research, authors are interested in developing a
more detailed MIP model with precedence constraints of wafer
batches. This model will require longer computation time. How-
ever, practical bounding constraints from semiconductor pro-
duction can substantially reduce the computational time as ob-
served in the current research. Combining these bounding con-
straints with MIP-based heuristics [39] would be explored in
future study.
ACKNOWLEDGMENT
The authors would like to express sincere appreciation to Dr.
J. M. A. Tanchoco at the Department of Industrial Engineering,
Purdue University, West Lafayette, IN, for his advice on this
work. He helped the authors present this work better.
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Jaewoo Chung received the B.S. degree from
Sungkyunkwan University, Korea, in 1995, the M.S.
degree from the University of Wisconsin-Milwaukee
in 2004, and the Ph.D. degree from Purdue Univer-
sity, West Lafayette, IN, in 2008, all in industrial
engineering.
He worked for LCD/Semiconductor division at
Samsung Electronics for eight years on production
scheduling and dispatching, automated material
handling, and design and simulation of fab layouts.
He is currently an Assistant Professor of Opera-
tional Management in the School of Business Administration at Kyungpook
National University, Daegu, Korea. His areas of interests are the semicon-
ductor/LCD/solar cell manufacturing systems, logistics planning, material
handling automation and facilities layout, and combinatorial optimization.
Jaejin Jang received the B.S. degree in industrial
engineering from Seoul National University, Seoul,
Korea, in 1984, the M.S. degrees in industrial engi-
neering and operations research from Seoul National
University, in 1986 and the University of California,
Berkeley, in 1989, and the Ph.D. degree in industrial
engineering from Purdue University, West Lafayette,
IN, in 1993.
He worked for Samsung Electronics and Hankuk
University of Foreign Studies from 1994 to 2001.
From 2001 to 2002, he was a visiting professor
and researcher at Purdue University. Since 2003, he has been an Associate
Professor in Industrial Engineering Department at the University of Wisconsin,
Milwaukee. His areas of interest include scheduling and real-time resource
management.