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Summer 2007 | Issue 2
Article Topics
Defect Management
Metrology
Fab Economics
Mask
Data Storage
Product News
The 45nm Innovation Challenge

This issue of YMS magazine features a range of articles related to 45nm
inspection and metrology, from the latest in mask inspection technology
to unique cases involving the application of specialized metrology wafers
Contents
1
Featured Articles 7
D efect M anagement 8
3 A New Approach to Identify Large, Yield Impacting 9
Defects on Polished Si Wafers 10

Hynix Semiconductor Corporation and KLA-Tencor Corporation 11
12
8 Etch Process Monitoring by Electron Beam Wafer Inspection 13
Powerchip Semiconductor and KLA-Tencor Corporation
14
15
11 Enabling Manufacturing Productivity Improvement and
16
Test Wafer Cost Reduction
17
KLA-Tencor Corporation
18
M etrology
14 Wafer-Level Metrology Expands Process Applications at 45nm 19
KLA-Tencor Corporation 20
21
19 Spectroscopic Ellipsometry Film Metrology Braces for 22
45nm and Beyond 23

F ab E conomics 25
24 Reducing Cycle Time Has Many Benefits 26
KLA-Tencor Corporation
27
M ask 28
27 Field Results from 45nm Die-to-Database Reticle Inspection
29
Toppan Printing Co., Ltd, Advanced Mask Technology Center GmbH & Co and KLA-Tencor Corporation
D ata S torage 30
34 Applications of a Laser-Assisted Defect Detection System 31
for CMP Slurry Development in Rigid Disk Polishing 32
34
42 Product News 35
Editor-in-Chief
Charles Lewis 36
Contributing Writers 37
Becky Pinto
Reeti Punja 38
Lisa Garcia
39
Production Editor
40
Robert DellaCamera
41
Art Director and Yield Management Solutions is published by KLA-Tencor Corporation.
Production Manager 42
Inga Talmantiene To receive Yield Management Solutions www.kla-tencor.com/ymsmagazine
43
Production Consultant For literature requests, visit: www.kla-tencor.com/products
Jovita Rinkunaite 44
Circulation Editor 2007 KLA-Tencor Corporation. All rights reserved. Material may not be reproduced without permission from KLA-Tencor Corporation.
45
Cathy Silva Products in this document are identified by trademarks of their respective companies or organizations.
46
Summer 2007 Yield Management Solutions | www.kla-tencor.com/ymsmagazine
F eature S tory
1
A New Approach to Identifying 5
Large, Yield-Impacting Defects 7
on Polished Si Wafers
9
10
11
Kerem Kapkin, KeunSu Kim, Jason Saito, Hyosik Suh KLA-Tencor Corporation
Chung Geun Koh, Dae Jong Kim, Byeong Sam Moon, Seung Ho Pyi Hynix Semiconductor Corporation 12
13
14
15
16
For 45nm-generation wafers, innovations in bare wafer inspection technology provide enhanced capture and
17
classification of large, shallow defects. New classification technology, combined with multi-channel processing, enables 18
wafer manufacturers and IC device makers to find and separate these defects into categories based on whether they are 19
cleanable, or require scrapping the wafer. Identifying these defects early in the manufacturing process enables improved 20
21
product quality and higher yield.
22
As devices continue to shrink, wafer surface condition, defect identify and sort out wafers with LLPDs before beginning 23
size, shape and type are becoming increasingly important device processing. 24
factors in device yield, performance and reliability. ITRS (Inter 25
national Technology Roadmap for Semiconductors) guidelines Wafer manufacturers need to detect, accurately identify and
stipulate a sensitivity to critical defects on a bare wafer surface separate these defects from the background population of large 26
of a size equal to one-half the design rule. particles, which may be cleaned or reworked, while avoiding 27
unneeded wafer rejection. Also, since LLPDs are a result of
28
At the same time, IC manufacturers have been reducing the various wafer manufacturing process issues, wafer manufactur-
specification for the total number of defects allowed for accep- ers must quickly identify the LLPD root cause and implement 29
tance of incoming wafers and are now specifying limits on the fixes to prevent unnecessary wafer scrap. 30
number of large light point defects (LLPDs). These LLPDs are
In this article, we demonstrate a method for classifying these 31
large but very shallow: they may be several microns wide but
have a height of only a few nanometers. LLPDs are generated critical LLPDs by utilizing a new unpatterned wafer inspection 32
both during single-crystal silicon ingot growth and during system, the Surfscan SP2XP. The systems latest technologies
33
the subsequent wafer-making and surface-preparation pro- of GC (global composite) and RBB (rules-based binning) have
proven effective for both the wafer manufacturers final inspec- 34
cesses. These LLPDs manifest themselves on incoming bare
silicon wafers in the form of faceted pits or bumps, air pockets tion step and IC device manufacturing IQC (Incoming Quality 35
and polishing scratches, and have a very high likelihood of Control) applications. 36
becoming yield killer defects. Thus, IC manufacturers must 37
Particle COP Residue Scratch 38
39
40
41
42
43
0.1m 0.1m 0.1m 0.1m
44
Figure 1: Conventional defects or LPDs (Light Point Defects) which require increased sensitivity for detection and classification. 45
46
F eature S tory
Wafer Defect Types and Their Sources 1
Conventional small (sub-micron) defects that impact device Large defects (~16m) 2
yield include particles, COPs (crystal originated pits or 3
particles), residues and scratches, and are well characterized. 4
Examples of these defect types are pictured in Figure 1. Large
particle defects on the wafer may originate from handling 5
contamination, process equipment, or from the cleanrooms 6

ambient environment. Many of these can be removed with 7
various cleaning processes.
8
LLPDs are more challenging to identify and characterize. A Figure 3: Emerging (faceted) LLPD defects (polishing related defects,
9
typical simplified Si wafer production scheme is shown in air pockets and etch-related defects, respectively).
10
Figure 2. The source of faceted LLPD defects can be divided
into two primary groups: the crystal-growing process and the 11
important defect type on bare Si wafers faceted LLPDs
wafering process. (Figure 3). The most critical faceted LLPD is the air pocket 12
defect, which forms during the crystal-pulling process and is 13

distributed across the wafer within the silicon substrate. The
The Surfscan SP2 inspection XP
size of the air pocket exposed to the surface is a function of
14
15
system can identify large light point its location and how much has been revealed during cutting
and polishing of the wafer. While exposed air pockets can be 16
defects by type, size and number. measured in various sizes as pits, the buried ones in the bulk 17
remain as voids.
18
Other types of faceted defects are created by either mechanical or 19
Previously, the full spectrum of LLPD defects could not be chemical damage during etching or polishing steps. Although
separated by type or source and could only be categorized as 20
they are limited to the wafer surface and do not exist within
one group based on their darkfield scattering signatures. the substrate, they can affect implant profile, device topogra- 21
However, their identification and classification by individual phy and electrical properties, which can destroy a die. Some 22
type is very important. Wafer manufacturers can use this infor- faceted LLPDs can be reworked with further polishing and
mation to isolate various process-related problems and crystal 23
etching if caught during inline process monitoring.
growth issues, then implement corrective measures. IC device 24
manufacturers can use classification information to create their 25
incoming wafer quality acceptance specifications based on Methods to Detect and Classify LLPD to Prevent
specific LLPD type, defect size and number. Yield Impact 26
Wafer manufacturers require a production-worthy inspection 27

Conventional technology and methods in use by IC manufac-
turers for testing incoming wafer quality are as follows: technology that allows inspection of all outgoing wafers for all 28
1st Step - Unpatterned inspection tool 1st sampling defects of interest (DOIs), with high throughput and economi- 29
2nd Step - Manual visual inspection for confirmation cal operating cost. It is necessary to capture the full range of
30
3rd Step - SEM verification DOI types and to automatically classify them with the highest
accuracy and purity. This will prevent out-of-spec wafers from 31
Until now, wafer manufacturers have been unable to identify reaching the IC device manufacturer and eliminate unneces- 32
and classify LLPDs effectively, especially the separation of an sary wafer rejection and scrap due to false positives.
33
34
35
Crystal Wire Saw Lapping Etching Polishing Inspection
36
37
38
39
40
41
42
LLPD (Crystal) LLPD (Wafering process) 43
44
Figure 2: Simplified Si wafer manufacturing process and faceted LLPD. 45
46
F eature S tory
capture a phase difference, which reveals height or slope in- 1

Wide
formation, as shown in Figure 5. This DIC technology allows 2
Narrow Normal and BF detection of defects that are large, flat or shallow and may not 3
Illumination be detected by darkfield channels.
4
After complete optical information of the wafer surface has 5
been captured, it is analyzed using a new algorithm known as
Bright 6
rules-based binning (RBB). RBB allows the user to compare
Field mathematical or logical conditions between the five defect 7
Collector
DIC channels (BF DIC, DF Normal Wide, DF Normal Narrow, DF 8
Oblique Wide, DF Oblique Narrow), as shown in Figure 6.
9
Rotating The results of these logical comparisons can be used to classify 10

Wafer Scan the defects of interest. All darkfield channels can be combined
Oblique 11
as the darkfield composite and all five channels, including
Illumination 12
brightfield, can be combined as the grand composite. The
Figure 4: Surfscan SP2XP illumination and optics technology. grand composite and brightfield channels serve to identify 13
14
15
The most important goal of the first inspection step is to Oblique Normal BF DIC
capture complete surface optical information with the highest 16
possible sensitivity at a production-worthy throughput. As 17
Wide
shown in Figure 4, the new system illuminates the bare
18
Si wafer with both normal and oblique incidence 355nm
UV laser beams to provide darkfield (DF) detection of DOIs. 19
The light scattered from the various defect types is collected 20
by both wide and narrow detectors, enabling further analysis
21
and classification. This architecture results in four distinct
Narrow
light collection channels (oblique narrow, oblique wide, nor- 22
mal narrow and normal wide). 23
24
In addition to the multi-channel darkfield collection, the sys-
tem also employs a new brightfield (BF) illumination channel Figure 6: Surfscan SP2XP creates five (5) channels of information for 25
to capture other defect types or surface characteristics. This BF each defect. 26
technology utilizes differential interference contrast (DIC) to
27
28
29
Signal Convex Step Concave
30
31
A B C D E
0 32
33
34
Time 35
36
37
38
39
40
41
A B C D E
42
Beam motion Arbitrary surface
43
44
Figure 5: Brightfield (BF) illumination and differential interference contrast (DIC) technology. 45
46
F eature S tory
Case Study 2: Twenty-three 200mm wafers 1

Grand Classification with Defect
composite rules-based binning classification In this case study, twenty-three 200mm wafers obtained from 2
various wafer manufacturers were similarly scanned and the 3
Brightfield RBB LPD results combined for comparison of the conventional method 4
versus the new RBB approach. SEM review confirmed a total
of 28 LLPD defects on these 23 wafers. 5
LLPD The conventional method reported a total of 65 LLPDs 6
crystal
Grand Grand composite -- 20 LLPDs were classified correctly 7
composite with RBB -- 45 particles were misclassified as LLPDs 8
LLPD
wafering
-- 8 LLPDs were not detected at all 9
The results of this case study are shown in Figure 10. 10
Darkfield LLPD 11
The conventional method would have caused a 69% increase
composite wafering
in false wafer rejection due to misclassification of particles as 12
LLPD defects, and a 29% miss rate on LLPD defects which 13
Figure 7: Rules-based binning classification results. could have caused an unexpected device yield impact at the
14
IC device manufacturer.
15
LLPD defects, and RBB is used to further separate LLPD de- The new approach detected all of the 28 LLPDs successfully, as
fects into particles, air pockets, polishing pits and etch defects. 16
verified by the SEM review.
Schematic analysis is shown in Figure 7. 17
18
The data used in Figure 8 were obtained from seven 300mm Electrical Analysis of LLPD Defect Types: Large Particles
wafer inspections. The DF channel information (oblique (LPDs) versus Large Pits (LLPDs) 19
narrow and wide, normal narrow and wide) was merged into 20
In order to analyze the yield impact of various types of LLPD
one DF composite plus BF. When the DF composite and BF
defects, an incoming prime wafer was inspected for LLPD defects. 21
defects were overlaid, the common defects were revealed as
Two LLPD defects were captured on this wafer. SEM analysis
LLPD defects. SEM analysis verified 100% purity of this 22
automatic classification. 23
Darkfield Brightfield Grand composite
Once the LLPD defects were identified, it was possible to composite LLPD : DF & BF 24
further identify and separate the large particles, air pockets, oblique + normal common defects 25
polishing pits and etch defects precisely using BF (DIC) infor-
26
mation combined with DF channel data through RBB. LLPD
Cluster
27
28
A comparison of LLPD results using conventional 8950 DFC Defects 56 BF Defects 17 LLPD Defects
methods versus new technology with RBB 29
An overlay of inspection LLPD
data from seven LLPD LPD Purity 30
300mm wafers
Case Study 1: Twenty 300mm wafers LLPD 17 0 100%
31
LPD 0 8950 100%
Twenty 300mm wafers obtained from various wafer manufac- Accuracy 100% 100%
32
turers were inspected, and the scan results were combined to
33
compare the conventional method versus the new approach. Figure 8: Grand composite of DF and BF(DIC) for LLPD classification.
SEM review showed a total of 29 LLPD defects. 34
The conventional method identified a total of 28 LLPD True LLPD 35

-- 16 LLPDs were correctly identified Missed LLPD
36
Particles classified as LLPD
-- 12 particles were incorrectly classified as LLPDs 37
1ea.
-- 13 LLPD defects were missed LLPD 38
12ea.
The results of this case study are shown in Figure 9. 29ea. 29ea. 39
16ea.
The conventional method would have caused a 43% increase 40
in false wafer rejection at the wafer manufacturers final inspec- 13ea. 41
Missed
tion step due to particles being reported as LLPD defects. LLPD
Conventional New Identified LLPD 42
Additionally, 45% of the total LLPD population was missed, method approach by review
passing the risk to the IC manufacturers customers. 43
44
The new RBB-based approach was able to detect all 29 LLPDs; Figure 9: Current challenges with faceted LLPD in 300mm
wafer manufacturing. 45
only one particle was misclassified as an LLPD.
46
F eature S tory
Further analysis of the failure mechanism caused by the 1

polished pit revealed that after the CMP process, the SiO2 STI 2
True LLPD
(Shallow Trench Isolation) film was not completely polished 3
Missed LLPD
Particles classified as LLPD
and removed over the Si3N4 etch stop. Therefore the subse-
45ea. quent wet chemical Si3N4 removal process was unsuccessful 4
LLPD
in and around the pit, preventing formation of the working 5
transistor structure necessary for the memory cell. 6
20ea. 28ea. 28ea.
7
8ea. Conclusions
Missed 8
LLPD Conventional New Identified LLPD Although shrinking device design rules are driving sensitivity 9
method approach by review requirements to capture smaller critical size defects, large,
10
yield-impacting defects have been growing in importance.
11
Figure 10: Current challenges with faceted LLPD in 200mm Wafer manufacturers require a better method to capture and
wafer manufacturing. 12
accurately classify LLPDs to prevent unnecessary false wafer
rejection or shipping of defective wafers to IC device makers 13
that do not meet IQC specifications. Capturing and correctly 14
identified them as a large particle and a polishing pit. This classifying these defects early in the wafering process has the
prime wafer was allowed to proceed through complete process- additional benefit of rapid root-cause identification that allows
15
ing for 80nm DRAM memory devices. Electrical test results of wafer manufacturers to quickly implement corrective measures 16
the die built on the LLPD defect locations revealed that both at the right process steps to ensure consistent product quality. 17
had yield-related issues, although at differing levels of severity.
While the large particle generated a few bad memory cells, 18
The new wafer inspection technology has demonstrated the
the polishing pit completely destroyed the memory device, as ability to address the challenges faced by both wafer manufac- 19
shown in Figure 11. turers and IC device manufacturers and has provided a solution 20
for improving product quality, cost and productivity. The new
21
rules-based binning technology, combined with multi-channel
LLPD Wafering Large Particles processing, gives wafer manufacturers and IC device makers 22
dramatically increased effectiveness in defect capture and 23
accurate classification for both conventional defect types and
24
yield-killer LLPDs. This achieves the goal of improving wafer
quality, an important factor in overall yield, ultimately 25
improving the fabs financial bottom line. 26
27
8M1A
90 1A
2104K1C
46 1C
Acknowledgments 28
The authors would like to thank the engineering and applica- 29
s
tions staff at Hynix Semiconductor Wafer Engineering Group,
30
1A
93 1A
300mm prime wafer inspection

77
87 77
before device processing

and KLA-Tencors Surfscan division for their valuable contri-
butions to this original work and team effort. 31
Killer Device Yielding Die
32
This work also would not have been successful without the
direction, information and strong support from wafer manufac- 33
Figure 11: DRAM device memory cell bitmap; yield impact of faceted
LLPD vs. large particle on 80nm DRAM in IC manufacturing. turers across the globe. 34
35
References 36
Before CMP Device failure area
1. International Technology Roadmap for Semiconductors 2005 Edition, 37
After CMP Yield Enchancement, pp. 710.
38
2. C.G. Koh, D.J. Kim, Hynix Technical Report, A06041883, Evaluation
Result of SP2 SSIS - 200mm Wafers, UNPUBLISHED. 39
3. C.G. Koh, B.S. Moon, D.J. Kim, Hynix Technical Report, A06095565, 40
STI
Evaluation Result of SP2 SSIS - 300mm Wafers, UNPUBLISHED.
Si 41
42
43
Figure 12: Device failure caused by remaining oxide and the unstripped 44
nitride film due to patterning and CMP issues of the faceted LLPD. 45
46
D efect M anagement
1
Etch Process Monitoring by 5
Electron Beam Wafer Inspection 7
9
Luke Lin, Jia-Yun Chen, and Wen-Yi Wong Powerchip Semiconductor
Mark McCord, Alex Tsai, Steven Oestreich, Indranil De, Jan Lauber, and Andrew Kang KLA-Tencor Corporation 10
11
12
13
14
Using E-beam inspection to establish defectivity levels from contact etch, Etch Process Window Qualification (Etch-PWQ)
15
can provide accurate yield data to help users center the etch process within the process yield window, then monitor the
16
etch process condition. 17
18
Process Window Qualification is a technique commonly used the end of processing can provide confirmation. However, this
19
with optical and electron beam wafer inspection to keep the approach can have several drawbacks. For instance, uncon-
lithography process centered within the process window. trolled variables can add uncertainty to the data, especially if 20
Different dies across the wafer are exposed with varying focus the defect signature used to determine the optimum process 21
and dose parameters. An inspection is used to determine the setting is subtle. These variables can include changes in prior 22
defectivity of the dies with different exposure conditions, and layer processes, changes in the lithography, changes in etch
special software is used to analyze the results. process (or tool/chamber), and the stability variance in the 23
inspection tool. For electron beam inspection, differences in 24

For etch processing, it is also critical to center the process the residual surface charge or atmospheric molecular 25
within the process window. For instance, under-etch on a contamination (AMC) between wafers can also affect the
contact layer can result in blocked or resistive contacts, while inspection results. 26
over-etch can cause shorts between source, drain, and/or gate 27
on the transistor. Traditionally, wafer splits are used to deter- For these reasons, it would be preferred to use a single wafer
28
mine optimum etch process conditions. Two or more wafers in order to determine the optimum etch process condition.
are used, and each wafer is processed with a different etch In this study, we have developed such a technique, and have 29
condition. Optical or electron beam inspection can then be successfully used it to optimize etch process conditions. 30
used to compare overall wafer defectivity. Electrical test at
31
Experimental Approach 32
Three full-flow DRAM wafers with 0.11m design rule were 33
Test 1 used in this study. All wafers were processed normally up to
34
the contact etch step. On each wafer at the transistor contact
Test 2 etch level, various dies received either nominal etch process 35
Test 3 condition or one of several different etch conditions, as shown 36

in Table 1. The dies were arranged to facilitate die-to-die 37
comparison of nominal and test dies in an automatic wafer
inspection tool. Columns of test dies were alternated with two 38
39
Etch condition Gas flow Over-etch time 40
Nominal 20 sccm 69 seconds 41
Test 1 21 sccm 55 seconds
42
43
44
Figure 1: Wafer die layout showing location of nominal dies and dies
with different etch process conditions. Table 1: Summary of the etch process conditions used for different die on each wafer. 45
46
D efect M anagement
Following the etch process steps, wafer #1 was checked for 1
Wafer preparation and contact size using a CD-SEM, then continued with normal 2
photo exposure shot edit processing through electrical test. Wafer #2 was removed from 3
the process flow and inspected first with an eS31 electron beam
inspection tool, then with an eS32 electron beam inspection 4
PR coating and etch
Condition 1~N tool. Wafer #3 was held after the contact etch step for poten- 5
Shot exposure/development tial further study, such as FIB or TEM. 6
Photo rework
7
Overlay measurement
Repeat in spec? No Using a 70nm pixel 8
1~N
Condition 1~N etch
Yes
to increase sensitivity 9
PR strip & wafer clean and a precharge step to enhance 10
11
CD measurement
contrast, subtle under-etch defects 12
were detected that correlated 13

Scan by e-beam inspector
with both the etch condition 14
15
Figure 2: Process flow for creating dies with multiple etch conditions
and with the end-of-line 16
on a single wafer. bit yield results. 17
18
columns of dies processed using the nominal condition. In this
way, each test die could be compared to two adjacent nominal Results 19
dies. In addition, the various test dies were distributed across Initially wafer #2 was inspected on an eS31 electron beam in- 20
the wafer so that the process signature could be distinguished spection tool using a landing energy of 1000eV, beam current 21
from any wafer level signature that might be present. The of 212nA, and a pixel size of 100nm. Field conditions were set
wafer layout of nominal and test dies is shown in Figure 1. up such that underetched contacts would appear brighter than 22
normal contacts, which are dark. The inspection failed to show 23

any significant correlation between the etch conditions and 24
In order to process the various etch conditions on different the die defectivity. However, end-of-line bit failure testing on
dies on a single wafer, multiple lithography steps were wafer #1, which continued with normal processing, showed a 25
utilized. First the nominal dies were exposed and etched, definite yield loss correlated with the etch process conditions. 26
while the test dies were protected by blank resist. Then the The bit yield map is shown in Figure 3; slashes indicate dies 27
lithography and etch process steps were repeated for each of with poor bit yield results.
the different etch process conditions on the test dies, while 28
the nominal dies were protected by unexposed resist. In this At this point, the wafer was re inspected using an eS32, which 29
way, the various process conditions were all placed on a single has improved sensitivity and a wider range of optics settings.
30
wafer. Figure 2 shows a flow chart of the lithography and etch The inspection care area was extended to the very edge of the
processing steps. array, where it was found that most defects were occurring. 31
32
33
34
35
36
37
38
39
40
41
42
43
44
Figure 3: End-of-line bit failure map showing correlation with both etch Figure 4: Defect inspection map of etch wafer showing variation in
process die split and in-line defect inspection map. defectivity with etch process condition. 45
46
D efect M anagement
from the inspection tool containing some defective contacts is 1

shown in Figure 5. 2
ePM is a new eS32 algorithm currently under development at 3
KLA-Tencor that can be used to find out-of-tolerance wafers 4

more quickly than standard e-beam inspection. Images are 5
taken from identical locations on each of a selected number
6
(or all) dies on the wafer. The average gray level of each image,
which correlates to the average secondary electron yield, is 7
computed and mapped. Because slight process variations can 8
cause a significant variation in secondary yield, this technique
9
can be used to establish process tolerance limits on etch or
other process steps. Figure 6 shows the ePM gray level map 10
of the wafer, clearly indicating differences between nominal 11
Figure 5: Review image from the eS32 inspection showing a cluster and test die. Figure 7 shows a comparison between the contact
12
of under-etched contacts. CD measured on wafer #1 and the average gray level seen by
ePM, for each of the four etch process conditions. Again, there 13
is excellent correlation between the two measurements. As 14

2 expected, underetch conditions resulted in a brighter average 15
gray level because the normal contacts are darker than the
16
4 surrounding oxide.
17
6 18
Conclusion
Etch Process Window Qualification (Etch-PWQ) has been 19
8
shown to be a promising technique for establishing defectivity 20
10 levels from contact etch and for providing accurate yield data 21
to center the etch process within the process yield window.
22
12 By placing the experimental design on a single wafer, data
2 4 6 8 10 12 14 uncertainty caused by wafer process variations or inspection 23
tool drift is avoided. In order to see subtle under-etch defects 24
Figure 6: Gray level ePM map of wafer showing correlation between from marginal etch process conditions, it was necessary to use
etch process condition and gray level intensity of images. 25
a precharge step and to select optics conditions to optimize
sensitivity. Good correlation was seen between the inspection 26
A special precharge step was implemented to bring the wafer defectivity and the electrical bit yield. Finally, ePM, an electri- 27
surface voltage to a condition that enhanced the contrast of cal process monitor capability on the eS32 inspection tool that
28
the defective contacts. Finally, the inspection pixel size was measures secondary yield across the wafer, shows promise as a
reduced to 70nm in order to further increase sensitivity. This tool for monitoring the etch process condition. 29
time, subtle under-etch defects were detected that also cor- 30

related with both the etch condition and the end-of-line bit
Acknowledgements 31
yield results. The defect map is shown in Figure 4. A good
The authors gratefully acknowledge the support of 32
correlation was found between inspection defect density on
wafer #2 and electrical bit yield on wafer #1. A review image Jason Lim and Kumar Raja for their help in this study. 33
34
CD (nm) Gray level
35
0.195 60
CD (nm) Gray level 36
0.190
70
37
0.185
80 38
0.180
0.175 90
39
0.170 40
100
0.165 41
110
0.160 42
0.155 120 43
nominal test 1 test 2 test 3 nominal test 1 test 2 test 3
44
Figure 7: Comparison between measured CD and average image gray level for the different etch test conditions. 45
46
D efect M anagement
1
Enabling Manufacturing 5
Productivity Improvement and 7
Test Wafer Cost Reduction

9
10
11
Ming Li, Lisa Cheung, and Mark Keefer KLA-Tencor Corporation
12
13
14
15
Use of a Surfscan SP2 inspection system can cut production costs by extending the reuse lifetimes of some monitor 16
wafers and reducing the need for new test wafers. For a large foundry, this new technology can increase the in-house 17
18
recycle rate and decrease the repolish rate by 15%, which translates to over $3M in annual savings.
19
Todays wafer fabrication plants must carefully balance the wafer is inspected, passes through the process tool (with or 20
need to increase productivity while simultaneously reducing without activating the process chamber) and is reinspected. 21
variable costs. There are a couple of main areas where process Added defects are calculated using a traditional post- minus
22
control (metrology and inspection) equipment can help pre-count calculation, or a more sophisticated map-to-map
minimize variable cost. The first is reducing consumables defect overlay comparison (reference 1). Post-scan inspection 23
minimizing the number of wafers that are processed for results reveal any defects added by the process tool, expressed 24
non-revenue operations, i.e., test wafers. Second is process as particles per wafer pass (PWP) added.
25
equipment productivity improvements, by reducing the
number of maintenance cycles per year and the associated 26
The Process Tool Monitoring Procedure
time lost due to resolving process excursion false alarms. This 27
article will explore these ideas in more detail, to determine an The first step of the process tool monitoring procedure is to
28
effective method for reducing test wafer cost in a leading-edge assign the test wafers into bins by grade. Grade (usually A, B
or C) refers to the quality of the test wafer appropriate for 29
65nm design rule foundry.
different monitoring applications, in this case its surface 30
roughness, since smaller-size particles can be more reliably
Process Tool Monitoring 31
detected on smooth wafers than on rough wafers. Surface
Particle counts on unpatterned test (or monitor) wafers are roughness is normally measured by using the inspection tool 32
typically used to monitor the health of process tools, either to detect haze, the low-frequency, low-amplitude component 33
after preventive maintenance (tool qualification) or prior to of the light scattered from the wafer surface. Haze is measured
34
running production wafers, after a specified number of hours in ppm, a ratio of the average surface scattering intensity to the
incident laser beam intensity. For bare wafers, haze is strongly 35
or at the beginning of each shift (tool monitoring). Process
tool qualification occurs after preventive maintenance or to correlated with surface roughness. (When a transparent film is 36
requalify the tool after unscheduled downtime. Tool monitor- present, haze also includes film parameter variation.)
37
ing is used to quickly detect process tool excursions. Addi-
The second step is the actual process tool monitoring step: 38
tionally, unpatterned wafer inspection tools can be used for comparing pre- and post-processing inspections and quantify-
engineering analysis work, either to characterize new process 39
ing the added defects. In order to re-use the test waters, they
tools or diagnose specific contamination problems that led to are chemically stripped to remove any film layers and particles 40
a process tool being removed from production (tool-down that were added by sending them through the process tools. 41
problems). The chemical stripping results in higher surface roughness or 42
Process tool monitoring uses a single unpatterned test wafer haze (the upper loop in Figure 1), and the test wafers must be
regraded. After a certain number of recycle steps the test wafers 43
for each process chamber, with higher grade wafers used for
front-end-of-line processes, where critical dimensions are fail the roughest grade specifications, and are then sent for re- 44
smaller and greater inspection sensitivity is required. The test claim (repolished) or scrapped (the lower left loop in Figure 1). 45
46
D efect M anagement
Extending the Useable Life 1

In-house chemical clean of Monitor Wafers 2
Regeneration area Defect detection sensitivity 3
SP1 Grade Pre SP1 Post SP1

is determined by the ratio of 4
PWP < X Process
Test
Inspection A, B, C Inspection Inspection the defect signal to its back-
5
wafers
Grading
ground. As the background
A < X1 counts <Y1 ppm
level (haze) approaches the 6
B < X2 counts <Y2 ppm detection threshold, the 7
C < X3 counts <Y3 ppm
signal-to-noise ratio decreases
8
(Figure 2, left). To ensure that
Reclaim 1 Reclaim 2 Reclaim 3 defects can be detected with- 9
Scrap $300/wfr Re-polish $30 / wfr
New
out the occurrence of false 10
wafers Grade A B C
alarms, it is desirable to keep
11
a high defect signal-to-noise
Roughness ratio, typically above 3. 12
13
However, as the number of
Figure 1: Process monitoring loop using test wafers 14
chemical strips (recycles)
increases the surface roughness 15
Threshold Threshold and haze of the test wafer, 16
the signal-to-noise ratio for
17
Laser scattering signal (ppm)
detection of small defects on

Laser scattering signal (ppm)
the wafer surface decreases. 18

Manufacturing considerations 19
Noise such as matching one inspection
20
tools results to other tools
dictate that the inspection 21
Haze Haze sensitivity threshold remains 22
at a fixed value. This means
23
that the detection threshold
Scan position Scan position
cannot simply be increased to 24
Figure 2: Relationship between wafer surface roughness (haze) and inspection sensitivity, for a wafer having a low mitigate the increased back- 25
haze value (left) and a high haze value (right). Note: Noise is proportional to the haze. ground noise, as suggested in 26
Figure 2 (right). Hence, the
27
number of recycle steps that
can be performed on any given 28
Surfscan SP1 Surfscan SP2
test wafer is limited by this 29
increase in surface roughness.
30
What is needed is a way to 31
increase the inspection signal-
32
to-noise ratio for small defects
on rough wafers. The current 33
generation wafer surface 34
Figure 3: Rough wafer sensitivity comparison. Surfscan SP1 map on left shows predominantly false defects, while
SP2 map on right shows predominantly real defects, with the smallest defects having a S/N > 3.
inspection system, the 35
Surfscan SP2, has a smaller
spot size than the previous- 36
SP1 HT Mode S/N vs. Wafer Haze Level SP2 HT Mode S/N vs. Wafer Haze Level generation SP1, which means 37
18
Low Haze
18
Low Haze that less background is 38
15
acceptable
inspection
Medium Haze
High Haze
15
acceptable Medium Haze
High Haze
included when the spot is
12 inspection 39
12
focused on a small defect. This
S/N Ratio
S/N Ratio
window window
9 9
gives the Surfscan SP2 better 40
6 6
sensitivity on rough wafers 41
3 3
than the SP1. Figure 3 shows
0 0 42
0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.15 0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.15 a comparison of the same
Defect Size (m LSE) Defect Size (m LSE) high-haze wafer, recycled 43
many times, scanned using 44
Figure 4: Signal-to-noise vs. wafer haze level comparison (Surfscan SP1 left, SP2 right) for defects of varying size.
the Surfscan SP1 (left) and
The acceptable inspection window has S/N ratio above 3, and defect size below 88nm LSE. 45
SP2 (right) systems. The SP1
46
D efect M anagement
center in the fab where these 1
Recycle rate from 70% to 85%

measurements were taken. 2
In-house chemical clean Wafers that would have been
$5 / water recycle 3
in the Grade B category for
Regeneration area Surfscan SP1 inspection are 4
SP2 PWP < X Grade Pre SP2

Process
Post SP2 now in the Grade A category 5
Inspection A, B, C Inspection Inspection
for SP2 inspection. Conse- 6
Test quently, wafers can be recycled
7
wafers $75K/month more times the recycle rate
in the in-house chemical clean 8
SP2 center was estimated to have 9

increased by 15%. This higher
Reclaim 3 10
Reclaim 1 Reclaim 2 recycle rate corresponds to a
Scrap $300/wfr Re-polish $30 / wfr
decreased reclaim (repolish) 11
New 10% 20% 5% Grade A B rate (Figure 5). 12
wafers
Roughness Using these new recycle rates, 13
we can estimate the cost sav- 14

ings as follows, for a 300mm 15
Figure 5: Net increase in wafer recycle rate
foundry running 25K WSPM,
16
with test wafer usage equal
map shows a significant population of false defects caused by to 3x the production rate, 17
the low signal-to-noise value. The inspection threshold, set to or 75K WSPM. Surfscan SP2 implementation increases the 18
capture the real defects, is also capturing the peaks of the haze in-house recycle rate and decreases the reclaim rate by 15%,
19
signal. On the other hand, the SP2 map shows significantly which translates to approximatly $3M in annual savings for
this case ( Table 1). The model can be adjusted to accommo- 20
fewer false defects, since its superior sensitivity allows the scan
threshold to be set well above the haze level. The capability of date different wafer starts, test wafer usage, etc. 21
the Surfscan SP2 to enhance signal and better suppress noise 22
Summary
enables this type of inspection, in turn allowing test wafers to
23
be recycled for a longer period of time before they are re- Wafer fab productivity benefits from reduction of variable
claimed or scrapped. 24
costs. Test wafer lifetimes directly impact their usability for
process tool monitoring. Using a Surfscan SP2 inspection 25
Figure 4 shows signal-to-noise analyses for SP1 and SP2 on
system instead of a previous-generation tool has been shown 26
wafers of varying haze levels. The acceptable inspection
to enable further reuse of some monitor wafers, which also
window is at the upper left portion of the chart (better than 27
reduces new test wafer purchases. In addition to the quantifi-
88nm sensitivity at S/N ratio 3). The SP1 high throughput
able economic impact of test wafer cost reductions, fab manu- 28
mode cannot meet the 3:1 signal-to-noise requirement at the
facturing productivity also increases, while disruptions due 29
required 88nm defect sensitivity on high-haze wafers. SP2s
to false excursion alarms resulting from unstable inspection
enhanced sensitivity and background noise suppression is able 30
results of roughened reclaimed wafers are minimized.
to meet the required sensitivity, even when using high-haze 31
wafers, in high-throughput mode.
32
Acknowledgements
33
Economic impact This material was originally presented at the KLA-Tencor
Yield Management Seminars in Shanghai (August 2006) 34
Figure 4 shows that the Surfscan SP2 can achieve sufficient
and Beijing (September 2006). 35
sensitivity and signal-to-noise on rougher wafers; as a result, a
dedicated SP2 inspector was placed into the in-house reclaim 36
37
Wafer Type Recycle Reclaim Scrap Total Test
38
Wafer Cost $5 $30 $300 Wafer Cost References
39
Wafer Volume 52.5 > 63.75K 15.0 > 3.75K 7.5K 1. Lorrie Houston, Motorola; John
Anderson, Motorola; Rhonda Stanley, 40
(total =75K)
KLA-Tencor;
41
Recycle Rate (SP1) 70% 20% 10% $2.96M Process tool qualification using
SP1TBI automated overlay feature, 42
Recycle Rate 85% 5% 10% $2.68M
(SP1+SP2) KLA-Tencor Surfscan Applications
43
Note (2002).
Cost saving per month $56,250 $337,500 no change $0.28M 44
45
Table 1: Estimated monthly cost savings from increased wafer recycle rate: $0.28M, for an annual savings rate of $3.36M.
46
M etrology
1
Wafer Level Metrology 5
Expands Process Applications at 45nm 7
8
Paul MacDonald, Greg Roche, Mark Wiltse - KLA-Tencor Corporation
9
10
11
12
Instrumented wafers, including KLA-Tencors Integral SensorWafers, are increasingly being used to optimize, 13
14
troubleshoot and monitor many different process applications. These specialized substrates contain complete
15
metrology instrumentation that can provide high-precision, time-sequence measurements that show a wafers response to
16
the dynamic process environment. 17
18
One of the outcomes of the continuing trend to smaller Physical Vapor Deposition (PVD): Copper Barrier/ Seed
19
geometries is the need to incorporate real-time tool data with Chamber Matching with Temperature
other forms of metrology data.1 The semiconductor industry With the addition of copper to the semiconductor metalliza- 20
defines metrology data in terms of its relation to the process tion portfolio came the need for careful attention to seed layer 21
tool: offline (apart from), in-line (attached to for measurement and barrier growth. With the attendant reduction in deposi- 22
immediately before and after) and in-situ (integrated into, tion temperatures, wireless sensor wafers became a viable
for measurement during processing). The subject category 23
method to characterize these processes and provide a means for
offline/in-line/in-situ metrology will be included in the chamber matching. 24
ITRS Metrology and Factory Integration sections beginning
25
with the 2007 revision.2 Two production Cu seed chambers were investigated for vari-
ous RF power and chuck temperature conditions.3 Low-and 26
Instrumented substrates straddle the categories described high-power conditions were evaluated in a matrix with room, 27
above in that they gather real-time information from inside low, and ultra-low cathode temperature conditions. Baseline
the process (in-situ), simultaneous with spatial information 28
conditions (low power, low temperature) are depicted in
(off-line); yet these instruments can be read immediately Figures 1a and 1b. Immediately visible are differences in 29
before and after the process (in-line). The sections below thermal uniformity and mean temperature. Chamber A shows 30
describe a range of 45nm node-relevant application examples high non-uniformity at the edge near the notch. Chamber B 31
showing the use of instrumented substrates. shows a concentric, uniform pattern with tighter range. Spatial
32
temperature data from the SensorWafer runs were examined
and modeled with respect to the RF power and chuck tem- 33
perature parameters. The source of the mismatch was localized 34
to the area near the notch and was determined to be due to
35
non-uniformities in RF power delivery.
36
37
Chemical Vapor Deposition (CVD): Plasma Nitridation
38
The properties of these CVD films are strongly dependent on
the temperature of the substrate during deposition. Substrate 39
temperature is controlled by power input to the substrate 40
a) b) through the source and bias electrodes, as well as temperature
41
Mean 81.121 Mean 71.807 control within the electrostatic chuck or heated plate.
Range 47.365 Range 33.599 42
Smaller feature nodes have reduced the temperature budget of 43
Figure 1: Low power, low temperature Cu Barrier deposition:
CVD processes. Thermal process CVD furnaces have historically
44
a) Baseline 2-D thermal profile of chamber A (left); b) Baseline 2-D operated in the regime of 6001000C. With the addition
thermal profile of chamber B. of plasma enhancement (PECVD), the substrate temperature 45
46
M etrology
dropped to the 250550C range. Subsequently, with the 1

45nm node, substrate temperature has dropped even further 2
with the advent of ultra low-k dielectrics as well as some
Temperature C
3
high-k gate structures. Recently, PECVD films have been
developed as ultra low-k barrier layers using substrate tem- 4
peratures in 3050C range.4 Plasma nitridation has come 5

into use for adding insulating or barrier properties to some 6
high-k gate materials.5
7
In Figure 2, a plasma nitridation process was characterized Time (s)
8
with the maximum temperature ~40C. The initial tests gave
Figure 2: Temperature response of a room temperature plasma 9
some insight into the temperature uniformity and behavior
nitridation process. Each trace represents one temperature sensor, so
as the substrate approached its peak temperature. The spatial 10
the spread across the traces is indicative of spatial non-uniformities.
tempe-rature profile is shown in the right portion of the figure. 11
Next, an experiment was run in a low-temperature plasma Temperature profile vs. seasoning wafers 12
6
nitridation system to determine the effect of seasoning wafers on 39
T-mean 13
wafer temperature profile. Here the SensorWafer was run before
Temperature range (C)

Temperature mean (C)
T-range 5
38 14
and after every series of three seasoning wafers (Figure 3). The 4
37 15
chamber appeared to reach steady-state temperature after nine 3
seasoning wafers. Interestingly, the across-wafer temperature 36 16
2
profile changed during the course of the seasoning (Figure 4). 35 17
1
34 6 18
Chemical Mechanical Polish (CMP) 0 5 10 15 20
Cumulative seasoning wafers 19
Chemical mechanical polishing (CMP) is a process of film removal 20
that combines both physical and chemical aspects of abrasives in a Figure 3: SensorWafer mean temperature and range as a function of 21
slurry with a polishing pad on the surface of the wafer. Tempera- chamber seasoning.
ture is not controlled for this process, but is a function of several 22
key control parameters: polishing head rotation speed, platen 23
rotation speed, head pressure and slurry flow.6 SensorWafers were
24
used to study the wafer surface during polishing as a function of
process conditions. 25
26
Figure 5 shows the temperature versus time trace as collected
by the Integral SensorWafer. Interesting temperature data fea- 27
tures are visible in the traces: global temperature, across-wafer 28
variation, and rotational effects. 29
Figure 4: Temperature spatial profile before seasoning (left) and after
9 wafers seasoning (right). 30
Lithography Direct CD Tuning with Temperature
31
Lithography is one of the most important application areas of Global temperature rise during polishing 32
SensorWafer metrology. With each node, the processes within Across-wafer variation by radial zone
lithography have become progressively more temperature Rotation effects 33
Edge variation due to rotation is much greater than the center
sensitive, placing a strain on hardware matching and control 34
in the litho cell. For example, the SensorWafer is frequently 35
used to adjust the temperature profile, both spatially (across a
36
bake plate) and temporally (temperature rate of change), and
20C
from plate to plate. Temperature profiles are then stored in the 4C
37
litho tool. The tool is then monitored with a SensorWafer on a 38
routine basis, after PM, and by exception.
39
2C /1sec
In this study, the SensorWafer output was used to adjust the CD 40
directly. That is, the processed wafer CD was optimized by ad-
41
justment of the photoresist bake plate temperature profile. The
adjustment of the temperature profile occurs in three steps: 42
1) collect baseline temperature information; 43

2) calculate optimal control inputs and provide 44
Figure 5: Temperature versus time trace for CMP characterization
adjustments to bake plate;
experiment using an Integral wafer. 45
3) verify temperature performance.7
46
M etrology
In this example, a 48nm CD process with a seven-zone PEB 1

CD
plate was adjusted in one run, utilizing specialized software 2
50.97 (AutoCD) to calculate the control inputs. Figure 6 shows 3
49.50 the results for the wafer mapped CD before and after plate
48.02
adjustment. The pre/post range improvement was 22%. 4
46.65
5
Pre CD Validation Plasma Etch 6

Mean: 48.56 nm Mean: 48.83 nm 7
Normalized 3: 1 Normalized 3: 0.78 Plasma etch is one of the most important applications for
SensorWafers. Plasma etch processes are extremely complex; 8
Figure 6: Wafer level CD maps for pre - (left) and post - (right) temperature the processed wafer results are a strong function of the process 9
profile adjustment. controls as well as the materials and topology of the devices
10
being etched.8 Further, conditions in etch chambers are not
constant; chamber surfaces change over time due to physical 11
and chemical exposure. The etch results are typically very 12
temperature dependent, and temperature is, in many cases, a
13
Chamber Recovered
good metric for conditions of the plasma at the wafer surface.
Deviation Chamber
Commercial reactors typically have power delivered to source 14
20T - Range [All]
11.55
and bias electrodes. Below are four examples of key applica- 15
10.13 tions for SensorWafers.
8.70
UCL 16
7.27
Nominal Plasma Etch Example 1: Chamber Periodic Maintenance 17
5.84
4.41 Qualification with Temperature 18

16141210 8 6 4 2 0
Time Units Etch processing chambers require frequent preventive mainte- 19

nance (PM) activities to achieve consistent device performance.
Figure 7: SPC chart of SensorWafer temperature, with details of spatial 20
SensorWafers provide a useful, mobile platform for verification
temperature profile.
of chamber health. 21
PM1 PM2 22
Figure 7 provides a representation of chamber health during a
Golden Problem Difference
chamber chamber clean cycle. Temperature range (maximum temperature minus 23
Lower
electrode
5.00E-02 2.50E-02 minimum temperature) was measured periodically to under- 24
RF power stand chamber health. When the temperature range deviated
25
C / W
C / W
increase
above the upper control limit (UCL), a PM was executed. The
UCL chamber deviation was inspected spatially and the devia- 26
0.00E+02 -2.50E-02
Model A Model B Difference tion was found at the wafer edge. After the PM was completed, 27
Edge He
cooling
5.00E-01 7.00E-01
chamber performance was verified and the chamber was placed 28
back into production.
C / T
C / T
29
Plasma Etch Example 2: Chamber Matching with Temperature 30
-5.00E-01 -3.00E-01
Model A Model B Difference
Chamber matching for critical etch processes continues to be 31
Center He 0.00E+00 3.00E+01
cooling a challenge. Shrinking geometries and increasing aspect ratios
32
demand that subtle chamber differences be identified and
C / T
C / T
resolved to achieve the desired level of performance. To isolate 33

-5.00E-00 -2.00E-00 the source of a yield-limiting deviation, two chambers were 34
compared.9 Critical response knobs were characterized in a golden
Lower 35
electrode
1.70E+00 3.00E+01
chamber and a problem chamber (Figure 8). The response of
temp each critical process knob was characterized with a combination 36
C / C
C / C
of SensorWafer data and advanced analysis software. 37

7.00E-00 -7.00E-00
Process variable and response - Summary 38
Chamber 1.00E+01 5.00E+02 Process Variable Response to Increased Process Variable 39
pressure
Lower Electrode RF Power Increase Increases Heat to the Entire Wafer 40
C / mt
C / mt
Edge Helium Cooling Decreases Heat at the Edge of the Wafer

41
-2.00E-00 -1.00E-01 Center Helium Cooling Decreases Heat at the Center of the Wafer
Model A Model B Difference 42
Lower Electrode Temperature Increases Heat to the Entire Wafer
Figure 8: Comparison of golden chamber and problem chamber. Each 43
Chamber Pressure Radial Effect
plasma reactor subsystem was characterized with PlasmaRx software.
44
A spatial analysis engine determined the lower electrode temperature to
Table 1: Plasma etch control variables with associated response for
be the source of reactor deviation. 45
temperature SensorWafer.
46
M etrology
Process variables for both reactors responded as intuitively through the tool, showing that observed temperatures were 1
expected (Table 1). To identify the source of the performance elevated approximately 3C at the wafers center. Spatial data 2
issue, shape-matching algorithms were applied to each response. review clearly revealed a strong local pattern of the problem 3
Through this approach, the lower electrode temperature was in the two-dimensional maps of the temperature profiles
targeted for fast repair as the source of the chamber mismatch. (Figure 9). The faulty temperature pattern correlated directly 4
with lift pin locations. The lift pins were examined, and it was 5
Plasma Etch Example 3: Problem Troubleshooting discovered that their retraction heights were set incorrectly. 6
with Temperature Subsequent analysis of the probe data confirmed that the
7
In-line defect inspection maps revealed unacceptable perfor- localized SAC under-etch was limited to the die located over
mance levels localized to specific die with self-aligned contact the lift pins. The hardware problem was repaired, and the 8
(SAC) etch.10 The SensorWafer (PlasmaTemp) was run resulting temperature signature closely resembled the baseline 9
temperature profile, indicating the fault was repaired. Probe
10
Hot spot results upon resumption of production confirmed this finding.
11
Plasma Etch Example 4: Plasma Process Monitoring
12
with SensorWafer Electrical Measurement
13
Although temperature has proven to be a good metric for
14
plasma etch characterization, in some plasma etch environ-
-11.0
-7.2
-11.0
-7.0 ments it is not enough. In this example, measurement of 15
-3.6 -3.0
-0.0 -0.0 voltage at the wafer surface (PlasmaVolt) provided a more 16
Faulty Normal useful diagnostic.
17
Figure 9: 2D normalized temperature profile. Faulty condition where
hot spot caused by lift pins is discernible (left panel); after fault was
The example in Figure 10 shows the drifting down of Vpp as 18
corrected (right panel). measured by the tool and a corresponding detection by
19
PlasmaVolt of the drift downward. However, the temperature
PlasmaVolt Data wafer reported a steady state as the thermal inertia of the 20
process and the lesser power created opposing thermal flux 21
and resulted in relative equilibrium.
RF Voltage (V)
6000
22
4000
The increased sensitivity of electrical measurements allowed 23
2000
enhanced characterization of subtle process effects that were not 24
temperature-related. In this production fab example, the electri-
0 850 900 950 1000 1050 25
Time (s) cal measuring SensorWafer was called into use to help diagnose
Reported Chamber Vpp an etch CD issue that had been localized to chamber E.11 In 26
this situation, existing testing methodologies were unable to 27
identify any functional differences between the two chambers.
28
Comparing data traces from bad chamber E and good chamber
D, the SensorWafer electrical measurement indicated instability 29
Temperature Data during the etch step (Figure 11). Since it is a voltage measure- 30
100
ment, it was logical to assume that this instability was located
Temperature (C)
31
80 in the RF power delivery system. The problem was soon found
to be a faulty power delivery cable. After cable replacement, 32
60
follow-up metrology wafers were run and the CD values were 33
40
50 100 150 200 250 300 found to have returned to normal. 34
Time (s)
35
Figure 10: Plasma etch chamber time synchronized data. PlasmaVolt Conclusions
(top); Vpp as reported from bias power delivery system (middle); 36
SensorWafer temperature data (bottom). Some examples of in situ wafer level metrology have been pro- 37
vided. It is evident that instrumented silicon wafers, including
KLA-Tencors SensorWafers, have shown great utility in aiding 38
Chamber D Chamber E
Nominal CD bad CD the understanding of semiconductor processing. Some of the 39
2900 2900
key trends identified here are:
RF Voltage (V)
RF Voltage (V)
2800 2800 40
2700 2700
2600 Shrinking process windows with concomitant manufac-
2600 41
2500 2500 turability issues will continue to create demand for in
2400 2400
situ wafer level metrology. 42
420 440 460 480 500 520 300 320 340 360 380 400
Time (s) Time (s) Reduced process temperatures and thermal budget favor 43
the use of wireless SensorWafers. 44
Figure 11: PlasmaVolt traces for two plasma etch chambers, each
providing nominal and out-of-specification CD performance. Electrical measurements provide powerful augmentation 45
to temperature for plasma systems.
46
M etrology
SensorWafers References 1
Wireless instrumented wafers (generically SensorWafers) have 2

1. International Technology Roadmap Semiconductors 2006 Update, Li-
the advantage of being run through standard semiconductor thography. http://www.itrs.net/Links/2006Update/FinalToPost/08_Lithogra- 3
equipment robotics. SensorWafers are limited by the tempera- phy2006Update.pdf.
4
ture of on-board electronics, which is typically on the order 2. M. Janakiram, ITRS Factory Integration Presentation, Presentation to
of a sustained 140C. Each semiconductor roadmap node has Create, Arizona State University, January 2007, http://create.asu.edu/calen- 5
brought with it lower processing temperatures and smaller dar2/pdfs/ITRS_Factory%20Facilities_Jan2007.pdf. 6

thermal budgets, which has aided the use and acceptance of the 3. P. MacDonald,In situ thermal measurements for Cu barrier seed deposi- 7
wireless metrology. Most SensorWafers measure temperature. tion, OnWafer Technologies, Inc., 2005.
8
More recent additions measure voltage. 4. L. Zambov, K. Weidner, V. Shamamian, R. Camilletti, U. Pernisz, M.
Loboda, G. Cerny, D. Gidley, H Peng, R. Vallery, Advanced chemical vapor 9
deposition silicon carbide barrier layer technology for ultralow permeability
10
applications, JVST A Vol 24(5) September 2006 pp. 17061713.
11
5. A. Callegari, P. Jamison, D. Deumayer, F. McFeely, J. Shepard, W. An-
dreoni, A.Curioni, C. Pignedoli, Electron Mobility dependence on annealing 12
temperature of W/HfO2 gate stacks: the role of interfacial layer, Journal of
13
Applied Physics, Volume 99, 2006.
6. H. Hocheng and Y.L. Huang, In situ endpoint detection by pad tempera- 14
ture in chemical mechanical polish of copper overlay, IEEE Transactions on 15
Semiconductor Manufacturing, Vol 17, No 2 May 2004 pp. 180187.
16
7. S. Wang, P. MacDonald, M. Kruger, C. Spanos, M. Welch, CD uniformity
improvement and IC process monitoring by wireless 17
sensor technology, IEEE 2004. 18
8. I. Husala, K. Enke, H. Grunwald, G. Lorenz, H. Stoll, In situ silicon wafer
19
temperature measurements during RF Ar-ion plasma etching via flouroptic
thermometry, J. Phys D Applied Physics 20 (1987) pp. 889896. 20
The image above shows an Integral wafer with a 10m poly-
imide coating. The polyimide is transparent to visible light, 9. P. MacDonald and M. Kruger Component health monitoring and diagnos- 21
tics in plasma Etch Chambers using in-situ temperature metrology, SEMI
thereby allowing a view of details of the electronics and 22
Technical Symposium: Innovations in Semiconductor Manufacturing (STS:
temperature sensor locations. All sensors and electronics lie ISM) 2004. 23
beneath the plane of the wafer surface. There are several pos-
10. Brown, T. Schrock, K. Poolla, M. Welch, P. MacDonald Rapid diagnostics 24
sible alternative configurations of this temperature SensorWafer, of etch processes in high-volume production using temperature metrology,
which include having a cover layer of silicon, silicon dioxide, or Semiconductor Manufacturing. Volume 4(10), pp.140156, October 2003. 25
an other customer-specified material. Depending on configura- 26
11. G. Roche, P. Arleo, P. MacDonald, Wafer based diagnostics for dielectric
tion, these instrumented wafers find use in wet processing, CMP, etching plasmas, Northern California AVS, Meeting of Plasma Etch Users
lithography low temperature CVD, PVD, and plasma etch. 27
Group, May 2007, http://www.avsusergroups.org/peug_pdfs/PEUG_07_5_
Roche.pdf. 28
The image below shows a 300mm PlasmaVolt wafer with
29
electrical sensors and measuring electronics visible on the sur-
face. Sensors and electronics have a profile 3.4 mm or less above 30
the wafer surface. With this profile these SensorWafers can be 31
loaded with standard robotics through most 300mm production
32
vacuum equipment. The entire wafer is covered with polyimide,
which is chemically very similar to photoresist. These types of 33
SensorWafers find use primarily in plasma etch. 34
35
36
37
38
39
40
41
42
43
44
45
46
M etrology
1
Spectroscopic Ellipsometry Film 5
Metrology Braces for 45nm and Beyond 7
8
Arun R. Srivatsa - KLA-Tencor Corporation
9
10
11
12
Spectroscopic Ellipsometry (SE) is a key technology for production monitoring of films in todays fabs. Advancements 13
14
in spectral fidelity, use of shorter wavelengths, and many other improvements enable SE technology to measure
15
thickness and refractive index, but also material composition in many films, including nitrided oxides, boron-doped silicon
16
germanium (SiGe:B) and high-k materials at the 65nm and 45nm nodes. 17
18
With the advent of new materials and structures at the 65 and challenges and requirements for handling new materials and
19
45nm nodes, demands on thin film metrology are increas- complex structures, and new applications data and potential
ing in complexity while metrology budgets get tighter. In solutions using optical thin film metrology will be discussed. 20
several key processes, it is no longer sufficient to monitor just 21
thickness and refractive index for process control. One must
Multiple-Front Challenges 22
measure or infer composition, porosity, and other parameters
for effective process control. Using the systematic variation of There is almost universal agreement that at the 65nm and 23
optical properties with these parameters, recent advances in 45nm nodes, films metrology is getting more complex and 24
the application of spectroscopic ellipsometry (SE) have led to intensive (Figure 1). Along with the usual tightening of pro-
25
the successful adoption of this technique in R&D and produc- cess windows and metrology budgets (a general rule of thumb
tion for monitoring composition in varied materials like high-k is that the total films metrology budget should be <10% of 26
gate dielectrics, nitrided gate oxide and boron-doped silicon the process budget), this is driven by two other factors: the 27
germanium (SiGe:B). There are important process control introduction of many new materials and innovative structures1-5
28
in both the front end and the back end, and the migration
of metrology from proxy measurements of films on monitor 29
er ALD-Seed Elect wafers to measurements on product wafers. 30

ar r i r ol
D-B es s
AL Cu 31
-K m inated Material At the front end, many new materials introduce new chal-
ow La En
E
gi lenges for metrology and process control. The challenges begin 32
ng
Pd
L
ne
a-
+ HfO2 BS
in
O3
tr
T
Al 2 with the gradual migration from Si to silicon-on-insulator
ee
l
er
2 U
Ni 33
re
Ru
ed
O3 (SOI) substrates. These changes generate new requirements:

dM
O
N4 P
C-Si
34
ate
Al
at e
3 SOI substrates require monitoring of the thickness and uni-

Ti
TiN
ol
Si
rial
y
r ia l
2
SiOC
HfO
I S formity of the thin superficial silicon layer and buried oxide. 35

Co
SO
iG
The use of SOI substrates also makes it much more difficult

e
36
Substrate
to measure gate dielectrics and multilayer structures. The fact
37
Si-Epi
that superficial Si is transparent at HeNe wavelength (633nm)
W
O makes this a multiparameter measurement (simultaneously 38

x
ix
P-
O
Si
SiO
WS
HD
x
2
Si
Hf
Isolation
measuring gate oxide, superficial Si, and buried oxide), which
W
SG
y
x
O2
39
N
SiO
SiO ly
BP
Po
y
L is impossible with standard fixed-angle, single-wavelength

ol
P
A
N
2O 2 Transistor
y
40
xN
3 y
xN ellipsometry (SWE).
PS
S iO
i
iS
Si O T
G
Cu 2
Capacitor TiN 41
Ta
/Ta Ti
N Al
W Multiple approaches are being pursued to introduce strain 42
Interconnect
in the Si channel. These include the use of SiGe:B (need to
monitor Ge, B and SiGe:B thickness) in source/drain areas to 43
compressively stress the channel, and the use of highly stressed 44

Figure 1: Many new and highly complex materials are being introduced
at a faster rate compared with previous technology nodes.
nitride layers (monitor stress) to introduce tensile or compres- 45
sive stress in the channel. The process control requirements
46
M etrology
and methods vary depending on the path used. Gate oxide As geometries shrink, many critical processes are impacted. In 1
dielectrics are becoming thinner and more heavily nitrided, shallow trench isolation (STI), for example, there is a marked 2
requiring control of both thickness and nitrogen in the oxide. lack of correlation between CMP rates on pads in the scribe 3
lane and CMP rates in the die. For process control in STI, in-die
High-k gate dielectrics will most likely be first introduced at measurements of oxide and nitride film stacks are required. 4
the 45nm node. Candidate materials like HfSiOxNy require 5
the monitoring of multiple elements/compositions simulta-
neously for effective process control. Along with the difficulty Solving Film Metrology Problems 6
of monitoring more variables, the allowed variation for each of Optical thin film metrology, largely based on SE, is used ex- 7
these variables typically gets tighter, since the error bars from tensively for process control throughout the fab. SE is a rapid, 8
these parameters can add up to consume the total metrology nondestructive technique used for both monitor and product 9
budget. There are additional challenges associated with high-k wafer measurements. The SE technique comprises two key
metrology, including monitoring the metal gate electrodes and 10
ingredients: hardware with good spectral fidelity to extract
the interfacial layer between the high-k dielectric and silicon. information from the films and applications expertise to create 11
In the front end, bilayer and nanolaminate-based high-k material viable solutions using the spectral information and algorithms 12
stacks for capacitors are also being introduced. tools. Recent advances on both fronts have led to viable SE-
13
based solutions for applications like compositional monitoring
While there are many more challenges arising in the front end, 14
of complex films in both R&D and production environments.
the introduction of low-k materials and copper also brings sig-
15
nificant challenges to the back end. The use of low-k C-doped The primary improvements from a hardware perspective are
oxides (CDO) with the associated barrier and etch stop layers improved optics design, leading to better spectral fidelity, and 16
demands tighter metrology control with more complex stacks. extension of SE to DUV wavelengths (down to 150nm). Com- 17
Porous low-k dielectrics add complexity since, while it appears bined, these two factors are important because the extension to 18
at this time that pore size and pore distribution are parameters DUV wavelengths enables the extraction of more information
that may not be required for production monitoring, an from the thin dielectric films that have more absorption at 19
estimate of porosity and/or dielectric constant is required for these wavelengths, while spectral fidelity gives better resolu- 20
production control. tion and minimizes the metrology error bars, helping to satisfy 21
increasingly stringent requirements.
The trend toward product wafer metrology is driven largely by 22
a desire to eliminate monitor wafers, especially at 300mm. In The quality of spectral fidelity can easily be determined by 23
some instances, in-die measurements are required for process evaluating the spectral errors (differences between measured
control due to a lack of correlation between variations in the 24
spectra and theoretical spectra) from a thin oxide film. As an
die and larger features in the scribe lanes.6 Product wafer example using KLA-Tencors tools, examine the spectral quality of 25
measurements are usually done on large pads in the scribe lane. two generations of production SE systems (Figure 2). The errors 26
27
28
Residual spectral errors
29
ASET-F5x SpectraFx 30
0.03 0.03 Error-SE1 31
0.02 0.02 Error-SE2
Error-SE3 32
0.01 0.01 Error-SE4 33
SE
SE
0.00 0.00 Error-SE5

34
-0.01 -0.01
35
-0.02 -0.02
300 400 500 600 700 300 400 500 600 700 36
37
0.02
0.02 38
0.01
39
0.00 0.00
40
SE
SE
-0.01
-0.02 -0.02
41
-0.03
-0.04 -0.04 42
300 400 500 600 700 300 400 500 600 700 43
44
Figure 2: Residual spectral errors are close to zero across all wavelengths, and the residual error signature is repeatable in newer generations of SE systems. 45
46
M etrology
are plotted on the same scale in both sets of graphs. It is seen interested in pursuing the matter in more detail.6 Using 1
that the residual errors on the newer SE systems are consider- ellipsometric techniques and a desorber to address AMC, a 2
ably smaller across all the wavelengths and close to zero. The viable production-proven solution has been formulated for 3
magnitude of the errors on these production tools was found monitoring the thickness and nitrogen concentration (%N)
to be comparable to that of errors from a research-grade system in thin SiON gate dielectrics. The solution has repeatedly 4
using a similar test. Equally as important, it is seen that the demonstrated good correlation between the measured SE 5
signa-ture of the remaining small residual errors on the latest parameter and %N baseline data across wide DoE. This type 6
SE tools is virtually identical from one system to another. of optical solution is currently implemented successfully at
7
From a spectral standpoint, the measurement hardware is in- several fabs worldwide.7
trinsically matched. High spectral fidelity and system-system 8
spectral matching are key factors for meeting the extremely 9
High-k Gate Optical Metrology
tight requirements on the most challenging film applications.
10
Candidate materials are largely Hf-based oxides or silicates
Any discussion of optical monitoring of thin gate dielectric and include HfO2, HfSiOx and HfSiOxNy. With these ma- 11
films must address the issue of airborne molecular contami- terials, there is typically an interfacial layer about 510 12
nation (AMC). Detailed discussions are available for those thick between the 20-40 high-k dielectric and silicon. The
13
interlayer has a lower dielectric constant than the bulk high-k
material. Process control schemes typically rely on thickness 14
SE vs XPS and composition monitoring of bulk high k dielectric, coupled 15

with electrical monitoring of the interface between the high-k
a) %SiO2 in HfSiOx 16
dielectric and silicon. These high-k materials optical proper-
ties vary systematically with composition. At lower wave- 17
lengths, especially in DUV down to 150nm, there is increased 18
50%SiO2
sensitivity to these materials due to increased absorption. Using 19
%SiO2 (SE)
this information, and by leveraging recent advances in the

hardware, algorithms and applications methodologies, SE can 20
simultaneously monitor two compositional parameters. 21

y = 0.9881x + 1.0923
R2 = 0.9954 22
Figure 3 shows examples of optical measurements of composi-
tion in high-k films in a development fab. Figure 3a shows 23
%SiO2 (XPS) results across an HfSiOx DoE. In this case, SE was used to 24
map and output %SiO2 in the HfSiOx films. A wide range of
25
b) %SiO2 compositions, nearly 50% SiO2 variation in the HfSiOx, were
sampled across a DoE with multiple wafers. X-ray photoelec- 26
tron spectroscopy (XPS) was used as the reference technique. 27
Measurements at 21 sites were carried out across each wafer
25%SiO2 28
%SiO2 (SE)
(from center to edge) in the DoE using both XPS and SE.
DUV wavelengths down to 150nm were used to build up the 29
optical models. The results show a strong correlation between 30

y = 0.8012x + 11.828 the SE output for composition and the XPS baseline across 31
R2 = 0.9096
the DoE and within each wafer in the DoE. For the HfSiOxNy
32
films (Figure 3b), a recently developed algorithmic model was
%SiO2 (XPS) used to simultaneously compute both %SiO2 and %N in the 33
film. As with the HfSiOx films, 21 site measurements were 34
%N carried out across each wafer in the DoE to verify capability
35
to track compositional variation within each wafer across the
wide range of compositions in the DoE. Again, there is good 36
correlation with the baseline across the wide range of composi- 37
8%N
tions sampled in the DoE.
%N (SE)
38
39
y = 1.1088x + 1.0751 Monitoring Bilayer Structures
R2 = 0.9676 40
As with the high-k materials, there is a systematic variation in
41
optical properties of SiGe with increasing Ge concentration.
%N (XPS) The presence of boron (B) at high dopant concentrations has a 42
secondary effect on the optical properties. Using a DoE with 43
relatively constant B concentration (with some variation) and a
44
Figure 3: (a) Tracking composition in HfSiOx films with SE; (b) Simul- systematic variation in Ge concentration, an SE-based optical
taneous determination of two compositions in HfSiON films with SE. solution was formulated to measure both single-layer SiGe:B 45
46
M etrology
and bilayer Si-cap/SiGe:B/Si structures using the same recipe. six-layer, low-k BEOL film stack, a seven-wafer DoE was 1
The SiGe:B and Si-cap layers thicknesses were simultaneously carried out to evaluate the measurements robustness in cor- 2
measured along with Ge concentration in the SiGe:B layer. rectly predicting the introduced changes with a single recipe. 3
Here, X-ray diffraction (XRD) and secondary ion mass spec- Sixteen parameters were measured simultaneously: thickness,
trometry (SIMS) were used as baseline techniques. As with the n, and k for all the layers except the top oxide layer, where 4
other applications described earlier, excellent correlation was only the thickness was measured. The refractive index was 5
achieved between the optical measurement of Ge concentration not measured for the oxide layer on top since this is usually 6
and the baseline techniques. well controlled. It is seen thatwith a single recipethe
7
various changes simultaneously introduced in this seven-wafer
The ability to track multiple parameters simultaneously in a DoE can be correctly predicted. The circles in different colors 8
production environment can be seen from the results in Figure 4. outline missing layers, double-deposited layers, half-deposited 9
Results from a four-wafer DoE with roughly similar SiGe: layers, and layers with a random variation in thickness.
B and Si-cap thicknesses, but varying Ge concentration, are 10
plotted. Measurements were carried out from the center to the The migration of metrology from monitor wafers to product 11
edge of the wafer using a standard nine-site Prometrix pattern. wafers is being accelerated with the introduction of 300mm
12
The nominal thickness of the SiGe:B layer was in excess of wafers. On monitor wafers, it is easier to keep the metrology
1000, with a thin Si cap layer. Within the nine-site pattern, simpler and monitor individual films or processes. Product 13
the signature of the reactor was reproduced for the SiGe:B wafers call for the added requirement to monitor the same films 14
and Si-cap thicknesses at varying Ge concentrations. The data and processes in multilayered stacks. Metrology requirements 15
from three tools in a production environment also show that for individual films and processes are unchanged, though the
16
the results for the different parameters are well matched. Such
tool-tool matching is possible because of the spectral fidelity 17
described earlier. Multiple parameter tracking
18
%Ge in the SiGe:B layer in Si-cap/SiGe:B/Si 19
Ultra-thin ONO Film Stack Metrology
20
wfr4
Thin oxide/nitride/oxide (ONO) film stacks are used in both 21
DRAM and Flash memory stacks. At the 90nm node, the 10%range
wfr3
22
target for the nitride thickness of floating-gate Flash is around
%Ge
50 (and may be as low as 30 for 65nm). This is a challeng- wfr2 23
ing measurement due to extremely high correlation demands wfr1 Tool A
24
Tool B
between the top and bottom oxide layers. The extent of the Tool C 25
correlation is driven by the thickness of the nitride layer separat-
ing the two oxides, since correlation increases significantly as 26
the nitride gets thinner. Because the nitride film has increased Si-cap thickness in Si-cap/SiGe:B/Si 27
absorption characteristics at shorter wavelengths, use of shorter Nom + 40 28
wavelengths increases the contrast between the top and bottom wfr3 wfr4
Si-cap thickness ()
wfr2 29
oxides. To enable these measurements, SE technology must be wfr1
extended down to DUV wavelengths (190nm) for ONOs with 30
the nitride at 50, and down to VUV (150nm) for ONOs with Nom
31
nitrides down to 30. Tool A
32
Tool B
The capability of both 190SE and 150SE systems to accurately Tool C 33
Nom - 40
track the introduced process changes was monitored. It is seen
34
that both the systems accurately track the nitride thickness.
The 190SE system shows a flat response for the top and bottom SiGe:B thickness in Si-cap/SiGe:B/Si 35
oxide thickness down to a nitride thickness of 50, but begins Nom + 150 36
to show deviations and correlations between the oxides when the
37
SiGe:B thickness ()
wfr1 wfr2 wfr3 wfr4

nitride thickness is lower. The 150SE system, on the other hand,
shows a flat response for the top and bottom oxide thicknesses for 38
Nom
the entire DoE, per the design. So for thin ONO stacks with the 39
nitride thickness below 50, 150SE capability is recommended Tool A 40
to monitor the process. Tool B
Tool C 41
Nom - 150
42
Multilayer, Multiparameter Measurements
Figure 4: Simultaneous measurement of thickness of Si-cap and 43
Table 1 (next page) shows an example of the type of measure-
thickness and composition of SiGe:B layer across Ge concentration
ments achieved using advanced systems with high spectral 44
DoE with SE. Good tool-tool matching in a production environment
fidelity and robust algorithms. In this measurement of a is especially important. 45
46
M etrology
measurement is more complicated since more parameters must Acknowledgements 1

be simultaneously measured in a film stack. Spectral fidelity The author wishes to thank several colleagues for detailed 2
and tool-tool spectral matching become more critical for technical discussions on several metrology topics and for 3
multilayered films. The above example for the measurement of making available many of the figures used. They include
multiple parameters in a six-layer stack illustrates the evolution 4
Arun Chatterjee, Torsten Kaack, Zhengquan Tan, Sungchul Yoo
of this capability. It must be noted, though, that in typical and Shankar Krishnan from KLA-Tencor; and Simona Spadoni, 5
production environments one does not measure so many Rosella Piage and Davide Lodi from ST Microelectronics. 6
parameters simultaneously.
Note: This article was originally published in Semiconductor 7
International magazine, December 2006. 8
SE into the Future
9
SE continues to be the technology of choice for production References
10
monitoring of films in todays fabs. The continual advance- 1. International Technology Roadmap for Semiconductors,
ments in spectral fidelity, extension of SE to lower wave- http://www.itrs.net. 11
lengths, and improvements in hardware, algorithms, and 2. Y.-C Yeo, Q. Lu, T.-J King, C. Hu, T. Kawashima, M. Oishi, 12
applications capabilities are enabling the use of SE technology S. Mashiro and J. Sakai, Proc of the International Electron Devices Meeting
13
to report additional parameters like compositions in very thin (IEDM), p. 753, 2000.
to thick films, potentially satisfying the increasingly complex 14
3. H. van Meer and Kristin De Meyer, 2002 Symp. on VLSI
metrology requirements at the 65 and 45nm nodes. Opti- Technology, Digest of Technical Papers, p. 170 2002. 15
cal film metrology solutions based on SE are currently being 4. H.S.P. Wong, IBM Journal of Research and Development, V46, N2/3, 16
adopted to monitor composition in several complex processes 2002.
involving nitrided oxides and SiGe:B, and in the development 17
5. David Lammers, EE Times, 4/4/2005.
of high-k materials. Recent technology advances on multiple http://www.eetimes.com/showArticle.jhtml?articleID=160401538. 18
fronts are also facilitating the accelerated migration to product 6. Arun R. Srivatsa, Yield Management Solutions, Winter 2005, p. 22. 19
wafer metrology and multiparameter, multilayer measure-
7. Sungchul Yoo, Zhiming Jiang, Eric Wang and Zhengquan Tan, 20
ments throughout the fab. With these continued advances, YMS Seminar, Semicon West, San Francisco, July 2006.
SE-based films metrology could continue to be the workhorse 21
technology for production metrology at 45nm and beyond. 22
23
24
Seven-wafer DoE of six-layer low-k stack 25
26
Wafer 1 Wafer 2 Wafer 3 Wafer 4 Wafer 5 Wafer 6 Wafer 7 27
28
Ox
Thickness Mean 650.6 1048.5 9.9 1007.5 1019.9 1045.4 1001.3 29
30
SiC(1) Low-K SiC(2)
Thickness Mean 653.4 577.3 613.6 647.2 617.0 593.9 649.4 31
RI @ 633 nm Mean 1.7161 1.7224 1.7370 1.7075 1.7193 1.7210 1.7095 32
33
Thickness Mean 2568.9 2640.4 2513.1 2575.5 1238.1 4939.2 2561.6
34
RI @ 633 nm Mean 1.3807 1.3640 1.3805 1.3662 1.3785 1.3713 1.3647
35
Thickness Mean 423.4 414.8 419.6 789.4 412.9 418.4 363.3 36
37
RI @ 633 nm Mean 1.8548 1.8384 1.8472 1.8368 1.8418 1.8441 1.8394
38
Low-K
Thickness Mean 1266.1 4921.4 2491.6 2551.3 2501.1 2468.0 56.4 39
RI @ 633 nm Mean 1.3943 1.3923 1.4042 1.3907 1.3925 1.4069 1.4153 40
41
Thickness Mean 524.0 529.2 526.7 526.2 515.6 521.3 559.3
SiN
42
RI @ 633 nm Mean 2.0350 2.0317 2.0443 2.0361 2.0572 2.0526 2.0594
43
44
Table 1: Robustness of measurement of this six-layer low-k stack across a seven-wafer DoE was tested by randomly introducing missing layers, double-deposited
layers, half-deposited layers and other variations in the film stack. 45
46
F ab E conomics
1
Reducing Cycle Time 5
Has Many Benefits 7
Doug Sutherland KLA-Tencor Corporation 9
10
11
12
13
As consumer electronics increasingly drive fab economics, cycle time of wafers within the fab largely determines the
14
time to market of semiconductor products. Decreased cycle time and increased operational efficiency can provide higher
15
availability and speed time to market in the wafer fab environment. 16
17
Metrology and inspection steps usually account for about 5% market turns down. One of the best value statements for cycle
18
of a wafer fabs total cycle time, but the value they provide in time was summarized by Clayton Christensen2 who said,
terms of improved yield is typically an order of magnitude 19
greater than the cycle time cost that they impart to the process. Extending development an extra day, to get a stepper or 20
However, a cycle time management program, to be success- process qualified, is like paying $3.44 for every wafer that
the factory will make. In addition, if it takes one more day to 21
ful, must be a fab-wide activity with equal attention paid to
reducing the cycle time at every toolset in the fab. In recent reach mature die yield, it is like paying $1.35 for every wafer 22
years there has been a trend in wafer fabs away from maximiz- that will be made, or if the cycle time is one day longer, it is 23
ing tool utilization, which reduces cost per wafer, and toward like paying $3.04 per wafer.
24
minimizing cycle time, which increases revenue and profit. From this quote we can get a feel for the value of CT, which 25
The two objectives are at odds with each other, as decreasing is approximately $1 million per year for every day of CT
utilization decreases cycle time but also decreases producti- 26
reduction (30,000 WSPM x 12 months x 3.04 per wafer =
vity. The optimal operating point is one that strikes a balance $1.1 million per year). 27
between the two.
28
Mathematically, CT is equal to the queue time (the time a lot
Reduced cycle time (CT) has many benefits; the primary one spends waiting to be processed) plus the processing time (the 29
is faster time to market. The price of nearly all semiconduc- time it spends in the tool). The processing time is a straight 30
tor products, DRAM, Flash, Logic, etc., declines rapidly over forward calculation but the queue time (QT) is the product of
time - typically from 50% to 80% per year from the time 31
three separate functions.3
the product is first released. Shorter CT ensures less decline 32
in price from the time the product enters manufacturing to QT = {(Variability)} {(Utilization)} {(Availability)} 33
the time it reaches the market, thereby commanding a higher
34
ASP. The other benefits revolve around having shorter cycles of There is no single correct version of the equation above; it comes
learning (COL) and reduced work in progress (WIP). In R&D in several incarnations with varying degrees of complexity 35
shorter COL equates to shorter development time and, when depending on the level of detail one wishes to incorporate. 36
transferred to production, faster yield ramp. The relationship However, essentially all the mathematical expressions of QT
37
between WIP and CT is expressed through what is called have the following four features in common:
Littles Law:1 38
1) A system with no variability has no queue
39
WIP = (CT) x (Start Rate) time: when (Variability)=0, QT=0
40
2) (Utilization) is proportional to 1/(1-Utilization):
From the equation above it can be seen that, for a given start CT increases exponentially with increased utilization. 41
rate, the WIP will decrease linearly with CT. The advantage of 3) (Utilization) is also proportional to 1/(# of tools): 42
this are that there are fewer lots in the fab at any given time, CT decreases with more tools.
which reduces overhead, exposes fewer lots to any required 43
4) (Availability) is proportional to 1/(Avail-
process changes, and reduces the number of lots at risk during ability): CT decreases exponentially with 44
any yield excursions that may occur. Carrying less WIP also increased availability (uptime). 45
means there are fewer unfinished goods on hand when the
46
F ab E conomics
Low utilization and high availability do not in themselves en- often adopt the pragmatic philosophy that if were here to fix 1
sure that the CT will be low; only by eliminating all sources of Problem A we might as well do adjustments B, C and D at 2
variability can one guarantee that the QT will vanish. Mathe- the same time. This well-intentioned approach increases the 3
matically, variability is measured as the standard deviation of a tools MTBI and MTTR but does not substantially improve the
availability (i.e., the total repair time remains unchanged) and 4
system divided by its average. In a wafer fab variability comes
from three main sources: consequently increases the CT. Often our best intentions tend 5
to be counter-intuitive (and counter-productive) in terms of 6
1) Variability in the lot arrival rate reducing our customers CT.
2) Variability in the lot processing time 7
3) Variability in the downtime of the tool 8

Large fabs generally have lower 9
Figure 1 shows the operating curve (a plot of CT vs. utilization)
for identical toolsets with one to five tools assuming unit varia- CT and lower cost per wafer 10
bility and 100% availability. The salient point here is that
changing from one tool to two does much more than simply
because they can run their tools 11
12
double the capacity. For the same CT as one tool at 60% uti- at higher utilization without 13
lization, you can run two tools at nearly 80% utilization. Not
only do you have twice as many tools but each one of them is climbing into the steepest part 14
processing about 30% more wafers a 260% improvement.
The impact of having n+1 tools is less dramatic with larger
of the operating curve. 15
16
toolsets but the same principle applies and this is one of the
Another interesting case is that of matching, as having dedi-
underlying tenets of the economy of scale enjoyed by larger 17
cated (or golden) tools is one of the worst things for CT.
wafer fabs. Large fabs generally have lower CT and lower cost 18
Figure 3 shows the impact to CT of having five matched
per wafer because they can run their tools at higher utilization
brightfield inspection tools inspecting five layers in the process 19
without climbing into the steepest part of the operating curve.
versus 4 matched tools inspecting four layers and one dedicated 20
In addition to the number of tools, the other first-order effects (golden) tool inspecting one layer (for the sake of simplification
21
on CT are the related variables, availability and utilization. this assumes 100% sampling). Instead of having five layers all
If we artificially set availability and utilization to 95% and experiencing cycle times represented by the operating curve for 22
85%, respectively, we can see some interesting and unexpected five tools (see Figure 1) you have four layers with cycle times 23
trends in cycle time. For instance, for a given availability, CT represented by the curve for four tools and one layer with a CT
24
actually increases with increasing MTBI. That is, it is better to represented by the curve for a toolset with only a single tool.
divide the same downtime into many short events (low MTBI The net effect of unmatched tools in this case is to double the 25
and low MTTR) rather than fewer long events (high MTBI total CT for that toolset (Figure 3). Fabs can mitigate the effect 26
and high MTTR), as shown in Figure 2. This isnt a problem of this by treating the tools as if they were matched whenever
27
in terms of tool design, as we usually make the assumption the golden tool is unavailable (i.e., instead of holding the lot to
wait for the golden tool they run it on one of the other tools), 28
that higher MTBI (fewer system-down events) equates to
higher availability. However, from a service perspective we but this comes at the cost of increased beta risk. 29
30
31
6 4.0 32
Cycle Time ( x Process Time)
1 Tool 1000 Hrs MTBI

5 2 Tools 100 Hrs MTBI 33
3 Tools 3.0
Cycle Time (Days)
4 4 Tools 34
5 Tools
35
3 2.0
36
2
37
1.0
1
38
0 39
0.0
0% 20% 40% 60% 80% 100%
50% 60% 70% 80% 90% 100%
40
Utilization
Utilization 41
42
Figure 1: Cycle Time vs. Utilization for a toolset with 1 to 5 tools. Units Figure 2: Cycle Time vs. Utilization for two toolsets with the same avail-
of CT are in multiples of the tools processing time. Large fabs with ability (95%) but different MTBI (and MTTR). From a CT perspective, for 43
more tools in each toolset have an advantage because they can run at the same availability, it is better to have many short down events (MTBI 44
higher utilizations without as much impact on CT. = 100 Hrs) than comparatively fewer long ones (MTBI = 1000 Hrs). The
difference in this example is about 1 day at 85% utilization. 45
46
F ab E conomics
Service contracts provide a threefold advantage for cycle time 1

management. First and foremost, they increase the availability 2
4.0
1 Golden & 4 Matched
of the tool. This in turn has the added advantage of automati- 3
5 Matched Tools cally reducing the utilization (utilization is equal to produc-
3.0 tion time divided by available time). Finally, service contracts 4
Cycle Time (Days)
significantly reduce the variability in the downtime, which 5

itself is a significant contribution to CT. Figure 4 shows the 6
2.0
operating curves for six brightfield inspection tools under two
7
different conditions: one where their reliability characteristics
1.0 are typical of billable tools and the other where the six tools 8
are covered under a service contract. The faster response time 9
0.0
(less time down, higher availability) and the reduced variability
10
50% 60% 70% 80% 90% 100% in the downtime result in a CT reduction of about 1.9 days.
Another key factor is that because utilization is equal to the 11
Utilization
production time divided by the available time, a toolset run- 12
ning at 85% utilization while billable can be run at about
13
Figure 3: Dedicating layers to specific golden tools creates a single 82% utilization under service contract.
tool environment (see Figure 1) and causes a dramatic increase in 14
cycle time that is exacerbated at higher utilizations. In this case the As the IC industry becomes increasingly driven by consumer 15
cycle time almost doubles as a result of having unmatched tools. electronics, cycle time (or equivalently, time to market) will
16
become ever more important to wafer fabs as they strive
to produce exactly the right amount of product at exactly 17
4.0
the right time. Being the first IC manufacturer to provide 18
Billable engineering samples to a prospective customer can result in
19
Contract design wins that could literally make or break its business.
3.0 Similarly, being caught with hundreds of millions of dollars 20
Cycle Time (Days)
worth of WIP still in the pipeline when the market enters a 21

2.0 downturn or when the consumer simply moves on to the next
22
new thing can make the difference between a year that closes
with a profit and a year that closes with a loss. There are, and 23
1.0
will continue to be, niches within the IC industry where cycle 24
time is less important, but the general trend for the foreseeable 25
0.0 future is in the direction of decreased cycle time and increased
50% 60% 70% 80% 90% 100%
operational efficiency. As a result of this, more emphasis will 26
Utilization be given to products and services that provide higher availability 27

and that reduce variability in the wafer fab environment. 28
Figure 4: The cycle time impact of converting six brightfield tools from
billable to service contract. The increased availability achieved by 29
having the tools on contract flattens out the operating curve and also References
30
contributes to lower utilization (utilization equals production time divided
by available time). For tools that are at 85% utilization when billable, a
1. W.J. Hopp and M.L. Spearman, McGraw-Hill, Factory Physics, 2001, p. 223.
31
service contract can reduce the cycle time by 1.9 days. 2. Clayton Christensen, Solid State Technology, August 2001.
3. W.J. Hopp and M.L. Spearman, McGraw-Hill, Factory Physics, 2001, p. 325. 32
33
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35
36
37
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40
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44
45
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1
Field Results From 45nm 5
Die-to-Database Reticle Inspection 7
William Broadbent, Ichiro Yokoyama, Paul Yu, Heiko Schmalfuss, Jean-Paul Sier KLA-Tencor Corporation 9
Ryohei Nomura, Kazunori Seki Toppan Printing Co., Ltd
10
Jan Heumann Advanced Mask Technology Center GmbH & Co
11
12
13
Testing of the TeraScanHR system at Toppan and the AMTC demonstrated high sensitivity, low false detections, and high
14
scan speed. The systems higher NA optics, new autofocus, smaller pixel size, and improved rendering and modeling
15
algorithms resulted in significant improvements in inspection capability of small linewidths, small defects, and aggressive 16
OPC. Reflected light inspection integrated with transmitted light can be used with no additional scan time for some modes, 17
18
providing the best defect detection capability and resulting in the highest quality reticles.
19
A new reticle inspection platform, the TeraScanHR, improves tivity and inspectability when using the available pixel sizes 20
upon the prior TeraScanTR platform with higher optical imaging (72/90/125/150nm). The beta systems are currently being 21
resolution to better resolve small features; higher precision used for advanced production.
22
database modeling to better represent small OPC in die-to-
database inspection; and higher speed image processing for 23
Reticle Inspection Development
higher productivity, especially when using integrated modes 24
(e.g., transmitted + reflected). Besides its 45nm capability, the To serve the 45nm node advanced production requirements
25
TeraScanHR platform can also be configured for 65nm, 90nm, and 32nm node development requirements, the TeraScanHR
and 130nm nodes. platform delivers higher performance and new capabilities. 26
This platform can be configured as a variety of different models 27
This paper describes technical aspects of the TeraScanHR that are intended to cost-effectively inspect reticles from the
28
platform and presents selected results from the field testing 130nm node to the 32nm node. In this way, a reticle manu-
of beta systems located at Toppan Printing in Japan and the facturer or wafer fab can purchase just the capability needed 29
Advanced Mask Technology Center in Germany. The testing at the time, and then upgrade as more capability is needed in 30
used applicable programmed defect test reticles to measure the future. A typical TeraScanHR system is shown in Figure 1 31
defect detection sensitivity, along with a large set of product (note that the three electronic racks may be remotely located).
and product-like reticles from the 90nm to the 32nm logic 32
nodes, and comparable memory nodes, to assess both sensi- The new systems imaging technology uses significantly higher 33
resolution imaging of the reticle than the wafer lithography
34
system, allowing direct inspection of both the primary struc-
tures and the sub-resolution structures; its single wavelength 35
can provide good performance inspecting reticles from a 36
variety of lithographic wavelengths. The TeraScanHR handles
37
typical binary (COG), 6% EPSM (including simple tri-tone),
and dark field alternating PSM reticles. The system supports 38
both transmitted and reflected light inspection modes, which 39
can be easily integrated into a single inspection.
40
Using the new 72nm pixel, the system enables development 41

of 32nm logic reticles and approximately 45nm half-pitch 42
memory reticles. Additional capability extensions are in de-
43
velopment for more aggressive RET, such as Mask Enhancer,
complex tri-tone, and chromeless. Larger pixels are available 44
Figure 1: The new TeraScanHR system enables 45nm generation
mask inspection.
with faster scan times for the 65nm logic node up to the 45
130nm node.
46
M ask
Image Acquisition To achieve the needed performance level, the new system pro- 1
The image acquisition subsystem is shown in Figure 2. A vides a higher NA capability to resolve smaller lines, OPC, 2
high-resolution microscope and linear sensor architecture are and defects (approximately 1.2 times higher NA than the 3
used with both transmitted and reflected illumination paths. previous 90nm pixel TeraScanTR platform). The higher NA
supports the new 72nm pixel. A new autofocus subsystem 4
The illumination source is a 257nm wavelength continuous provides the necessary precision for the higher NA optics, 5
wave (CW) laser (>5,500 hours lifetime). An active beam which have lower depth of focus; an advanced pre-mapping 6
steering subsystem compensates for beam drift. The transmit- technique improves the ability to maintain proper focus,
7
ted illuminator has several different configurations that can especially when inspecting reticles with significant topology
be selected by the user. Two illuminator configurations are such as the quartz etch types. 8
currently implemented: standard contrast for COG and EPSM 9
reticles, and phase contrast for quartz etch reticles such as al- Image Processing 10
ternating, Mask Enhancer, chromeless, etc. The phase contrast
mode provides improved imaging contrast to quartz phase de- The TeraScanHR image processing subsystem features a Tera 11
fects (bumps and divots), allowing for higher defect sensitivity. Image Supercomputer, which utilizes a fully programmable 12
and scalable multi-processor architecture using high-speed
13
The custom-designed objective images the reticle surface processors.
through a zoom lens onto the imaging sensor. The zoom 14
lens allows different pixel sizes to be selected by the user at The basic detection method is to overlay a test image with
15
runtime; this provides faster scan times when a less sensitive a matching reference image and identify differences above a
pre-selected size; since the images should basically match, any 16
inspection is desired four pixel sizes are available depending
upon the model (72, 90, 125, and 150nm). Image pickup is differences are the result of a defect. For die-to-die inspection, 17
done with a time-domain-integration (TDI) sensor, which of- the test and reference images compared are from adjacent die; 18
fers high-speed continuous image pick-up at much lower light for die-to-database inspection, the reference image is recon-
structed from the design or write database. For a STARlight 19
levels than a conventional CCD linear sensor.
inspection, the transmitted light image is compared to the 20
For reflected light inspection, the system uses a single imaging reflected light image any differences are the result of a con- 21
sensor with a switching device to select between transmit- tamination-type defect.
ted and reflected illumination. This allows an integrated 22
inspection using both transmitted and reflected illumination The new image computer uses higher speed processors and 23
(integrated T+R mode). Since each illumination mode has the contains 2x the number of processors compared with the
24
best performance for different classes of defects and different previous image computer. The additional processing power
improves scan time for the more processing-intensive modes; 25
geometry types, the integrated T+R mode provides the highest
quality inspection. this can also allow multiple modes to be processed together 26
with minimal inspection slowdown. For example, a transmit-
27
ted light inspection and a reflected light inspection can be
processed together without slowing the inspection station; this 28
allows a much more cost-effective T+R inspection than the 29

Condenser prior TeraScanTR system. 30
Additional processing blocks for die-to-database inspection 31

Transmitted
Photomask
Illumination
reconstruct a database image in real time from the reticle design 32
or write database. Sophisticated modeling algorithms ensure
33
Objective that the database image exactly matches the optical image since
DUV
Laser Source
any error reduces defect detection sensitivity. A new die-to-da- 34
Reflected tabase defect detection algorithm, UHR, provides much more 35

Illumination precise modeling of small OPC structures in both transmitted
36
and reflected light as compared to the previous algorithm. The
test image is subtracted from the reference image to produce 37
a difference image. Since the test and reference images should 38
Reflected exactly match, the difference image should have a uniform gray
39
Image background except where there is a defect.
TDI Sensor 40
Transmitted
Image 41
Test Results
42
Figure 2: High resolution transmitted and reflected images show that Four months of field testing and tuning at Toppan Printing in
the sub-resolution clear serifs are fully imaged and clearly visible. An Japan and the Advanced Mask Technology Center (AMTC) in 43
oversize clear serif defect is present and visible in both the transmitted Germany provided extensive verification of system performance. 44
and reflected images, whereas a particle on the dark material is also Each beta site verified the sensitivity and false detection perfor-
present but is only visible in the reflected light image (dark spot). 45
mance using K-Ts standard programmed defect test reticles, as
46
M ask
well as unique test reticles from each site. The customers test 1
reticles contained geometry patterns typical of the 32nm, 45nm, 2
Prior Image Acquisition New Image Acquisition and 65nm logic nodes, as well as the 5xnm half-pitch memory 3
Difference Image Difference Image node. These reticles were tested at both maximum sensitivity
settings and a variety of production settings. 4
Small lines &
dark SRAF 5
Production-suitable detector settings were also determined by
Same pixel 6
Real using a variety of product and product-like reticles from the
90nm defect 45nm, 65nm, and 90nm logic nodes and the 4xhp, 5xhp, and 7
Same algo 7xhp memory nodes. These reticles were for ArF lithography 8
UCF (old) and included primarily critical layers of 6% EPSM, with some
9
dark field alternating PSM and EUV reticles. The testing
Imaging limitations Improved imaging demonstrated excellent full-area inspection of advanced product 10
Optical & database Better optics reticles with aggressive OPC, showing high sensitivity and low 11
matching errors New autofocus
false detections.
False detection Improved stage 12
13
Improved Imaging with New Image Acquisition
14
Figure 3: Comparison of imaging small SRAF between prior image
The improved optical imaging uniformity of the new system
acquisition and new image acquisition. 15
can be seen on small structures, such as SRAF. Figure 3
shows a comparison of SRAF difference image noise between 16
the previous system (left side) and the new TeraScanHR 17
90nm Pixel 72nm Pixel (right side). These difference images are from the same 65nm
Transmitted light 18
Spica-200 193
node reticle using the 90nm pixel and the previous UCF
die-to-database algorithm. 19
260nm dark line
20
The lower noise and improved imaging uniformity are a result
21
of the new autofocus subsystem, lower aberration optics, and
lower vibration stage. In this example, there is still some 22
1.25x Mag
noise in the difference image, which is caused by the older 23
UCF algorithm and its limited modeling capability of small
Dark extention 24
structures. The new UHR algorithm includes higher-precision
defect ~ 30nm
modeling, which will result in lower noise difference images 25
and lower false detection rates. 26
~ 40% more
modulation 27
than 90nm pixel High Resolution and Improved Database Modeling 28
The new systems high NA optics enable a new 72nm pixel 29
that can resolve small OPC structures, small lines and spaces,
30
and small defects. Figure 4a compares a small dark extension
Figure 4a: Comparison of imaging a small dark extension defect defect imaged with the previous 90nm pixel (left images) and 31
between 90nm pixel and 72nm pixel. the new 72nm pixel (right images). The 72nm pixel has about 32
40% higher modulation (note the larger size and darker signal
33
Difference Image in the difference image). Additionally, the 72nm pixel includes
the new UHR family of die-to-database algorithms, which 34
provide higher precision modeling, resulting in lower noise in 35

45nm Logic 72nm pixel
the difference image and therefore lower false detection rates. 36
Poly Layer Database Transmitted
6% Tri-tone High detector settings Figure 4b shows the difference image from a 45nm logic gate 37
layer with aggressive OPC being imaged by the new 72nm pixel 38
Aggressive OPC UHR Algorithm
and the database modeled by the new UHR algorithm. The dif-
39
ference image shows very low noise on this small geometry, which
will result in low false detections and high detector settings. 40
Excellent matching
41
of optical image and
database model Die-to-Database Sensitivity for 72nm Pixel 42
Figure 5 (next page) shows typical sensitivity performance in 43

Figure 4b: Higher resolution enabled by a new 72nm pixel, plus new die-to-database mode using the KLA-Tencor Spica-200-193 44
database modeling, shows very low noise, low false detections and high programmed defect test reticle. This test reticle is standard
detector settings on this small geometry. 45
6% EPSM for 193 lithography and includes a typical semi-
46
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wire programmed defect test section in multiple linewidths, the 1

10
smallest being 260nm dark lines (shown). This result uses the 90nm P
2
72nm pixel die-to-database with transmitted illumination and 65nm P 3
the standard high-resolution detectors set at maximum sen- 45nm P
4
sitivity (HiRes1 and HiRes2). Each gray box indicates 100% 0
detection from 20 contiguous inspections. The upper number 5
CD
in the gray box is the defect size using the KLA-Tencor maxi- 6
mum inscribed circle (MIC) sizing method from SEM images.
-10 7
The lower number is the detection percentage. For the smallest
defect detected 100% in each column, the defect size is also 57% 8
shown in a larger font below the printed size for easier reading. 73% 9
Note that small pinholes are difficult to manufacture, so none -20
10
were present on the reticle for this upper portion (NP=no Target CD
defect present). Also, pinholes are best detected with reflected 11
Figure 6: Toppan 45nm process with a 57% process linearity improvement.
light rather than transmitted light due to imaging effects. 12
13
Toppan 45nm Process Level
is a line/space design while the Cyclics is a hole design (360nm
14
and 420nm). The Carbonate test reticle includes several rep-
The test reticles used at Toppan Printing were made with their resentative patterns for line/space critical layers typical of the 15
latest 45nm process. This process showed significant improve- 45nm node. These patterns contain aggressive OPC designs 16
ments in linearity, corner rounding, and resolution versus the with jogs, serifs, and SRAF and a variety of programmed defects
previous processes. Figure 6 shows a 57% improvement in 17
on or near both primary geometry and OPC structures.
linearity versus the previous 65nm process. 18
Figure 7 (next page) shows the defect detection performance of
19
the 72nm pixel in the die-to-database and die-to-die transmit-
Defect Detection Performance using Toppan 20
ted light modes for the 45nm section of the Carbonate test
Programmed Defect Test Reticles reticle (selected defects shown) when using the maximum 21
Toppan Printing designed two programmed defect test reticles detector settings, and also when using production settings. 22
for the purpose of testing advanced reticle inspection system The production settings were determined by inspecting more
23
performance (Carbonate and Cyclics). The Carbonate reticle than 50 different patterns and selecting the tightest setting
24
25
26
27
0.017m 0.000m 0.000m 0.000m 0.005m 0.005m 0.005m 0.005m 0.005m 0.005m 0.000m 0.000m
28
0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 29
0.019m 0.000m 0.000m 0.000m 0.010m 0.010m 0.010m 0.010m 0.010m 0.010m 0.000m 0.000m
30
0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 75.00% 95.00% 0.00% 0.00%
31
0.024m 0.015m 0.000m 0.018m 0.015m 0.015m 0.015m 0.015m 0.015m 0.015m 0.028m 0.000m
15nm 15nm 32
0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 5.00% 100.00% 100.00% 40.00% 0.00%
0.031m 0.022m 0.000m 0.030m 0.020m 0.020m 0.020m 0.020m 0.020m 0.020m 0.024m 0.000m 33
31nm 20nm 20nm 24nm
100.00% 0.00% 0.00% 0.00% 0.00% 0.00% 100.00% 100.00% 100.00% 100.00% 100.00% 0.00%
34
0.039m 0.031m 0.017m 0.030m 0.026m 0.026m 0.026m 0.026m 0.026m 0.026m 0.033m 0.000m 35
100.00%
31nm
100.00% 0.00% 0.00%
26nm
100.00% 90.00% 100.00%
Edge Placement
100.00% 100.00% 100.00% 100.00% 0.00% 36
0.039m 0.031m 0.028m 0.033m 0.031m 0.031m 0.031m 0.031m 0.031m 0.031m 0.034m 0.000m
37
31nm
100.00% 100.00% 0.00% 0.00% 100.00% 100.00% 100.00% 100.00% 100.00% 100.00% 100.00% 65.00% 38
0.046m 0.039m 0.032m 0.036m 0.036m CD0.036m 0.036m 0.036m 0.036m 0.036m 0.055m 0.033m
36nm 39
100.00% 100.00% 5.00% 100.00% 100.00% 100.00% 100.00% 100.00% 100.00% 100.00% 100.00% 80.00%
40
0.047m 0.046m 0.039m 0.017m 0.041m 0.041m 0.041m 0.041m 0.041m 0.041m 0.059m 0.044m
Outside
41
100.00% 100.00% 45.00% Corner
100.00% 100.00% 100.00% 100.00% 100.00% 100.00% 100.00% Diagonal
100.00% 100.00%
0.017m 0.017m 0.017m 0.047m 0.046m 0.046m 0.046m 0.046m 0.046m 0.046m Extension
0.046m 0.046m 42
Horizontal Inside
Extension
100.00% 100.00% Corner
100.00% 100.00% 100.00% 100.00% 100.00% 100.00% 100.00% 100.00% 100.00% 100.00%
43
44
Figure 5: Die-to-database transmitted 72nm pixel defect detection sensitivity with Spica-200-193 test reticle. 45
46
M ask
1
2
: p72 ddT Max Sense : p72 dbT Max Sense
: p72 ddT Production Sense* : p72 dbT Production Sense* 3
7
Pindot Extension Pinhole Mis-Place Mis-Place Intrusion Intrusion CD
50nm spec 50nm spec 50nm spec 25nm spec 25nm spec 50nm spec 50nm spec 25nm spec 8
10
11
12
13
14
15
16
17
18
19
*More than 50 various patterns tested
20
21
Figure 7: 72nm pixel sensitivity performance on Toppan 45nm line/space programmed defect test reticle (Carbonate) for selected defects.
22
23
that provide low false detections. Note that the production 24
: p72 ddT Max Sense : p72 ddR Max Sense settings provided virtually the same sensitivity performance
25
as the maximum settings. Note also that the die-to-database
: p72 dbT Max Sense : p72 dbR Max Sense
performance is very close to the die-to-die performance, which 26
indicates both very good database modeling and very good 27
reticle uniformity (die-to-die typically has the highest perfor-
28
mance since many system and mask errors are common).
29
Figure 8 shows the sensitivity relationships between die-to- 30
Small
Dark Extension Clear Extension Pinhole

die and die-to-database along with transmitted and reflected
31
light for the maximum sensitivity settings. This example
uses the Toppan Cyclics test reticle, which has various pro- 32
grammed defects using hole geometry patterns, including 33
both dense and isolated holes of various sizes. As shown in
Defect size
34
this example, the general relationships are: (1) die-to-die is
more sensitive than die-to-database, (2) transmitted light is 35
generally more sensitive than reflected light for dark defects, 36
and (3) reflected light is generally more sensitive than trans-
37
mitted light for clear defects. This suggests that the best
overall defect detection performance is achieved when both 38
transmitted and reflected light are used together. The green 39
Big
line shows the ITRS requirement. 40
Figure 9 (next page) shows the defect images and defect map 41
of an oversize SRAF defect in transmitted mode (32nm node 42
section of the Toppan Carbonate test reticle); the enhanced
Figure 8: TeraScanHR 72nm pixel sensitivity performance on Toppan 43
edges function is enabled to more easily discern the geometry.
45nm hole programmed defect test reticle (Cyclics) for selected
The low residue in the difference image indicated very good 44
defects and 360nm dense holes. Die-to-die and die-to-database
performance shown for both transmitted and reflected light.
database modeling of the small SRAF. The defect map has no 45
nuisance and no false detections.
46
M ask
Advanced Product Reticles using Die-to-Database 1
Transmitted Light Mode Trans-only or Refl-only

2
Current TeraScanTR
A number of product and product-like reticles were used to New TeraScanHR 3
Standard T+R
test the large-area false detection performance of the system 4
and to determine the production settings under production Trans-only or Refl-only 5
conditions. Advanced production-critical layer reticles from
the 45nm node were used to test the 72nm pixel, while cur- Fast T+R*
6
rent production reticles from the 65nm node were used to test 7
the 90nm pixel (latter data not shown); comparable memory
Inspection Time (arbitrary units) 8
reticles were also used. Both die-to-die and die-to-database
modes were tested in both transmitted and reflected illumina- 9
tion; the standard HiRes detectors were used, along with the Figure 10: TeraScanHR scan time improvement for T+R: the new 10
optional Litho2 detector for hole layers. The system demon- system allows full speed operation for most T+R modes.
11
strated excellent inspectability performance at all three beta
sites, with low false detections using high detector settings Difference Reflected 12
(most sensitive). 13
14
Transmitted and Reflected Illumination Clear extension defect 15
Modes Highest Quality Inspection (detected in R not T)
16
Testing of the reflected light capability showed that higher 17
sensitivity can typically be achieved versus transmitted light
18
for clear pattern defects (e.g., pinholes, clear extensions, clear
bridges, etc.). Similarly, reflected light typically achieves 19
higher sensitivity versus transmitted light to defects on small 20
Figure 11: 45nm active layer - clear extension defect detected in die-to-
clear lines and clear SRAF. In addition, reflected light can database reflected light mode and not detected in transmitted light mode. 21
typically achieve higher sensitivity to defects on top of opaque
areas such as particles or residual chrome on EPSM material. 22
Therefore, the highest quality inspection can be achieved heavy image processing computation requirements. The new 23
when using both transmitted and reflected light die-to-die or TeraScanHR allows full-speed operation for most T+R modes.
24
in die-to-database modes to detect both pattern defects and These Fast T+R modes include: (1) 72/90/125/150nm pixels
contamination defects. An integrated mode capability allows in die-to-die mode with COG, EPSM, and tri-tone reticle 25
two or more inspection modes to be integrated into one in- types, and (2) 90/125/150nm pixels in die-to-database mode 26
spection with one setup, one scan, one review, and one report. for COG and EPSM reticle types (not tri-tone). Fast T+R is 27
When transmitted and reflected light modes are integrated, not currently available for the 72nm pixel die-to-database
28
it is known as T+R and can be used in both die-to-die and mode. Standard T+R is available for COG, EPSM, tri-tone,
die-to-database modes. and altPSM reticle types. 29
30
The systems new image computer reduces scan time for sev- The previous 45nm active layer (Figure 11) was also inspected
eral inspection modes. Scan times are significantly improved with the 72nm pixel die-to-database mode in reflected light 31
when using transmitted and reflected light inspection modes rather than the previous transmitted light. Figure 11 shows a 32
together in the same inspection (integrated). As shown in clear extension defect that was detected in reflected light that
33
Figure 10, for the previous TeraScanTR platform, a die-to-die was not detected in the transmitted light inspection. This ad-
or die-to-database T+R inspection requires approximately ditional defect would have been detected with integrated T+R 34
twice the scan time as transmitted or reflected alone due to the mode, providing a higher quality result. 35
36
Database Image Difference Image Optical Image Defect Map
37
38
39
40
41
42
43
44
Figure 9: Over-size SRAF in the optical image 72nm pixel die-to-database transmitted mode. Toppans Carbonate test reticle in the 32nm node section
with 150nm primary lines and 50nm SRAF. 45
46
M ask
The previous 7xnm half-pitch DRAM layer (Figure 12) was small linewidths, small defects, and aggressive OPC. A new 1
also inspected with the 72nm pixel die-to-database mode in image computer gives the system productivity improvements 2
reflected light rather than the previous transmitted light. by reducing scan time for some situations and modes. Reflected 3
Figure 12 shows a defect that bridges two holes this defect light inspection is now a more viable inspection mode since it
was detected in reflected light but was not detected in the can be integrated with transmitted light with no additional scan 4
transmitted light inspection. By inspecting with integrated time for some modes. Using integrated transmitted and reflected 5
T+R mode this additional defect would have been detected, light inspection provides the best defect detection capability and 6
thus providing a higher quality result. results in the highest quality reticles for the industry.
7
A 4xnm half-pitch DRAM hole layer was inspected in die- 8
to-die integrated T+R mode using both the HiRes detec- Acknowledgements
9
tor and Litho2 detector (Litho2 in T only). The reticle was The authors thank the many individuals and organizations
manufactured by the AMTC and is standard ArF 6% EPSM 10
that contributed to the development, internal testing, and
material. The inspection used production detector settings most recently, field beta testing of the new TeraScanHR 11
and resulted in low false detections. Figure 13 shows over- platform, including: 12
size clear SRAF defects detected (upper images) and under-
size holes (lower images). -- NIST for technology development funding of the original 13
TeraScan platform 14
Conclusions -- KLA-Tencor RAPID TeraScanHR Development 15

Engineering Team
The TeraScanHR system was tested in die-to-database and 16
die-to-die transmitted and reflected illumination modes using -- Worldwide reticle manufacturers and fabs for providing
17
numerous programmed defect test reticles and product reticles reticles used in development and internal testing
18
representative of the 45nm node (and comparable memory -- Beta sites including Toppan Printing and the Advanced
nodes), as well as early reticles from the 32nm node. Data from Mask Technology Center* 19
testing at Toppan and the AMTC showed that the platform met -- KLA-Tencor RAPID Applications Team for data collection 20
the targets for high sensitivity, low false detections, and scan and analysis 21
speed. Testing of the larger pixels was also performed using cur- *
AMTC is a joint venture of AMD, Qimonda/Infineon and Toppan Photomasks
22
rent generation reticles (65nm and 90nm data not shown).
23
The systems higher NA optics, new autofocus, smaller pixel General References
24
size, and improved rendering and modeling algorithms 1. W. Broadbent, et al, Results from a new reticle defect inspection platform,
showed significant improvements in inspection capability of 23rd Annual BACUS Symposium on Photomask Technology, Kurt R. Kimmel, 25
ed., Proc SPIE Vol 5256, pp. 474488, 2003.
26
2. W. Broadbent, et al, Results from a new die-to-database reticle defect inspec-
Difference Reflected 27
tion platform, Photomask and Next Generation Lithography XI, Hiroyoshi
Tanabe, ed., Proc SPIE Vol 5446, pp. 265278, 2004. 28
3. J. Heumann, et al, Detailed comparison of inspection tools: capabilities and 29
limitations of the KLA 576, 25th Annual BACUS Symposium on Photomask
Bridging holes (in R) 30
Technology, J. Tracy Weed, ed., Proc SPIE Vol 5992, p. 599246, 2005.
(detected in R not T)
4. A. Dayal, et al, Optimized inspection of advanced reticles on the TeraScan 31
reticle inspection tool, 25th Annual BACUS Symposium on Photomask
32
Technology, J. Tracy Weed, ed., Proc SPIE Vol 5992, p. 599245, 2005.
33
5. K. Bhattarcharyya, et al, Process window impact of progressive mask defects,
its inspection and disposition techniques (go/no-go criteria) via a lithographic 34
Figure 12: 7xnm half-pitch DRAM layer - defect bridging two holes
detector, 25th Annual BACUS Symposium on Photomask Technology, J. Tracy
35
detected in die-to-database reflected light mode and not detected in
Weed, ed., Proc SPIE Vol 5992, p. 599206, 2005.
transmitted light mode. 6. S. Maelzer, et al, High-resolution mask inspection in advanced fab, Photo- 36
mask Technology 2006, Patrick M. Martin, Robert J. Naber, ed, Proc SPIE Vol 37
Under-size holes ~ 5% flux error 6349, p. 63490S, 2006.
38
7. S. Teuber, et al, Limitations of optical reticle inspection for 45nm node and
beyond, Photomask Technology 2006, Patrick M. Martin, Robert J. Naber, ed, 39
Proc SPIE Vol 6349, p. 63490T, 2006. 40
8. W. Broadbent, et al., Results from a new die-to-database reticle inspection
41
platform, Metrology, Inspection, and Process Control for Microlithography XXI,
Chas N. Archie, Ed., Proc. of SPIE, Vol. 6518, p. 651821, 2007. 42
43
44
Figure 13: 4xnm DRAM hole layer inspected in die-to-die mode using
integrated T+R with 72nm pixel. 45
46
D ata S torage
1
Applications of a Laser-Assisted 5
Defect Detection System for Chemical 7
Mechanical Planarization (CMP) Slurry

9
10
11
Development in Rigid Disk Polishing 12
13
Toshi Kasai, Charles Dowell Cabot Microelectronics Corp 14

Anoop Somanchi KLA-Tencor Corporation
15
16
17
18
For hard disk manufacturing, characterizing CMP scratches is key to improving the reliability of the device. 19
KLA-Tencors CandelaTM optical surface analyzer (OSA) systems equipped with ellipsometer, reflectometer, 20
21
scatterometer and optical profiler capabilities can be used for defect detection, allowing detection tunability and
22
consistency and eliminating the subjectivity of manual detection. The Candela OSA technology demonstrated significantly
23
lower variability than conventional darkfield microscopes (DFMs); it also more easily identified small scratches (<10m). 24
25
26
Introduction Several detection systems are available for scratch characteriza- 27
In the hard disk drive (HDD) industry, the demand for tion on rigid disk substrates. One example is the dark field
28
increased data capacity in the last decade has necessitated microscope (DFM) based scratch count tool. While the DFM
several technological implementations.1 From the head disk is convenient and easy to use, it has been known that scratch 29
interface (HDI) standpoint, the reduction of the distance counts and analysis using the DFM are very subjective and 30
between a flying read/write head and a disk media has been have a strong operator dependency. Its manual handling opera-
31
a main driver to achieve higher data density on the HDD. In tion imparts relatively poor repeatability and reproducibility
(R&R) and cumbersome defect classification (e.g., by size). It is 32
order to minimize the gap between a head and a disk, the
surface roughness of the disk needs to be low enough, and also hard to acquire total particle counts, due to the relatively 33
more important, the number of surface defects, such as scratch- large number of defects. 34
es and particles, must be small enough to improve mechanical
Recent developments in laser-assisted optical surface analyzer 35
reliability of the HDD operation.
(OSA) systems provide more repeatable and reliable surface 36
The chemical mechanical planarization (CMP) process is a morphology information.4-6 For instance, a series of the
37
key step for smoothing rigid disk surfaces.2 Typically, CMP Candela instrument is equipped with ellipsometer, reflec-
is accomplished through the combination of chemical reac- tometer, scatterometer and optical profiler capabilities.6-8 38
tion and mechanical abrasion of the disk surface in contact Each operational mode and combination of modes can be used 39
with a polymeric pad and a slurry containing sophisticated for defect detection with the availability of specific defect data
40
chemistries and abrasives under an applied load.3 It has been such as the types, numbers and locations. Moreover, versatile
defect scan and analysis recipes allow constructive detection 41
recognized that the slurry has a significant impact on rigid
disk scratch defect performance. Scratches can be created tunability and consistency. This helps eliminate the subjectiv- 42
from handling, chemistry unbalance, or the presence of large ity of manual detection. The Candela tools are widely used in
43
abrasive particles in the CMP slurry. It is therefore essential to the hard disk drive industry for defect identification.
44
utilize a consistent scratch characterization technique for
This report presents the recent development of a defect detec- 45
slurry development.
tion recipe and scratch count results for rigid disks measured
46
D ata S torage
with a Candela instrument. The scratch data compiled with directly collected by the CCD. If defects are present on a disk, 1
the Candela are compared to those acquired with a conven- the incident light is scattered and scattering signals are detect- 2
tional DFM and another type of OSA tool. It is shown that ed by the CCD camera. The defects appear as bright images 3
tuning of the recipe parameters is a key to obtaining consistent on a dark background in the monitor. The operator rotates the
scratch counts. This option is not available with the DFM disk to inspect the surface and manually counts the number 4
technique. Additional advantages of using the Candela tool for of defects. An advantage of using the DFM technique is its 5
scratch defect analysis are also discussed. relatively short processing time and easy setup as compared to 6
the Candela tool.
7
Experimental
8
Sample preparation and experimental setup for
Candela and DFM 9
Candela defect detection system
10
The Candela CS10 is a 405nm laser assisted multi functional Disk samples were ground and nickel-phosphorous coated9
tool. It is equipped with two lasers, called the circumferential prior to the CMP process. The inner and outer diameters 11
and radial lasers, as shown in Figure 1. The two laser beams and thickness of the disks were 25mm, 95mm and 1.27mm, 12
form a 90 degree angle and converge at the analysis point of respectively. The disks were polished with several kinds of
13
the sample. The instrument offers the ability to scan the disk CMP slurries, cleaned, and then forwarded to defect inspec-
with either beam or both lasers simultaneously. Signal detection. Cleanliness of disks is critical for scratch inspection, since 14
tion is performed with two detection channels for reflected residual chemicals and stains possibly caused by handling can 15
and scattering beams. For scratch and particle defect identi- lead to miscounting.
16
fication, the scatter channel, consisting of a photo multiplier
The Candela measurement procedure was performed automati- 17
tube (PMT) detector, is used. In this mode, the laser, interact-
cally by placing the disk on the platen of the instrument. The
ing with the sample surface, produces scattering signals that 18
data outputs included the scratch and particle distributions
appear as bright areas on the scattering signal images. Three 19
for each bin, together with a map showing the defect location
modes of polarization for the incident lasers are available: P, S
on the disk. The defect data collected can be classified by size 20
and Q (combination of P and S). During the measurement, the
into five bins. Nominal settings for the scratch defect bins were 21
disk rotates and the laser source and detection system move in
as follows: bin 1: 20-100m; bin 2: 100-500m; bin 3: 500-
a transverse direction, so that the entire area of the disk sample 22
1000m; bin 4: 1000-5000m and bin 5: >5000m.
can be scanned.
23
In the DFM technique, the number of scratches was counted
24
Candela CS10 system apparatus with a manual counter. The scratch length analysis was
performed by measuring the length of each scratch on the 25
monitor using a scale for classification. For the specific inspec- 26
tion work, scratches were categorized in four groups: short 27
Scatter channel Circumferential (< 2mm) and shallow, short and deep, long (> 2mm) and
laser 28
shallow, and long and deep. The depth of the scratches was
estimated by visual inspection depending on the brightness 29
of the defect on the monitor. 30
Reflection
The area analyzed on the disk using the DFM ranged from 31
channel middle diameter (MD) to outer diameter (OD), whereas it 32
ranged from inner diameter (ID) to outer diameter (OD) for
33
Disk sample the Candela. Therefore, the scan area was about 1.5 times
larger for the Candela than for the DFM. 34
35
OSA-2 scratch detection system 36

Figure 1: X beam technology used for Candela C10. The radial and cir-
cumferential laser beams, orthogonally situated, probe the disk surface, Another OSA tool used at a customers site will be later intro- 37
which generates scattering signal collected by the scatter channel. duced and compared with the Candela tool. This tool also 38
uses a laser as a probe and employs scattering signals for the
39
scratch detection but does not use the Candela technology.
Dark field microscope (DFM) scratch detection system 40
Since the tool was originally developed by the customer and
The DFM technique uses several light sources to illuminate is not commercially available, it is conveniently called OSA-2 41
the disk surface from different angles. A charge-coupled device in this paper. Very limited information was available due to
42
(CCD) camera is situated above the disk and dark field images confidentiality; therefore, establishing the correlation was
of the disk surface are displayed on a monitor. The magnifica- more challenging. As seen in the following section, the tuning 43
tion of the CCD camera system was 10X for this study. The capability of the Candela tool plays an important role in order 44
incoming direction of the light makes a shallow angle with to acquire better correlation with this tool. 45
respect to the disk surface so that the reflected light is not
46
D ata S torage
In the case that the texturing is made along the circumferen- 1
tial direction, radial scratches remaining are unfavorable. In 2

Beam
direction this study, both lasers were enabled for comprehensive analysis. 3
Figure 3 shows an atomic force microscopy (AFM) height
4
image of a scratch defect found on a rigid disk surface; (a) and
its cross sectional view; (b). The width and depth of scratches 5
are typically ~1m and several nanometers, respectively. It has 6
been demonstrated that a 0.1m wide and 1nm deep scratch
Scratch 7
visible can be clearly observed by the Candela system.
8
As also shown in Figure 2, particle defects can be recognized 9
Particle
in both images. The scattering signals were relatively inde-
10
(a) 200m pendent of the beam direction, though images of the particles
become elongated in the laser direction. This occurs because 11
Beam the laser beam has an incident angle, approximately 60 degrees 12

direction from normal on the plane of incidence. The elongated features 13
resemble scratches, which makes the distinction between
14
scratches and particles difficult in some cases. One can over-
Scratch come this difficulty by optimizing the scratch classification 15
visible
parameters, such as the aspect ratio, in the analysis recipe. 16
The encoder multiplier settings and photo multiplier tube (PMT) 17
voltages were found to significantly affect signal-to-noise (S/N) 18

Particle ratio. The encoder multiplier setting defines the number of 19
circumferential data points at each radial location. For example,
(b) 200m
an encoder multiplier setting of 64x allows one to take 64 x 1,024 20
(=65,536) data points at one radial location.7 Figure 4 presents 21

Figure 2: Candela scattering signal images of a polished rigid disk Candela scattering signal image of one scratch and its cross-sec- 22
surface using (a) radial and (b) circumferential laser. The incoming beam tional view at a fixed radius near the center of the image under
directions are indicated by thick arrows. 23
three different settings of the encoder multiplier and PMT voltage:
24
(a) 16X and 475V, (b) 16x and 525V and (c) 64x and 475V.
Results and Discussion 25
The peak intensities of the scratch and S/N ratio are summarized
26
Candela recipe creation issues in Table 1. The peak intensity, obtained from the cross-sectional
analysis, is the amplitude (%) of the peak measured from the 27
The scan and analysis recipes need to be optimized prior to
average background noise level. Note that the unit is repre- 28
measurements. In this section, the effects of some key parame-
sented as a percentage of PMT output voltage given by the 29
ters of the Candela recipes for scratch detection are scrutinized.
tool. The S/N ratio is defined as the ratio of the peak intensity
30
Figure 2 shows Candela scattering images for the use of (a) the to the maximum amplitude in the background noise. Case (a)
radial and (b) the circumferential laser. The horizontal direc- exhibited an S/N ratio of 1.2, indicating that the signal was 31
tion in the figure is parallel to the circumferential direction not well distinguished from the background noise. An increase 32
of the disk sample. As shown, the direction of the incoming in the PMT voltage from 475 V to 525 V (Case (b)) signifi-
33
laser highly affects the appearance of defects. Circumferential cantly enhanced the S/N ratio from 1.2 to 2.1 (1.8 times).
Also, an increase in the encoder multiplier showed a 2.4 times 34
scratches, the angular orientation of which are more aligned
with the circumferential direction of a disk, are visible using better S/N ratio (Case (c)). Increases in both parameters led to 35
the radial laser (Figure 2(a)), but become invisible with the cir- saturation of the scattering signal; therefore, the encoder mul- 36
cumferential laser (Figure 2(b)). This anisotropy occurs because tiplier settings and PMT voltages were taken as 64x and 475V,
37
more scattering signals are generated when the angle between respectively, in this study.
38
the direction of the laser beam and the longitudinal direction
After the scan, the scattering signal images obtained were pro-
of the scratch becomes closer to 90 degrees. The advantage of 39
cessed through the analysis recipe in order to identify defect
using two lasers is that it minimizes the effect of scratch ori- 40
sites. Optimization of the analysis recipe parameters is also
entation. If radial scratches are the main concern, it is possible
highly critical. A key parameter here is the threshold parameters 41
to intentionally use the circumferential laser only so that the
that define the minimum scattering signal intensity to be 42
system becomes more sensitive to radial scratches. This is the
recognized as a defect site. To best set the recipe parameters,
case for disks that are forwarded to the texturing process after 43
the following operation was performed. First, scattering signal
CMP. The texturing process allows the formation of uniform, 44
images were processed with the analysis recipe and the number
controlled scratch marks along which magnetic crystal growth
of scratch counts was recorded. Second, the same scattering 45
can be performed in the magnetic layer deposition process.9
46
D ata S torage
signal images were checked by 1

5.0
5.0 an operators visual inspection 2
A B and recognized scratches were 3

manually counted. Finally,
4
the two scratch counts were
(nm)
compared. We assumed that 5
the scratch counts made by the 6
operator were accurate and pre-
7
-5.0 cise so that those could be used
0 (m) 5.0 0 5.0 8
(m) as a standard to evaluate the
(a) (b)
Candela scratch counts. Two 9
Figure 3: (a) AFM image of a scratch on a rigid disk after CMP and (b) section analysis along the line AB of the types of potential errors exist: 10
scratch indicated by arrows. Type I error occurs when the
11
Candela does not recognize a
scratch even though the scratch 12
33610m
187.90 191.75 deg
defect is present; Type II 13
error occurs when the Candela 14
33235
categorizes a scratch that is
15
not a real scratch defect. These
Units
32860 16
categorizations are illustrated
in Table 2. The probability of 17
32485
error is dependent upon the 18
(a) Angle (), Radius ()
threshold parameters set in the
19
33610m
analysis recipe. Higher thresh-
187.90 191.75 deg
olds lead to reduced type II 20
33235 error but an increase in type I 21
error, and vice versa. The value
22
Units
32860 of optimized threshold param-

eters for both circumferential 23
32485 and radial laser scattering 24
(b) Angle (), Radius () signals was found to be 0.12%. 25
The associated scratch counts
34250m 26
189.39 190.35 deg
for four disk samples are shown
33875 in Table 3. The type I and II 27
errors occurred at 30% and 28
Units
33500 2% on average, respectively. 29

A rate of 0% is ideal for both
30
33125 errors; however, it is challeng-
(c) Angle (), Radius () ing since the two errors are in 31
the correlation of a trade-off. 32
We selected the condition that
Figure 4: Comparison between measured CD and average image gray level for the different etch test conditions. 33
produced type II error close
to zero and minimized type 34
Case (a) Case (b) Case (c) I error. As found later, the 35
Encoder multiplier 16X 16X 64X threshold setting is a key in 36

the study of tuning capability.
PMT voltage (V) 475 575 475 37
Peak intensity (%) 0.04 0.16 0.12 The scratch identification sys- 38
S/N ratio 1.2 2.1 2.9 tem developed and described
39
above can be also applied to
Table 1: Peak intensity and S/N ratio of a scratch under various encoder multiplier and PMT voltage setting for Candela. other types of samples such 40
State of Nature
as integrated circuit (IC) 41
silicon wafers, though some 42
Scratch Not scratch
adjustments in parameters
Decision by Candela Scratch Good Type II error 43
are required.
Not scratch Type I error Good 44
45
Table 2: Definition of Type I and II errors for Candela recipe confirmation test.
46
D ata S torage
Disk Number of scratch count Type I Type II Correlation between Candela and DFM 1
sample error error Figure 5 shows disk surface images at the same location viewed 2
Correct False Missed Total
number (%) (%)
using (a) the Candela and (b) the DFM. The Candela image 3
1 39 0 17 56 30 0 was obtained using the P-polarized radial laser, directed from 4
2 11 2 1 12 8 15 the top in the figure. The differences found in the two images
can be explained as discussed in the previous section consid- 5
3 7 0 8 15 53 0
4 30 0 12 42 29 0 ering the experimental setup of the Candela tool. A radial 6
scratch slightly seen at the center bottom of the DFM image 7
Overall 87 2 38 125 30 2
is not recognized in the Candela image. On the other hand,
several circumferential scratches, which have a horizontally 8
Table 3: Candela scratch count data used for Type I and II error evaluation.
transverse direction, are more visible in the Candela image. 9
Candela C10 DFM Particles are elongated parallel to the beam direction in the 10
Light source Violet laser (405 nm) White light Candela image. Stains at the left bottom corner are highlight-
11
ed in both images.
Number of light sources 2 Multiple
12
Detector Photo multiplier tube CCD Representative differences between the tools are summarized
(PMT) 13
in Table 4. The spatial detection limit is much smaller for
Spatial resolution limit >4 m ~100 m the Candela than for the DFM. In the case of the Candela, the 14
% Study variation of Gauge 7% 25% detection limit is regulated by the laser spot size (4m), while 15
R&R for scratch counts for DFM, the limit is dependent on the resolution of the CCD
16
camera and the ability of the operators eye. The study varia-
Table 4: Comparison of characteristics between Candela C10 and dark field 17
microscope (DFM) techniques.
tion of the Gauge R&R is defined as the contribution of R&R
to the total variation including repeatability, reproducibility 18
and part-to-part variations. In general, a value larger than 9%
19
indicates that the system needs improvement. The Candela
performed at a 7% study variation for ten samples. This leads 20
to acceptable R&R performance. On the other hand, the DFM 21
showed a 25% study variation, which was less satisfactory 22
since the DFM required more manual operation.
23
A comparative study on scratch counts between the DFM and 24
Candela was conducted. Figure 6 shows the correlation be-
25
(a) 1 mm (b) 1 mm
tween the DFM long scratch count (> 2mm) and the Candela
long scratch count (> 1mm). The variations in scratch count 26
originated from the use of different kinds of slurries with 27
Figure 5: Rigid disk surface images using (a) Candela and (b) dark
various scratch performance. The value of the linear regres-
field microscope (DFM) techniques. 28
sion correlation coefficient, R2, was 71%. This indicates that
the correlation between the DFM and Candela scratch counts 29
Candela vs DFM (long scratches) was marginal. Generally, an R2 of at least 75% is required 30
40 for satisfactory correlation.10 In addition, the correlation was
31
Regression not matched since the regression line was not identical with
95% Confidence Interval the line y = x at a 95% confidence level. This is probably due 32
to the differences in the detection systems of the two instru- 33
30
ments, including the poor Gauge R&R of the DFM system.
Y = 0.56 X + 3.4 34
Candela counts (>1mm)
The correlation was examined for scratch counts under various

R 70.7% size categories, as summarized in Table 5. The largest R2 was 35
20 71%, found in the case described above. 36
The slope of the regression line in Figure 6 is 0.56, which is 37
less than unity. This suggests that, under the analysis criteria, 38
10 the Candela failed to spot scratches that the DFM could detect. 39
Considering the difference in the scan area (the scan area of the
Candela was about 1.5 times larger than that of the DFM) and 40
the size of scratches categorized (> 1mm for the Candela and 41
0 10 20 30 40 > 2mm for the DFM), the overall number of scratches the 42
DFM counts (>2mm) Candela failed to spot may have been even larger. The most
43
likely reason for this discrepancy is that the Candela instru-
ment is not sensitive to shallow scratches due to the relatively 44
Figure 6: Correlation between Candela long scratch count (> 1 mm)
and DFM long scratch count (> 2 mm).
low scattering signal from these defects and the threshold set- 45
ting issue of the tool as discussed previously. The data shown
46
D ata S torage
Candela scratch DFM scratch size a b R square Candela tuning capability and 1
size category category (slope) (y intercept) (%) its use in CMP slurry screening 2
1 1 mm> 2 mm> 0.56 3.4 71 A set of disk samples was 3
2 1 mm> 2 mm> and deep 1.5 3.9 70 polished using a series of 4
3 Total Total 2.8 84 56 slurries expected to exhibit
5
4 0.1 mm> Total 0.99 35 57
different scratch performance.
These disks were inspected 6
5 0.2 mm> Total 0.53 18 64
with the OSA-2 laser-assisted 7
Table 5: Regression analysis of Candela and DFM scratch counts for various size categories. optical surface analyzer and
8
classified into two groups:
Sample: G1 Scattering intensity range (%) Scratch passed (Good) or 9
Scratch bin Lower limit (m) Upper limit (m) 0.12 0.2 0.2 0.3 0.3 0.4 >0.4 Scratch rejected. The same 10
1 20 100 179 31 23 15 disks were then analyzed by 11

the Candela and the DFM.
2 100 500 76 8 9 12 12
The data shown in Figure 7(a)
3 500 1000 7 4 0 2 and (b) are the total scratch 13
4 1000 5000 0 9 3 1 counts for the Candela and 14
5 5000 N/A 6 0 0 1 the DFM, respectively. In each
15
Total 268 52 35 31 graph, the classification by the
OSA-2 tool is incorporated. A 16
Table 6: An example of categorization for Candela scratch counts using scattering intensity ranges and length bins, used threshold setting for the 17
for the data plot in Fig. 8(a).
Candela is a key in this section 18
and the value of 0.12% was
19
taken for the measurement in
(a) Candela: Total scratches (b) DFM: Total scratches 20
500 500
Figure 7(a). In the slurry iden-
Good Good tification, the combination of 21
400
Scratch rejected
400
Scratch rejected a letter and a number is used, 22
where the letter refers to a
Scratch count
Scratch count
category given by the OSA-2 23

300 300
with either G as Good 24

200 200 or R as Rejected and the 25
number refers to the slurry
100 100 26
used. Slurry 1 was a standard
rigid disk slurry. Slurries 2, 27
0 0
G1 G2 G3 G4 R1 R2 R3 R4 G1 G2 G3 G4 R1 R2 R3 R4 3 and 4 contained a scratch- 28
Disk sample number Disk sample number reduction additive with the 29
concentration of 100, 1,000
30
and 4,000 (unit: relative con-
Figure 7: Total scratch counts measured using (a) Candela and (b) DFM for Good and Scratch rejected disks
centration), respectively. The 31
categorized by another laser assisted defect detection system (OSA-2). Disk sample number specifies the OSA-2
category and slurry used. Slurry 1 is a standard CMP slurry for rigid disks and slurry 2 to 4 contain scratch
Candela total scratch count 32
reduction additive with different concentrations. clearly exhibits the effect of
33
the scratch-control additive.
This trend is less pronounced 34
with the DFM technique. The 35
in Table 5 support this hypothesis. The slope of the regres- OSA-2 tool, however, failed to observe the effect of the addi- 36
sion line was 1.5, up from 0.56, when deep scratches are only tive. This occurred possibly due to the different classification
37
counted for the DFM detection from the previous comparison. methods taken by the OSA-2. Our next task was to find how
to obtain consistent results with the OSA-2 using the Candela. 38
As discussed above, the experimental evidence showed that the
39
Candela scattering signal under the current parameter setting An attempt was made to have a better correlation by com-
might be insensitive to shallow scratches. This is not necessar- paring scratch counts with selected scratch length, as was 40
ily a drawback for the tool. Its ability to provide meaningful performed to obtain a correlation between the Candela and 41
information in terms of scratch geometries such as length, DFM (see Table 5); however, the result was not satisfactory. It 42
depth and width is more important than a simple count of was later suggested that the OSA-2 classified the defects with
43
defects. An advantage of the Candela is its flexible tuning scratch width and depth together with scratch length. From
capability for defect recognition as a function of the targeted this information, we came to the conclusion that the scattering 44
scratch geometry, as illustrated in the following section. intensity should have been additionally focused on. The scat- 45
tering signal originating from the interaction between scratch
46
D ata S torage
defects and a laser beam possibly contains the information of correlation. For the DFM data, an attempt was made to obtain 1
width and depth of scratches in its intensity. The standard a better correlation with the OSA-2 by selecting deep and long 2
Candela classification technique does not allow this capability. scratches, since the result suggested that scratches with larger 3
Possible scratch defect sites that show higher scattering signal scattering intensities could be better highlighted in the OSA-2
than a threshold value are all considered to be defects. In order detection. As shown in Figure 8(b), such a correlation as found 4
to classify the scratch defects with scattering intensity, scatter- for the Candela was not obvious for the DFM scratch counts. 5
ing signal data were re-analyzed with different threshold val- 6
ues, and then scratch counts obtained were manually classified
7
depending on the scattering intensity ranges. The Candela system provided 8
An example of such a categorization for the G1 sample in
Figure 7(a) is shown in Table 6. The scratches are classified
meaningful information 9
depending on their length and scattering intensity. The for scratch geometries such as 10
number of significant scratches was identified from this table.
Scratch defects that showed higher intensity than 0.4% were length, depth and width, as well as 11
12
categorized as the most significant defect, no matter how
long they were and then would be all counted as scratches.
a flexible tuning capability 13
Those that showed 0.3 to 0.4% in intensity range were the for defect recognition 14
second most significant and classified as scratches if they were
longer than 500m in length. Likewise, scratches with 0.2 as a function of the targeted 15
to 0.3% intensity range were recognized to be the third most scratch geometry. 16
significant and classified as scratches if they were longer than 17

5000m in length. The sum of the scratch count mentioned 18
above was obtained to be a newly categorized scratch count. The data analysis showed that a better correlation was obtained
19
between the Candela and the OSA-2 with a relatively higher
Figure 8(a) exhibits the scratch counts under the new defini- Candela threshold setting. As shown in Table 6, the majority 20
tion for the same disk samples in Figure 7(a). It becomes of scratches exhibited the scattering intensity below 0.2% for 21
clearer to discern the two categories given by the OSA-2, the G1 sample. The use of the scratch-control additive was
named Good and Rejected. When the number of scratches 22
effective in reducing the number of scratches in this category,
is below approximately 40 on the Candela measurement, the but less significant in eliminating those with a larger scatter- 23
OSA-2 rates the disks as Good while above this value, the ing intensity that could be primarily focused on in the OSA-2 24
disks are evaluated as Scratch rejected. This result suggests detection. This recognition is critical for development of a
that scattering intensity can be another key parameter to be 25
new CMP slurry product. To satisfactorily meet the require-
considered for obtaining better correlation with other defect ment from customers in terms of scratch reduction, the scratch 26
metrology tools. Though the correlation may not be satisfac- definition criteria are very important, i.e., to know which 27
tory enough for some data (e.g., scratch counts of G1 and R3 scratch geometries (depth, length, width and direction) should 28
are close in Figure 8(a)), the difference of scratch count profiles be focused on. The root cause of the various types of scratches
found between Figures 7(a) and 8(a) is significant. Probably, may be different. The short/shallow scratches may be due to 29
optimization of the analysis parameters will help improve the agglomeration of abrasive particles or by-product contamination 30
31
(a) Candela: Intensity & length categorization (b) DFM: Intensity & length categorization 32
33
150 20
Good Good 34
Scratch rejected Scratch rejected 35
15
36
100
Scratch count
Scratch count
37
10
38
50 39
5 40
41
0 0 42
G1 G2 G3 G4 R1 R2 R3 R4 G1 G2 G3 G4 R1 R2 R3 R4
43
Disk sample number Disk sample number
44
Figure 8: (a) Candela scratch count categorized with scattering intensity and length and (b) DFM scratch counts (deep and long), for the same disk samples in Fig. 7. 45
46
D ata S torage
generated from disk materials. The long/deep scratches may be scratch reduction. This effect was not apparent with the DFM 1
caused by large particles that were not filtered out and entered technique, due to the limitation of resolution stated above. 2
the slurry as a contaminant. Depending on the mechanistic 3
reasons, our approach for CMP slurry development should be 5. The sensitivity adjustment (tuning) capability of the
different. With the use of the recipe-oriented Candela tool that Candela gave the possibility of correlating scratch counts to 4
can flexibly and efficiently provide necessary scratch informa- those obtained with another laser-assisted scratch detection 5
tion, slurry development work will be significantly enhanced. tool. This was not achieved with the use of the DFM tech-
6
Throughout this study, we have learned that extracting and nique. Depending on the criteria of the scratch defects, the
selecting required information from metrology tools is a key Candela is tunable with modification of the recipes to extract 7
step in slurry product development. necessary scratch information. 8
9
This tuning capability is not currently available for the
Acknowledgments
Candela system as a standard procedure. The addition of this 10
capability to the system may require complicated design The authors would like to thank Li Wang for the data collec- 11
changes for the Candela scratch analysis process, but will tion and Francois Batllo, Haresh Siriwardane, Edward Remsen,
12
provide more flexibility for the tool. Vamsi Velidandla and Laurie Bechtler for the fruitful discus-
sions and suggestions in completing this project. 13
14
Conclusions
References 15
Evaluations of scratch counts using a laser-assisted optical sur-
1. Sarid D, McCarthy B and Jabbour G E, 2004 Nanotechnology for data 16
face analyzer (Candela CS10: KLA-Tencor Corp.) and dark field
storage applications, in bhushan B (ed.), Springer Handbook of Nanotech-
microscope (DFM) techniques led to the following conclusions. nology Springer-Verlag, Heidelberg, Germany. 17
1. A gauge repeatability and reproducibility (R&R) study 2. Lei H and Luo J 2004, CMP of hard disk substrate using a colloidal SiO2 18
slurry: preliminary experimental investigation, Wear 257 pp. 46170.
showed the Candela tool had 7% study variation. This leads 19
to acceptable R&R performance (less than 9%) . On the other 3. Michael R. Oliver (ed.) 2004, Chemical mechanical planarization of
semiconductor materials, Springer-Verlag, Heidelberg, Germany. 20
hand, the DFM showed 25% variation and this discrepancy is
4. Knollenberg R G, A polarization diversity two-color surface analysis system, 21
most likely due to the manual operation of the DFM.
1987 Journal of Environmental Sciences 30, pp. 358.
22
2. The correlation between the Candela and DFM scratch 5. Takami K, 1997, Defect inspection of wafers by laser scattering, Mat. Sci.
23
counts was given an R2 of 71% for specific scratch size Eng. B 44 pp. 1817.
categorization. This marginal correlation occurred due to the 6. Meeks S W 2003, Optical surface analyzer inspects transparent wafers, Laser 24
relatively poor R&R of the DFM measurement capability and Focus World 39 pp. 1056, 8.
25
differences in detection system between the tools. 7. Bechtler L, Velidandla V and Lane G, 2003, Optical surface analysis of
26
transparent substrates for manufacturing applications, Proceedings of
3. It was demonstrated that the Candela can more easily Electrochemical Society 2003-3, pp. 5407. 27
identify small scratches (less than 10m) and be less sensitive 8. Candela Instruments, 2003, Optical Surface Analyzer C10 Users Manual, 28
to faint scratches than the DFM under the parameter setting Software version 1.0, Rev 1.0.
used, due to differences in detection, analysis, and 29
9. Johnson K E, Mate C M, Merz J A, White R L and Wu A W, 1996 Thin
data processing systems. film media - current and future technology, IBM J. Res. Develop. 40 (Sept). 30
10. Miller J N and Miller J C, 2000, Statistics and chemometrics for analytical 31
4. The Candela scratch counts with a standard threshold chemistry, 4th ed. Pearson Education Limited, Edinburgh Gate.
clearly demonstrated the effect of a CMP slurry additive on 32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Product News
1
2810 and 2815 10
11
12
Brightfield Patterned Wafer Inspection Systems
13
14
Memory manufacturers require high throughput detection of small defects on dense, repetitive 281x Benefits 15
patterns and in high vertical structures. Logic manufacturers must find and isolate all critical
16
defects on complex geometries and in dense repetitive patterns which employ new materials and Customized optical modes
rapidly changing processes. In addition to these distinct inspection requirements, both memory and selectable full-spectrum
17
and logic chipmakers need improved sensitivity and speed in order to quickly ramp new processes 18
DUV/UV/visible illumination
to high yield. The 2810 and 2815 are the industrys first memory- and logic-specific full-spectrum
produce the highest sensitivity 19
brightfield inspectors, helping solve yield issues with features specialized by device type. Part of
to defects of interest on all
KLA-Tencors comprehensive wafer inspection portfolio, the 281x inspectors provide effective 20
line monitoring and engineering analysis capabilities for < 55nm memory and < 45nm process layers
21
logic manufacturing.
Highest weighted average 22
The 281x tools are based on the widely adopted 2800 Series full-spectrum DUV/UV/visible throughput in production (WATIP) 23
brightfield inspectors, utilizing memory- and logic-customized optics modes and algorithms to allows increased sampling, lower 24
capture a broad range of yield-critical defects on all process layers. The 281x inspectors include cost-of-ownership or higher
a selectable spectrum illumination source and a pixel-independent high numerical aperture (NA) 25
sensitivity inspections
which maximize material contrast, suppress nuisance and work with advancements in automatic 26
defect binning to produce a meaningful defect Pareto. With nearly double the 2800s throughput,
Commonality and connectivity 27
the 281x inspectors enable engineers to quickly achieve systematic yield improvements and
reduced baseline defectivity, for critical etch, CMP and photo line monitoring. The 281x tools with other KLA-Tencor inspec- 28
offer flexibility for process development, reliability for production, and extendibility for future tors and review tools optimize
29
nodes and emerging device technologies. inspector capacity and reduce
30
production integration time
Questions about how the 2810 or 2815 can address a specific use case or yield challenge? 31
Please contact Mark Shirey at mark.shirey@kla-tencor.com. Established, production-proven, 32
highly extendible tool architecture 33
provides reliable line monitoring
34
capability for multiple technology
nodes 35
100
Normalized Defect Count
2800 36
90nm Pixel (BBDUV BF) 2810
75 Process Window Qualification
Defect Count
50nm Pixel (BBDUV BF) 37

(PWQ) application enables
50 38
lithographers to assess designs
prior to production 39
25
Pattern Line Bridge Particle SEM Non- 40

Thinning Visual/Bump 0
Layer 1 Layer 2 Layer 3
41
Defects of Interest Equivalent 2810: 75 80% throughput
Throughput improvement over 2800 42
2815 defect Pareto demonstrating a 2x increase With increased throughput and new pattern suppres- 43
in critical bridge defect capture provided by the new sion modes customized for memory devices, the 2810
50nm pixel. The industrys smallest pixel enables demonstrates improved sensitivity at throughput over 44
improved capture of defects of interest for earlier the 2800 for three front end memory layers.
detection of process excursions. 45
46
Product News
1
Puma 9150 10
11
12
Darkfield Patterned Wafer Inspection System
13
14
Puma 9150 Benefits Semiconductor device manufacturers must address the yield issues related to shrinking dimen- 15
sions, new materials and innovative device structures in order to ramp to high yields quickly
16
New optical modes and Streak and profitably. Patterned wafer inspectors help improve yield by enabling engineers to solve
defect problems at all stages of the product lifecycle from process development to production. 17
darkfield imaging technology
provide improved capture of
Part of KLA-Tencors comprehensive wafer inspection portfolio, the Puma 9150 darkfield 18
inspector provides effective excursion monitoring capability for 45nm and beyond.
defect types across an extended 19
applications space The latest in the Puma family of laser imaging, darkfield inspectors, the Puma 9150 utilizes 20
the revolutionary Streak technology and introduces extended capability to capture the broadest 21
Highest production throughputs range of defect types at high throughputs. New optical modes allow for increased sensitivity to
at required sensitivity enable bridging and other pattern defects for non-critical etch applications, deliver improved capture 22
increased yield sampling or of residue and other defects for CMP, and detect photo defects at high throughputs. In addition 23
lower cost-of-ownership to providing benchmark films performance, the Puma 9150 complements higher sensitivity 24
broadband brightfield inspections by offering an improved sampling option for photo-cell
25
Commonality and connectivity monitoring, after-develop inspection, and other tool monitoring applications.
26
with other KLA -Tencor inspec-
Questions about how the Puma 9150 can address a specific use case or yield challenge?
tors and review tools optimize 27
Please contact Amir Azordegan at amir.azordegan@kla-tencor.com.
inspector capacity and reduce 28
production integration time
29
30
Ease-of-use improvements and
innovative algorithms result in 31
quick and easy recipe setup 32
33
Established tool architecture
34
and production-proven matching
produce consistent and reliable 35
inspection results Traditional Optical Modes

36
Signal-to-Noise Ratio
New Optical Modes

37
38
39
40
41
Bridge Cu Residue Missing Contact
42
Signal-to-noise ratios of three defects demonstrating the The new optical modes of the Puma 9150 43
complementary detection capabilities of the traditional and provide increased capture of low profile defect
new optical modes of the Puma 9150. The multiple optical types, such as incomplete copper polish (shown), 44
modes enable the broadest darkfield defect type capture deformed contacts, bridging and residues.
across an extended applications space. 45
46
Product News
1
eDR-5200 10
11
12
Electron Beam Review and Classification System
13
14
As design rules shrink below 45nm, defect and yield engineers are increasingly concerned about eDR-5200 Benefits 15
smaller defects and the quality of the defect Pareto coming from their review tools. The eDR-5200
16
wafer defect review and classification system successfully addresses these concerns by imaging Higher stage accuracy and
sub-50nm defects and producing a more accurate defect Pareto with dramatically fewer SEM 17
image resolution allow detection
Non-Visual (SNV) defects. A critical piece of KLA-Tencors comprehensive defect solutions and imaging of <50nm defects 18
portfolio, the eDR-5200 leverages advances in resolution and defect re-detection sensitivity, along
19
with unique connectivity with KLA-Tencor inspectors, to enable better review performance, faster
Production-worthy manual, 20
yield learning and higher tool productivity for the 45nm node and beyond.
power-assisted, and fully
21
The eDR-5200 introduces an electromagnetic immersion column design, delivering the resolu- automated defect classification
tion required to image <50nm defects. In addition, a high precision stage, innovative defect achieve the fastest time to the 22
deskewing algorithms, and advanced re-detection methods provide the capabilities necessary best defect Pareto 23
to find low contrast or tiny defects, effectively reducing the number of reported SNVs. Further 24
improvements in the defect Pareto are obtained with novel approaches to defect classification, Proprietary connectivity to
25
including power assisted classification (ePAC) and fully automated defect classification (eADC). KLA-Tencor inspectors produces
In order to address the inspection-review cycle as a single use case, the eDR-5200 offers seamless faster, more accurate recipe 26
connectivity to KLA-Tencor optical inspectors. This produces a greater number of higher quality setup on the SEM, plus a lower 27
defect Paretos per hour, allowing engineers to rapidly resolve yield issues for even the smallest percentage of SEM non-visuals 28
critical defects on 45nm node devices. and other nuisance defects
29
Questions about how the eDR-5200 can address a specific use case or yield challenge?
30
Please contact Christophe Fouquet at christophe.fouquet@kla-tencor.com. Innovative EDX design enables
analysis and classification of 31
defects <100nm, based on 32
their composition
33
34
Connectivity between KLA-Tencor
inspection and review tools 35
0.5m FOV 100 offers a significant reduction in 36

POR Method 85
eDR Method 73
78 Process Window Qualification 37
75 71
(PWQ) time
SNV Rate %
38
50
40
36 39
27
25 22 22
11 12 13 13 40
2
0
1- 2- 3- 4- 5- 6- 7- 41
FEOL FEOL BEOL FEOL BEOL BEOL BEOL
50nm Defect Layer 42
43
With an immersion column design and higher The eDR-5200 includes improved coordinate accuracy and
stage accuracy, the eDR-5200 detects and connectivity with KLA-Tencor inspectors, resulting in a dra- 44
images <50nm defects. matic reduction in the number of reported SEM non-visuals.
45
46
Product News
1
SURFmonitor 10
11
12
Process Signature and Metrology Module
13
14
SURFmonitor Benefits The SURFmonitor system extends the industry-leading Surfscan SP2 unpatterned surface inspection 15
system beyond traditional defect inspection into the realm of metrology. SURFmonitor can
16
Defect and film morphology measure variations in surface morphology on bare wafers or blanket films, which correlate to a
broad array of process parameters such as surface roughness, grain size, and process temperature. 17
information in the same
inspection, with no additional
With sub-ngstrom repeatability, the SURFmonitor system creates detailed parametric maps 18
while defect information is being collected, enabling fabs to monitor both process drift and
throughput impact 19
defectivity simultaneously with no impact on inspection throughput. SURFmonitor also extends
the defect detection capability of the SP2 into the sub-threshold region, identifying process 20
Powerful algorithms for extract-
anomalies and defect signatures that are not typically captured in the defect channels. 21
ing defect signatures and trans-
lating surface scattering results The SURFmonitor module uses the low spatial-frequency, low amplitude scattering signals from 22
into usable metrology data the defect scan to generate high resolution, full wafer maps with sub-ngstrom height resolution. 23
SURFmonitor then analyzes these maps for within-wafer or wafer-to-wafer parametric spatial 24
Sub-ngstrom vertical (feature variations, and can apply the results for statistical process control. SURFmonitor data have shown
25
height) resolution and industry- excellent correlation to several parameters such as surface roughness for copper, tungsten and
leading lateral resolution poly-silicon films, transparent film thickness, surface damage and surface temperature variations. 26
SURFmonitor also provides the ability to detect defects with low signal-to-noise ratio, such as 27
watermarks and stains that are difficult to detect in traditional defect channels. Built on the
Available as an add-on module 28
Surfscan SP2 platform, SURFmonitor results demonstrate unparalleled repeatability and matching.
to the Surfscan SP2 products 29
Questions about how the SURFmonitor can address a specific use case or yield challenge?
30
Several proven applications Please contact Andy Steinbach at andy.steinbach@kla-tencor.com.
across all process modules 31
in the fab 32
33
34
35
300 36
SURFmonitor signal (ppm)
250
37
200
38
150
39
100
50 40
0 41
0.0 1.0 2.0 3.0 4.0 5.0 6.0
AFM RMS roughness (nm) 42
43
This SURFimage exhibits wet clean drying stains, which SURFmonitor results for a Cu ECD film show excellent
are extracted and reported as defects by SURFmonitor correlation to surface roughness as measured by AFM. 44
algorithms. The quadratic relationship between SURFmonitor signal
and roughness matches theoretical predictions. 45
46
Product News
1
HRP-350 10
11
12
Advanced 45nm semiconductor profiling technology at production throughputs
13
14
With profile control requirements for critical etch and CMP processes becoming much tighter HRP-350 Benefits 15
every device generation, customers require a single-system solution that will support yield critical
16
nano-scale applications, as well as control macro-scale topography on the wafer. Extends the measurement
17
The HRP-350 is the industrys most advanced high-resolution surface topography profiling capability to support advanced
requirements for 65nm 18
system, offering chipmakers the ability to monitor significantly smaller lateral and vertical
dimensions. Featuring diamond styli down to 20nm radius and a lower-noise platform for and beyond 19
enhanced measurement sensitivity, the HRP-350 system offers nanometer-scale stylus technology 20
which matches AFM resolution without modeling requirements. The systems high-resolu- Smaller styli and improved noise
21
tion mode enables accurate control of nano-scale features for applications that directly impact performance enable topography
device performance, such as Shallow Trench Isolation, CMP in the interconnect, metal film measurements of advanced 22
roughness and tungsten plug recess. For larger scale features, the systems long-scan mode nano-scale features (e.g., recess) 23
operates at high throughput to measure Cu CMP dishing and erosion, copper plating, die 24
planarity, and C4 bump height in packaging. Higher scan speeds elevate the HRP-350s Provides 33% tighter gauge
25
production worthiness across a wide range of critical transistor and interconnect applications. performance for the most
26
stringent process control
The systems broad portfolio of styli, including the proprietary 20nm UltraSharp stylus, are
27
based on diamond materials to offer the longest operating lifetimes, typically up to 100 times
longer than AFM tips. New stylus developments further advance the technology not only by Novel processing abilities enable 28
shrinking the stylus dimensions, but also enhancing the robustness to enable scanning up to small styli to scan at 5X higher 29
five times faster than the previous HRP-340 system. Other system productivity enhancements scan speeds to support both
30
contribute up to 40% higher system throughput while profiling critical structures in advanced macro- and micro-topography
65nm and 45nm devices. In addition to the 300mm HRP-350 system, a 200mm or less without stylus exchange 31
HRP-250 is also available for IC semiconductor and disk drive manufacturing applications. 32
Up to 40% higher throughput 33
Questions about how the HRP-350 can address your surface profiling challenges?
and a more reliable isolation
Please contact Petrie Yam at petrie.yam@kla-tencor.com. 34
system make for the most
prodution worthy surface 35
Stylus Lifetime Step Height Measurement metrology solution 36

-1030.0
37
-1040.0
Cursor Height (A)
38
-1050.0
39
-1060.0
40
-1070.0
41
-1080.0
>100k 42
43
Featuring proprietary 20nm UltraSharpTM Diamond based styli offering the longest operating lifetimes,
diamond styli and a lower-noise platform for typically up to 100 times longer than AFM tips. 44
enhanced lateral resolution.
45
46

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The 45nm Innovation Challenge

3 A New Approach to Identify Large, Yield Impacting 9

Defects on Polished Si Wafers 10

19 Spectroscopic Ellipsometry Film Metrology Braces for 22

45nm and Beyond 23

34 Applications of a Laser-Assisted Defect Detection System 31

for CMP Slurry Development in Rigid Disk Polishing 32

A New Approach to Identifying 5

Large, Yield-Impacting Defects 7

Particle COP Residue Scratch 38

Wafer Defect Types and Their Sources 1

contamination, process equipment, or from the cleanrooms 6

defect, which forms during the crystal-pulling process and is 13

Wafer manufacturers require a production-worthy inspection 27

LLPD (Crystal) LLPD (Wafering process) 43

Figure 2: Simplified Si wafer manufacturing process and faceted LLPD. 45

capture a phase difference, which reveals height or slope in- 1

Rotating The results of these logical comparisons can be used to classify 10

light collection channels (oblique narrow, oblique wide, nor- 22

mal narrow and normal wide). 23

Case Study 2: Twenty-three 200mm wafers 1

The conventional method identified a total of 28 LLPD True LLPD 35

Further analysis of the failure mechanism caused by the 1

300mm prime wafer inspection

before device processing

Etch Process Monitoring by 5

Electron Beam Wafer Inspection 7

inspection tool. For electron beam inspection, differences in 24

Test 3 condition or one of several different etch conditions, as shown 36

Following the etch process steps, wafer #1 was checked for 1

PR strip & wafer clean and a precharge step to enhance 10

were detected that correlated 13

normal contacts, which are dark. The inspection failed to show 23

from the inspection tool containing some defective contacts is 1

ePM is a new eS32 algorithm currently under development at 3

KLA-Tencor that can be used to find out-of-tolerance wafers 4

is excellent correlation between the two measurements. As 14

time, subtle under-etch defects were detected that also cor- 30

Productivity Improvement and 7

Test Wafer Cost Reduction

Extending the Useable Life 1

Regeneration area Defect detection sensitivity 3

SP1 Grade Pre SP1 Post SP1

detection of small defects on

the wafer surface decreases. 18

center in the fab where these 1

Recycle rate from 70% to 85%

SP2 PWP < X Grade Pre SP2

SP2 center was estimated to have 9

we can estimate the cost sav- 14

Wafer Level Metrology 5

Expands Process Applications at 45nm 7

dropped to the 250550C range. Subsequently, with the 1

peratures in 3050C range.4 Plasma nitridation has come 5

Temperature range (C)

1) collect baseline temperature information; 43

In this example, a 48nm CD process with a seven-zone PEB 1

Pre CD Validation Plasma Etch 6

4.41 Qualification with Temperature 18

Time Units Etch processing chambers require frequent preventive mainte- 19

resolved to achieve the desired level of performance. To isolate 33

of SensorWafer data and advanced analysis software. 37

Edge Helium Cooling Decreases Heat at the Edge of the Wafer