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Peak Current Mode and Continuous

Current Mode DC-to-DC Converter
Modeling and Loop Compensation
Design Considerations
Van Yang,
Field Applications Engineer, Analog Devices, Inc.

Introduction
In many applications, such as computing, the power rails load transient L
RS VO
requirements are becoming more and more restrictive. Furthermore,
because it involves complex Laplace transfer function calculations, the RC RL
VIN
loop compensation design is often viewed as a difficult and time consum-
ing task for many engineers.
CO
This article discusses, step by step, the average small signal modeling
of widely used peak current mode (PCM) and continuous current mode Comp
(CCM) dc-to-dc converters. With the mathematical model, ADIs ADIsimPE/
R1
SIMPLIS, a switching circuit simulation tool is utilized to minimize the work
gm
of complex calculations. Then a simplified model is shown for simpler and PWM
faster loop compensation design and simulation. Finally, ADP2386EVAL
R2
A (s)
evaluation board test results are used to prove that the loop crossover
VREF
frequency, phase margin, and load transient response simulation results
were well matched with the test results.

PCM Average Small Signal Modeling

As Figure 1 shows, six blocks contribute to the current mode dc-to-dc Figure 1. Current-mode buck block diagram.
converter function: the feedback resistor divider, the compensator net- Modeling the power stage as a 3-terminal switch:
work, the current sensing and sampling, the comparator, the power stage,
and the output network. In the loop, the inductor current ramp signal is com- XX Active switch mode (A)
pared with the compensator error amplifier output, which feedbacks from XX Common mode (C)
output voltage. The PWM signal is generated to drive the switches to modu- XX Passive switch mode (P), as shown in Figure 2, we get the following
late the inductor current. Inductor current flows into the output capacitor and
Equation 1:
load. Out of these six blocks, the power stage is the only nonlinearized block
and it can be the most difficult block for dc-to-dc modeling. iIN = iL d, VPC = vIN d (1)

iIN = ^iL D + ^
^ ^ =^
dIL, V vIN D + ^
dVIN
PC

^
iL, i^IN,^d, ^
vIN, and ^
vPC

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 Peak Current Mode and Continuous Current Mode DC-to-DC Converter Modeling
2 and Loop Compensation Design Considerations
iIN = iL d, VPC = vIN d
iINaverage
Its an = iL d, model,
VPC = only
vIN dvalid in continuous current mode, equivalent to Comparator gain Fm is shown in Equation 5, Sn is the rising slope of induc-
a transformer with
^ ^ ratio^1:d. The
turns ^ model^ gets us^differential Equation 2: tor current, Se is the Vi VOTs is the switch
1 slope compensation, VOperiod:
iIN = iL D^+ dI^
L, VPC = vIN D + dVIN Fm = 1 , Sn = V V RT, Sf = V RT
iIN = ^iL D + ^
^ dIL, VPC = vIN D + ^
dVIN (2) (Se + Sn) Ts i L O LO
Fm = 1 , Sn = Vi VO RT, Sf = VO RT
Fm = (Se + Sn) Ts , Sn = L RT, Sf = L RT (5)
^
i^ ^ ^^ vIN, and ^ (Se + Sn) Ts L L
Small
^ signals
^ ^ L, iIN, d, ^ vPC have been employed into the
iL, iIN
average , d, vtoINbecome
model , and vthe
PC average small signal model (ASSM). With
The gain function of the sampling effect is shown in Equation 6:
this model, the power stage can be linearized for analysis. STs s2 s
He(s) = STs s 22 + s + 1, wn = fs, Qn = 2/
eSTs 1 w w Q
He(s) = STs s 2n2 + ns n + 1, wn = fs, Qn = 2/ (6)
C
A VIN d
He(s) = eSTs 1 w n2 + wnQn + 1, wn = fs, Qn = 2/
eSTs 1 w n wnQn
VIN
The gain function from input voltage to inductor current is shown in
IL d
C R Equation 7: 1
^i (SCO + R ) D
L ^
1:D
Gvi(s) = ^ (d = 0) = (SCO + 11 RO ) D (7)
iL ^
^ sL
+ O + +Rs 2OLC
O) D
P Gvi(s) = ViINL (d ^= 0) = 1(SC O
Gvi(s) = V^ (d = 0) = RsL
O
Figure 2. Average small signal model for the 3-terminal switch. ^
IN 1 + sL + s 22 LCO
The Tcurrent FVIN
i (s) =loop
mG di (s)H
gain e (s)R
function + RO in+Equation
is1Tshown s LCO 8:
Still using the PCM CCM buck as the example, the entire regulator has Ti (s) = FmGdi (s)He (s)RT R O
been modeled into the Laplace transfer function block diagram, as shown Ti (s) = FmGdi (s)He (s)RT (8)
in Figure 3. There are two control loops: the voltage loop and the current
loop. In the current loop, inductor current is sensed by RT and sampled The voltage loop gain function is shown in Equation 9:
into a ramp on the first negative input of the comparator. In the voltage Tv (s) = KAv (s)FmGdi (s)RO (s)
Tv (s) = KAv (s)FmGdi (s)RO (s) (9)
loop, output voltage ripple is sensed by the resistor divider with a gain of Tv (s) = KAv (s)FmGdi (s)RO (s)
K and sampled into the compensator network Av(s) as error voltage into The loop gain function is shown in Equation 10:
the comparators positive input. With the slope compensation ramp as the Tv (s)
second negative input signal, the comparator generates a regulated duty T = Tv (s) (10)
cycle signal into the average small signal model of the power stage to 1 +
T = Tv (s) T i (s)
modulate the inductor current. Ti=(s)1=+FTmiG (s)di (s)He (s)RT
There are +=
T1i (s)
four Tconsiderations
iF(s)
mGdi (s)Hefor(s)R
theT dc-to-dc loop gain design target:
XX ^ for low dc error
High dc loop gain
Vi Gvi(s)
vO FmGdi (s)RO
XX GOCloop
Wide v^O =for
(s) =bandwidth
v ^ Gditransient
Fmfast (s)RO response
+ TiO(s)
1 (s)R
G (s)(s)
TvOC == v^
KAvcomp
(s)F=mGF1mdiG
+diT(s)R
(s)O
==vKAv^ i (s)
20 O the
Vc d iL Vo XX
GOCTdBv(s)
slope
(s) near
comp = crossover
(s)F G
m di (s)R
frequency
O (s)
for higher phase margin
Av(s)
+
Fm Gdi(s) Ro(s) (>45) vcomp
^ 1 + Ti (s)
XX High attenuation at high frequency for noise attenuation
T (s)
In a Tregulatorvloop, only the compensator Av(s) and the feedback resistor
= TR (s)
O(s)
He(s) RT
T 1
= + Tiv(s)
GOC (s) 1customized
divider K are
+ R
T (s) by the designer. So in the loop design, two steps
O(s)
He(s)R
GOC (s) Firstly,
are included. i
RO(s)disconnect
T the resistor divider with the output to get
the open-loop
He(s)R
GOC (s) gain, T
as shown in Equation 11:
K
He(s)RT
v^O ^ FmGdi (s)RO
GOC (s) = vO= FmGdi (s)R
O (11)
Figure 3. PCM CCM dc-to-dc control model block diagram. GOC (s) v=comp
^ =1 + Ti (s)
vcomp
^ 1 + Ti (s)
The gain function from inductor current to output voltage is shown in
Secondly, design the compensator Av(s) to compensate the zeros and
Equation 3:
poles of the open-loop gain Goc(s) to meet the loop gain design target.
(SCOORRCC ++ 1)
(SC 1) RoRo (3)
Ro(s)
Ro(s)== An example is shown in Figure 4 for the normal load condition when
R (s)
SC (RCC ++ RROO)) ++ 11
SCOO(R GOC (s)
O
RO(s)
Ti>>1, GOC (s)He(s)R
T . In the low frequency domain, there are
The gain function from PWM duty cycle to inductor current is shown in He(s)RT
Equation 4: one pole (1/2RoCo) and one zero (1/2RcCo) and one 2-order pole
^
i^ VVinin (SC (1/fs) in the high frequency domain caused by the sampling effect
iLL ^^ (SCOORROO ++ 1)
1)
G (s)== ^ (V
Gdidi(s) (Vinin== 0)
0) == ,, (4) He(s). Compensator Av(s) is designed to enlarge the crossover frequency,
^ RROO 11 ++ ss ss22
dd QwOO++ ww22
Qw OO ensure a 20 dB slope near the crossover point, and to get more than
11 RR a 45 phase margin. The compensator has two poles and one zero; one pole
wwOO== ,, Q
Q==
LC LC LL is used to compensate the open-loop gain capacitor ESR zero, the other
CC pole functions as an integrator to increase the loop dc gain, and the zero
pole compensates the open-loop load effect. The second-order pole at
high frequency (1/fs) is beneficial for noise attenuation.

11 VVii VVOO VVOO

FFmm== ,, SSnn== RRTT,, SSff == RRT
(Se ++ Sn)
(Se Sn) Ts
Ts LL LL T
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Integrator
The ADsimPE tool, powered by SIMetrix/SIMPLIS, is a personal edition cir-
Av (s) cuit simulator ideally suited to evaluate linear and switching components
from Analog Devices. SIMetrix is very useful for linear circuits like op
One Zero amps, and SIMPLIS is targeted for switching components such as dc-to-dc
One Pole converters and PLLs. In Figure 5, a PCM CCM buck reference circuit has
Goc (s)
been setup as the reference to check circuit behavior and model accuracy.
Its a PCM sync buck regulator with 3.3 V input, 1.2 V output, and 1.2 MHz
| T (s) | switching frequency.
As Figure 6 shows, in the left loop gain calculation results of the average
small signal model, the crossover frequency is 50 kHz and the phase mar-
gin is 90.35. The SIMPLIS simulation result, as seen on the right side of
Figure 6, shows a 90.8 phase margin at a 47.6 kHz crossover frequency.
This proves that the ADIsimPE/SIMPLIS switching circuit simulation result
<T (s) 90 is matched with the complex ASSM calculation, which offers the designer
a fast way for loop design. However, the schematic, as shown in Figure 5,
180 is not very simple.
Figure 4. PCM CCM dc-to-dc loop design steps.
X1 IN OUT
Ideal LG_IN LG_OUT
= OUT/IN
D4
S Current Sensing
40 m 1.5 F IC = 100 m
I3-pos
H1 R7 L1
+
150 m
LG_OUT
+ 200 1.5 F IC = 1.2 1.2 k
C6 R1 + AC 1
Ideal
+ D1 5m V5
3.3 S2 R9
V1

E1
1 1.1
LG_IN
5
V7
V6

0.6
V4 V3 10 k
+ Slope Compensation 500 u R4
U3

D2 QN R
Q S V2 36 k G1
U4 Ideal 10 k
1 k + R2
U2 R3
6.8 pf 1.5 n
10 k R8 C2 C1
R10 60 pF IC = 0
C4
PWM Type II Compensator
D3 U7

U5
Ideal
1 k
10 k
R6 R5
60 pF IC = 0
C3

Figure 5. PCM CCM buck SIMPLIS reference circuit.

47.63999k 47.82854k
189.65782
Y4 Y1
120 90.803528
60
80
100 50

40 60
80
Gain and Phase Margin

30 91.03286
Phase ()

40
60
Gain (dB)

20

40 10 20

0 229.331m
20 0
Gain (dB)
10
Phase ()
0 20 20

30
20
1 100 10k 100 200 500 1k 2k 5k 10k 20k 50k 100k 200k 500k 1M
Frequency (Hz) Frequency (Hz)
Ref
Figure 6. ASSM calculation result and SIMPLIS simulation result.
 VIN Mode
Peak Current RO Continuous
(SCOand + 1) VINCurrent Mode DC-to-DC Converter Modeling
4 Gdi(s) = , wO =
and Loop R O 1+ s s 2 Considerations
Compensation 2 sL
+Design
QwO wO

PCM R
1 Simplified Average Small Signal Modeling And crossover frequency is much bigger than 1LCo, therefore, the open-
, Q=
LCO L loop gain function in Equation 13 could be further simplified as Equation 14:
Considering theC crossoverfrequency is much bigger than 1LCo in the
O
application, an estimation could be performed for the complicated equa- 1 1 1 Re||Ce
H(s) = =
tions. For Equation 4, the gain function from PWM duty to inductor current, RT 1 + sL 1 + sReCe RT Re||Ce + sL
could be simplified, as shown in Equation 12: Re
(14)
VIN (SCORO + 1) VIN
Gdi(s) = VIN (SCORO + 1) VIN , wO = 1 Re||Ce
Gdi(s)iL= ^ RO 1 + s F sGdi(s)
2
2 sL , wO =
QwO + ms 2 w RT Re||Ce + sL + RO||CO
H(s) R
= Vc (VINO =10) + =s1Qw + w
+ FOmGdi (s)H
O2 sL
O e(s)Rs
1 R (12) The result is that the open-loop ASSM could be simplified, as shown in
1 LC 1 , Q = RL 1 Figure 7, into a compensator output voltage controlled current source
O, Q = =
RT LCO TsL(SCCLOn + Se) Ts s2 flowing into an RLC network generating inductor current. This is a much
1+S + 2
VINORT 2  easier model to use for simulation or calculations than the original compli-
From Figure 3, we could get the open-loop T s2 gain function, which is com- cated equations.
pensator
1 output 1voltage to inductor current, as shown in Equation 13: L
, iL
RT iLTs(S^n + Se) Ts FsmGdi(s)
H(s)
= iL (V^IN = 0) = + F2mGdi(s)
1 + sL
V L(S + Sf) =12L + FmGLdi (s)He(s)Rs
H(s) = Vcc (VnIN = 0) 1 + FmTGsdi (s)He(s)Rs
2
1 1 Vc/Ri Ce Re C R
1 Vi VO T L(S +VSO1 ) T 2 =
Sn R= T
1 + S Sf n=+ Se)RT Ts + ss 2 =
RTTs,L(S
RT L s V n R Le
2s + 22
1+S IN T
VIN RT 2 T s22
1 1 Ts (13)
, Figure 7. Simplified ASSM open-loop circuit.
1 1
RT Ts(Sn + Se) Ts s ,
RT 1 + sL Ts(Sn + Se) T 2Ls + s2L
Using the Figure 5 reference circuit, calculate Re and Ce, then set up the
1 + sL L(S n + Sf) + closed-loop simplified ASSM circuit in ADSimPE, as shown in Figure 8.
L(Sn + Sf) 2L T2s2L
The SIMetrix simulation result is shown in the right half of Figure 8 with
T s2
Vi VO VO the crossover frequency as 49 kHz and the phase margin is 90.5, which
Sn = Vi VO RT , Sf = VO RT matches the ASSM calculation result and the SIMPLIS simulation result
Sn = L RT , Sf = L RT shown in Section 2.
L L
Se is the slope of the compensation slopes positive edge. Take
2L T2 Sf Se ,
Re = , Ce = 2sL , =
2 Se + Sn
Ts 1 + 1

IN OUT
LG_IN LG_OUT
= OUT/IN LG_OUT

2L 1.5 F 2 Sf Se
sns T s2
Re1 = 1 2L 1 , Ce = L1 T2s 1, =Re ||C Y3 Y2

Re=
H(s) =R 2 Cee=
, sR = , = SSefRo
L +
Se
e(s)
SsL 60 90
2+
TsT 1 + 11+ C e  2 R
L R ||C +
T e See + S
n
150 m sL 1 n 80
Ts 1 + C3 Re2.64 + 200 F 1.2
50
R6 46.9 n R5 C6 R1 + AC 1
70
1 Re||Ce 5m
R9
V5 40
H (s)
60
RT Re||Ce + sL + RO||CO 30
Phase ()

50
Gain (dB)

20
LG_IN 40
10

1 1 1 Re||Ce 30
H(s) = 1 1 = 1 Re||Ce
0

H(s) = RT 1 + sL 1 + sReCe = RT Re||Ce + sL 0.6 20

RT 1 + sL 1 + RsR C RT Re||Ce + sL V3
ee e 10 k
10

E1 Re 500 F R4
20
10

1 Re||Ce Type II Compensator

1 Re||Ce
RT Re||Ce + sL
1
+ RO||CO 36 k G1
100 200 400 1k 2k 4k 10k 20k 40k 100k 200k 400k 1m

RT Re||Ce + sL + RO||CO R2 10 k
Frequency (Hz)

6.8 pF 1.5 n R3
C2 C1

Figure 8. Simplified ASSM simulation circuit and result.

 Visit analog.com 5

ADP2386 Modeling Simulation and Test Result
The ADP2386 is a synchronous PCM CCM buck regulator from
Analog Devices. It ranges from 20 V input voltage down to 0.6 V output
voltage at up to 6 A output current, with switching frequency ranges from
200 kHz to 1.2 MHz. The devices versatility allows it to be used in step-
down applications and inverting buck-boost topologies without additional
cost and size. In this section, the ADP2386EVAL evaluation board will be
utilized to verify the model simulation results. Two tests are compared:
a loop test and a load transient test.
Figure 9 shows the schematic diagram of the ADP2386EVAL. For testing, the
board is set up under the conditions as shown in Table 1, row 1, below.
The internal slope compensation of the ADP2386 is adaptive with duty
0.6 fs
cycle, Se = , and Equation 14 was used to get the simplified
2.5 (1 D)
ASSM parameters as shown in Table 1, row 2. The output capacitors dc
bias spec drops about 30% at 3.3 V, so in the simplified ASSM simulation
the output capacitor value has been changed to 100 F, not the 147 F in
the evaluation board.

Table 1. ADP2386EVAL Test Condition and Simplified ASSM Parameters

VIN VO FS IO L C Compensator
12 V 3.3 V 600 kHz 3A 2.2 H 147 F/5 44.2 k, 1.2 n, 4.7 p
RT Se Sn Sf Re Ce Gm
123 m 0.2 V/s 0.49 V/s 0.18 V/s 2.51 128 nF 580 S

J1 J2 J3
SYNC VREG PWG

1 1 1

J4 J5
1 1
R1
GND GND NC
R2 100 k 1 J6
2
3
EN
R3
NC
100 k

C1
22 nF
R4

J7
2
C2 1
4.7 pF
U1 24 23 22 21 20 19 VIN
SS
SYNC
RT
PGOOD
EN
PVIN4

R5 C3 R6
2.21 k 1200 pF 44.2 k J8
R7 1 COMP 18 1
PVIN3
J9 10 k 17
2 FB VIN
1 PVIN2
C5 1 F 3 16
VREG PVIN1
VOUT ADP2386
R8 C4 4 GND 15 C7 C8
J10 NC NC L1 BST C6
SW 0.1 F
1 1 2 5 SW1 14
SW4
10 F/25 V

10 F/25 V
2.2 H 6 SW2 13
2 PGND6
PGND1
PGND2
PGND3
PGND4
PGND5

VOUT C9 C10 C11 1 R9 26 E_SW 25 J12

SW3

NC EXP 1
NC
100 F/6.3 V
47 F/6.3 V

J11 7 8 9 10 11 12 GND
SW C12 SW
J13 NC
J14
1 2
1
2
GND GND
J15
1 VIN = 12 V, VOUT = 3.3 V, IOUT = 6 A, fSW = 600 kHz
GND

Figure 9. ADP2386EVAL schematic.

 Peak Current Mode and Continuous Current Mode DC-to-DC Converter Modeling
6 and Loop Compensation Design Considerations

Figure 10 reveals the ADP2386EVAL loop simplified ASSM simulation and
test results. The left side is the simulation by ADIsimPD/SIMetrixthe
crossover frequency is 57 kHz, the phase margin is 71. The right side is
the test result under AP model 300the crossover frequency is 68.7 kHz
and the phase margin is 59.3. Although there is a difference between
test results and model simulation, we know from the ADP2386s data
sheet that its error amplifier gain is varying from 380 S to 580 S,
coupled with the inaccuracy of the inductor and output capacitor. So this
difference between the two results is acceptable.
Mag[B/A] (dB)
For the load transient test, two tests are included. Test 1 is a test under
Table 1 compensator conditions with good phase margin and wide
crossover frequency. Test 2 is a test with the compensator changed to
100 pF/1.2 nF/44.2 k, in which the crossover frequency is down to
39 kHz and phase margin down to 36. Figure 11 shows the load transient
(0.5 A to 3 A, 0.2 A/s) Test 1 simulation and test result. Overshoot peak is
tested to be 67 mV and the simulation result is 59 mV, with the transient
curves being well matched. Figure 12 shows the load transient (0.5 A to
3 A, 0.2 A/s) Test 2 simulation and test result. The overshoot peak is
tested to be 109 mV and the simulation result is 86 mV, again with the
transient curves being very well matched.
Phase [B/A] ()

Y4 Y2
50.000 250.000
40
40.000 200.000
30 60
30.000 150.000

20 20.000 100.000
40
Phase ()

10 10.000 50.000
Gain (dB)

20 0.000 0.000
0
10.000 50.000
10 0
20.000 100.000
20
30.000 150.000
20
30 40.000 200.000

50.000 250.000
1k 2k 4k 10 k 20 k 40 k 100 k 200 k 400 k 1M 1 2
Frequency (Hz) 1 kHz 10 kHz 100 kHz 1 MHz
Data M1 M2 M2M1
Frequency 68.77 kHz 663.61 kHz 594.84 kHz
Magnitude 0.037 dB 37.592 dB 37.629 dB
Phase 59.309 deg 98.896 deg 158.205 deg
Figure 10. ADP2386EVAL loop simulation and test results.
T
TEK
999.5584 s 1.015175 mS
2.00 s a 1.000 mV 15.61679 s
11.20 s b 68.00 mV 1.5
13.20 s 67.00 mV
1.0
I (R1-P)/A

0.5
1
a
0
b 0.5
Y1
0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25
Time (m/s) Ref A 5 s/Div

3.32 3.3149321
3.31
3.30
59.3893 mV
Vo/V

3.29
3.28
4 3.27
3.2555428
3.26

1 50.0 mV BW 4 1.00 A 20.0 s 500 M 4 1.02 A 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25
T 0.00000 s 100 k Time (m/s) Ref A 5 s/Div

Figure 11. ADP2386EVAL load transient Test 1 simulation and test results.

T
TEK
999.8218 s 1.014588 mS
2.000 s a 1.000 mV 14.6656s
9.600 s b 110.0 mV 1.5
11.60 s 109.0 mV
1.0
I (R1-P)/A

0.5
1
a
0
0.5
b Y1
0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15
Time (m/s) Ref A 5 s/Div

3.34
3.32 3.3149321
3.30
Vo/V

3.28 86.2197 mV
4
3.26
3.24
3.2287124
3.22
1 50.0 mV BW 4 1.00 A 20.0 s 500 M 4 1.02 A 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15
T 0.00000 s 100 k Time (m/s) Ref A 5 s/Div

Figure 12. ADP2386EVAL load transient Test 2 simulation and test results.

Conclusion
Loop compensation is often viewed as a very challenging design task
by engineers, especially in fast load transient applications. Based on the
widely used peak current control mode continous current buck device,
this article has summarized the average small signal mathmatical model-
ing and loop calculation, and the ADISimPE/Simplis fast and easy simula-
tion technique. It also introduced a simplified average small signal model
and offered a simplified way of handling loop compensation design. The
ADP2386EVAL evaluation board loop and load transient bench test results
proved the accuracy of the simplified model and its simulation.
References
1
ADP2386 Data Sheet.
2
ADP2386EVAL User Guider.
3
Brad Brand and Marian K. Kazimierczuk.Sample and Hold Effect in PWM
DC-to-DC Converters with Peak Current Mode Control. 0-7803-8251-X
10.1109/ISCAS.2004.1329944 Circuits and Systems, 2004. ISCAS 2004.
Visit analog.com 7
About the Author
Van Yang [van.yang@analog.com] is a field applications engineer
at Analog Devices. Inc., in Shanghai, China. He joined ADI in 2015
to support regional medical and industrial customers in China.
Prior to joining ADI, Van worked at Texas Instruments as an FAE
for four years. Van earned his masters degree in communication
and information systems from Huazhong University of Science and
Technology in Wuhan, in 2011. In his spare time he is a super fan
of basketball and enjoys hiking.
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