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BUILT-IN SELF-CALIBRATION AND DIGITAL-TRIM TECHNIQUE FOR 14-BIT SAR ADCS

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ACHIEVING 1 LSB INL 2015
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TestingProjects February3,2017

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Builtin SelfCalibration and DigitalTrim Technique for 14Bit SAR ADCs

Achieving1LSBINL2015
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Abstract:
Subject
Several stateoftheart monitoring and control systems, such as dc motor
controllers, power line monitoring and protection systems, instrumentation Re: Builtin SelfCalibration and DigitalTrim Technique for 14Bit SAR ADCs Achievin
systems, and battery monitors, require direct digitization of highvoltage (HV)
Message
input signals. Analogtodigital converters (ADCs) that can digitize HV signals
require high linearity and lowvoltage coefficient capacitors. A builtin self
calibration and digitaltrim algorithm correcting static mismatches in capacitive
digitaltoanalogconverter(DAC)usedinsuccessiveapproximationregisteranalogtodigitalconverters(SARADCs)isproposed.The
algorithmusesadynamicerrorcorrection(DEC)capacitortocancelthestaticerrorsoccurringineachcapacitorofthearrayasthefirst
step upon powerup and eliminates the need for an extra calibration DAC. Selftrimming is performed digitally during normal ADC
operation.Thealgorithmisimplementedona14bitHVinputrangeSARADCwithintegratedDECcapacitors.TheICisfabricatedin
0.6m HVcompliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32dB
signaltonoiseanddistortionratio,whichisanimprovementof12.03dBafterselfcalibrationat400kS/ssamplingrate,consuming90
mW from a 15 V supply. The calibration circuitry occupies 28% of the capacitor DAC and consumes <15 mW during operation.
Measurementresultsshowthatthisalgorithmreducesintegralnonlinearityfromashighas7LSBsdownto1LSB,anditworksevenin
I'm not a robot
the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces differential nonlinearity errors from 10 LSBs down to 1 reCAPTCHA
LSB.TheADCoccupiesanactiveareaof9.76mm2. Privacy - Terms

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