Escolar Documentos
Profissional Documentos
Cultura Documentos
September 2013
What are Semiconductor Devices?
How Semiconductors are Made
Front-End Process
Back-End Process
Fabrication Facility and Equipment Issues
Business Aspects of Supplying Semiconductors
TM 2
TM 4
A conductor carries
electricity like a pipe
carries water.
Conductor
A semiconductor
controls the flow of
electricity like a faucet
controls water.
An insulator stops
the flow of
electricity like a
plug blocks water.
Insulator
TM 5
Copper, a conductor, has
one electron per atom
available for conduction.
A useful semiconductor
requires about 10 orders
of magnitude less
Impurities have to be
n Type doped with p Type doped with B
below one in 10 billion
P or As
TM 6
A MOSFET transistor is nothing more than a voltage controlled switch!
A transistor is just like a light switch on a wall, except that a voltage is used to turn the
switch on and off instead of a lever.
A good analogy to a transistor is two lakes connected by a canal.
"flood gate"
Water
reservoir
(SOURCE) Water
reservoir
(DRAIN)
The "flood gate" regulates the flow of water between the two lakes (source and drain).
A real transistor switches the flow of electric current on and off instead of water.
TM 7
Current (water) will not flow from an n-type reservoir to a p-type
region because it would have to flow uphill. .
p-type channel
water
reservoir water
(SOURCE) reservoir
(DRAIN)
n-type
n-type
Only way we can get water from one p-type reservoir to another is by
way of a n-type channel.
By using a capacitor and applying a positive voltage to that capacitor,
we can change the apparent conductivity of the channel from p to n
and turn the transistor on.
In reality, the drain is usually at a lower elevation than the source so
the water will flow downhill to the drain.
TM 8
A MOS transistor is nothing more than a voltage-controlled switch.
A MOS transistor is really just a capacitor with two extra terminals.
Capacitor Doped
(gate) polysilicon
Direction of
current flow
isolation n+ n- n- n+ isolation
(oxide) channel (oxide)
source drain
p-type silicon
Cross-Section View
TM 9
Capacitor
Isolation
(oxide)
source drain
Top View
TM 10
VDD
PMOS Normally ON
IN OUT
NMOS
Normally OFF
GND IN OUT
V Logic V Logic
0V 0 ~Vdd 1
Vdd 1 0V 0
TM 11
Analog semiconductor devices deal in precise electric properties, most
commonly voltages. Transistors within the device are designed to measure
and manipulate these properties. Analog devices are well suited to
processing real-world signals, as electronic patterns are used to directly
represent the original.
Digital devices do not deal in the values of actual voltages; rather, they
simply detect the presence or absence of a voltage. The presence of a
voltage is represented digitally as a 1, with the absence represented as a
0. These 1s and 0s can be processed and manipulated digitally with great
flexibility.
Mixed Signal These devices include both analog and digital circuitry.
Mixed signal devices are difficult to design and build, but bring the benefits of
both analog and digital processing together.
TM 12
Discretes, Optoelectronics, Sensors Includes all non-integrated circuit
semiconductor devices. A discrete is a single transistor in a package. Sensors are
discrete devices that measure real-world input. Optoelectronics are discrete
devices that produce or measure light.
Memory Memory devices are used to store data either for short periods of time
or permanently. Includes volatile (DRAM, SRAM) and non-volatile (flash, ROM)
memory.
TM 13
Microcomponents: Devices designed to perform intensive
compute processing and system control
Three Key Types:
Microprocessors digital processors that execute intructions and
perform system control functions. MPUs are optimized for general
purpose data processing
Microcontrollers stand-alone devices that perform embedded
compute functions within an overall system. MCUs contain single of
multiple processing elements as well as on-chip, RAM, ROM, and I/O
logic.
Digital Signal Processors specialized high speed programmable
processors designed to perform real-time processing of digital signals
TM 14
TM 15
Semi-Discrete Solution Multi-die SiP Monolithic SiP
Application Specific
Analog IC (ASIC)
TM 17
Poly Silicon, Folded Beam
Z-Axis Sensing
Z axis
Elements
X axis
Elements
TM 18
Wire bonds g-cell cap
1.98mm
g-cell device
ASIC
Lead Frame
6 mm
g-Cell
Die
TM 19
G-Cell Die
ASIC Die
Mold Compound
TM 20
Door Lock H-bridge
Multiplexer
MSDI Various sensor inputs
System Timer PWM ADC
CAN Basis Chip Multiplexer
SBC Various sensor inputs
Real MSDI
CAN Time Multiplexer
Clock Various sensor inputs
CAN MSDI
CAN Transceiver
MCU
CAN UHF
CAN Transeiver
MPC5xxx / S12x
Transceiver Amplifier
MC33696
LIN LIN Transeiver Antenna
LIN SPI
LIN LIN Transeiver
Power Drivers
5 million transistors
2 polysilicon layers
0.25 m technology
TM 24
Red CPU ADC
Blue ETPU
Green EQADC
Purple DSPI Flash
RAM
Yellow EMIOS
Orange FlexCAN
White EBI
Dark Green SIU
Magenta JTAG
Grey SCI
PLL
TM 25
~350 process steps, 55 mask layers
~75 million transistors
~400 to 1,600 chips per 200 mm wafer
Embedded ADC, SRAM, non-volatile memory
1.15 um2 SRAM
6 Layers of Cu Metal Bitcell Array
TM 26
0.5 micron is 1/200th
the width of a human hair
55 nm is 1/2000th the
width of a human hair
TM 27
The fab-provided Design Rule Manual (DRM) is an important
way that the semiconductor fab communicates with the IC
Design team
TM 28
Approved voltages, temperatures, etc
Process Options
Individual device offerings
Allowed / forbidden device combinations
Metallization options
Main process features
Brief process flow
TM 29
Poly
Active
TM 30
TM 31
TM 32
TM
Raw silicon substrate
E
Poly/Nitride/TEOS Coat
Oxide Growth
Silicon Wafer
Chemical deposits
TM 34
Test and back-end
Outgoing
Room Temp Hot Temp Dicing Inspection,
Probe Probe (for KGD) Pack & Ship
TM 35
A MOS transistor is nothing more than a voltage-controlled switch.
A MOS transistor is really just a capacitor with two extra terminals.
Capacitor Doped
(gate) polysilicon
Direction of
current flow
isolation n+ n- n- n+ isolation
(oxide) channel (oxide)
source drain
p-type silicon
Cross-Section View
TM 36
Silicon is the second most abundant element on earth after
oxygen ( 25% of crust )
Purification operations
SiHCL3 + H2 Si + 3HCl
The white sand of Abel Tasmans beaches in New Zealands South Island
is a typical source of silicon dioxide.
TM 37
A pure silicon seed crystal is
placed into a molten sand bath.
TM 38
Single crystal silicon ingot
length: 110 cm
TM 39
The ingot is ground into the
correct diameter for the
wafers.
TM 40
Next, the wafers are
polished in a series of
combination chemical and
mechanical polish
processes.
TM 41
The Process
Start with ultra-pure glass plates with
a surface deposition of chromium.
Computer generated layouts of the
IC drive a laser beam or electron
beam to selectively remove
chromium and create the mask or
reticle.
Design Driven
Increased complexity
Long write times
New product acceleration
TM 42
No OPC With OPC
Optical Proximity
Correction (OPC)
Chrome
Phase Shift Mask
Resist
TM 43
Growth of an ultra-
pure layer of
crystalline silicon
Approximately 3%
of the wafer
thickness
Contaminant-free
for the subsequent
construction of
transistors
TM 44
The wafer is coated with
photoresist material.
The reticle containing a layers
image of one or more die are
exposed by a light source
through a lens system onto the
wafer.
The wafer is then stepped over
to the next die and the process
repeated until the wafer is
completely exposed.
Expose Resist
Develop Resist
Etch
TM 46
The epi-wafer is exposed to high
temperature to grow an oxide
layer.
TM 47
Dispenses
Wafers receivers
Hot plate
Unloading
Track 1
Loading
Track 2
Control keyboard
TM 48
Mercury Lamp
Shutter
Reticles Reticle
Storage
Lens
Wafer Stage
Wafer
Loading /Unloading
TM 49
Wafers receivers
Hot plates
Dispense
Un loading
Track 1
Loading
Track 2
Control panel
TM 50
An etch process (wet or dry) is used
to remove the oxide where the
photoresist pattern is absent.
TM 51
Process gases
Process
Radio frequency chamber
under
power supply vacuum
Ionized
Gas ETCH
Exhaust management
Acid Acid
QDR
Heating
QDR QDR element
Acid waste Drain Rinse
TM 52
The oxide acts as a barrier when
dopant chemicals are deposited on
the surface and diffused into the
surface.
TM 53
Atmospheric Pressure Furnace
Exhaust
Heating elements
Vertical Furnace
TM 54
Gas
box
Too heavy ions
Source
Ion Accelerator Ion Accelerator
Too light ions
Loading
Machine Management
TM 55
optical
oxidation mask
photoresist
acid etch development
process spin, rinse, dry
step
TM 56
Contact locations
Process Conditions
1 2 3 4 5
Temperature: Piranha Strip
is 180 degrees C. 1 Organics 2 Oxides 3 Particles 4 Metals 5 Dry
H2SO4 + HF + NH4OH + HCl + H2O or IPA +
H2O2 H2O H2O2 + H2O H2O2 + H2O N2
H2O Rinse H2O Rinse H2O Rinse H2O Rinse
TM 57
Using the same oxidation and
photolithography process, an
opening is made in the oxide to
build the transistors gate region.
TM 58
Various oxides are grown or deposited
to insulate or protect the formed
transistors.
TM 59
Using the same photolithography process, via contact holes are
etched down to the three transistor regions that need to be connected to
other components on the chip.
TM 60
A layer of aluminum is deposited
on the surface and down into the
via holes.
TM 61
A 4 B
3 Process Chamber
EtchChamber
Aluminium
Target
C 2
Gas: Al Sputerred
Heating Argon
Chamber
1
Load-lock
Vacuum Pump
TM 62
Without CMP, the wafer will have a lot of topography
(mountains and valleys).
Excessive topography will:
Limit how small photo can print
Cause thinning of films on side walls
Compromise etch uniformity
Compromise film deposition uniformity
TM 63
TM 64
Another set of via holes are
etched in the dielectric isolation
oxide to enable access down to
the layer below.
TM 65
POLYIMIDE Cleared Bond POLYIMIDE
Pad Opening
SION exposed
Via 2 Via 2
PETEOS
PEN ESL
METAL 2 METAL 2
Via 1 Via 1
PEN ESL
METAL 1 METAL 1
TEOS+SION
LI LI BAR LI LI
BPTEOS
ESL
n+ n+ n+ P+ P+
P-Well
N-Well
Epi 2.0 m
P + Substrate
TM 66
1. Silicon substrate
2. Oxide growth
3. Oxide etching
4. Deposition of
structural layer
5. Structural layer
etching
6. Oxide removal
TM 67
Charge is placed on floating gate
with hot carrier injection or Fowler
Nordheim tunnelling
Charge remains trapped on floating
gate giving non volatile memory
function
TM 68
Parametric testing of test structures
Test structures in scribe lines between product die
CDs
FNF
AG004
FNF
Reticle
CDs
PID1
ESD17
TS311 BITD1 C180 FE47 TS311
BE751 C190 BE752
FE05 BITM1 C22 FE48 BE102
PRB01
CDs
PID3
SIMS
PID4
TM 69
Transistors
Metal to
metal
linkage
Contact
chains Poly over active stack
D05 Gate
Metal 1
Active
TM 70
Wafer thickness is reduced from 640m to 300m
2
3 1
Rotated table
Loading
Unloading
TM 71
TM
Air Air Air Air Air
Recirc Recirc Recirc Recirc Recirc Fan Deck
ULPA Ceiling Interstitial SEM,
Center Computer Center,
Work Utility Zone
Work
Zone
Utility Zone
Class 100
Work
Zone
Corridor
Zone Class 100
Work
Zone
Smock Rooms
Class 1 Class 1 Class 1 Class 1
Process Level
Process Process Process Process
Tool Tool Tool Tool
Raised Floor
Electric
HPM Rooms Exhaust Exhaust
Rooms
Maintenance Shops
Piping Piping
Subfab Parts, Quartz,
Wafer Storage
Ele
c. Ele
Support Support c.
Tools Tools
Crawl Space
TM 73
TM 74
First stage makeup air pre-filters are 30% efficient for 3-10um
sized particles.
TM 75
North & South
Cleans/ISD
2.5k sf CVD East Module (Bldg M)
(TEOS,
PAS)
Implant 5.6k sf
Etch Metals
4.2k sf Implant
PVD
23k sf
C Bldg 11 k sf
Diffusion/ Epi
6.5ksf
Photo
Cleans Photo
10k sf i - line Gown MRAM
Analytical Probe 2.1ksf
Polyimide 7k sf
8.3k sf 5.8k sf 9k sf
Lot
Start
Ship Implant YE Probe
2.5k sf 27k sf
Diffusion/
N
Cleans Photo CMP
6.6k sf 22k sf
DUV
Implant 6.1k sf
Cleans
CVD A Building to the East of M Building
4k sf ETCH has additional 8k sqft of Probe
8.2k sf
ETCH CLNS
Metals
(W,RTP)
TM 76
85,000+ square feet of sub-class 1 clean room space supporting wafer capacity of
6,000 WPW
Factory moves ~6,400,000 CFM, enough to fill 120 hot air balloons every minute
Factory has more than 17 miles of stainless steel piping and more than 50 miles
of electrical wiring
TM 77
200MM Equipment List for .18 Micron Facility
Equipment Number Price ($M) Total ($M)
Chemical Vapor Deposition 24 3 60
Physical Vapor Deposition 23 4 81
Steppers 54 8 432
Photoresist Processing 54 2 108
Etch 55 3 187
Cleaning- Strip 30 1 18
CMP 20 1 24
Diffusion - RTP 32 1 32
Ion Implant 13 3 43
Process Control - - 60
Automation/Handling - - 15
Miscellaneous - - 67
Total 1,126
TM 78
TM 79
TM 80
2000
4"
8"
5"
10%
12%
45% 2012
33%
6"
6"
13%
Source: Gartner (March 2012) 2016
52% 6"
29%
8" 10%
8"
12"
Source: Gartner (March 2012)
Larger wafers = more die per wafer = lower cost per 61%
24%
die
300mm (12) wafers yield more than twice as many
die for the same product as a 200mm (8) wafer 12"
Source: Gartner (March 2012)
TM 81
First 450mm fab expected in Albany NanoTech Complex in
2013 followed by another in 2016
MSI
3,000
2,500
2,000
1,500
1,000
500
0
4Q97 4Q98 4Q99 4Q00 4Q01 4Q02 4Q03 4Q04 4Q05 4Q06 4Q07 4Q08 4Q09 4Q10 4Q11 4Q12 4Q13
TM 82
R&D provides two major benefits:
Increases productivity
Enhanced process capabilities (required to remain competitive)
TM 83
TM 84
Increase partnership
Low Power
CMOS
HPSOI LP-Bulk
High
CMOS
Performance
SOI LP / GP
TM
e-Non
RF
Packaging Volatile
CMOS
Memory
TM
SmartMOS Research
Sensors Power &
Analog
TM
GaAs
GaN
RF
Increase differentiation
TM 85
TM
TM 87
Wafer Mount Process Description
Wafers are mounted on UV tape and carefully
placed on the metal frame to ensure correct
rotational alignment.
TM 88
Process Description
Epoxy is dispensed in the die flag area of the
substrate in a specified pattern (usually star)
followed by a pick and place process that
removes the die from the tape carrier and
places it over the dispensed epoxy.
TM 89
Plasma Clean Process Description
Plasma clean is then used to remove contaminants from the die
bond pad surface to improve wire bondability and adhesion.
He/O2 and Ar/H2 are two common gas mixtures that are used. Ar
plasma treatments used to bombard loose contaminants from the
surface. Oxygen-based plasma is used to react with carbon to
form gaseous CO & CO2.
TM 90
Transfer Mold Process Description
Substrate panels are loaded from a carrier into
the heated mold tool. Mold pellets are loaded into
the mold gate where clamp pressure is used to
create a seal between top and bottom die around
the substrate. Mold compound is transferred
through the gate runners into the mold cavity.
TM 91
Laser/Pad Marking Process Description
Molded substrate panels are then loaded into the
laser marking machine from a carrier and marked to
a defined set of criteria.
TM 92
Solder Flux Clean Process Description
A flux clean step follows the reflow process utilizing heated de-ionized water.
TM 93
Plasma Clean & Wire Bond
TM 94
TM 95
TM
$350 +5%
-2% to
to +6%
-4%
$300
Billions of Dollars
$250
$200
$150
$100
$50
$0
'84 '85 '86 '87 '88 '89 '90 '91 '92 '93 '94 '95 '96 '97 '98 '99 '00 '01 '02 '03 '04 '05 '06 '07 '08 '09 '10 '11 '12 '13
TM 97
Average Growth
50
46 2001-2011: 8.0% per Year
42
38 37
40 32
29 28 32
30 23 23 19
18
20
8 8 10 9
10 5 4 7 3 0 5
1
0
-10
-3
-9 -8 -9
-20
-2
-17
-30
Semiconductor Market
Billions of Dollars -32
-40 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011
$204 $139 $141 $166 $213 $227 $248 $256 $248 $226 $298 $299
-50
'84 '86 '88 '90 '92 '94 '96 '98 '00 '02 '04 '06 '08 '10 '12
Source: WSTS, Freescale Strategy, iSuppli, Gartner
TM 98
Percent of Total Semiconductor Market
60
Asia
55 Pacific
50
45
40
35
30
25 China
20 Americas
Japan
15
Europe
10
'96 '97 '98 '99 '00 '01 '02 '03 '04 '05 '06 '07 '08 '09 '10 '11 '12
Source: WSTS
Years By Quarter
TM 99
Electronics revenues
CAGR 2007-11: 1%
CAGR 2001-11: 3%
CAGR 1991-11: 3%
Semiconductor content
Semiconductor revenues
TM 100
Semiconductor Market Revenues in Billions of Dollars
Bil $ 1000
SC Market
Annual Trend Growth
1970s 18%
100 1980s 16%
1990s 14%
2000-06 7%
10 2000-10 4%
0.1
1970 1975 1980 1985 1990 1995 2000 2005 2010
Years By Quarter
TM 101
8%
Automotive
40% Communication
Consumer
22%
Industrial
Military
Data Processing
1% 18%
11%
TM 102
15%
20% MPU
MCU
5% DSP
2%
Logic
7%
Analog
Sensors
8% Opto
26% Discretes
Memory
3%
14%
TM 103
Automotive Market
Overall Market
Logic 24.3%
MPU:14% MCU:5%
DSP:3% Memory 4.8%
Logic:26%
DRAM:12% Discrete 13.2%
Flash:
9%
Analog 12.8%
Other Sensor 10.2%
Analog: 14% Sensors: Opto:6%
Discretes:
Memory:
2%
Opto 4.8%
7%
2% MCU 29.8%
TM 104
Automotive Industrial Consumer Wireless Networking
Handsets Infrastructure
Multimedia
processors Multimedia processors
Microcontrollers Communication
processors
Wireless connectivity: baseband processing, RF transceivers, and power amplifiers RF, PA and
baseband
Sensors
TM 105
Capacity How to make automotive
golden years attractive
Total
Demand Volume: individual parts &
overall market ?
Other Markets
Demand
Factory Closure
Automotive
or Obsolete
Demand
Technology
Qual
TM 106
TM
MC68HC11 MC68F333
2T-S Flash
EEPROM 1.5T Flash
MPC555
MPC565
MPC5554
CDR1
CDR3
1T Fl as h
130nm ETOX Flash High Density
Scale Drawing High Density
ETOX Flash
High Density
TM 108
CDR1 0.35m CDR3 0.25m HiP7 130nm CMOS90 CMOS55 CMOS40
FN/FN 1T HCI/FN 1T HCI/FN 1T HCI/FN 1T HCI/FN 1T HCI/FN 1T
2.7m2 0.995m2 0.359m2 0.18m2 <0.15m2 < 0.1m2
TM 109
MPC555 MPC565 MPC5554
Black Oak Spanish Oak Copperhead
CDR1 0.35u CDR3 0.25u HIP7 0.13u
448K Flash 1MB Flash 2MB Flash
7 million transistors 14 million transistors 34 million transistors
TM 110
8 Output Switch 16 Output Switch
0.375 ohm 0.375 ohm
SMARTMOS 2.5 SMARTMOS 5AP
TM 111
Frequency
Test time
EMC
Frequency components
Package Capital
Die Test equipment
Tape & Reel Package
Machinery
Board size
Capital
equipment
Tier 1
volume
TM 112
TM
Static PAT (Process
BMY (Below Minimum Yield) Average Testing)
Screen wafers with lower than Screen die with
statistical distribution of yield parametrics that are
3500
outside statistical
distribution
3000
2500
2000
1500
500
0
10 30 50 70 90 110 130 150 170 190 210 230 250 270 290 310 330 350 370
Cluster)
SBL (Statistical Bin Limits) Screen die with failing
Screen wafers with unusual bin neighbors
signatures Dynamic PAT
Screen die with parametrics that are
outside the wafer distribution
Upper
limit
0 3 6 9 12 15 18 21 24 27 30
outliers
TM 114
SBL (Statistical Bin Limits)
SBL contains outlier wafers in Freescale and
provides faster feedback on slight process/tool Median 95th percentile
anomalies causing higher bin fallout
Bin Limit Setting: Upper limit
Bins with very low fallout are set at fixed level to SBL = Median + K*Robust Sigma
detect excursions
Limits are reviewed every 3-6 months (Product
Volume Dependent
Specification window
Typical distribution
Static PAT **
Statistical test limits are set in the Outliers ** *
probe program to screen outlier **** *
* **
die. ** Outliers
**** *
Limits are reviewed every 3-6 * *
* ** * ** *** * ** ***
months (Product Volume Spec Limit
Typical product Spec Limit
dependent) PAT Limit PAT Limit
TM 115
Before After
TM 116
Defect isolation in a semiconductor device uses the same troubleshooting methodology to
isolate a failure in any large system.
The problem description is first described at the system level (Die level failure description)
Data is collected to isolate the failure to a sub system (Functional Blocks within a device)
Analysis continues, eliminating all the possible causes until the source of the failure is identified
Electrical
Freescale Failure
test Analysis
diagnostic Process
TM 117
Known Good Die (KGD) analysis samples are typically returned to Freescale still
attached to the target application. The die must be removed and packaged for
analysis and protection of the die. Due to the fragile nature of the die, a visual
inspection is performed at each step to ensure device integrity.
Step 1: Die Removal
Wirebonds pulled
Die encapsulation in epoxy
Customers board is milled down from the
backside until the die is freed from the target
application
Die removed from epoxy encapsulant
PBGA Package
TM 118
Step 1: Device level testing
Device is evaluated on the bench using an
EVB (Evaluation board) using standard
evaluation tool to assess basic functionality.
TM 119
After completion of the electrical verification, the device is submitted to the Product Analysis Lab
Step 2: Microprobe
In-circuit measurement technique that uses very fine wires to
collect parametric data (signals Voltages, Resistances,)
Similar to using a multi-meter to troubleshoot an electrical
system.
Requires microscopic holes to be drilled in the silicon order to Microprobe Station
access nodes of interest.
TM 120
TM 121
In order to collect data via microprobe, the Analyst needs to be able to access various circuit nodes within the die.
A FIB (Focused Ion Beam) is used to drill sub-micron holes and .
Conceptually can be thought of as an electric knife or a microscopic Mill/Drill. Removal rate is measured on the order of
molecules.
Completed
probe pad
TM 122
Once the analyst has isolated the failure to a single circuit element, physical analysis begins.
There is no turning back once physical analysis begins as the device will no longer be
functional.
Microprobe complete and
There are 2 primary physical analysis techniques; failure isolated.
1. Layer by layer deprocessing Deprocessing is deemed
2. Cross section. the best method
P assiva tio n
M etal3 Pa ssiva tio n M eta l3
M etal3 M eta l3
A 29
M etal2 M etal2 A 29
I L D2
Meta l1 ILD2
M etal2 M etal2
M etal1 M etal2 M etal2
D 19
I L D1 D 19
DM06eta l1 LI_ SO UR CE BA R D 19
M etal1 I L D1
ILD1 M eta l1
Meta l1 M etal1
ILD0 D 06 L I_ SO UR CE B A R M etal1
ILD0
LI_BA R LI_ SQ UA RE D 06 L I_ SO UR CE B A R
D 06 LI_ SO UR CE BA R
I L D0
I L D0
L I_B A R L I_ SQ UA RE I L D0
Z - d e v ice ILD0 I L D0
H V PW ell P o ly 1 a c c ess
L I_B A R ILD0
LV PW ELL H V NW E LL H V P W e ll H V N W el l
LI_BA R L I_ SQ UA RE LI_ SQ UA RE
L V N W ELL L V PW EL L A(Isolated
rr a y W e) ll
Z - d e v ice H V P W el l P o ly 1 a c c es s
ILD0
ILD0
LI_BA R LI_SQ UA RE
LV NMOS LV PMOS HV Z-DEVICE HV NMOS HV PMOS Array LV NMOS LV PMOS HV Z-DEVICE HV NMOS HV PMOS Array
complete
TM 123
The FA analyst can also perform a cross section of a suspect circuit
element.
A very thin sample is cut out of the die using the FIB tool.
Transmission Electron Microscopy (TEM) is used to look through the
sample to identify a defect.
Sample Prep and TEM completion can take 3-5 days.
TEM TEM
TM 124
TM
Flexible Sourcing
Exit 150mm
200mm Internal/External
300mm External
Front-End
Invest in Differentiating Technologies
Manufacturing eNMV
Sensors
SmartMOS/Analog
RF
Flexible Sourcing
Auto, Industrial, Networking Int/External
Consumer External
Burn-in External
Back-End
Manufacturing Invest in Differentiating Technologies
Power Analog
High Performance Networking assembly and test
Automotive sensor test
TM 126
Freescale Chandler Fab 8
Chandler, AZ
AMERICAS
ASIA PACIFIC/
JAPAN
Freescale Kuala
Lumpur Final
Manufacturing-Kuala
Lumpur, Malaysia
TM 127
TSMC Dalsa
KES
Fab11 IBM
TSMC, UMC,
ASE, Amkor,
Tower Global Test
Amkor, ASE,
StatsChipPac
AMERICAS
EMEA
ASIA PACIFIC/
JAPAN
Amkor
StatsChipPac,
Carsem
TM 128
Continue Our Strategy
Flexible
Manufacturing: The
Right Model
Maximize
Efficiency
Key priorities
Customer Success
Quality
Partner Cross
Best Cost Aggressively Qualifications
Asset Utilization
Flexibility & Assurance of
Supply
TM 129
Sourcing
Technology
Internal External
TM 130
External Foundries Locations Key Technologies
Taiwan GaAs
TM 131
External Foundries Locations Key Technologies
Taiwan, Korea,
SOIC, MAPBGA, Sensors, FCPBGA
Philippines
Malaysia, Korea,
MAPBGA, PBGA
Singapore
Malaysia QFN
TM 132
TM 133
TM