Escolar Documentos
Profissional Documentos
Cultura Documentos
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM Cortex-M4
32-bit processor core
Data Sheet
V1.4 2016-01
Microcontrollers
Edition 2016-01
Published by
Infineon Technologies AG
81726 Munich, Germany
2016 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
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Warnings
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
XMC4500
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM Cortex-M4
32-bit processor core
Data Sheet
V1.4 2016-01
Microcontrollers
XMC4500
XMC4000 Family
Trademarks
C166, TriCore, XMC and DAVE are trademarks of Infineon Technologies AG.
ARM, ARM Powered, Cortex, Thumb and AMBA are registered trademarks of
ARM, Limited.
CoreSight, ETM, Embedded Trace Macrocell and Embedded Trace Buffer are
trademarks of ARM, Limited.
Synopsys is a trademark of Synopsys, Inc.
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4 Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.1 Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.2 Port I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.2.1 Port I/O Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3 Power Connection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1.3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.1.4 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.1.5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2.2 Analog to Digital Converters (VADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2.3 Digital to Analog Converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.2.4 Out-of-Range Comparator (ORC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.2.5 Die Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.2.6 USB OTG Interface DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.2.7 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.2.8 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.2.9 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3.2 Power-Up and Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.3.3 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.3.4 Phase Locked Loop (PLL) Characteristics . . . . . . . . . . . . . . . . . . . . . . 73
3.3.5 Internal Clock Source Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 74
1 Summary of Features
The XMC4500 devices are members of the XMC4000 Family of microcontrollers based
on the ARM Cortex-M4 processor core. The XMC4000 is a family of high performance
and energy efficient microcontrollers optimized for Industrial Connectivity, Industrial
Control, Power Conversion, Sense & Control.
CPU RTC
USB WDT
GPDMA0 GPDMA1 Ethernet
OTG
System DCode ICode FCE
Bus Matrix
Data Code
PMU PSRAM DSRAM1 DSRAM2 EBU
ROM & Flash
ERU1 VADC POSIF0 CCU40 CCU41 CCU42 SDMMC USIC2 USIC1 CAN
CPU Subsystem
CPU Core
High Performance 32-bit ARM Cortex-M4 CPU
16-bit and 32-bit Thumb2 instruction set
DSP/MAC instructions
System timer (SysTick) for Operating System support
Floating Point Unit
Memory Protection Unit
Nested Vectored Interrupt Controller
Two General Purpose DMA with up-to 12 channels
Event Request Unit (ERU) for programmable processing of external and internal
service requests
On-Chip Memories
16 KB on-chip boot ROM
64 KB on-chip high-speed program memory
64 KB on-chip high speed data memory
32 KB on-chip high-speed communication
1024 KB on-chip Flash Memory with 4 KB instruction cache
Communication Peripherals
Ethernet MAC module capable of 10/100 Mbit/s transfer rates
Universal Serial Bus, USB 2.0 host, Full-Speed OTG, with integrated PHY
Controller Area Network interface (MultiCAN), Full-CAN/Basic-CAN with 3 nodes, 64
message objects (MO), data rate up to 1MBit/s
Six Universal Serial Interface Channels (USIC),providing 6 serial channels, usable as
UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces
LED and Touch-Sense Controller (LEDTS) for Human-Machine interface
SD and Multi-Media Card interface (SDMMC) for data storage memory cards
External Bus Interface Unit (EBU) enabling communication with external memories
and off-chip peripherals
Input/Output Lines
Programmable port driver control module (PORTS)
Individual bit addressability
Tri-stated in input mode
Push/pull or open drain output mode
Boundary scan test support over JTAG interface
VBAT (1)
V DDC
V DDP
P 0.11
P 0.12
P 0.13
P 0.14
P 0.15
P 3.14
P 3.15
P 0.2
P 0.3
P 0.4
P 0.5
P 0.6
P 3.3
P 3.4
P 3.5
P 3.6
P 0.7
P 0.8
P 4.0
P 4.1
P 4.2
P 4.3
P 4.4
P 4.5
P 4.6
P 4.7
P 1.6
P 1.7
P 1.8
P 1.9
P 1.0
P 1.1
P 1.2
P 1.3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
P0. 1 1 108 P1. 4
P0. 0 2 107 P1. 5
P0. 10 3 106 P1. 10
P0. 9 4 105 P1. 11
P3. 2 5 104 P1. 12
P3. 1 6 103 P1. 13
P3. 0 7 102 P1. 14
P3. 13 8 101 P6. 0
P3. 12 9 100 P6. 1
P3. 11 10 99 P6. 2
P3. 10 11 98 P6. 3
P3. 9 12 97 P6. 4
P3. 8 13 96 P6. 5
P3. 7 14 95 P6. 6
US B_DM 15 94 P1. 15
US B_DP 16 93 TCK
V B US 17 92 TMS
V DDP 18 XMC4500 91 P ORS T
V DDC 19 90 V DDC
HIB _IO _1 20 (Top View) 89 VSSO
HIB _IO _0 21 88 X TA L2
RTC_X TA L1 22 87 X TA L1
RTC_X TA L2 23 86 V DDP
VBAT 24 85 VSS
P15. 7 25 84 P5. 0
P15. 6 26 83 P5. 1
P15. 5 27 82 P5. 2
P15. 4 28 81 P5. 3
P15. 3 29 80 P5. 4
P15. 2 30 79 P5. 5
P14. 15 31 78 P5. 6
P14. 14 32 77 P5. 7
P14. 13 33 76 P2. 6
P14. 12 34 75 P2. 7
P14. 7 35 74 P2. 0
P14. 6 36 73 P2. 1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
V A GND
V DDC
V SS A
VDDA
VDDP
VA REF
P 14.5
P 14.4
P 14.3
P 14.2
P 14.1
P 14.0
P 15.15
P 15.14
P 15.13
P 15.12
P 14.9
P 14.8
P 15.9
P 15.8
P 5.11
P 5.10
P 5.9
P 5.8
P 2.15
P 2.14
P 2.13
P 2.12
P 2.11
P 2.10
P 2.9
P 2.8
P 2.5
P 2.4
P 2.3
P 2.2
1 2 3 4 5 6 7 8 9 10 11 12
A VSS V DDC P 0.2 P 0.3 P 0.5 P 0.6 P 3.6 P 0.8 P 4.1 P 1.8 V DDP VSS A
B V DDP P 3.1 P 3.2 P 0. 10 P 0.4 P 3.5 P 0.7 P 4.0 P 1.6 P 1.7 P 1.9 V DDC B
US B_D
D P 3. 12 P 3. 11 P 0.9 P 0. 12 P 3. 14 P 3. 15 P 4.5 P 1.0 P 1.5 P 1. 11 P 1. 10 D
M
US B_D
E V B US P 3.8 P 3.7 P 0. 11 P 0. 14 P 3.4 P 4.2 P 1.1 P 1. 14 P 1. 12 P 1. 13 E
P
G V B A T P 15. 3 P 15. 5 P 15. 4 P 15. 6 P 15. 7 TMS TCK P 6.3 P 6.0 P ORS T P 1. 15 G
J P 14.12 P 14. 7 P 14. 6 P 14. 3 P 5. 11 P 2. 15 P 5.7 P 5.5 P 2.6 P 5.3 P 2.0 VSSO J
K P 14. 4 P 14. 5 P 14. 2 P 15.15 P 15.12 P 5.9 P 2. 14 P 5.6 P 2.7 P 5.4 P 2.2 P 2.1 K
L V DDA P 14. 1 P 14. 0 P 15.14 P 14. 9 P 15. 9 P 2. 12 P 2. 10 P 2.8 P 2.4 P 2.3 V DDP L
1 2 3 4 5 6 7 8 9 10 11 12
V DDC
V DDP
P 0.11
P 0.12
P 0.2
P 0.3
P 0.4
P 0.5
P 0.6
P 3.3
P 3.4
P 3.5
P 3.6
P 0.7
P 0.8
P 4.0
P 4.1
P 1.6
P 1.7
P 1.8
P 1.9
P 1.0
P 1.1
P 1.2
P 1.3
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P0. 1 1 75 P1. 4
P0. 0 2 74 P1. 5
P0. 10 3 73 P1. 10
P0. 9 4 72 P1. 11
P3. 2 5 71 P1. 12
P3. 1 6 70 P1. 13
P3. 0 7 69 P1. 14
US B_DM 8 68 P1. 15
US B_DP 9 67 TCK
V B US 10 66 TMS
V DDP 11 65 P ORS T
V DDC 12 64 V DDC
HIB _IO _1 13 XMC4500 63 VSSO
HIB _IO _0 14 62 X TA L2
RTC_X TA L1 15 (Top View) 61 X TA L1
RTC_X TA L2 16 60 V DDP
VBAT 17 59 VSS
P15. 3 18 58 P5. 0
P15. 2 19 57 P5. 1
P14. 15 20 56 P5. 2
P14. 14 21 55 P5. 7
P14. 13 22 54 P2. 6
P14. 12 23 53 P2. 7
P14. 7 24 52 P2. 0
P14. 6 25 51 P2. 1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
V A GND
V DDC
V SS A
VDDA
VDDP
VA REF
P 14.5
P 14.4
P 14.3
P 14.2
P 14.1
P 14.0
P 14.9
P 14.8
P 15.9
P 15.8
P 2.15
P 2.14
P 2.10
P 2.9
P 2.8
P 2.5
P 2.4
P 2.3
P 2.2
The table is sorted by the Function column, starting with the regular Port pins (Px.y),
followed by the dedicated pins (i.e. PORST) and supply pins.
The following columns, titled with the supported package variants, lists the package pin
number to which the respective function is mapped in that package.
The Pad Type indicates the employed pad type (A1, A1+, A2, special=special pad,
In=input pad, AN/DIG_IN=analog and digital input, Power=power supply). Details about
the pad properties are defined in the Electrical Parameters.
In the Notes, special information to the respective pin/function is given, i.e. deviations
from the default configuration after reset. Per default the regular Port pins are configured
as direct input with no internal pull device active.
Pn.y
PAD VDDP
Input 0
MODA.INA ...
Input n
MODA HWI0
HWI1 Pn.y
MODB
SW
ALT1
MODB.OUT ...
ALTn
HWO0
GND
HWO1
ALT1 ALT2 ALT3 ALT4 HWO0 HWO1 HWI0 HWI1 Input Input Input Input Input Input Input Input
P0.0 CAN. CCU80. LEDTS0. U1C1. ETH0. ERU0. ETH0.
N0_TXD OUT21 COL2 DX0D CLK_RMIIB 0B0 CLKRXB
P0.5 ETH0. U1C0. CCU80. U1C0. EBU. U1C0. EBU. U1C0. ERU1.
TXD0 DOUT0 OUT00 DOUT0 AD3 HWIN0 D3 DX0B 3A0
P0.7 WWDT. U0C0. EBU. DB. EBU. U0C0. DSD. ERU0. CCU80. CCU80. CCU80. CCU80.
28
SERVICE_OUT SELO0 AD6 TDI D6 DX2B DIN1A 2B1 IN0A IN1A IN2A IN3A
P0.8 SCU. U0C0. EBU. DB. EBU. U0C0. DSD. ERU0. CCU80.
EXTCLK SCLKOUT AD7 TRST D7 DX1B DIN0A 2A1 IN1B
Subject to Agreement on the Use of Product Information
P0.9 U1C1. CCU80. LEDTS0. ETH0. EBU. ETH0. U1C1. USB. ERU0.
SELO0 OUT12 COL0 MDO CS1 MDIA DX2A ID 1B0
XMC4000 Family
P0.15 U1C0. CCU40. U1C1. U1C1. CCU42.
SELO2 OUT0 DOUT2 HWIN2 IN2C
P1.1 DSD. U0C0. CCU40. ERU1. SDMMC. U0C0. POSIF0. ERU0. CCU40.
V1.4, 2016-01
XMC4500
P1.2 CCU40. ERU1. U0C0. EBU. U0C0. EBU. POSIF0. ERU1. CCU40.
OUT1 PDOUT1 DOUT3 AD14 HWIN3 D14 IN1A 2B0 IN1A
P1.3 U0C0. CCU40. ERU1. U0C0. EBU. U0C0. EBU. POSIF0. ERU1. CCU40.
MCLKOUT OUT0 PDOUT0 DOUT2 AD15 HWIN2 D15 IN0A 2A0 IN0A
P1.4 WWDT. CAN. CCU80. CCU81. U0C0. U0C0. U0C0. CAN. ERU0. CCU41.
SERVICE_OUT N0_TXD OUT33 OUT20 DOUT1 HWIN1 DX0B N1_RXDD 2B0 IN0C
Table 11 Port I/O Functions (contd)
Data Sheet
ALT1 ALT2 ALT3 ALT4 HWO0 HWO1 HWI0 HWI1 Input Input Input Input Input Input Input Input
P1.5 CAN. U0C0. CCU80. CCU81. U0C0. U0C0. U0C0. CAN. ERU0. ERU1. CCU41. DSD.
N1_TXD DOUT0 OUT23 OUT10 DOUT0 HWIN0 DX0A N0_RXDA 2A0 0A0 IN1C DIN2B
P2.0 CCU81. DSD. LEDTS0. ETH0. EBU. ETH0. EBU. ERU0. CCU40.
OUT21 CGPWMN COL1 MDO AD20 MDIB D20 0B3 IN1C
Subject to Agreement on the Use of Product Information
P2.1 CCU81. DSD. LEDTS0. DB.TDO/ EBU. EBU. ETH0. ERU1. CCU40. ETH0.
OUT11 CGPWMP COL0 TRACESWO AD21 D21 CLK_RMIIA 0B0 IN0C CLKRXA
P2.2 VADC. CCU81. CCU41. LEDTS0. LEDTS0. EBU. LEDTS0. EBU. ETH0. U0C1. ERU0. CCU41.
EMUX00 OUT01 OUT3 LINE0 EXTENDED0 AD22 TSIN0A D22 RXD0A DX0A 1B2 IN3A
P2.3 VADC. U0C1. CCU41. LEDTS0. LEDTS0. EBU. LEDTS0. EBU. ETH0. U0C1. ERU0. POSIF1. CCU41.
EMUX01 SELO0 OUT2 LINE1 EXTENDED1 AD23 TSIN1A D23 RXD1A DX2A 1A2 IN2A IN2A
P2.4 VADC. U0C1. CCU41. LEDTS0. LEDTS0. EBU. LEDTS0. EBU. ETH0. U0C1. ERU0. POSIF1. CCU41.
EMUX02 SCLKOUT OUT1 LINE2 EXTENDED2 AD24 TSIN2A D24 RXERA DX1A 0B2 IN1A IN1A
P2.5 ETH0. U0C1. CCU41. LEDTS0. LEDTS0. EBU. LEDTS0. EBU. ETH0. U0C1. ERU0. POSIF1. CCU41. ETH0.
TX_EN DOUT0 OUT0 LINE3 EXTENDED3 AD25 TSIN3A D25 RXDVA DX0B 0A2 IN0A IN0A CRS_DVA
P2.6 U2C0. CCU80. LEDTS0. U2C0. U2C0. DSD. CAN. ERU0. CCU40.
SELO4 OUT13 COL3 DOUT3 HWIN3 DIN1B N1_RXDA 1B3 IN3C
XMC4000 Family
P2.7 ETH0. CAN. CCU80. LEDTS0. DSD. ERU1. CCU40.
MDC N1_TXD OUT03 COL2 DIN0B 1B0 IN2C
P2.8 ETH0. CCU80. LEDTS0. LEDTS0. EBU. LEDTS0. EBU. DAC. CCU40. CCU40. CCU40. CCU40.
TXD0 OUT32 LINE4 EXTENDED4 AD26 TSIN4A D26 TRIGGER5 IN0B IN1B IN2B IN3B
V1.4, 2016-01
P2.9 ETH0. CCU80. LEDTS0. LEDTS0. EBU. LEDTS0. EBU. DAC. CCU41. CCU41. CCU41. CCU41.
TXD1 OUT22 LINE5 EXTENDED5 AD27 TSIN5A D27 TRIGGER4 IN0B IN1B IN2B IN3B
XMC4500
P2.10 VADC. DB. EBU. EBU.
EMUX10 ETM_TRACEDA AD28 D28
TA3
ALT1 ALT2 ALT3 ALT4 HWO0 HWO1 HWI0 HWI1 Input Input Input Input Input Input Input Input
P2.12 ETH0. CCU81. ETH0. DB. EBU. EBU. CCU43.
TXD2 OUT33 TXD0 ETM_TRACEDA AD30 D30 IN3C
TA1
P2.14 VADC. U1C0. CCU80. DB. EBU. U1C0. CCU43. CCU43. CCU43. CCU43.
EMUX11 DOUT0 OUT21 ETM_TRACECLK BC0 DX0D IN0B IN1B IN2B IN3B
P2.15 VADC. CCU80. LEDTS0. LEDTS0. EBU. LEDTS0. ETH0. U1C0. CCU42. CCU42. CCU42. CCU42.
EMUX12 OUT11 LINE6 EXTENDED6 BC1 TSIN6A COLA DX0C IN0B IN1B IN2B IN3B
P3.4 U2C1. U1C1. CCU42. DSD. SDMMC. EBU. U2C1. DSD. CCU42. CCU80.
MCLKOUT SELO2 OUT2 MCLK3 BUS_POWER HOLD DX0B MCLK3B IN2A IN0B
P3.5 U2C1. U1C1. CCU42. U0C1. SDMMC. EBU. SDMMC. EBU. U2C1. ERU0. CCU42.
DOUT0 SELO3 OUT1 DOUT0 CMD_OUT AD4 CMD_IN D4 DX0A 3B1 IN1A
30
P3.6 U2C1. U1C1. CCU42. U0C1. SDMMC. EBU. SDMMC. EBU. U2C1. ERU0. CCU42.
SCLKOUT SELO4 OUT0 SCLKOUT CLK_OUT AD5 CLK_IN D5 DX1B 3A1 IN0A
Subject to Agreement on the Use of Product Information
P3.13 U2C1. U0C1. CCU42. LEDTS0. U0C1. U0C1. U0C1. CCU80. CCU81.
XMC4000 Family
SCLKOUT DOUT0 OUT1 LINE6 DOUT0 HWIN0 DX0D IN3C IN1C
XMC4500
P4.0 DSD. SDMMC. EBU. SDMMC. EBU. U1C1. DSD. U0C1. U2C1.
MCLK1 DATA0_OUT AD8 DATA0_IN D8 DX1C MCLK1B DX0E DX0C
P4.1 U2C1. DSD. U0C1. SDMMC. EBU. SDMMC. EBU. U2C1. DSD. U2C1.
SELO0 MCLK0 SELO0 DATA3_OUT AD9 DATA3_IN D9 DX2B MCLK0B DX2A
ALT1 ALT2 ALT3 ALT4 HWO0 HWO1 HWI0 HWI1 Input Input Input Input Input Input Input Input
P4.3 U2C1. U0C0. CCU43. CCU43.
SELO2 SELO5 OUT3 IN3A
P5.0 U2C0. DSD. CCU81. U2C0. U2C0. U2C0. ETH0. U0C0. CCU81. CCU81. CCU81. CCU81.
DOUT0 CGPWMN OUT33 DOUT0 HWIN0 DX0B RXD0D DX0D IN0A IN1A IN2A IN3A
XMC4000 Family
P6.1 ETH0. U0C1. CCU81. DB. EBU. U0C1.
TXD3 SELO0 OUT30 ETM_TRACEDA A17 DX2C
TA3
TA2
XMC4500
P6.3 CCU43. U0C1. ETH0.
OUT2 DX0C RXD3B
ALT1 ALT2 ALT3 ALT4 HWO0 HWO1 HWI0 HWI1 Input Input Input Input Input Input Input Input
P6.6 DSD. DB. EBU. DSD. ETH0.
MCLK3 ETM_TRACEDA BC3 MCLK3A CLK_TXB
TA0
P14.0 VADC.
G0CH0
P14.1 VADC.
G0CH1
P14.12 VADC.
Subject to Agreement on the Use of Product Information
G1CH4
P14.13 VADC.
G1CH5
P15.2 VADC.
G2CH2
P15.3 VADC.
G2CH3
P15.4 VADC.
G2CH4
XMC4000 Family
P15.5 VADC.
G2CH5
P15.6 VADC.
G2CH6
V1.4, 2016-01
P15.7 VADC.
XMC4500
G2CH7
ALT1 ALT2 ALT3 ALT4 HWO0 HWO1 HWI0 HWI1 Input Input Input Input Input Input Input Input
P15.12 VADC.
G3CH4
P15.13 VADC.
G3CH5
P15.14 VADC.
G3CH6
P15.15 VADC.
G3CH7
USB_DP
USB_DM
TCK DB.TCK/
SWCLK
TMS DB.TMS/
SWDIO
PORST
XTAL2
Subject to Agreement on the Use of Product Information
RTC_XTAL1 ERU0.
1B1
RTC_XTAL2
XMC4000 Family
V1.4, 2016-01
XMC4500
XMC4500
XMC4000 Family
XMC4000
VBAT
Hibernate domain
Hibernate
2.1...3.6 V RTC
control
32 kHz Retention
Clock Memory
GND
M x VDDC
Core Domain
100 nF x M
Dig.
CPU
Peripherals
10 F x 1 GPIOs
RAMs
Level
shift.
GND
3.3V
EVR FLASH
N x VDDP
100 nF x N
VSS
10 F x 1 PAD Domain
Exp. Die Pad
VSS
GND Analog Domain
Reference
ADC DAC
VAREF
100 nF VAGND Out-of-range comparator
AGND 3.3V
VDDA
100 nF VSSA
GND
The XMC4500 has a common ground concept, all VSS, VSSA and VSSO pins share the
same ground potential. In packages with an exposed die pad it must be connected to the
common ground as well.
VAGND is the low potential to the analog reference VAREF. Depending on the application it
can share the common ground or have a different potential.
When VDDP is supplied, VBAT must be supplied as well. If no other supply source (e.g.
battery) is connected to VBAT, the VBAT pin can also be connected directly to VDDP.
3 Electrical Parameters
Figure 10 explains the input voltage ranges of VIN and VAIN and its dependency to the
supply level of VDDP.The input voltage must not exceed 4.3 V, and it must not be more
than 1.0 V above VDDP. For the range up to VDDP + 1.0 V also see the definition of the
overload conditions in Section 3.1.3.
V V
VDDP
A
B
V SS VSS
-1.0 -1.0
Figure 11 shows the path of the input currents during overload via the ESD protection
structures. The diodes against VDDP and ground are a simplified representation of these
ESD protection structures.
VDDP VDDP
Pn.y IOVx
GND
GND
ESD Pad
VDDP
E F
e
D oltag
igh V
C ut H
Outp
B
VOH
A
VOL
ge
w Volta
ut Lo
Outp
VSS
t
A Strong sharp drive strength D Strong slow drive strength
B Strong medium drive strength E Medium drive strength
C Strong soft drive strength F Weak drive strength
A B C E F Class A2 Pads
C D E F Class A1+ Pads
E F Class A1 Pads
3.2 DC Parameters
The digital input stage of the shared analog/digital input pins is identical to the input
stage of the standard digital input/output pins.
The Pull-up on the PORST pin is identical to the Pull-up on the standard digital
input/output pins.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
VDDP
VDDP
0.6 x VDDP
IN B IPUH 10 A Invalid digital input
0.36 x VDDP
IPUH A IPUH 100 A
A Valid Low
XMC4000
VSS
Pull-up active
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
VDDA + 0.05
Precise conversion range (12 bit)
VDDA
Valid V AREF
Conversion error
increases by 5/4
VAGND + 1
Minimum VAREF - VAGND is 1 V
VAGND
VSSA
t
VAREFx RAREF, On
Analog_InpRefDiag
IOZ1
200 nA
100 nA
V IN [% VD D A]
-100 nA
3% 97% 100%
-500 nA
ADC-Leakage.vsd
Conversion Time
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Conversion Calculation
Unsigned:
DACxDATA = 4095 (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN)
Signed:
DACxDATA = 4095 (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN) - 2048
DAC output
VOUT_MAX
64 LSBs 64 LSBs
DAC output
20 LSBs
VOUT_MAX
tSETTLE
tSETTLE
20 LSBs
VOUT_MIN
1) Always the standard VADC reference, alternate references do not apply to the ORC.
VOHYS
VODC
VAREF
GxORCy
VSS
GxORCOUTy
tODD tORD
VAIN (V)
VAREF + 400 mV
tOPDN < T < tOPDD T > tOPDD
T < tOPDN
VAREF + 200 mV
T > tOPDN
VAREF + 100 mV
VAREF
Never Overvoltage Never Overvoltage Always detected Never Overvoltage Always detected
detected may be detected may be Overvoltage Pulse detected may be Overvoltage Pulse
Overvoltage detected Overvoltage detected Overvoltage detected
Pulse (level uncertain) Pulse Pulse
(Too low) (Too short) (Too short)
The Die Temperature Sensor (DTS) measures the junction temperature TJ.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bit field of the DTSSTAT register.
Temperature TDTS = (RESULT - 605) / 2.05 [C]
This formula and the values defined in Table 27 apply with the following calibration
values:
DTSCON.BGTRIM = 8H
DTSCON.REFTRIM = 4H
XTAL1
f OSC
GND XTAL2
Damping resistor
may be needed for
some crystals
VPPX_min
VPPX
External Clock
Source
Direct Input Mode XTAL1
V
VIHBX_max
ltage e
h Vo oltag
t Hig tH igh V
Inpu Inpu
VIHBX_min
VILBX_max
g e
VSS Volta
t Low
Inpu
VILBX_min
t
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
3.3 AC Parameters
VD D P
90% 90%
10% 10%
VSS
tR tF
AC_Rise-Fall-Times.vsd
VD D P
VD D P / 2 Test Points VD D P / 2
VSS
AC_TestPoints.vsd
AC_HighImp.vsd
VDDP
VDDP XMC4000
RPORST
(optional)
PORST
PORESET
External
reset
Supply
trigger Monitoring
IPPD
GND GND
threshold
Core supply voltage reset VPV CC 1.17 V
threshold
VDDP voltage to ensure VDDPPA 1.0 V
defined pad states CC
PORST rise time tPR SR 2 s 4)
Startup time from power-on tSSW CC 2.5 3.5 ms Time to the first
reset with code execution user code
from Flash instruction
VDDC ramp up time tVCR CC 550 s Ramp up after
power-on or
after a reset
triggered by a
violation of
VPOR or VPV
1) Minimum threshold for reset assertion.
3.3 V
VPOR
VD D P
VD D PPA
1.3 V
VDDC VPV
tVCR
PORST
tPR t SSW
Pads as programmed
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
t1
t2 t3 t4 t5
JTAG_TCK .vsd
TCK
t6 t7
TMS
t6 t7
TDI
t9 t8 t10
TDO
t18
JTAG_IO.vsd
tSC
t1 t2
SWDCLK
t6
SWDIO
(Output)
t5
t3 t4
SWDIO
(Input)
t1
TRACECLK
t2 t5 t3 t4
TRACECLK
t6 t6
TRACEDATA
t1 t2 t3
MCLK
t5 t4
DIN
t1 t2
Select Output Inactive Active Inactive
SELOx
t3 t3
Data Output
DOUT[3:0]
t4 t4
t5 t5
Data Input Data Data
DX0/DX[5:3] valid valid
t1 0 t1 1
Select Input Inactive Active Inactive
DX2
t1 2 t1 2
t1 3 t13
Data Input Data Data
DX0/DX[5:3] valid valid
t14 t1 4
Data Output
DOUT[3:0]
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched .
Drawn for BRGH .SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal.
USIC_SSC_TMGX.VSD
t1 t2 t4
70%
SDA 30%
t1 t3 t2 t6
SCL
th
9
t7 t5 clock
S t10
SDA
t8 t7 t9
SCL
th
9
Sr P S
clock
t1
t2
t5
t3
SCK
t4
WA/
DOUT
t6
t7
t8
SCK
t9 t10
WA/
DIN
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating Conditions apply, total external capacitive load CL = 40 pF.
t pp (Clock Cycle)
SD Clock at Driving
Host Pin Edge
tCLK_DELAY
SD Clock at Sampling
Card Pin Edge
Output Valid Time: t ODLY_H
tWL
Output Hold Time: tOH_H
Output at
Host Pins
Output at
Card Pins
tDATA _DELAY
+ tTAP_DELAY t IH
t ISU
No clock delay:
(1)
t ODLY_F + t DATA_DELAY + t TAP_DELAY + t ISU < t WL
(3)
t DATA_DELAY + t TAP_DELAY + t WL < t PP + t CLK_DELAY t ISU t ODLY_F
The data can be delayed versus clock up to 5 ns in ideal case of tWL= 20 ns.
The clock can be delayed versus data up to 18.2 ns (external delay line) in ideal case of
tWL= 20 ns, with maximum tTAP_DELAY = 3.2 ns programmed.
SD Clock at Sampling
Host Pin Edge
tCLK_DELAY
SD Clock at Driving
Card Pin Edge
Output at
Host Pins
Output at
Card Pins
tISU_H tIH_H
The data + clock delay must be greater than 2 ns if tTAP_DELAY is not used.
If the tTAP_DELAY is programmed to at least 2 ns, the data + clock delay must be greater
than 0 ns (or less). This is always fulfilled.
SD Clock at Driving
Host Pin Edge
t CLK_DELAY
SD Clock at Sampling
Card Pin Edge
Output Valid Time: t ODLY_H
tWL
Output Hold Time: tOH_H
Output at
Host Pins
Output at
Card Pins
tDATA _DELAY
+ tTAP_DELAY tIH
tISU
No clock delay:
(7)
t ODLY_H + t DATA_DELAY + t TAP_DELAY + t ISU < t WL
(9)
t DATA_DELAY + t TAP_DELAY t CLK_DELAY < t WL t ISU t ODLY_H
The data delay is less than the clock delay by at least 10 ns in the ideal case where tWL=
10 ns.
The clock can be delayed versus data up to 13.2 ns (external delay line) in ideal case of
tWL= 10 ns, with maximum tTAP_DELAY = 3.2 ns programmed.
SD Clock at Sampling
Host Pin Edge
t CLK_DELAY
SD Clock at Driving
Card Pin Edge
Output at
Host Pins
Output at
Card Pins
t ISU_H tIH_H
The data + clock delay must be greater than -0.5 ns for a 20 ns clock cycle. This is always
fulfilled.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating Conditions apply, with Class A2 pins and CL = 16 pF.
Note: For each timing, the accumulated PLL jitter must be added separately.
Read Timing
pv + ta
pv + t3
ADV
pv + ta
RD
pv + t9
RD/WR
pv + ta
pv + ta t4
BC[3:0]
pv + t5 t6
WAIT
pv + t14 t7
pv + t13 t8
2)
AD[31:0] Address Out Data In
1)
For 16-bit MUX and Twin 16-bit MUX only
2)
* 16-bit MUX: - Address A[15:0], Data D[15:0] on pins AD[15:0] only
* Twin 16-Bit MUX: - Address A[15:0] on pins AD[15:0] and AD[31:16] in parallel
- Data D[31:0] on pins AD[31:0]
* 32-bit MUX: - Address A[24:0] on pins AD[24:0]
- Data D[31:0] on pins AD[31:0]
pv = programmed value,
TEBU_CLK * sum (corresponding bitfield values) EBU_MuxRD_Async.vsd
pv + ta pv + t3
ADV
pv + ta
RD
pv + t9
RD/WR
pv + ta
pv + ta t4
BC[3:0]
pv + t5 t6
WAIT
t7 t8
D[15:0]2) Data In
1)
Address A[max:16] on pins A[max:16], Address A[15:0] on pins AD[31:16]
2)
Data D[15:0] on pins AD[15:0]
pv = programmed value,
TEBU_CLK * sum (corresponding bitfield values) EBU_DeMuxRD_Async.vsd
Write Timing
EBU Address Address Hold Command Data Hold Recovery New Addr.
STATE Phase Phase (opt.) Phase Phase Phase (opt.) Phase
Duration Limits in 1...15 0...15 1...31 0...15 0...15 1...15
EBU_CLK Cycles
ADV
pv + t39
RD
pv + ta
RD/WR
t34
pv + ta
pv + ta
BC[3:0]
t35 t36
WAIT
pv + t14 pv + t37
pv + t13 pv + t38
AD[31:0]2) Address Out Data Out
1)
For 16-bit MUX and Twin 16-bit MUX only
2)
* 16-bit MUX: - Address A[15:0], Data D[15:0] on pins AD[15:0] only
* Twin 16-Bit MUX: - Address A[15:0] on pins AD[15:0] and AD[31:16] in parallel
- Data D[31:0] on pins AD[31:0]
* 32-bit MUX: - Address A[24:0] on pins AD[24:0]
- Data D[31:0] on pins AD[31:0]
pv = programmed value,
TEBU_CLK * sum (corresponding bitfield values) EBU_MuxWR_Async.vsd
EBU Address Address Hold Command Data Hold Recovery New Addr.
STATE Phase Phase (opt.) Phase Phase Phase (opt.) Phase
Duration Limits in 1...15 0...15 1...31 0...15 0...15 1...15
EBU_CLK Cycles
pv + ta pv + t33
ADV
pv + t39
RD
pv + ta
RD/WR
t34
pv + ta
pv + ta
BC[3:0]
t35 t36
WAIT
pv + t37 pv + t38
2)
D[15:0] Data Out
1)
Address A[max:16] on pins A[max:16], Address A[15:0] on pins AD[31:16]
2)
Data D[15:0] on pins AD[15:0]
pv = programmed value,
TEBU_CLK * sum (corresponding bitfield values) EBU_DeMuxWR_Async.vsd
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating Conditions apply, with Class A2 pins and CL = 16 pF.
BFCLKI
BFCLKO1)
t10 t10
A[max :0] Burst Start Address Next
Addr.
t22 t2 2 t22
ADV
t1 2 t12
RD
RD/WR
t2 2 a t2 2a
BAA
t2 4 t2 4
t23 t23
D[31:0]
(32-Bit) Data (Addr+0) Data (Addr+4)
1) Output delays are always referenced to BCLKO . The reference clock for input
characteristics depends on bit EBU _BFCON.FDBKEN.
EBU_BFCON.FDBKEN = 0: BFCLKO is the input reference clock .
EBU_BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBU clock
feedback enabled ). EBU_BurstRDWR.vsd
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating Conditions apply.
BFCLKO
t1 t1
HLDA Output
t1 t1
BREQ Output
BFCLKO
t3 t3
t2 t2
HOLD Input
HLDA Input
EBU_Arb .vsd
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating Conditions apply, with Class A2 pins and CL = 16 pF.
t1
0.9 VD D P
SDCLKO 0.5 VD D P
0.1 VD D P
t2 t3 t5 t4
EBU_SDCLKO.vsd
SDCLKO
t6 t7
1)
A[15:0] Row Column
t9
CS[3:0]
CSCOMB
RAS
t1 2 t1 3
CAS
RD/WR
t1 6 t1 7
BC[1:0]
t2 0 t21
2)
D[15:0] Data (0) Data (n- 1)
1)
Address A[15:0] on pins AD[31:16]
2)
Data D[15:0] on pins AD[15:0]
EBU_SDRAM-RD.vsd
SDCLKO
t6 t7
1)
A[15:0] Row Column
t8 t9
CS[3:0]
CSCOMB
t1 0 t1 1
RAS
t1 2 t1 3
CAS
t1 4 t1 5
RD/WR
t1 6 t1 7
BC[1:0]
t1 8 t19
2) Data Data
D[15:0] (0) (n-1 )
1)
Address A[15:0] on pins AD[31:16]
2)
Data D[15:0] on pins AD[15:0]
EBU_SDRAM-WR.vsd
Rise time tR CC 4 20 ns CL = 50 pF
Fall time tF CC 4 20 ns CL = 50 pF
Rise/Fall time matching tR/tF CC 90 111.11 % CL = 50 pF
Crossover voltage VCRS CC 1.3 2.0 V CL = 50 pF
D+
90% 90%
VC R S
10% 10%
D-
VSS
tR tF
USB_Rise-Fall-Times.vsd
2.0 V 2.0 V
ETH I/O
0.8 V 0.8 V
tR tF
ETH_Testpoints.vsd
t1
t3 t2
ETH_MDC
ETH_MDC
t4 t5
ETH_MDIO
(output) Valid Data
ETH_MDC
t6
ETH_MDIO
(input) Valid Data
ETH_Timing-Mgmt.vsd
t7
t9 t8
ETH_MII_RX_CLK
ETH_MII_TX_CLK
ETH_MII_RX_CLK
t1 0 t1 1
ETH_MII_RXD[3:0]
ETH_MII_RX_DV Valid Data
ETH_MII _RX_ER
(sourced by PHY )
ETH_MII_TX_CLK
t1 2
ETH_MII _TXD[3:0]
Valid Data
ETH_MII_TXEN
(sourced by STA )
ETH_Timing-MII.vsd
t1 3
t1 5 t14
ETH_RMII_REF_CL
ETH_RMII_REF_CL
t1 6 t17
ETH_RMII _RXD[1:0] Valid Data
ETH_RMII _CRS
(sourced by PHY )
ETH_RMII_REF_CL
t18
ETH_RMII _TXD[1:0] Valid Data Valid Data
ETH_RMII _TXEN
(sourced by STA ) ETH_Timing-RMII .vsd
Note: For electrical reasons, it is required to connect the exposed pad to the board
ground VSS, independent of EMC and thermal requirements.
power dissipation must be limited so that the average junction temperature does not
exceed 150 C.
The difference between junction temperature and ambient temperature is determined by
T = (PINT + PIOSTAT + PIODYN) RJA
The internal power consumption is defined as
PINT = VDDP IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = ((VDDP-VOH) IOH) + (VOL IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
Reduce VDDP, if possible in the system
Reduce the system frequency
Reduce the number of output pins
Reduce the load on active output drivers
STAND OFF
+0.073
7
1.6 MAX.
.03
1.4 0.05
0.10.05
35 x 0.5 = 17.5
0.127 -0
H
0...7
0.5 0.6 0.15
0.08 C 144x
C COPLANARITY
2) SEATING PLANE
0.2 +0.07
-0.03
0.08 M A-B D C 144x
22
0.2 A-B D C 144x Bottom View
1)
20
0.2 A-B D H 4x Ex 3)
D
A B
1)
Ay 3)
Ey 3)
20
22
144 144
1 1
Ax 3)
Index Marking Exposed Diepad Index Marking
1) Does not include plastic or metal protrusion of 0.25 max. per side
2) Does not include dambar protrusion
3) Refer table for exposed pad dimension PG-LQFP-144-22-PO V04
1.6 MAX.
1.4 0.05
0.10.05
0.15 +0.05
-0.06
24 x 0.5 = 12
H
0...7
0.5 0.6 0.15
C 0.08 C 100x
SEATING COPLANARITY
PLANE
0.22 0.05
0.08 M A-B D C 100x
16
1) 0.2 A-B D 100x Bottom View
14
0.2 A-B D H 4x Ex
D
A B
1)
Ey
16
14
100 100
1 1
Index Marking Exposed Diepad
1) Does not include plastic or metal protrusion of 0.25 max. per side
PG-LQFP-100-3, -4, -8, -11-PO V14
STAND OFF
0.127 +0.073
1.6 MAX.
-0.037
1.4 0.05
0.10.05
24 x 0.5 = 12
H
0...7
0.5 0.6 0.15
C 0.08 C 100x
SEATING COPLANARITY
2) PLANE
0.2 +0.07
-0.03
0.08 M C A-B D 100x
Bottom View
16
14 1) 0.2 C A-B D 100x Ex 3)
0.2 H A-B D 4x Ax 3)
D
Ay 3)
Ey 3)
A B
1)
16
14
100 100
1 1
Index Marking Exposed Diepad
1) Does not include plastic or metal protrusion of 0.25 max. per side
2) Does not include dambar protrusion of 0.08 max. per side
3) Refer table for exposed pad dimension details PG-LQFP-100-24, -25-PO V04
Figure 59 PG-LFBGA-144-10 (Plastic Green Low Profile Fine Pitch Ball Grid Array)
All dimensions in mm.
You can find complete information about Infineon packages, packing and marking in our
Infineon Internet Page Packages: http://www.infineon.com/packages