(EE

EE6205
6205)) VLSI Design

IC fabrication process &

Layout Design Techniques

By Dr. Yaseer A. Durrani

Dept. of Electronics Engineering
University of Engineering & Technology, Taxila

Outline
IC Manufacturing Sequence
Overview of Silicon Process
Photolithography Process
Die Assembly & Testing
Layout Design Methodology
Design Rules
Stick Diagram
Layout Example

2
Wafer Manufacturing from Sand to Si

Si Starting material
Silicon prepared by the reaction of high-purity silica with wood,
charcoal, & coal, in electric arc furnace using carbon electrodes
at more than 1900 , carbon reduces silica to silicon
SiO2 + C Si + CO2
SiO2 + 2C Si + 2CO (~1800C)
Form of metallurgical grade Si (MGS)
Si has impurities like Al, Fe & heavy metal at 100s to 1000s parts/million
MGS is further refined with electronic-grade Si (EGS): Levels of impurities are
reduced to parts pet billion or ppb 5x1013 cm-3
Si +3HCl SiHCl3 + H2
2SiHCl3+2H2 2Si+6HCl

4
Growth of Single-Crystal Ingots
Growth process of purifying silicon: It converts high purity but still polysilicon
EGS to single crystal Si ingots or boules
Heating to produce 95% ~ 98% pure polycrystalline Si
Czochralski (CZ) Growth: Main stream growth technology for large diameter
wafer
Float Zone (FZ) Growth: For small & medium diameter wafer less
contaminations than CZ method

Seed Crystal
A seed crystal is a small piece of single crystal/polycrystal material from which
a large crystal of same material typically is to be grown. The large crystal can
be grown by dipping the seed into a supersaturated solution, into molten
material that is then cooled, or by growth on the seed face by passing vapor of
the material to be grown over it

6
Czochralski Si Growth
To grow single-crystal material, it is necessary to have a seed which can provide
a template for growth
To melt EGS in a quartz-lined graphite crucible by resistively heating it to
melting point of Si (1412C)
Seed crystal is lowered into molten material and then is raised slowly, allowing
crystal to grows to provide a slight stirring of melt & to average out any
temperature variations that would cause in homogenous solidification of
compound semiconductors

Cylindrical Ingot
Cylindrical ingot of high purity monocrystalline semiconductor, such as Si or
Ge, is formed by pulling a seed crystal from a 'melt
Donor impurity atoms, such as boron or phosphorus in case of Si, can be
added to molten intrinsic material in precise amounts in order to dope the
crystal, thus changing it into n-type or p-type extrinsic semiconductor

8
Wafer
Si IC is created on larger circular sheets of Si called Wafers
Typically 100-300mm in diameter, Thickness 0.4-0.7mm
Large Si circuit is about 1-cm on a side so that many individual circuits can be
made on a single wafer
To construct Wafer thousands of steps in manufacturing processes
Not every wafer turns out to be functional

Diameter
Wafer
Die

Die
Die is a small piece of Si wafer upon which a given circuit is fabricated
Die cutting, or dicing, is the process of separating a wafer of multiple identical
integrated circuits into dies

Defective IC

10
IC Package
IC Package is a plastic, ceramic, laminate or metal seal that encloses the chip or
die inside. It can protect the chip from contamination or damage by foreign
material in environment
Packages are classified into two types:
Pin-through-hole packages: Pins are inserted into through-holes in board &
soldered in place from opposite side of board
Surface-mount technology: Packages have leads that are soldered directly
to metal leads on surface of circuit board
IC packaging process step:
Die attaching: Die is mounted and fixed to package or support structure
Bonding: Creating interconnections b/w die and outside world
Encapsulated: Die being encapsulated with ceramic, plastic, metal or epoxy
to prevent physical damage

11

IC Package
Two types of mounting devices to Printed Wiring Boards (PWB):
Through-hole (TH) mounting:
Dual-in-line packages (DIP)
Pin-grid-array (PGA)
(Available in hermetic plastic & ceramic) (pitches: 2.54, 1.78, 1.27mm)
Surface mounting (SM)
Up to 48 terminals:
Small outline (SO) (available in plastic only)
Small Outline Package (SOP)
Shrinked Small Outline Package (SSOP)
Quad types: Chip carriers (CC) & flatpacks (available in ceramic & plastic)
Above 48 terminals: Quad types only
Leaded Plastic (PLCC), Leaded Ceramic (LDCC), Leadless Ceramic (LLCC)
(pitches: 1.37 or 0.635 mm)

12
 IC Package

Wire-bonded package

13

IC Package

CAD template for positioning bonding pads

CAD template for checking the maximum

distance that wire spans over silicon. Here:
violation of the guidelines. The circle must be at
minimum tangent to the step-and-repeat
centerline (case of maximum distance) or cross it

CAD template for checking adherence to wire-span 14

IC Package
Interconnects in high-density IC chips are formed by multilevel networks
For 90 nm CMOS process, 7/8 levels of metals. Between any two adjacent
metal levels dedicated layer called Vertical Interconnect Access (VIA) that is
used to make the necessary connection between the two metals
Through-silicon via (TSV) is VIA passing completely through silicon wafer or die
TSVs pass through silicon substrate(s) b/w active layers and/or b/w an
active layer & external bond pad

15

IC Package
Good chips are
attached to a lead
frame package

Lead frame Gold wire

Bonding pad

Connecting pin
16
IC Package

17

IC Package

Dual in-line package (DIP) Quad flat package (QFP) Small outline (SQIC)

Small outline J-leaded (SOJ) Plastic leadless chip carrier (PLCC)

Pin grid array (PGA) Thin small outline package (TSOP)

Ball grid array (BGA)

18
IC Package

19

Multi-Chip Module
Multi-chip module (MCM) is a specialized electronic package where multiple ICs,
semiconductor dies or other discrete components are packaged onto unifying
substrate, facilitating their use as single component (as though larger IC)

MCM packaging is an important facet of modern electronic miniaturization &

micro-electronic systems. MCMs are classified according to the technology used
to create the HDI (High Density Interconnection) substrate
Laminated MCM (MCM-L): Substrate is a multi-layer laminated PCB
Deposited MCM (MCM-D): Modules are deposited on base substrate using
thin film technology
Ceramic substrate MCM (MCM-C): Such as LTCC

20
IC Processing Flow

Oxidation Diffusion
Layout Mask Etching

Ion
Implantation

Chemical Chips
Vapor Deposition Processed
wafer
Wafers
Fabrication

21

IC Processing Flow

Materials IC Fab

Chemical Dielectric Test

Metallization Mechanical deposition
Polishing
Wafers
Packaging
Thermal Implant PR Etch
Processes strip PR strip
Masks
Final Test

Photo-
lithography
IC Design

22
Front End/Back End Fabrication
Front-end processing refers to formation of transistors directly on silicon
Back-end processing is the creation of metal interconnecting wires, which are
isolated by insulating materials, to connect the transistor formations

Silicon Crystal Growth Front End Front End

Wet Cleaning
Photolithography Device interconnection
Ion Implantation Fabrication
Dry, Wet Plasma Etching
Thermal Treatments (Rapid Thermal Metallization
Annealing, Furnace Annealing, & Si Thermal
oxidation) Oxidation
Chemical Vapor Deposition
Inter-level
Physical Vapor Deposition Lithography
Molecular Beam Epitaxy
Dielectrics
Electrochemical Deposition Deposition
Etching
Metallization
Chemical Mechanical Planarization
Doping Gate Oxide
Wafer Testing
Formation
Wafer Back Grinding
Wafer Mounting
Gate Oxide
Die Cutting
Formation 23

IC Processing Flow
Electronic circuits are fabricated with sequence of multiple photographic &
chemical processing steps
Semiconductor fabrication processes are grouped into four general categories:
Deposition:
Deposition is any process that grows, coats, or transfers a material onto the
wafer. Available deposition technologies are:
Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD),
Electrochemical Deposition (ECD), Molecular Beam Epitaxy (MBE),
Atomic Layer Deposition (ALD)
Removal:
Removal processes are techniques for removing material from wafer either
in bulk or selectively
Primary removal methods are wet & dry etching, ChemicalMechanical
Planarization (CMP)

24
IC Processing Flow
Patterning: Series of processes that pattern or alter existing shape of deposited
materials is called lithography

Si-substrate Chemical or plasma

etch
(a) Silicon base material Hardened resist
Photoresist SiO
2
SiO
2 Si-substrate
Si-substrate
(d) After development and etching of resist,
(b) After oxidation and deposition chemical or plasma etch of SiO2
of negative photoresist Hardened resist
UV-light SiO
2
Patterned
optical mask Si-substrate

Exposed resist (e) After etching

SiO
2

Si-substrate Si-substrate

(c) Stepper exposure (f) Final result after removal of resist

25

IC Processing Flow
Normal Mask Phase Shift Mask

Constructive Phase shift

Interference coating Total Light
Intensity
Total Light
Intensity Destructive
Interference

PR PR
Substrate Substrate
Final Pattern Final Pattern

PR PR
Substrate Substrate
Designed Pattern Designed Pattern

26
IC Processing Flow
Modifying Electrical Properties:
Consists of doping a transistors source & drain in diffusion furnaces or by
implanting it with ions
Doping processes are followed by furnace annealing or Rapid Thermal
Annealing (RTA), which activates the implanted dopants
Modification of electrical properties includes the reduction of dielectric
materials via ultraviolet light

Rapid Thermal Annealing

27

IC Processing Flow
Oxidation: High-temperature exposure of Si to O2 to form SiO2

Etching: Removal of undesired material to create geometric patterns

Dry Etching

Wet Etching
Diffusion: Doping process to form n-type or p-type material by high-
temperature exposure to donor or acceptor impurities

28
IC Processing Flow
Ion implantation: High-energy bombardment of Si with donor or acceptor ions
from particle accelerators followed by an anealing step to activate implants and
repair any damage

Chemical Vapor Deposition: Materials such as metal or oxide are deposited out
of a gaseous mixture. Metals can also be deposited using

29

Lithography
Process through which we make (microfluidic) chips is called lithography
There are two types
Photolithography
Making a mold on a silicon wafer using UV light to etch a design
Soft lithography
Using mold to make a chip from polydimethyl siloxane (PDMS) polymer

Ion Implant
E-Beam or
Photo Etch

EDA Mask or Mask or

Photoresist
Reticle Reticle

30
Photolithography
Photolithography is the technique to create a pattern on each layer with
submicron features to material layer
Optically projected the shadow of pattern onto the surface chip, then employ
photolightographic-type techniques to transfer the pattern to surface

31

Photolithographic Process
Photolithography Steps:
Photoresist Optical
Oxidation Mask
Wafer priming
Spincoating
Prebaking
Exposure
Development
Post-Baking

Photoresist Photoresist Coating

Removal (ashing)
Stepper Exposure Photoresist
Typical operations in a single Development
Photolithographic Cycle

Acid Etch
Process Spin, Rinse, Dry
\Steps

32
Photolithography
Light
Source Light Reference
Source Mark

Projection
Lens

Alignment
Laser
Reticle
Reticle Stage Reticle

Projection Interferometer
Lens Projection
Laser
Lens

Wafer X Interferometer
Mirror Set
Wafer Stage

Wafer
Wafer Stage
33

Light Diffraction Without Lens

Short wavelength waves have less diffraction
Optical lens can collect diffracted light & enhance the image
Name Wavelength (nm) Application feature
m)
size (
Diffracted light Mask G-line 436 0.50
Mercury Lamp H-line 405
Intensity of I-line 365 0.35 to 0.25
projected light
XeF 351
XeCl 308
Excimer Laser KrF (DUV) 248 0.25 to 0.15
ArF 193 0.18 to 0.13
Strayed Fluorine Laser F2 157 0.13 to 0.1
refracted light D Mask

Lens ro Future Trends

Diffracted light
collected by lens
Less diffraction after
focused by lens
Ideal light
Intensity pattern
Even shorter wavelength
193 nm, 157 nm
Silicate glass absorbs UV light when <
180 nm
CaF2 optical system
Next generation lithography (NGL)
Extreme UV (EUV), Electron Beam, X-ray (?)
34
Applications of Photolithography
IC patterning, Printed electronic board, nameplate, printer plate e.g.

35

Photoresist
To transfer the reticle pattern to surface of Si region, we first coat wafer with
light-sensitive liquid plastic material called photoresist
To create small structures or features on silicon wafer, made out of
photoresist by etching with UV light
Two types of photoresist:
Positive: Exposure to UV light removes resist
Negative: Exposure to UV light maintains resist
Photoresist

Substrate

UV light
Mask/reticle Mask Positive Negative
Resist Resist
Photoresist
Exposure Primer
Substrate
Negative
Photoresist
Photoresist
Substrate
After Polysilicon
Positive
Development STI USG
Photoresist

Substrate P-Well
Photoresist coating 36
Fabrication Equipment

Molecular Beam Epitaxy (MBE) Bake-out Ovens

Photoresist Spinner Mask Aligner 37

Fabrication Equipment

Reactive Ion Etching Perkin-Elmer MBE

(RIE)

Chemical Vapor Deposition (CVD) Plasma Sputter 38

Fabrication Equipment

Probe Station Scanning Electron Microscope (SEM)

39

IC Layouts

40
CMOS Layers

Metal 2
M1/M2 Via

Metal 1

Polysilicon

Diffusion
MOSFET (under polysilicon gate) 41

MOSFET Schematics

42
CMOS Schematics

Metal1: 1st level of interconnect

Metal2: 2nd level of interconnect
Metal3: 3rd level of interconnect
bonding pad
Metal4: 4th level of interconnect
Metal 2
nitride Metal5: 5th level of interconnect
Metal6: 6th level of interconnect
Metal7: 7th level of interconnect
p-well
Via1: Connect the metal1 & metal2
n-well
p-channel transistor n-channel transistor Via2: Connect the metal2 & metal3
p+ substrate
Via3: Connect the metal3 & metal4
Via4: Connect the metal4 & metal5
Via5: Connect the metal5 & metal6
Via6: Connect the metal6 & metal7

43

Cross-Sectional CMOS View

A
GND VDD
Y SiO2

n+diffusion

p+diffusion
n+ n+ p+ p+
polysilicon
nwell
psubstrate
metal1

nMOStransistor pMOStransistor

Six masks Y

n-well GND V DD

nM O S transistor pM O S transistor

Polysilicon subs trate tap w ell tap

n+ diffusion n w e ll

p+ diffusion P o ly s ilic o n

Contact
n + D iffu s io n

Metal p + D iffu s io n

C o n ta c t

M e ta l

44
Cross Sectional CMOS

45

Physical Layers

46
CMOS Process Flow

47

Latch-Up Effect
If base-emitter junction of pnp transistor becomes forward biased, transistor is
ON. The collector current of the npn transistor forces the pnp transistor to
conduct more current. This feedback leads to latch-up & circuit will be destroyed
by heat
Circuit can be prevented from latch-up by placing heavily doped guard ring
around MOSFETs. This reduces the effectiveness of base-emitter regions in
both transistors

48
IC Layout
IC layout, IC mask layout, or mask design, is the representation of IC in terms of
planar geometric shapes which correspond to patterns of metal, oxide, or
semiconductor layers that make up components of IC
Chips are specified with set of masks & guidelines for constructing process
masks
Required for resolution/tolerances of masks

Minimum dimensions of masks determine transistor size (Speed, Cost, Power)

Feature size F = Distance b/w Source & Drain
Set minimum width of polysilicon
Feature size improves 30% every 3 years or normalize for feature size when
describing design rules
Rules in terms of Interface b/w designer & process engineer
Fabrication processes defined by minimum channel width
Layout can be very time consuming
Design gates to fit together nicely
Build a library of standard cells

49

IC Layout
Generated layout must pass a series of checks in a process known as physical
verification. The most common checks in this verification process are:
Design Rule Checking (DRC)
Layout Versus Schematic (LVS)
Parasitic Extraction
Antenna Rule Checking
Electrical Rule Checking (ERC)

50
IC Layout
Design objective in which Wp & Wn are separated may take into account such
parameters as power dissipation, propagation delay, noise immunity, & area

Basic steps are as follows:

Identification of gates (i.e., Inverter, NAND, NOR) and compute an average
delay time
Calculation of worst-case propagation time to ration of Wp/Wn
Calculation of noise immunity to Wp/Wn
Selection of ratio that balances the functions
Cell I/O should be available, at same relative horizontal distance, on top &
bottom of cell
Horizontal metal are used to supply power & ground to cell. Well & substrate
tie downs should be under these busses

51

Layout Design Rules

Design rules are an abstraction of the fabrication process that specify various
geometric constraints on how different masks can be drawn
Design rules can be absolute measurements (e.g. in nm) or scaled to an
abstract unit, lambda ( ). Lambda-based designs are scaled to appropriate
absolute units depending on manufacturing process finally used

Design rules do not represent some hard boundary b/w correct & incorrect
fabrication. Rather, they represent a tolerance that ensures very high probability
of correct fabrication & subsequent operation

Rules provide necessary communication link b/w circuit designer & process
engineer during manufacturing phase

Design rules are used to obtain circuit with optimum yield in as small geometry
as possible without compromising reliability of circuit

52
Layout Design Rules
Design rules define ranges for features
Min. wire widths to avoid breaks
Min. spacing to avoid shorts
Min. overlaps to ensure complete overlaps
Minimum line width
Scalable design rules:
lambda parameter = f/2, E.g. = 0.3 m in 0.6 m process (which is
half of the minimum channel length)
Classes of MOSIS SCMOS rules:
Submicron, Deep Submicron
Absolute dimensions measured in microns (micron rules)
Exclusion rule
Surround rule Extension
rules

Width
rules

Spacing rules
53

Layout Design Rules

Uniform cell & well height, when standard cells are placed, power & ground
busses line up
Cell width should be as narrow as layout will allow
NMOS at bottom & PMOS at top
Vdd & Vss in metal at top & bottom of the cell with standard height
Metal-1 Vdd & Vss rails
Metal-2 access to I/Os
Well/substrate taps
Vertical polysilicon lines for each gate input
Adjacent gates should satisfy design rules
All gates include well & substrate contacts
Layout should be labeled to indicate power, ground, input, & output
connections. Cell outline is useful in alignment, should be added to cell layout
Ordering polysilicon gate signals to allow maximal connection b/w transistors
via abutting source-drain connections

54
Lambda-based Design Rules
One lambda ()= one half of the minimum mask dimension
Typically the length of a transistor channel is 2. Usually all edges must be on
grid, e.g., in the MOSIS scalable rules, all edges must be on a lambda grid
Length of the
transistor channel Layer Color Representation
is usually the Well (p,n) Yellow
Active Area (n+,p+) Green
feature that sets Select (p+,n+) Green
the process Polysilicon Red
Metal1 Blue
technology name Metal2 Magenta
Contact To Poly Black
(e.g., 0.18m has Contact To Diffusion Black
Via Black
0.18m transistor
length)
Same Potential Different Potential
9 2
0
Well or Polysilicon
6
10 2
3 3
Active
Metal1
3
3
2 Contact
or Via 2 4
Select Hole
Metal2
2
3

55

Vias & Contacts 2

Transistor 4
Via
1 1
5
Metal to
1 Metal to 1 Poly Contact
A ctive Contact 3 2

3 2
2
2
5

2
Select
3
2

1
3 3

2 5

Well
Substrate
56
Layout Design Rules
Transistor dimensions are in W/L ratio
NFETs are usually twice the width
PFETs are usually twice the width of NFETs
Holes move more slowly than electrons (must be wider for same current)

57

Layout Design Rules

58
Wiring Tracks
Wiring track is space required for a wire
4 width, 4 spacing from neighbor = 8 pitch
Transistors also consume one wiring track

Wells must surround transistors by 6

Implies 12 between opposite transistor flavors
Leaves room for one wire track

59

Area Estimation & Guard Rings

Estimate area by counting wiring tracks
Multiply by 8 to express in

Latch-up risk greatest when diffusion-to-substrate diodes could become

forward-biased
Surround sensitive region with guard ring to collect injected charge

60
VDD & VSS Connections

Section shown

A C Metal
B D Poly
C A
D E
E B

61

Stick Diagrams
Stick diagrams are capturing topography & layer information using simple diagrams
Stick diagrams convey layer information through colour codes or monochrome
encoding
Acts as an interface between symbolic circuit & actual layout
Stick diagrams help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers

Does show:
VDD 3
All components/vias
It shows relative placement of components
Goes one step closer to the layout In Out
Helps plan the layout and routing
1
Does not show:
Exact placement of components
GND
Transistor sizes
Wire lengths, wire widths, tub boundaries.
Any other low level details such as parasitics..

62
Stick Diagrams
Metal 1 Can also draw
Poly in shades of
gray/line style
N-Diff
P-Diff
Similarly for contacts, via, tub etc..
Rule 1: When two or more sticks of the same type cross or touch each other that
represents electrical contact

Rule 2: When two or more sticks of different type cross or touch each other there
is no electrical contact
(If electrical contact is needed we have to show the connection explicitly)

Rule 3: When a poly crosses diffusion it represents a transistor

Rule 4: In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff.
All pMOS must lie on one side of line & all nMOS will have to be on other side

63

Stick Diagrams
N+ N+

VDD VDD
X

X
x
x x x
X

X
Gnd
Gnd

metal1 VDD

Well

VSS
Routing Channel
signals 64
polysilicon
 Stick Diagrams

Power VDD VDD

x
x
A Out

GND GND
C
a c b a b c
B
(a) Input order {a c b} (b) Input order {a b c}
Ground Two Versions of (a+b).c 65

Stick Diagrams V
DD
V
DD
V V A
DD DD

A B B A B C B A B Ci B A Ci Co Ci A B
i
Kill
"0"-Propagate
A C
C i
o Co
C S
i
A C
i S
"1"-Propagate
Generate
GND
A B B A B C A
i

24 transistors B

Mirror Adder
VDD Propagate/Generate Row

P0 P1 P2 P3 V
DD
C3
P G P G
Ci,0 i i i+ 1 i+1
G0 G1 G2 G3

C C C
i i+1
i- 1

GND

C0 C1 C2 C3 Inverter/Sum Row

Manchester Carry Chain 66

 Example
Sketch a stick diagram & estimate area of Y = A + B + C D
( )

67

CMOS Inverter
V DD N Well
V DD

PMOS
PMOS Contacts

In Out GND In VDD

In Out A A
Polysilicon Metal 1
NMOS
Layout Out

NMOS A A
p-substrate n
GND Field
n+ p+ Oxide
Cross-Section along A-A

VDD VDD
VDD

M2
M4 PMOS

Vin Vout Vout2

In Out
Metal1
Polysilicon
M1 M3
NMOS
GND

68
CMOS Inverter Symbolic Layouts
a) Shows symbolic layout of inverter
corresponding to symbolic
schematic
b) Alternate inverter layout showing
horizontal active areas with vertical
poly stripe for gates & vertical metal
drain connections
c) Uses M2 metal to connect transistor
drains in order to allow passing
horizontal M1 metal wires
d) Uses diffused N & P source region
extensions (active mask) to Vss and
Vdd, respectively, in order to allow
passing M1 metal wires at top &
bottom of cell

69

Alternate Methods for Creating Inverter Layouts

Option (a): Increase Wn & Wp beyond
the min values
Option (b): Use parallel sections to obtain
increased Wn & Wp
Stitch Vdd & Vss in such a way as to
share drain regions b/w parallel
device sections
Option (c): Use of circular transistors
effectively quadruples the available
channel width of each device
Since drain regions are in center,
drain capacitance terms are minimum

70
 NAND Gate Layout
Single polysilicon lines (for inputs) are vertically across both N & P active regions
Single active shapes used for building both NMOS & PMOS devices
Power bussing is running horizontal across top & bottom of layout
Output wire runs horizontal for easy connection to neighboring circuit

VDD Vdd

In1 In2 In3 In4

Out
In1

In2

In3

In4
GND
In1 In2In3 In4
Pseudo-NMOS NAND Gate71

NOR Gate Layout

Features of the layout are similar to the 2-input NAND
Single vertical poly lines for each input
Single active shapes for N & P devices
Metal busing running horizontal

72
Examples

73

Examples

4-input NAND in CPL

V DD
S

A
M2

S F

M1
B

S
Pass-Transistor based MUX 74
Examples
A3 A3 A2 A2 A1 A1 A0 A0

VDD

word

GND

NANDgate bufferinverter

Row Decoder 75

SRAM Layout
Cell size is critical: 26 x 45 (even smaller in industry)
Tile cells sharing VDD, GND, bitline contacts

Bitline Conditioning
GND B IT B IT _ B GND

2 VDD

More
Cells
word_q1 W ORD

C e ll b o u n d a r y
bit_b_v1f
bit_v1f

SRAM Cell

write_q1

data_s1
76
10T CAM Cell
Add four match transistors to 6T SRAM
56 x 43 unit cell
bit bit_b
word
cell

cell_b

match

77

RAM Layout
WL

VDD VDD
M2 M4 M2 M4
Q
Q M6
M5

M1 M3 Q Q
M1 M3
BL BL
GND
6T-SRAM M5 M6 WL

BL BL
BL1 BL2

WWL BL2 BL1 GND

RWL RWL
M3

X M3 M2
M2
M1
WWL
CS M1

3T-DRAM
78
 ROM-Layout
Read-Only Memories are nonvolatile
Retain their contents when power is removed
Mask-programmed ROMs use one transistor per bit
Presence or absence determines 1 or 0
4-word x 6-bit ROM
Represented with dot diagram
Dots indicate 1s in ROM

weak
A1 A0 pseudo-nMOS
pullups

ROM
2:4
DEC

ROM Array
Unit
Cell

Y5 Y4 Y3 Y2 Y1 Y0

Looks like 6 4-input pseudo-nMOS NORs Unit cell is 12 x 8 l (about 1/10 size of SRAM) 79

PLA-Layout
A N D P la n e O R P la n e

b c
a c
a b
a b c
a b c
a b c
a b c

a b c
s c o u t

AND

GND VDD And-Plane Or-Plane

OR V DD G ND

OR
AND
VDD f0 f1 GND
x0 x0 x1 x1 x2 x2

AND-PLANE OR-PLANE x0 x0 x1 x1 x2 x2 f0 f 1
Pull-up devices Pull-up devices
Dynamic PLA 80
 Shifter-Layout
A3
B3
A3
Sh1
A2
B2
A2

Sh2 : Data Wire

A1
B1 : Control Wire A1

Sh3
A0 A0
B0

Sh0 Sh1 Sh2 Sh3

Area Dominated by Wiring Sh0 Sh1 Sh2 Sh3
Buffer
4x4 Barrel Shifter
S h1 Sh 1 Sh2 Sh 2 Sh4 S h4

A3 B3 A3
Out3

A2 B2 A2
Out2

A1 B1 A1
Out1

A0 B0 A0
Out0
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0-7 bit Logarithmic Shifter

Standard Cells

Automatic Layout Cell Generation

Oxide-isolation

PMOS

PMOS

NMOS

NMOS
NMOS

Using oxide-isolation Using gate-isolation

Manually Designed Cell Layout

82
Standard Cells
Floorplan: Defines overall topology of design, relative placement of modules,
and global routes of busses, supplies & clocks
Routing channel requirements are reduced by presence of more interconnect
layers
Macrocell
Feedthrough Cell Logic Cell
Routing
Channel

Interconnect Bus

Functional
Module
(RAM,
multiplier, )

3-input NAND gate 83

Standard Cells
polysilicon

VD D
rows of m etal
uncommitted
cells possible
Uncommited Cell
GN D conta ct

In 1 In 2 In 3 In4
routing
channel
Committed Cell
(4-input NOR)
Gate Array
O ut

84
Standard Cells based Chip

SRAM

SRAM Data
paths

Standard
Cells

Video-Encoder Chip

85

Layout Technique using Euler Graph Method

Euler Graph Technique can be used to determine if any complex CMOS gate can
be physically laid out in an optimum fashion
Start with either NMOS or PMOS tree & connect lines for transistor
segments, labeling devices, with vertex points as circuit nodes
Next place a new vertex within each confined area on pull-down graph &
connect neighboring vertices with new lines, making sure to cross each edge
of pull-down tree only once
New graph represents the pull-up tree & is dual of pull-down tree
Stick diagram is done with arbitrary gate ordering that gives non-optimum layout

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Layout with Optimum Gate Ordering
By using Euler path approach to re-order the polysilicon lines of previous chart,
we can obtain an optimum layout
Find a Euler path in both pull-down tree graph & pull-up tree graph with identical
ordering of inputs
Euler path: Traverses each branch of the graph exactly once!
By reordering input gates as E-D-A-B-C, we obtain an optimum layout of given
CMOS gate with single actives for both NMOS & PMOS devices

87

Automated Method to Design Gate Layouts

Place inputs as vertical poly stripes
Place Vdd & Vss as horizontal stripes
Group transistors within stripes to allow
maximum source/drain connection
Allow poly columns to interchange in
necessary to improve stripe wireability
Place device groups in rows
Wire up circuit by using vertical diffusions
for connections & manhattan metal routing
(both horizontal & vertical)

88
CMOS XNOR Gate Layouts
Separate sections & stack transistors for
each section over identical gate inputs
XNOR implementation in (b) shows
separate sections with X = (AB) & Z = ((A
+ B) X) = XNOR (A,B)
Uses single row of N & P transistors
with a break b/w active regions
Alternate layout in (c) uses vertical device
regions making it a bit more compact

89

Euler Method for OAI Circuit Schematic

Layout at is an optimum layout of (OR AND Inverter) OAI circuit
Single poly vertical inputs
Unbroken single active regions for both N & P transistors
Problem: Find an equivalent inverter circuit for layout assuming:
W/L)P = 15 for all PMOS transistors
W/L)N = 10 for all NMOS transistors

90
CMOS 1-Bit Full Adder Circuit
1-Bit Full Adder logic function:
Sum=A XOR B XOR C
=ABC+ABC+ABC+ABC
Carry_out = AB+AC+BC
Alternate representation of sum function allows the 1-bit full adder to be
implemented in complex CMOS with 28 transistors
Carry_out internal node is used as an input to adder complex CMOS gate

91

CMOS Full Adder Layout

Use Euler method
Carry_out inverter requires separate active shapes, but all other N & P
transistors were laid out in single active region
Layout is non-optimized for performance
All transistors are seen to be minimum W/L
Design of n-bit full adder:
Carry ripple adder design uses carry_out of stage k as carry_in for stage
k+1
Typically layout is modified in order to use larger transistors for carry_out
CMOS gate in order to improve the performance of ripple bit adder

92
PLL Design: Layout

Area 1.4 mm x 1.7 mm

PLL-Layout

94
PLL-Layout

95