Lecture 2

The 8086 Microprocessor

Architecture
[Register level organization]

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 In this lecture

The 8086 internal architecture

The Execution Unit
The Bus Interface Unit
Physical Address Generation

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 The Basic Arch.

The simplest microprocessor at least contains:

Program and data address bus (separate or unified)
Address decoder and generator
Instruction decoder
Arithmetic and Logic Unit (ALU)
A set of basic registers
Program Counter (PC)
Instruction Register (IR)
Accumulator or Working Register (AC)
Flag register (FR)
Input and output registers
General purpose (temporary)registers (GPRs)

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The 8086 Internal Architecture

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8086

40 pins
16-bit architecture
Clock Rate : 10MHz max

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 IBM PC
IBM PC (1981) was based on 8088 which is
identical to 8086 except the data bus

Memory: 16kB 256 kB

CPU: Intel 8088 @ 4.77MHz
$3000 at the time
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8086 Internal Arch.

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 8086 Internal Arch.cntd

Two functional parts

Execution Unit (EU)
Bus Interface Unit (BIU)

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 The Execution Unit (EU)

The EU contains :

Control Circuitry: Directs internal operations

A Decoder : Translates instructions fetched from

memory into a series of actions which the EU carries out

16-bit Arithmetic Logic Unit (ALU) : Does arithmetic and

logic operations (add, subtract, multiply, OR, AND,)

Registers : General purpose, flag

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 Flag register

Consists of bits that show the status of the CPU

or control the operation of the CPU

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 Status Flags

Carry Flag (C)

This flag is set when there is a carry out of MSB in case of
unsigned addition or a borrow in case of unsigned
subtraction

Zero Flag (Z)

This flag is set when the result of an arithmetic operation is
zero

Sign Flag (S)

This flag is set when the result an arithmetic operation is negative
For signed computations, the sign flag equals the MSB of the result

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 Status Flagscntd

Parity Flag (P)

This flag is set when the lower byte of a result contains even
number of 1s.

Overflow Flag (O)

This flag is set, if an overflow occurs, i.e. if the result of a
signed operation is either too large or too small to fit into a
destination

Auxiliary Cary Flag (AC)

This is set if there is a carry from the lowest nibble, i.e. bit
three, during addition or borrow for the lowest nibble, i.e. bit
three, during subtraction.

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 Control Flags

Interrupt Flag (I)

If this flag is set, the maskable interrupts are acknowledged
by the CPU, otherwise they are ignored.

Direction Flag (D)

This is used by string manipulation instructions.
If this flag bit is '0 the string is processed beginning from the
lowest to the highest address (auto-incrementing mode).
Otherwise, the string is processed from the highest to the
lowest address (auto-decrementing mode).

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 General Purpose Registers (GPRs)
The EU has eight 16-bit general purpose registers
AX, BX, CX, DX, BP, SP, SI, DI

AX, BX, CX and DX can be addressed as two separate 8-

bit values
AH-AL, BH-BL, CH-CL, and DH-DL.

AX
16
AH AL
8 8

Usually used as: A - accumulator, B - base, C - counter, D -

data
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The Bus Interface Unit (BIU)

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 Instruction Byte Queue

While the EU is decoding or executing an instruction,

which does not require use of the buses, the BIU fetches
up to six instruction bytes for the following instructions

The BIU stores these pre-fetched bytes in a first-in-first-

out register set called a queue. When the EU is ready for
its next instruction, it simply reads the instruction
byte(s) for the instruction from the queue in the BIU

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 Segment Registers

The four 16-bit segment registers :

Code segment (CS) register
Data segment (DS) register
Stack segment (SS) register
Extra segment (ES) register

Used to address memory (up to 1048576 bytes (1MB) )

20-bit Address
Memory
8086
16-bit Data

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 Physical address generation
FFFFFH In 8086 system memory was
64K
F0000H divided into 64kB units called
segments
.
. Memory is addressed using a
. combination of a segment register
90000H
and an offset register
64K
80000H 8FFFFH
.
.
.
20000H 8F000H
64K
10000H F000H (offset)
64K
00000H 80000H
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Physical address generationcntd

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 Physical address generationcntd
E.g. If the segment address is 1005h and the offset is
5555h, then the physical address is calculated as follows

Segment address --------- 1005h

Offset address------------- 5555h

Segment address--------- 1005h --------- 0001 0000 0000 0101

Shifted by 4 bit positions---------- 0001 0000 0000 0101 0000
Offset address----------------------- + 0101 0101 0101 0101

Physical address ------------------- 0001 0101 0101 1010 0101

1 5 5 A 5 h

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 Physical address generationcntd

A typical program has three segments: code,

data and stack

CS contains the 16-bit code segment address

DS contains the 16-bit data segment address
SS contains the 16-bit stack segment address
ES can point to alternate data segments

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 Instruction Pointer (IP)

The IP contains the distance or offset from the base

address in Code Segment (CS) to the next instruction
byte to be fetched

The 16-bit offset in IP is added to the 16-bit segment

base address in CS to produce the 20-bit physical
address.

Location of the next instruction in memory is, therefore

address of next instruction = (CS << 4) + IP or (CS:IP)

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Instruction Pointer (IP)cntd
E.g. Let CS holds 348Ah, and IP holds
4214h. Now the actual address in the
physical memory space is given by
CS:IP and calculated as:
CS is first shifted left four times
CS <<4= 348A0h
Then the offset in IP is added
348A0h
+ 4214h
Actual address 38AB4h

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 Other Registers
Stack Pointer

A stack is a section of memory set aside to store addresses

and data while a subprogram is executing

The 8086 allow you to set aside an entire 64KB segment as a

stack. The upper 16 bits of the starting address for this
segment are kept in the stack segment register (SS)

The stack pointer (SP) register holds the 16-bit offset from
the start of the segment to the memory location where a
word was most recently stored on the stack (Top of stack)
address of top of stack = (SS << 4) + SP or (SS:SP)

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Other Registerscntd
E.g. Let SS hold 5000h, and SP hold
FFE0h
Now the actual address in the physical
memory space is given by SS:SP and
calculated as:
SS is first shifted left four times
SS<<4 = 50000h
Then the offset in SP is added
50000h
+ FFE0h
Top of stack 5FFE0h

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 Other Registerscntd
Base Pointer and Index Registers

In addition to the SP, the EU contains a 16-bit base pointer

(BP) register, a 16-bit source index (SI) register and a 16-bit
destination Index (DI) register.

The base pointer can be used to hold the 16-bit offset of a

data word in one of the segments. Index registers are very
useful in string manipulation.

These three registers can be used for temporary storage of

data just as the general-purpose registers described above

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Summary of 8086 registers

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 After 8086

IA-32
Starting from 80386
32 bit registers (extended registers)
32 bit address bus
EAX
32

AX
16

AH AL
8 8
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 After 8086cntd

On chip Floating Point Unit (FPU)

Starting from 80486

Pipelining
Starting from 80486

Superscalar, MMX
Starting from Pentium

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 Next Class

8086 Pinouts
8086 Memory Interfacing

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 More Readings

1. Dr. Manojs Handout, Chapter 1

2. Kip R. Irvine, Assembly Language For Intel-
Based Computers, Chapter 2
3. 8086 Datasheet, Intel

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