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PACKAGE TYPE
DIP SOIC SOIC TSSOP
93LC46A/B
CS 1 8 Vcc CS 1 8 Vcc
93LC46AX/BX
1 8 VCC NC 1 8 NC 2 7
93LC46A/B
CS CLK NC
93LC46A/B
CLK 2 7 NC DI 3 6 NC
2 7 NC Vcc 2 7 Vss DO 4 5 Vss
CLK
DI 3 6 NC
DI 3 6 NC CS 3 6 DO
DO 4 5 Vss
DO 4 5 Vss CLK 4 5 DI
CLK is a Don't Care if CS is low (device deselected). The status signal is not available on DO, if CS is held
If CS is high, but the START condition has not been low during the entire ERASE or WRITE cycle. In this
detected, any number of clock cycles can be received case, DO is in the HIGH-Z mode. If status is checked
by the device without changing its status (i.e., waiting after the ERASE/WRITE cycle, the data line will be high
for a START condition). to indicate the device is ready.
CLK
DI 1 1 1 AN AN-1 AN-2 A0
TSV TCZ
HIGH-Z
DO BUSY READY
HIGH-Z
TWC
CLK
DI 1 0 0 1 0 X X
TSV TCZ
HIGH-Z
DO BUSY READY
HIGH-Z
TEC
CLK
DI 1 0 0 0 0 X X
TCSL
CS
CLK
1 0 0 1 1 X X
DI
CS
CLK
DI 1 1 0 An A0
HIGH-Z
DO 0 Dx D0 Dx D0 Dx D0
CS
CLK
DI 1 0 1 An A0 Dx D0
TSV TCZ
HIGH-Z
DO BUSY READY
HIGH-Z
Twc
CS
CLK
DI 1 0 0 0 1 X X Dx D0
TSV TCZ
HIGH-Z
DO BUSY READY
HIGH-Z
TWL
All rights reserved. 1998, Microchip Technology Incorporated, USA. 7/98 Printed on recycled paper.
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