Quiz for the session-1 on ASIC design flow:

1. What does 16nm indicate in the name of the technology node?

a. Width of the transistor
b. Placement grid for wires
c. Channel length of the transistor
d. Minimum achievable spacing between cells
2. Which level of abstraction does the gate level netlist belong to?
a. Logic level
b. Concept level
c. Physical level
d. RTL (Register Transfer Level)
3. What is meant by formal verification?
a. Functional verification of the logic
b. Formally checking the functionality
c. Validating correctness between RTL and the Synthesis netlist
d. Mathematically proving the function of netlist
4. What are the targets of the synthesis process?
a. Timing performance
b. Power
c. Area
d. All the above
5. Which DFT technique is used for detecting stuck-at faults in logic
implementation?
a. Boundary scan
b. SCAN
c. MBIST
d. JTAG
6. What happens to the setup margin when a capture flop has a positive
skew?
a. Setup margin of capture flop reduces
b. Setup margin of launch flop increases
c. Setup margin of capture flop increases
d. None of the above
7. Which is worst case operation condition for a silicon device?
a. Temperature-HIGH, Voltage-LOW, Process-Worst
b. Temperature-LOW, Voltage-HIGH, Process-Best
c. Both A & B
d. None of the above
8. Why is it important to fix the IR drop related problems in a die?
a. More power will get consumed
b. Cells will get more voltage and get damaged
c. It is not possible to provide stable power supply
d. Cells performance will be unpredictable
9. What are antenna violations?
a. Odd metal structures in the layout
b. Devices get damaged during manufacturing due to accumulated
charges

c. Radiating metal piece that causes EMI

d. All the above
 10.Why Metal Density checks are needed?
a. For improving reliability due to planarity mismatches in the layout
b. To provide shielding to the signal wires
c. To provide extra capacitance to the signal wires
d. None of the above

Key:

1. C
2. A
3. C
4. D
5. B
6. C
7. C
8. D
9. B
10.A