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Datasheet
Rev. 0.4
6 May, 2008
Track ID: xxxx-nnnn-nn
DISCLAIMER
Realtek provides this document as is, without warranty of any kind, neither expressed nor
implied, including, but not limited to, the particular purpose. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This
document could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this
document are trademarks/registered trademarks of their respective owners.
CONFIDENTIALITY
This document is confidential and should not be provided to a third-party without the permission
of Realtek Semiconductor Corporation.
REVISION HISTORY
Revision Release Date Summary
0.0 2008/01/18 First release.
0.1 2008/01/23 n Correcting pin 113 as OVDD
n Block diagram added
0.2 2008/01/30 n Correcting pin 12 as VSS
0.3 2008/01/31 n Correcting polarity of U1ID
0.4 2008/05/06 n U1ID should be input only, not I/O
n RTL8671BH added
Table of Contents
1. GENERAL DESCRIPTION............................................................................................................................1
2. FEATURES ......................................................................................................................................................2
3. SYSTEM APPLICATIONS.............................................................................................................................2
4. BLOCK DIAGRAM .........................................................................................................................................3
5. PIN ASSIGNMENTS.......................................................................................................................................4
6. PIN DESCRIPTIONS......................................................................................................................................5
7. SYSTEM OVERVIEW ..................................................................................................................................10
8. ELECTRICAL REQUIREMENTS ...............................................................................................................11
8.1. DC CHARACTERISTICS .............................................................................................................................................11
8.1.1. Absolute Maximum Rating...........................................................................................................................11
8.1.2. Recommended Operation Conditions ..............................................................................................................11
8.1.3. Power Consumption .....................................................................................................................................11
8.1.4. Reference Crystal .........................................................................................................................................12
8.1.5. ADSL Interface Clock Input .........................................................................................................................12
8.2. AC CHARACTERISTICS..............................................................................................................................................12
8.2.1. FLASH Parallel...........................................................................................................................................12
8.2.2. FLASH Serial..............................................................................................................................................13
8.2.3. SDRAM...........................................................................................................................................................13
8.2.3.1 SDRAM Input Timing ....................................................................................................................................13
8.2.3.2 SDRAM Output Timing .................................................................................................................................14
8.2.3.3 SDRAM Access Control Timing ..................................................................................................................15
8.2.4. AFE .................................................................................................................................................................16
8.2.4.1 Master clock ...................................................................................................................................................16
8.2.4.2 Transmission Interface .................................................................................................................................16
8.2.4.3 Reception Interface.......................................................................................................................................16
8.2.5. JTAG ...............................................................................................................................................................16
8.2.6. Reset...............................................................................................................................................................18
8.2.7. VREF Timing ....................................................................................................................................................18
8.2.8. Power-on sequence ......................................................................................................................................19
9. MECHANICAL DIMENSIONS ....................................................................................................................20
10. ORDERING INFORMATION .......................................................................................................................22
Integrated ADSL2+ Router Controller iii Track ID: xxxx-nnnn-nn Rev. 0.4
List of Tables
TABLE 1 PIN DESCRIPTIONS OF RTL8671B/ RTL8671BH (128-PIN LQFP)....................................................................5
TABLE 2 ABSOLUTE MAXIMUM RATING........................................................................................................................11
TABLE 3 RECOMMENDED OPERATION CONDITIONS ......................................................................................................11
TABLE 4 POWER CONSUMPTION ....................................................................................................................................11
TABLE 5 REFERENCE CRYSTAL .....................................................................................................................................12
TABLE 6 ADSL INTERFACE CLOCK INPUT.....................................................................................................................12
TABLE 7 PARALLEL FLASH TIMING .............................................................................................................................12
TABLE 8 SDRAM INPUT TIMING ...................................................................................................................................13
TABLE 9 SDRAM OUTPUT TIMING ...............................................................................................................................14
TABLE 10 SDRAM ACCESS CONTROL TIMING ...............................................................................................................15
TABLE 11 AFE MASTER CLOCK ......................................................................................................................................16
TABLE 12 AFE TX INTERFACE ........................................................................................................................................16
TABLE 13 AFE RX INTERFACE........................................................................................................................................16
TABLE 14 JTAG INTERFACE TIMING ...............................................................................................................................16
TABLE 15 RESET TIMING .................................................................................................................................................18
TABLE 16 VREF TIMING....................................................................................................................................................18
TABLE 17 DIMENSION OF LQFP-128 ...............................................................................................................................21
List of Figures
FIGURE 1 APPLICATION DIAGRAM I ...................................................................................................................................2
FIGURE 2 APPLICATION DIAGRAM II..................................................................................................................................2
FIGURE 3 BLOCK DIAGRAM ...............................................................................................................................................3
FIGURE 4 PIN-OUT DIAGRAM .............................................................................................................................................4
FIGURE 5 FLASH ACCESS TIMING.....................................................................................................................................13
FIGURE 6 SDRAM INPUT TIMING ....................................................................................................................................14
FIGURE 7 SDRAM OUTPUT TIMING ................................................................................................................................14
FIGURE 8 SDRAM ACCESS CONTROL TIMING .................................................................................................................15
FIGURE 9 BOUNDARY-SCAN GENERAL TIMING................................................................................................................17
FIGURE 10 BOUNDARY-SCAN RESET TIMING.....................................................................................................................17
FIGURE 11 RESET TIMING ..................................................................................................................................................18
FIGURE 12 DRAWING OF LQFP-128...................................................................................................................................20
1. General Description
The Realtek RTL8671B/ RTL8671BH are integrated SoC featuring a RISC, an ADSL2+ Discrete
Multi-tone (DMT) data-pump, a hardware-based ATM Segmentation and Reassembly (SAR),
two 10/100Mbps IEEE 802.3 compliant MACs with an embedded Ethernet transceiver, and a
USB PHY port. Mated with the Realtek RTL8271B (ADSL2+ Analog Front End), RTL8671B/
RTL8671BH provide a low cost integrated solution for ADSL2+ CPE modems, routers, or
gateways.
RTL8671B/ RTL8671BH encompass high-performance DSP technologies, optimized mix-signal
designs, and an efficient architecture to provide a seamless WAN to LAN router controller. The
embedded RISC network processor supports the MIPS I instruction set along with DSP
extensions and achieves a 340MHz clock rate in a six-stage pipeline to support layer 2, 3, and
other upper layer applications.
The DMT engine supports the upstream data rate from 32kbp to above 3Mbps and the
downstream data rate from 32kbps to above 24Mbps throughput, and complies with:
The Ethernet interface offers high-speed transmission over CAT-5 UTP cable or CAT-3 UTP
(10Mbps only) cable. Ethernet functions such as Crossover Detection & Auto-Correction and
polarity correction are implemented to provide robust transmission and reception capability at
high speeds.
2. Features
n Two-chip ADSL2+ CPE solution: n One on-chip USB PHY port supporting the
RTL8671B/ RTL8671BH (ADSL2+/Network host/device mode
Processor SoC) + RTL8271B (ADSL2+ n Support serial SPI interface for device
Analog Front End). control
n Field proven DMT data-pump complies n Network device management via HTTP,
with ANSI T1.413 Issue 2, ITU-T G992.1, SNMP, and CLI (UART).
G.992.2 , G.992.3, G.992.4, G.992.5 n IP layer processing, DHCP, NAT, and
supporting Annexes A, B, I, J, L, and M. typical higher layer applications supported
Supports S=1/3 coding.
n 16-bit-wide, 166MHz SDRAM support up
n High performance embedded RISC with to 256Mb
MMU, TLB and DSP instruction extension.
n 8/16-bit-wide parallel/SPI Flash support up
n Embedded hardware-based ATM SAR: up to 128Mb
to 8 distinct VCsATM AAL5 adaptation, n 3.3V signaling, 1.2V core voltage; a
F4/F5 OAM cell, HEC, CRC, IP/TCP/UDP embedded linear regulator controller to
checksum offloading, and error packet reduce an external LDO
filtering and QoS supported for CBR,
n Two 32-bit timers and a watchdog timer
UBR, rt-VBR, and nrt-VBR.
n Embedded Dying-Gasp detection circuit
n Embedded 10/100 Base-TX Ethernet MAC
n EJTAG interface
and transceiver supporting Crossover
n Package of 128-pin LQFP available
Detection & Auto-Correction and polarity
correction, IP/TCP/UDP checksum offload
supported as well.
3. System Applications
AFE
RTL8671B RTL8271B
LQFP-128
Buttons
& LEDs
FLASH
SDRAM
Parallel/SPI RS-232
4. Block Diagram
EJTAG
UART GPIO SPI
CPU
I-CACHE
Memory D-CACHE
I-RAM
Controller
D-RAM USB
16-bit OTG
NOR, SPI w/ PHY
Interrupt
FLASH Control Arbiter
Control
SDRAM
Control ATM
OBC
SAR ENET
PHY
(w/ MAC),
Clock & DMT & LED
System control AFE I/F
5. Pin Assignments
MCS3#
MCS2#
MD14
MD15
OVDD
RAS#
CAS#
DGND
IVDD
OVDD
IVDD
MA10
MA11
MA12
OVDD
MA13
MA14
MA15
MA16
MA17
MA18
WE#
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
MD13 97 64 MA19/SFCK/SVCK
MD12 98 63 MCS0#
IVDD 99 62 MA20
MD11 100 61 MA21/NICLED0
MD10 101 60 OVDD
OVDD 102 59 MA22/NICLED1
MD9 103 58 DGND
MD8 104 57 NICLED2
MD7 105 56 IVDD
MD6 106 55 NICLED3
SDCLK 107 54 USBLED1
MD5 108 53 RSRVD(NC)
IVDD 109 52 GPB7/JTDO
MD4
DGND
110
111
RTL8671B 51
50
GPB6/JTMS
GPB5/JTDI
MD3 GPB4/JTRST#
LQFP-128
112 49
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCTL
VDD33
VDD12
TXOP
TXON
VSS
RXIP
RXIN
VDD12
VDD12
CKIN
VSS
VDD12
VDD33
RSRVD(NC)
RSRVD(NC)
VSS
VSS
U1DM
U1DP
U1ID
U1VBUS
VDD33
DGND
GPA5/SVCS#
IVDD
AFTXD0
AFTXD1
AFTXD2
AFTXD3
AFRXD0
AFRXD1
6. Pin Descriptions
1. MA[10:9] and AFTXD[3:2] strap into the register at the power-on reset to configure the CPU speed. The value 00110 configures the
CPU running at 340MHz. This is a strict setting for RTL8671B/ RTL8671BH. That is, AFTXD3 and MA8 should be pulled up via a 4.7k
Ohm resistor, and AFTXD2 and MA[10:9] should be pulled low via a 4.7k Ohm resistor.
7. System Overview
TBD
8. Electrical Requirements
8.1. DC Characteristics
8.2. AC Characteristics
A[20..0]
F_CE0#
OE#
Twp
Tcs
WR#
D[n..0]
8.2.3. SDRAM
8.2.4. AFE
8.2.5. JTAG
Table 14 JTAG Interface Timing
Symbol Parameter Min. Typ. Max. Units Notes
TBSCL JTAG clock low time ns
TBSCH JTAG clock high time ns
TBSIS TDI, TMS setup time to rising edge of ns
TCK
TCK
TMS, TDI
TDO
RESET#
TMS
8.2.6. Reset
Table 15 Reset Timing
Symbol Parameter Min. Typ. Max. Units Notes
TPOWERON_RESET Minimum time required to hold TBD s
the PWRRST# at logic 0 state
after stable power has been
applied to RTL8671B/
RTL8671BH
3.3V
TPOWERON_RESET
TPUSH_RESET
RESET#
9. Mechanical Dimensions
Figure 12 Drawing of LQFP-128