4327d Wistron DMB40 (BMW-Z4-DIS) 11289-1 Dell Inspiron 14z-5423

5 4 3 2 1
BMW Z4 14" Schematics Document

D
Ivy/Sandy Bridge D
Panther Point
2012-04-02
C
REV : A00 C
DY : None Installed
UMA: UMA only installed
SG: PX solution installed.
B B
A <Core Design> A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size Document Number Rev
A3
BMW Z4 DIS A00
Date: Monday, April 02, 2012 Sheet 1 of 105
5 4 3 2 1
5 4 3 2 1
CHARGER
BQ24727 40
INPUTS OUTPUTS
Project Code: 91.4UV01.001
Block Diagram PCB P/N : 48.4SB02.011
AD+
SYSTEM DC/DC
BT+
TPS51125RGER 41
(Discrete / UMA) Revision : 11289-1 INPUTS OUTPUTS
5V_AUX_S5
3D3V_AUX_S5
DCBATOUT 5V_S5
3D3V_S5
15V_S5
D
CPU DC/DC D
Intel CPU VT1318+VT1326 42,43

Ivy / Sandy Bridge DDRIII 1600MHz Channel A
INPUTS OUTPUTS
DDRIII Slot A 5V_S5 VCC_CORE
17W 1600MHz 14
GFX DC/DC
AMD PCIe x 8 DDRIII 1600MHz Channel B
VT1318+VT1323 44
VRAM(GDDR5) GDDR5 DDRIII Slot B
INPUTS OUTPUTS
128M x 16b x 4(1GB) Thames Pro 1600MHz 15
5V_S5 VCC_GFXCORE
88,89
83.84,85,86,87 BGA1023 SYSTEM DC/DC
4,5,6,7,8,9,10 VT386
INPUTS OUTPUTS
5V_S5 1D05V_PCH
VCCP_CPU 45
FDIx4x2 DMIx4
SYSTEM DC/DC
VT385(DIS)/RT9026
Mini-Card VT386(UMA)/RT9026
TMDS *1
Intel PCIE x 1 USB2.0 x 1
HDMI 51 802.11a/b/g/n
PCH INPUTS OUTPUTS
BT V4.0 combo 65
1D5V_S3
Panther Point DCBATOUT 0D75V_S0
DDR_VREF_S3 46
LVDS 26
C
LCD 49 Mini-Card SYSTEM DC/DC C
BGA989 USB2.0 x 1 SATA GENIII x 1 SIM RT8068A 47
WWAN mSATA 66
66
INPUTS OUTPUTS
3D3V_S5 1D8V_S0
Daughter Board
Camera 49 USB2.0 x 1
HM77
SYSTEM DC/DC
Internal Digital MIC Codec APL5916 48
14 USB 2.0/1.1 ports HDA IDT Combo Jack INPUTS OUTPUTS
4 USB 3.0 ports 92HD94 VCCP_CPU 0D85_S0
10/100 Lan High Definition Audio VGA DC/DC

RJ45 ATHEROS PCIE x 1 6 SATA ports VT358 92
59 AR8162 31
8 PCIE ports INPUTS OUTPUTS
LPC I/F 5V_S5 VGA_CORE
2CH Speaker
ACPI 4.0a VGA DC/DC
( 2W, 4ohm /channel ) 93
APL5930
Left side USB3.0 x 1 INPUTS OUTPUTS
26
1D5V_S3 1V_VGA_S0
USB3.0 / PowerShare USB3.0 Redriver Right side Switches

USB3.0 x 1
TI Debug Port INPUTS OUTPUTS
USB PowerShare
62
USB2.0 x 1 SN65LVPE502RGER USB 3.0 1D5V_S3
5V_S5
1D5V_S0
5V_S0
TI 3D3V_S5 3D3V_S0
TPS2541A 62 USB2.0 x 1 3D3V_S5
3D3V_S5
3D3V_WLAN_AOAC
3D3V_VGA_S0
1D8V_S0 1D8V_VGA_S0
B 1D5V_S3 1D5V_VGA_S0 B
LPC BUS
CardReader Connector
LPC debug port UMA/Discrete
71
USB2.0 x 1 Realtek SD/SDHC/SDXC/SD UHS-I
RTS5179 MMC/MMC+, MS/MS Pro PCB LAYER
17,18,19,20,21,22,23,24,25
L1:Top L5:VCC
L2:GND L6:Signal
Thermal L3:Signal L7:GND
NUVOTON SMBUS L4:Signal L8:Bottom
SATA GenIII x 1 HDD
NCT7718W 28 KBC 56
Fan Control NUVOTON SPI

GMT NPCE885P SATA GenII x 1
G991P11U 28 27 ODD 56
PS2
Flash ROM
8MB 60
Int. Touch I 2C
KB69 PAD69
A A
DMB40
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Block Diagram
*1: Transition minimized differential signaling A2
BMW Z4 DIS A00
Date: Friday, March 30, 2012 Sheet 2 of 105
5 4 3 2 1
A B C D E
PCH Strapping Chief River Schematic Checklist Rev.0_72 Sandy & Ivy Bridge Compatibility Chief River Schematic Checklist Rev.0_xx
Name Schematics Notes Pin Name Configuration Schematic Notes
SPKR The signal has a weak internal pull-down. Sandy Bridge + Ivy Bridge DDR3 VREF, M1 and M3 function are required.
If the signal is sampled high, this indicates that the system is strapped to the
"No Reboot" mode (Panther Point will disable the TCO Timer system reboot feature). DDR3 VREF
Ivy Bridge No change.
4 INIT3_3V# Weak internal pull-up. Leave as "No Connect". 4
INTVRMEN Integrated 1 V VRMs is enabled when high, External when low.
Connect DF_TVS signal of the PCH to PROC_SELECT# of the processor
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. Sandy Bridge + Ivy Bridge through a 1K5% series resistor. PROC_SELECT# also needs a 2.2K5%
GNT2#/GPIO53 Mobile: Used as GPIO only PROC_SELECT# pull up resistor to PCH VccDFTERM rail.
GNT1#/GPIO51 Pull-up resistors are not required on these signals. &
If pull-ups are used, they should be tied to the Vcc3_3power rail. DF_TVS
DF_TVS DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms 5% resistor.
HAD_DOCK_EN# This signal controls the external Intel HD Audio docking isolation logic. This is
/GPIO[33] an active-low-signal. When deasserted the external docking switch is in isolate mode. The POR for Ivy Bridge mobile parts is now 1.05 V. There is no
When asserted the external docking switch electrically connects the Intel HD Audio Sandy Bridge + Ivy Bridge longer a need for a separate VR for the processor at 1.0 V and
dock signals to the corresponding Panther Point signals. This signal can instead VCCIO_SEL the PCH at 1.05 V. A single VR may be shared for both.
be used as GPIO33.
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
GPIO15 Low (0) Sandy Bridge + Ivy Bridge VCCSA[0:1] are the select pin of VCCSA's power control.
Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality
High (1) VCCSA_VID[0:1]
Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality Ivy Bridge No change.
3 3
Power Plane Processor Strapping Chief River Schematic Checklist Rev.0_72
Configuration (Default value for each bit is Default POP
Power Plane Voltage Actice Status Description Pin Name Strap Description 1 unless specified otherwise) Value Value
5V_S0 5V
3D3V_S0 3.3V CFG[2] PCI-Express Static 1: Normal Operation.
1D8V_S0 1.8V Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1 0
1D5V_S0 1.5V
1D05V_VTT 1.05V Disabled - No Physical Display Port attached to
1V_S0 1V CFG[4] 1: Embedded DisplayPort.
0D85V_S0 0.85V S0 CPU Core Rail 1 1
Graphics Core Rail Enabled - An external Display Port device is
0D75V_S0 0.75V 0: connectd to the EMBEDDED display Port
VCC_CORE 0.3V to 1.3V
VCC_GFXCORE 0 to 1.25V 11: 1x16 PCI Express
CFG[6:5] PCI-Express
1D8V_VGA_S0 1.8V
3D3V_VGA_S0 3.3V Port Bifurcation
10: 2 x8 - PCI Express
1V_VGA_S0 1V Straps 11 10
01: Reserved
00: 1x8, 2x4 PCI Express
2 2
5V_USBX_S3 5V S3
1D5V_S3 1.5V
DDR_VREF_S3 0.75V
USB Table PCIE Table SATA Table
BT+ 6V-14.1V Pair Device PCIE SATA
DCBATOUT 6V-14.1V 0 USB3.0 port1, with Power Share Lane Device Pair Device
5V_S5 5V
5V_AUX_S5 5V All S states AC Brick Mode only 1 USB3.0 port2, debug port
3D3V_S5 3.3V 1 NC 0 HDD1
2 NC
3D3V_AUX_S5 3.3V 2 NC 1 mSATA
3 NC
3 NC 2 NC
4 Touch Panel
3D3V_LAN_S5 3.3V WOL_EN Legacy WOL 4 WLAN 3 NC
5 NC
5 NC 4 ODD
6 NC
3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting 6 Onboard LAN 5 NC
Deep Sleep states 7 NC
7 NC
8 WWAN
8 NC
3D3V_AUX_S5 3.3V G3, Sx Powered by Li Coin Cell 9 NC
1 in G3 and +V3ALW in Sx 10 Card reader
DMB40
1
11 WLAN
Wistron Corporation
12 CAMERA 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
13 NC
Title
Table of Content
A3 A00
BMW Z4 DIS
5 4 3 2 1
SSID = CPU
Layout Note:
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
D D
VCCP_CPU
CPU1A 1 OF 9
G3 PEG_IRCOMP_R R401 1 2 24D9R2F-L-GP
PEG_ICOMPI
[19] DMI_TXN[3:0] PEG_ICOMPO G1
DMI_TXN0 M2 G4
DMI_TXN1 DMI_RX#0 PEG_RCOMPO
P6 DMI_RX#1
DMI_TXN2 P1
DMI_TXN3 DMI_RX#2
P10 DMI_RX#3 PEG_RX#0 H22
J21
Layout Note: [19] DMI_TXP[3:0]
DMI_TXP0 N3
PEG_RX#1
B22
DMI_TXP1 DMI_RX0 PEG_RX#2
DMI trace length 2000~8000mil P7 DMI_RX1 PEG_RX#3 D21
DMI
DMI_TXP2 P3 A19
DMI_TXP3 DMI_RX2 PEG_RX#4
P11 DMI_RX3 PEG_RX#5 D17
[19] DMI_RXN[3:0] PEG_RX#6 B14
DMI_RXN0 K1 D13
DMI_TX#0 PEG_RX#7 PEG_RXN[7..0] [83]
DMI_RXN1 M8 A11 PEG_RXN7
DMI_RXN2 DMI_TX#1 PEG_RX#8 PEG_RXN6
N4 DMI_TX#2 PEG_RX#9 B10
DMI_RXN3 R2 G8 PEG_RXN5
DMI_TX#3 PEG_RX#10 PEG_RXN4
[19] DMI_RXP[3:0] PEG_RX#11 A8
DMI_RXP0 K3 B6 PEG_RXN3
DMI_RXP1 DMI_TX0 PEG_RX#12 PEG_RXN2
M7 DMI_TX1 PEG_RX#13 H8
DMI_RXP2 P4 E5 PEG_RXN1
DMI_RXP3 DMI_TX2 PEG_RX#14 PEG_RXN0
T3 DMI_TX3 PEG_RX#15 K7
PEG_RX0 K22
PEG_RX1 K19
[19] FDI_TXN[7:0] PEG_RX2 C21
C FDI_TXN0
FDI_TXN1
U7
W11
FDI0_TX#0 PEG_RX3 D19
C19
C
FDI_TXN2 FDI0_TX#1 PEG_RX4
W1 FDI0_TX#2 PEG_RX5 D16
FDI_TXN3 AA6 C13
FDI_TXN4 FDI0_TX#3 PEG_RX6
W6 D12
Layout Note: FDI_TXN5 V4
FDI1_TX#0 PEG_RX7
C11 PEG_RXP7
PEG_RXP[7..0] [83]
FDI_TXN6 FDI1_TX#1 PEG_RX8 PEG_RXP6
FDI trace length 2000~6500mil
PCI EXPRESS -- GRAPHICS

Y2 FDI1_TX#2 PEG_RX9 C9
FDI_TXN7 AC9 F8 PEG_RXP5
FDI1_TX#3 PEG_RX10
Intel(R) FDI
C8 PEG_RXP4
PEG_RX11 PEG_RXP3
[19] FDI_TXP[7:0] PEG_RX12 C5
FDI_TXP0 U6 H6 PEG_RXP2
FDI_TXP1 FDI0_TX0 PEG_RX13 PEG_RXP1
W10 FDI0_TX1 PEG_RX14 F6
FDI_TXP2 W3 K6 PEG_RXP0
FDI_TXP3 FDI0_TX2 PEG_RX15
AA7 FDI0_TX3
FDI_TXP4 W7 G22
FDI_TXP5 FDI1_TX0 PEG_TX#0
T4 FDI1_TX1 PEG_TX#1 C23
FDI_TXP6 AA3 D23
FDI_TXP7 FDI1_TX2 PEG_TX#2
AC8 FDI1_TX3 PEG_TX#3 F21
PEG_TX#4 H19
FDI_FSYNC0 AA11 C17
[19] FDI_FSYNC0 FDI0_FSYNC PEG_TX#5
FDI_FSYNC1 AC12 K15
[19] FDI_FSYNC1 FDI1_FSYNC PEG_TX#6
PEG_TX#7 F17 PEG_TXN[7..0] [83]
FDI_INT U11 F14 PEG_C_TXN7 1 2 C401 SCD1U10V2KX-5GP PEG_TXN7
[19] FDI_INT FDI_INT PEG_TX#8
A15 PEG_C_TXN6 SG
1 2 C402 SCD1U10V2KX-5GP PEG_TXN6
FDI_LSYNC0 AA10 PEG_TX#9
J14 PEG_C_TXN5 SG
[19] FDI_LSYNC0
FDI_LSYNC1 AG8 FDI0_LSYNC PEG_TX#10
H13 PEG_C_TXN4 SG
[19] FDI_LSYNC1 FDI1_LSYNC PEG_TX#11
M10 PEG_C_TXN3 SG
PEG_TX#12
F10 PEG_C_TXN2 SG
PEG_TX#13
D9 PEG_C_TXN1 SG
PEG_TX#14
J4 PEG_C_TXN0 SG
B VCCP_CPU R402 1 2 24D9R2F-L-GP DP_COMP AF3 EDP_COMPIO
PEG_TX#15 SG B
AD2 EDP_ICOMPO PEG_TX0 F22
AG11 EDP_HPD# PEG_TX1 A23
PEG_TX2 D24
PEG_TX3 E21
AG4 G19
Layout Note: AF4
EDP_AUX# PEG_TX4
B18
EDP_AUX PEG_TX5
Signal Routing Guideline: PEG_TX6 K17
eDP
EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_TX7 G17 PEG_TXP[7..0] [83]
AC3 E14 PEG_C_TXP7 1 2 C417 SCD1U10V2KX-5GP PEG_TXP7
EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils. AC4
EDP_TX#0 PEG_TX8
C15 PEG_C_TXP6 SG
1 2 C418 SCD1U10V2KX-5GP PEG_TXP6
AE11
EDP_TX#1 PEG_TX9
K13 PEG_C_TXP5 SG
AE7
EDP_TX#2 PEG_TX10
G13 PEG_C_TXP4 SG
EDP_TX#3 PEG_TX11
K10 PEG_C_TXP3 SG
AC1
PEG_TX12
G10 PEG_C_TXP2 SG
AA4
EDP_TX0 PEG_TX13
D8 PEG_C_TXP1 SG
AE10
EDP_TX1 PEG_TX14
K4 PEG_C_TXP0 SG
AE6
EDP_TX2 PEG_TX15 SG
EDP_TX3
IVY-BRIDGE-GP-NF
71.00IVY.A0U
Layout Note:
PEG trace length 1500~9000mil
A <Core Design>
A
Wistron Corporation
Title
CPU(PCIE/DMI/FDI)
A3 A00
BMW Z4 DIS
5 4 3 2 1
SSID = CPU
D CPU1B 2 OF 9
D
J3 CLK_EXP_P CLK_EXP_P [20]
BCLK CLK_EXP_N
BCLK# H2 CLK_EXP_N [20]
MISC
CLOCKS
[22] H_SNB_IVB# H_SNB_IVB# F49 RN503
PROC_SELECT# CLK_DP_P_R1
DPLL_REF_CLK AG3 4
AG1 CLK_DP_N_R2 3
TPAD14-OP-GP TP501 1 SKTOCC#_R C57
DPLL_REF_CLK# VCCP_CPU Layout Note:
PROC_DETECT# SRN1KJ-7-GP Checking the connector pin's LAYOUT
VCCP_CPU
TPAD14-OP-GP TP502 1 H_CATERR# C49 R507
R501 CATERR# 4K99R2F-L-GP
THERMAL
1 2 H_PROCHOT# 1 2
62R2J-GP H_PECI A48 AT30 SM_DRAMRST# SM_DRAMRST# [37]

[22,27] H_PECI PECI SM_DRAMRST#
R513 BF44 SM_RCOMP_0 R506 1 2 140R2F-GP

SM_RCOMP0
DDR3
MISC
1 2 H_PROCHOT#_R C45 BE43 SM_RCOMP_1 R508 1 2 25D5R2F-GP
[27,40] H_PROCHOT# PROCHOT# SM_RCOMP1
BG43 SM_RCOMP_2 R511 1 2 200R2F-L-GP
56R2J-4-GP SM_RCOMP2
H_THERMTRIP# D45
[22] H_THERMTRIP# THERMTRIP# Layout Note:
Layout Note: Signal Routing Guideline:
N53 XDP_PRDY# XDP_PRDY# [71] SM_RCOMP keep routing length less than 500 mils.
PRDY#
C R501, R513 place near to CPU PREQ# N55 XDP_PREQ# XDP_PREQ# [71] Trace width = 15mil C
L56 XDP_TCLK
TCK XDP_TMS VCCP_CPU
TMS L55
PWR MANAGEMENT
J58 XDP_TRST#
TRST#
JTAG & BPM

[19] H_PM_SYNC H_PM_SYNC C48 M60 XDP_TDI
PM_SYNC TDI
X03 2/6 TDO L59 XDP_TDO RN501
R504 XDP_TDI 1 8
0R0402-PAD-2-GP XDP_TMS 2 7
1 2 H_CPUPW RGD_R B46 XDP_TDO 3 6
[22] H_CPUPW RGD UNCOREPWRGOOD
K58 XDP_DBRESET# XDP_DBRESET# [19] 4
XDP 5
DBR#
1 R503 2
10KR2J-3-GP SRN51J-1-GP
[37] VDDPW RGOOD VDDPW RGOOD BE45 G58 XDP_BPM0 XDP_BPM0 [71]
SM_DRAMPWROK BPM#0 XDP_BPM1 RN502
BPM#1 E55 XDP_BPM1 [71]
E59 XDP_BPM2 XDP_BPM2 [71] XDP_TRST# 1 4
BPM#2 XDP_BPM3 XDP_TCLK
G55 2 3
BPM#3
G59 XDP_BPM4
XDP_BPM3
XDP_BPM4
[71]
[71]
XDP
BUF_CPU_RST# BPM#4 XDP_BPM5 SRN51J-GP
[18,27,31,65,66,71] PLT_RST# 1 2 D44 RESET# BPM#5 H60 XDP_BPM5 [71]
J59 XDP_BPM6 XDP_BPM6 [71]
BPM#6
1
R510 J61 XDP_BPM7 XDP_BPM7 [71]

BPM#7
1
1K5R2F-2-GP
R509 C501
698R2F-GP DY SC220P50V2KX-3GP
2
2
IVY-BRIDGE-GP-NF
71.00IVY.A0U
B Layout Note:
B
C501 place near to CPU
A <Core Design>
A
Wistron Corporation
Title
CPU(THERMAL/CLOCK/PM)
A3 A00
BMW Z4 DIS
5 4 3 2 1
SSID = CPU
CPU1D 4 OF 9
CPU1C 3 OF 9
M_B_DQ[63:0]
M_A_DQ[63:0] [15] M_B_DQ[63:0]
M_B_DQ0 AL4
[14] M_A_DQ[63:0] SB_DQ0
D M_A_DQ0 AG6 M_B_DQ1 AL1 BA34 D
M_A_DQ1 SA_DQ0 M_B_DQ2 SB_DQ1 SB_CK0 M_B_DIMB_CLK_DDR0 [15]
AJ6 SA_DQ1 SA_CK0 AU36 M_A_DIMA_CLK_DDR0 [14] AN3 SB_DQ2 SB_CK#0 AY34 M_B_DIMB_CLK_DDR#0 [15]
M_A_DQ2 AP11 AV36 M_B_DQ3 AR4 AR22
M_A_DQ3 SA_DQ2 SA_CK#0 M_A_DIMA_CLK_DDR#0 [14] M_B_DQ4 SB_DQ3 SB_CKE0 M_B_DIMB_CKE0 [15]
AL6 SA_DQ3 SA_CKE0 AY26 M_A_DIMA_CKE0 [14] AK4 SB_DQ4
M_A_DQ4 AJ10 M_B_DQ5 AK3
M_A_DQ5 SA_DQ4 M_B_DQ6 SB_DQ5
AJ8 SA_DQ5 AN4 SB_DQ6
M_A_DQ6 AL8 M_B_DQ7 AR1
AL7 SA_DQ7 AU4 SB_DQ8
M_A_DQ8 AR11 M_B_DQ9 AT2 BA36
M_A_DQ9 SA_DQ8 M_B_DQ10 SB_DQ9 SB_CK1 M_B_DIMB_CLK_DDR1 [15]
AP6 SA_DQ9 SA_CK1 AT40 M_A_DIMA_CLK_DDR1 [14] AV4 SB_DQ10 SB_CK#1 BB36 M_B_DIMB_CLK_DDR#1 [15]
M_A_DQ10 AU6 AU40 M_B_DQ11 BA4 BF27
M_A_DQ11 SA_DQ10 SA_CK#1 M_A_DIMA_CLK_DDR#1 [14] M_B_DQ12 SB_DQ11 SB_CKE1 M_B_DIMB_CKE1 [15]
AV9 SA_DQ11 SA_CKE1 BB26 M_A_DIMA_CKE1 [14] AU3 SB_DQ12
M_A_DQ12 AR6 M_B_DQ13 AR3
AP8 SA_DQ13 AY2 SB_DQ14
M_A_DQ14 AT13 M_B_DQ15 BA3
AU13 SA_DQ15 BE9 SB_DQ16
M_A_DQ16 BC7 M_B_DQ17 BD9 BE41
M_A_DQ17 SA_DQ16 M_B_DQ18 SB_DQ17 SB_CS#0 M_B_DIMB_CS#0 [15]
BB7 SA_DQ17 SA_CS#0 BB40 M_A_DIMA_CS#0 [14] BD13 SB_DQ18 SB_CS#1 BE47 M_B_DIMB_CS#1 [15]
M_A_DQ18 BA13 BC41 M_B_DQ19 BF12
M_A_DQ19 SA_DQ18 SA_CS#1 M_A_DIMA_CS#1 [14] M_B_DQ20 SB_DQ19
BB11 SA_DQ19 BF8 SB_DQ20
M_A_DQ20 BA7 M_B_DQ21 BD10
BA9 SA_DQ21 BD14 SB_DQ22
M_A_DQ22 BB9 M_B_DQ23 BE13
AY13 SA_DQ23 BF16 SB_DQ24 SB_ODT0 AT43 M_B_DIMB_ODT0 [15]
M_A_DQ24 AV14 AY40 M_B_DQ25 BE17 BG47
M_A_DQ25 SA_DQ24 SA_ODT0 M_A_DIMA_ODT0 [14] M_B_DQ26 SB_DQ25 SB_ODT1 M_B_DIMB_ODT1 [15]
AR14 SA_DQ25 SA_ODT1 BA41 M_A_DIMA_ODT1 [14] BE18 SB_DQ26
M_A_DQ26 AY17 M_B_DQ27 BE21
AR19 SA_DQ27 BE14 SB_DQ28
M_A_DQ28 BA14 M_B_DQ29 BG14
C M_A_DQ29 SA_DQ28 M_B_DQ30 SB_DQ29 C
AU14 SA_DQ29 BG18 SB_DQ30 M_B_DQS#[7:0] [15]
M_A_DQ30 BB14 M_A_DQS#[7:0] [14] M_B_DQ31 BF19 AL3 M_B_DQS#0
M_A_DQ31 SA_DQ30 M_A_DQS#0 M_B_DQ32 SB_DQ31 SB_DQS#0 M_B_DQS#1
BB17 SA_DQ31 SA_DQS#0 AL11 BD50 SB_DQ32 SB_DQS#1 AV3
M_A_DQ32 BA45 AR8 M_A_DQS#1 M_B_DQ33 BF48 BG11 M_B_DQS#2
M_A_DQ33 SA_DQ32 SA_DQS#1 M_A_DQS#2 M_B_DQ34 SB_DQ33 SB_DQS#2 M_B_DQS#3
AR43 SA_DQ33 SA_DQS#2 AV11 BD53 SB_DQ34 SB_DQS#3 BD17
M_A_DQ34 AW48 AT17 M_A_DQS#3 M_B_DQ35 BF52 BG51 M_B_DQS#4
M_A_DQ35 SA_DQ34 SA_DQS#3 M_A_DQS#4 M_B_DQ36 SB_DQ35 SB_DQS#4 M_B_DQS#5
BC48 SA_DQ35 SA_DQS#4 AV45 BD49 SB_DQ36 SB_DQS#5 BA59
M_A_DQ36 BC45 AY51 M_A_DQS#5 M_B_DQ37 BE49 AT60 M_B_DQS#6
SA_DQ36 SA_DQS#5 SB_DQ37 SB_DQS#6
DDR SYSTEM MEMORY B

M_A_DQ37 AR45 AT55 M_A_DQS#6 M_B_DQ38 BD54 AK59 M_B_DQS#7
SA_DQ37 SA_DQS#6 SB_DQ38 SB_DQS#7
DDR SYSTEM MEMORY A
M_A_DQ38 AT48 AK55 M_A_DQS#7 M_B_DQ39 BE53

M_A_DQ39 SA_DQ38 SA_DQS#7 M_B_DQ40 SB_DQ39
AY48 SA_DQ39 BF56 SB_DQ40
M_A_DQ40 BA49 M_B_DQ41 BE57
AV49 SA_DQ41 BC59 SB_DQ42
M_A_DQ42 BB51 M_B_DQ43 AY60
AY53 SA_DQ43 BE54 SB_DQ44
M_A_DQ44 BB49 M_A_DQS[7:0] [14] M_B_DQ45 BG54 M_B_DQS[7:0] [15]
M_A_DQ45 SA_DQ44 M_A_DQS0 M_B_DQ46 SB_DQ45 M_B_DQS0
AU49 SA_DQ45 SA_DQS0 AJ11 BA58 SB_DQ46 SB_DQS0 AM2
M_A_DQ46 BA53 AR10 M_A_DQS1 M_B_DQ47 AW59 AV1 M_B_DQS1
M_A_DQ47 SA_DQ46 SA_DQS1 M_A_DQS2 M_B_DQ48 SB_DQ47 SB_DQS1 M_B_DQS2
BB55 SA_DQ47 SA_DQS2 AY11 AW58 SB_DQ48 SB_DQS2 BE11
M_A_DQ48 BA55 AU17 M_A_DQS3 M_B_DQ49 AU58 BD18 M_B_DQS3
AV56 SA_DQ49 SA_DQS4 AW45 AN61 SB_DQ50 SB_DQS4 BE51
M_A_DQ50 AP50 AV51 M_A_DQS5 M_B_DQ51 AN59 BA61 M_B_DQS5
AP53 SA_DQ51 SA_DQS6 AT56 AU59 SB_DQ52 SB_DQS6 AR59
M_A_DQ52 AV54 AK54 M_A_DQS7 M_B_DQ53 AU61 AK61 M_B_DQS7
M_A_DQ53 SA_DQ52 SA_DQS7 M_B_DQ54 SB_DQ53 SB_DQS7
AT54 SA_DQ53 AN58 SB_DQ54
M_A_DQ54 AP56 M_B_DQ55 AR58
AP52 SA_DQ55 AK58 SB_DQ56
M_A_DQ56 AN57 M_B_DQ57 AL58
AN53 SA_DQ57 AG58 SB_DQ58
B M_A_DQ58 M_B_DQ59 B
AG56 SA_DQ58 AG59 SB_DQ59
M_A_DQ59 AG53 M_B_DQ60 AM60
M_A_DQ60 SA_DQ59 M_B_DQ61 SB_DQ60 M_B_A0 M_B_A[15:0] [15]
AN55 SA_DQ60 M_A_A[15:0] [14] AL59 SB_DQ61 SB_MA0 BF32
M_A_DQ61 AN52 BG35 M_A_A0 M_B_DQ62 AF61 BE33 M_B_A1
M_A_DQ62 SA_DQ61 SA_MA0 M_A_A1 M_B_DQ63 SB_DQ62 SB_MA1 M_B_A2
AG55 SA_DQ62 SA_MA1 BB34 AH60 SB_DQ63 SB_MA2 BD33
M_A_DQ63 AK56 BE35 M_A_A2 AU30 M_B_A3
SA_DQ63 SA_MA2 M_A_A3 SB_MA3 M_B_A4
SA_MA3 BD35 SB_MA4 BD30
AT34 M_A_A4 AV30 M_B_A5
SA_MA4 M_A_A5 SB_MA5 M_B_A6
SA_MA5 AU34 SB_MA6 BG30
BB32 M_A_A6 [15] M_B_BS0 BG39 BD29 M_B_A7
SA_MA6 M_A_A7 SB_BS0 SB_MA7 M_B_A8
[14] M_A_BS0 BD37 SA_BS0 SA_MA7 AT32 [15] M_B_BS1 BD42 SB_BS1 SB_MA8 BE30
[14] M_A_BS1 BF36 AY32 M_A_A8 [15] M_B_BS2 AT22 BE28 M_B_A9
SA_BS1 SA_MA8 M_A_A9 SB_BS2 SB_MA9 M_B_A10
[14] M_A_BS2 BA28 SA_BS2 SA_MA9 AV32 SB_MA10 BD43
BE37 M_A_A10 AT28 M_B_A11
SA_MA10 M_A_A11 SB_MA11 M_B_A12
SA_MA11 BA30 SB_MA12 AV28
BC30 M_A_A12 [15] M_B_CAS# AV43 BD46 M_B_A13
SA_MA12 M_A_A13 SB_CAS# SB_MA13 M_B_A14
[14] M_A_CAS# BE39 SA_CAS# SA_MA13 AW41 [15] M_B_RAS# BF40 SB_RAS# SB_MA14 AT26
[14] M_A_RAS# BD39 AY28 M_A_A14 [15] M_B_W E# BD45 AU22 M_B_A15
SA_RAS# SA_MA14 M_A_A15 SB_WE# SB_MA15
[14] M_A_W E# AT41 SA_WE# SA_MA15 AU26
IVY-BRIDGE-GP-NF
IVY-BRIDGE-GP-NF 71.00IVY.A0U
71.00IVY.A0U
A DMB40 A
Wistron Corporation
Title
CPU (DDR)
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CFG2
CPU1E 5 OF 9
D D
1
PEG Static Lane Reversal
R702
1KR2J-1-GP 1: Normal Operation; Lane #
[71] CFG0 CFG0 B50 N59 BCLK_ITP 1 TP721 TPAD14-OP-GP SG CFG[2] definition matches socket pin map definition
TPAD14-OP-GP TP701 CFG1 CFG0 BCLK_ITP BCLK_ITP# TP722 TPAD14-OP-GP
1 C51 N58 1
2
CFG2 CFG1 BCLK_ITP# 0:Lane Reversed
B54 CFG2
TPAD14-OP-GP TP702 1 CFG3 D53
TPAD14-OP-GP TP703 CFG4 CFG3
1 A51 CFG4 RSVD30 N42
CFG5 C53 L42
CFG6 CFG5 RSVD31
C55 CFG6 RSVD32 L45
TPAD14-OP-GP TP704 1 CFG7 H49 L47
TPAD14-OP-GP TP705 CFG8 CFG7 RSVD33
1 A55 CFG8
TPAD14-OP-GP TP706 1 CFG9 H51
1 K49 CFG10 RSVD34 M13
TPAD14-OP-GP TP708 1 CFG11 K53 M14 Display Port Presence Strap
1 F53 CFG12 RSVD36 U14
TPAD14-OP-GP TP710 1 CFG13 G53 W14 1: Disabled; No Physical Display Port
1 L51 CFG14 RSVD38 P13 CFG[4] attached to Embedded Display Port
TPAD14-OP-GP TP712 1 CFG15 F51 CFG15
TPAD14-OP-GP TP713 1 CFG16 D52 0: Enabled; An external Display Port device is
1 L53 CFG17 RSVD39 AT49 connected to the Embedded Display Port
RSVD40 K24
TPAD14-OP-GP TP715 1VCC_VAL_SENSE H43
RESERVED
TPAD14-OP-GP TP716 VCC_VAL_SENSE
1VSS_VAL_SENSE K43 VSS_VAL_SENSE RSVD41 AH2
RSVD42 AG13
RSVD43 AM14
TPAD14-OP-GP TP717 1VAXG_VAL_SENSE H45 AM15
TPAD14-OP-GP TP718 VAXG_VAL_SENSE RSVD44
C 1VSSAXG_VAL_SENSE K45 VSSAXG_VAL_SENSE
CFG5 C
N50 CFG6 PCIE Port Bifurcation Straps

TPAD14-OP-GP TP719 RSVD45
1VCC_DIE_SENSE F48 VCC_DIE_SENSE
1
TPAD14-OP-GP TP720 1VSS_DIE_SENSE G48 RSVD47 R701 R704 CFG[6:5] 11: 1x16 PCI Express
H48
K48
RSVD6 DY 1KR2J-1-GP SG 1KR2J-1-GP
10: 2 x8 - PCI Express
RSVD7 TP_DC_TEST_A4 TP723 TPAD14-OP-GP
A4 1
2
DC_TEST_A4
DC_TEST_C4 C4 01: Reserved
BA19 D3 DC_TEST_C4_D3
RSVD8 DC_TEST_D3 TP_DC_TEST_D1 TP724 TPAD14-OP-GP
AV19 RSVD9 DC_TEST_D1 D1 1 00: 1x8, 2x4 PCI Express
AT21 A58 TP_DC_TEST_A58 1 TP725 TPAD14-OP-GP
RSVD10 DC_TEST_A58
BB21 RSVD11 DC_TEST_A59 A59
BB19 C59 TP_DC_TEST_A59_C59
RSVD12 DC_TEST_C59
AY21 RSVD13 DC_TEST_A61 A61
BA22 C61 TP_DC_TEST_A61_C61
RSVD14 DC_TEST_C61 TP_DC_TEST_D61 TP726 TPAD14-OP-GP
AY22 RSVD15 DC_TEST_D61 D61 1
AU19 RSVD16 DC_TEST_BD61 BD61 TP_DC_TEST_BD61 1 TP727 TPAD14-OP-GP
AU21 RSVD17 DC_TEST_BE61 BE61
BD21 RSVD18 DC_TEST_BE59 BE59 TP_DC_TEST_BE59_BE61
BD22 RSVD19 DC_TEST_BG61 BG61
BD25 RSVD20 DC_TEST_BG59 BG59 DC_TEST_BG59_BG61
BD26 RSVD21 DC_TEST_BG58 BG58 TP_DC_TEST_BG58 1 TP728 TPAD14-OP-GP
BG22 BG4 TP_DC_TEST_BG4 1 TP729 TPAD14-OP-GP
RSVD22 DC_TEST_BG4
BE22 RSVD23 DC_TEST_BG3 BG3
BG26 BE3 DC_TEST_BE3_BG3
RSVD24 DC_TEST_BE3
BE26 RSVD25 DC_TEST_BG1 BG1
BF23 BE1 DC_TEST_BE1_BG1
B RSVD26 DC_TEST_BE1 TP_DC_TEST_BD1 TP730 TPAD14-OP-GP B
BE24 RSVD27 DC_TEST_BD1 BD1 1
IVY-BRIDGE-GP-NF
71.00IVY.A0U
DMB40
A A
Wistron Corporation
Title
CPU (RESERVED)
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1F POWER 6 OF 9
VCCP_CPU
A00 3/30 8.5A

X01 12/21 VCC_CORE AF46
VCCIO1
X01 12/16 AG48
X01 12/15 33A VCCIO3
VCCIO4
AG50 Voltage Rail Voltage(V) Iccmax(A)
C862
SC1U6D3V2KX-GP
C864
SC1U6D3V2KX-GP
C865
SC1U6D3V2KX-GP
C866
SC1U6D3V2KX-GP
C869
SC1U6D3V2KX-GP
C867
SC1U6D3V2KX-GP
C868
SC1U6D3V2KX-GP
C870
SC1U6D3V2KX-GP
X01 12/09 A26 AG51
1
VCC1 VCCIO5
A29 AJ17
VCC2 VCCIO6
A31 AJ21 VCC_CORE(ULV) 0.3~1.52 33
VCC_CORE A34
VCC3 VCCIO7
AJ25
DY DY DY DY DY DY DY
2
VCC4 VCCIO8
A35
VCC5 VCCIO9
AJ43 VAXG(ULV) 0~1.52 33
D A38 AJ47 D
VCC6 VCCIO10
A39
VCC7 VCCIO11
AK50 VCCIO 1.05 8.5
A42 AK51
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VCC8 VCCIO12
C801
C821
C822
C804
C805
C806
C807
C808
C809
C810
C26 AL14 VDDQ 1.5 5
1
1
VCC9 VCCIO13
C27 AL15
VCC10 VCCIO14
C32 AL16 VCCSA 0.9 4
DY C34
VCC11 VCCIO15
AL20
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
2
2
VCC12 VCCIO16
C874
SC1U6D3V2KX-GP
C876
SC1U6D3V2KX-GP
C875
SC1U6D3V2KX-GP
C877
SC1U6D3V2KX-GP
C878
SC1U6D3V2KX-GP
C37 AL22 VCCPLL 1.8 1.2
DY
1
VCC13 VCCIO17
C871
C872
C873
C39 AL26
VCC14 VCCIO18
C42 AL45
D27
VCC15 VCCIO19
AL48 DY DY DY DY
2
VCC16 VCCIO20
D32 AM16
VCC17 VCCIO21
D34 AM17
VCC18 VCCIO22
D37 AM21
VCC19 VCCIO23
D39 AM43
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PEG IO AND DDR IO

VCC20 VCCIO24
C823
C824
C828
D42 AM47
SC22U6D3V5MX-2GP
1
1
VCC21 VCCIO25
C811
C812
C813
C816
C818
C820
E26 AN20
VCC22 VCCIO26
C863
SC10U6D3V3MX-GP
C879
SC10U6D3V3MX-GP
C880
SC10U6D3V3MX-GP
C881
SC10U6D3V3MX-GP
C882
SC10U6D3V3MX-GP
E28 AN42
DY
1
VCC23 VCCIO27
E32 AN45
2
2
VCC24 VCCIO28
E34
VCC25 VCCIO29
AN48 Added, cause the DY DY
E37 1.05V far away CPU
2
VCC26
E38
VCC27
CORE SUPPLY
F25
VCC28
F26
VCC29 VCCP_CPU
F28
VCC30
F32
VCC31
F34
VCC32
F37 AA14
VCC33 VCCIO30
F38 AA15
VCC34 VCCIO31
F42 AB17
SC10U6D3V3MX-GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VCC35 VCCIO32
C885
SC1U6D3V2KX-GP
C883
SC1U6D3V2KX-GP
C884
SC1U6D3V2KX-GP
C886
SC1U6D3V2KX-GP
C888
SC1U6D3V2KX-GP
C887
SC1U6D3V2KX-GP
C889
SC1U6D3V2KX-GP
C890
SC1U6D3V2KX-GP
C891
SC1U6D3V2KX-GP
C892
SC1U6D3V2KX-GP
G42 AB20
1
1
VCC36 VCCIO33
C825
C830
C831
C832
C843
C847
H25 AC13
VCC37 VCCIO34
H26 AD16
DY H28
VCC38 VCCIO35
AD18 DY DY DY DY
2
2
VCC39 VCCIO36
H29 AD21
VCC40 VCCIO37
H32 AE14
VCC41 VCCIO38
H34 AE15
VCC42 VCCIO39
H35 AF16
VCC43 VCCIO40
H37 AF18
VCC44 VCCIO41
H38 AF20
VCC45 VCCIO42
H40 AG15
VCC46 VCCIO43
C895
SC10U6D3V3MX-GP
C897
SC10U6D3V3MX-GP
C893
SC10U6D3V3MX-GP
C894
SC10U6D3V3MX-GP
C896
SC10U6D3V3MX-GP
C J25 AG16 C
SC10U6D3V5KX-1GP
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
1
VCC47 VCCIO44
SC10U6D3V5KX-1GP
J26 AG17
SC10U6D3V3MX-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCC48 VCCIO45
C814
C815
C817
C827
C840
J28 AG20
DY DY DY DY
1
VCC49 VCCIO46
C802
C803
C829
J29 AG21
2
VCC50 VCCIO47
DY DY DY DY DY DY DY J32
VCC51 VCCIO48
AJ14
J34 AJ15
2
VCC52 VCCIO49
J35
VCC53
J37
VCC54
J38
VCC55
J40
VCC56
J42
VCC57
K26 W16
VCC58 VCCIO50
K27 W17
VCC59 VCCIO51
K29
VCC60
K32
VCC61
K34
VCC62
K35
VCC63
K37
VCC64
K39
VCC66 H_SNB_IVB#_PWRCTRL TP801 TPAD14-OP-GP
K42 BC22 1
VCC67 VCCIO_SEL
L25
VCC68
L28
VCC69
X03 2/6
L33
VCC70
L36
VCC71 +V1.05S_VCCPQE_R R812 VCCP_CPU VCCP_CPU
L40
VCC72 0R0402-PAD-2-GP
N26
VCC73
QUIET
RAILS
N30 AM25 1 2
VCC74 VCCPQE1
N34 AN22
Layout Note:
1
VCC75 VCCPQE2
N38
1
VCC76 C826 R803, R804, R805 need close to CPU
SC1U6D3V2KX-GP R805 R804
Alert# signal must be routed between the Clock and Data
2
75R2F-2-GP 130R2F-1-GP
lines to reduce the cross talk between them
R803
2
43R2J-GP
A44 H_CPU_SVIDALRT# 1 2
VIDALERT# VR_SVID_ALERT# [42]
B43 H_CPU_SVIDCLK
VIDSCLK H_CPU_SVIDCLK [42] Need place Pull Hi
SVID
C44 H_CPU_SVIDDAT
VIDSOUT H_CPU_SVIDDAT [42]
at IMVP page
VCC_CORE
B B
Layout Note:
1
R801 1. PH/PL resisors place close CPU
100R2F-L1-GP-U 2. SENSE signal recommend differential routing
2
F43 VCCSENSE
SENSE LINES
VCC_SENSE VCCSENSE [42]
G43 VSSSENSE VSSSENSE [42]
VSS_SENSE
1
VCCP_CPU
R802
100R2F-L1-GP-U
1
AN16
VCCIO_SENSE R807
AN17
2
VSS_SENSE_VCCIO
10R2F-L-GP
VCCIO_SENSE [45]
2
VSSIO_SENSE [45]
1
IVY-BRIDGE-GP-NF
71.00IVY.A0U R806
10R2F-L-GP
Layout Note:
2
1. PH/PL resisors place close CPU
2. SENSE signal recommend differential routing
A A
<Core Design>
Wistron Corporation
Title
CPU (VCC_CORE)
A2 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = CPU
Layout Note:
X01 12/09 X01 12/15
CPU1G POWER 7 OF 9
+V_SM_VREF_CNT should have 10 mil trace width Voltage Rail Voltage(V) Iccmax(A)
+V_SM_VREF_CNT VCC_CORE(ULV) 0.3~1.52 33

VCC_GFXCORE 33A
SM_VREF
AY43 VAXG(ULV) 0~1.52 33
AA46
VREF
VAXG1 RN902
AB47 VCCIO 1.05 8.5
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VAXG2
BE7 DDR_WR_VREFA
C901
C902
C903
C904
C905
D AB50 3 2 D
1
VAXG3 SA_DIMM_VREFDQ
AB51 BG7 DDR_WR_VREFB 4 1 VDDQ 1.5 5
AB52
VAXG4 SB_DIMM_VREFDQ DY
VAXG5
AB53 VCCSA 0.9 6
2
VAXG6 SRN1KJ-7-GP
AB55
VAXG7
AB56
VAXG8
VCCPLL 1.8 1.2
AB58
VAXG9
AB59
VAXG10
AC61
VAXG11 1D5V_S0
AD47
VAXG12
AD48
AD50
VAXG13 5A
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VAXG14
C955
C923
C920
C921
C922
C919
C911
AD51 AJ28
- 1.5V RAILS
1
1
VAXG15 VDDQ1
AD52 AJ33
VAXG16 VDDQ2
AD53 AJ36
VAXG17 VDDQ3
AD55 AJ40
1
VAXG18 VDDQ4
C944
SC1U6D3V2KX-GP
C945
SC1U6D3V2KX-GP
C946
SC1U6D3V2KX-GP
C947
SC1U6D3V2KX-GP
C948
SC1U6D3V2KX-GP
C949
SC1U6D3V2KX-GP
C950
SC1U6D3V2KX-GP
C951
SC1U6D3V2KX-GP
C952
SC1U6D3V2KX-GP
C953
SC1U6D3V2KX-GP
AD56 AL30
AD58
VAXG19 VDDQ5
AL34 DY
AD59
VAXG20 VDDQ6
AL38
DY DY DY DY DY DY DY
2
VAXG21 VDDQ7
AE46 AL42
VAXG22 VDDQ8
N45 AM33
VAXG23 VDDQ9
P47 AM36
VAXG24 VDDQ10
P48 AM40
VAXG25 VDDQ11
P50 AN30
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VAXG26 VDDQ12
C906
C907
C908
C909
C910
P51 AN34
1
VAXG27 VDDQ13
P52 AN38
VAXG28 VDDQ14
P53 AR26
DDR3
VAXG29 VDDQ15
P55 AR28
GRAPHICS
2
1
VAXG30 VDDQ16
C936
SC10U6D3V3MX-GP
C937
SC10U6D3V3MX-GP
C938
SC10U6D3V3MX-GP
C939
SC10U6D3V3MX-GP
C940
SC10U6D3V3MX-GP
C941
SC10U6D3V3MX-GP
C942
SC10U6D3V3MX-GP
C943
SC10U6D3V3MX-GP
P56 AR30
P61
VAXG31 VDDQ17
AR32
DY DY
T48
VAXG32 VDDQ18
AR34 DY DY DY
2
VAXG33 VDDQ19
T58 AR36
VAXG34 VDDQ20
T59 AR40
VAXG35 VDDQ21
T61 AV41
VAXG36 VDDQ22
U46 AW26
VAXG37 VDDQ23
V47 BA40
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VAXG38 VDDQ24
V48 BB28
VAXG39 VDDQ25
1 V50 BG33
1
VAXG40 VDDQ26
C912
C913
C914
C915
C916
C917
C918
V51
VAXG41
V52
DY DY DY DY DY DY V53
VAXG42
DY
2
2
VAXG43
C V55 C
VAXG44
V56
VAXG45
V58
VAXG46
V59
VAXG47
W50
VAXG48
W51
VAXG49
W52
VAXG50
W53
VAXG51
W55
VAXG52
W56
VCC_GFXCORE VAXG53
W61
VAXG54
Y48
VAXG55
Y61
VAXG56
X03 2/6
Layout Note:
1
1. PH/PL resisors place close CPU R903 +V1.5S_VCCD_Q 1D5V_S0
2. SENSE signal recommend differential routing 100R2F-L1-GP-U R909
0R0402-PAD-2-GP
QUIET RAILS
AM28 1 2
SENSE
LINES
2
VCC_AXG_SENSE VCCDQ1
[42] VCC_AXG_SENSE F45 AN26
VSS_AXG_SENSE VAXG_SENSE VCCDQ2
[42] VSS_AXG_SENSE G45
1
VSSAXG_SENSE
C954
SC1U6D3V2KX-GP
1
R904
2
100R2F-L1-GP-U
1.8V RAIL
2
BB3
VCCPLL1
BC1
1D8V_S0 VCCPLL2
BC4
1.2A VCCPLL3
BC43 TP_VDDQ_SENSE 1 TP901 TPAD14-OP-GP

1
VDDQ_SENSE
C924
SC1U6D3V2KX-GP
C925
SC1U6D3V2KX-GP
BA43 TP_VDDQ_VSS 1 TP902 TPAD14-OP-GP

VSS_SENSE_VDDQ
SENSE LINES
VCCSA Power Select
DY L17
2
VCCSA1
L21
VCCSA2
N16
VCCSA3
Voltage(V) VID[0] VID[1]
N20
0D85V_S0 VCCSA4
N22
6A
SA RAIL
B VCCSA5 B
P17
VCCSA6
0.9 0 0
P20 U10 VCCSA_SENSE [48]
VCCSA7 VCCSA_SENSE
R16
1
VCCSA8
C930
SC10U6D3V3MX-GP
C929
SC10U6D3V3MX-GP
C928
SC10U6D3V3MX-GP
C927
SC10U6D3V3MX-GP
C926
SC10U6D3V3MX-GP
R18
VCCSA9
0.85 0 1
R21
DY DY DY DY DY U15
VCCSA10
VCCSA VID
2
VCCSA11
V16 0.775 1 0
VCCSA12 VCCSA_SEL0
V17 D48
VCCSA13 VCCSA_VID0 VCCSA_SEL0 [48]
lines
V18 D49 VCCSA_SEL1
VCCSA14 VCCSA_VID1 VCCSA_SEL1 [48]
V21 0.75 1 1
2
1
VCCSA15
W20
VCCSA16 RN901
1
1
C935
SC1U6D3V2KX-GP
C934
SC1U6D3V2KX-GP
C933
SC1U6D3V2KX-GP
C932
SC1U6D3V2KX-GP
C931
SC1U6D3V2KX-GP
SRN1KJ-7-GP
DY DY DY
2
IVY-BRIDGE-GP-NF
3
4
71.00IVY.A0U
A A
<Core Design>
Wistron Corporation
Title
CPU (VCC_GFXCORE)
A2 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1H 8 OF 9
CPU1I 9 OF 9
A13 VSS1 VSS91 AM38 BG17 VSS181 VSS250 M4

A25 VSS4 VSS94 AM45 BG28 VSS184 VSS253 N1
D A28 VSS5 VSS95 AM48 BG37 VSS185 VSS254 N17 D
A33 VSS6 VSS96 AM58 BG41 VSS186 VSS255 N21
A37 VSS7 VSS97 AN1 BG45 VSS187 VSS256 N25
A53 VSS11 VSS101 AN33 C29 VSS191 VSS260 N40
A9 VSS12 VSS102 AN36 C35 VSS192 VSS261 N43
AA1 VSS13 VSS103 AN40 C40 VSS193 VSS262 N47
AA13 VSS14 VSS104 AN43 D10 VSS194 VSS263 N48
AA53 VSS18 VSS108 AP10 D26 VSS198 VSS267 N61
AA55 VSS19 VSS109 AP51 D29 VSS199 VSS268 P14
AB16 VSS22 VSS112 AR13 D40 VSS202 VSS271 P21
AB18 AR17 D43 P58
AB21
AB48
VSS23
VSS24
VSS25
VSS113
VSS114
VSS115
AR21
AR41
D46
D50
VSS203
VSS204
VSS205
VSS VSS272
VSS273
VSS274
P59
P9
AB61 VSS26 VSS116 AR48 D54 VSS206 VSS275 R17
AC10 VSS27 VSS117 AR61 D58 VSS207 VSS276 R20
AC14 VSS28 VSS118 AR7 D6 VSS208 VSS277 R4
AC46 VSS29 VSS119 AT14 E25 VSS209 VSS278 R46
AC6 VSS30 VSS120 AT19 E29 VSS210 VSS279 T1
AD17 VSS31 VSS121 AT36 E3 VSS211 VSS280 T47
AD20 VSS32 VSS122 AT4 E35 VSS212 VSS281 T50
AD4 AT45 E40 T51
C AD61
AE13
VSS33
VSS34
VSS35
VSS VSS123
VSS124
VSS125
AT52
AT58
F13
F15
VSS213
VSS214
VSS215
VSS282
VSS283
VSS284
T52
T53
C
AE8 VSS36 VSS126 AU1 F19 VSS216 VSS285 T55

AF1 VSS37 VSS127 AU11 F29 VSS217 VSS286 T56
AF17 VSS38 VSS128 AU28 F35 VSS218 VSS287 U13
AF21 VSS39 VSS129 AU32 F40 VSS219 VSS288 U8
AF47 VSS40 VSS130 AU51 F55 VSS220 VSS289 V20
AF48 VSS41 VSS131 AU7 G51 VSS221 VSS290 V61
AF50 VSS42 VSS132 AV17 G6 VSS222 VSS291 W13
AF51 VSS43 VSS133 AV21 G61 VSS223 VSS292 W15
AF52 VSS44 VSS134 AV22 H10 VSS224 VSS293 W18
AF58 VSS48 VSS138 AV55 H4 VSS228 VSS297 Y4
AF59 VSS49 VSS139 AW13 H53 VSS229 VSS298 Y47
AG10 VSS50 VSS140 AW43 H58 VSS230 VSS299 Y58
AG14 VSS51 VSS141 AW61 J1 VSS231 VSS300 Y59
AG18 VSS52 VSS142 AW7 J49 VSS232
AG47 VSS53 VSS143 AY14 J55 VSS233
AG52 VSS54 VSS144 AY19 K11 VSS234
NCTF TEST PIN

A5,A57,BC61,BG5
AH4 AY4 K8 A5
BG57,C3,E1,E61
VSS57 VSS147 VSS237 VSS_NCTF_1#A5
AH58 VSS58 VSS148 AY41 L16 VSS238 VSS_NCTF_2#A57 A57
AJ13 VSS59 VSS149 AY45 L20 VSS239 VSS_NCTF_3#BC61 BC61
AJ16 VSS60 VSS150 AY49 L22 VSS240 VSS_NCTF_8#BG5 BG5
AJ20 VSS61 VSS151 AY55 L26 VSS241 VSS_NCTF_9#BG57 BG57
AJ22 VSS62 VSS152 AY58 L30 VSS242 VSS_NCTF_10#C3 C3
B B
AJ26 VSS63 VSS153 AY9 L34 VSS243 VSS_NCTF_13#E1 E1
AJ30 VSS64 VSS154 BA1 L38 VSS244 VSS_NCTF_14#E61 E61
NCTF
AJ34 VSS65 VSS155 BA11 L43 VSS245
AJ38 VSS66 VSS156 BA17 L48 VSS246
AJ42 VSS67 VSS157 BA21 L61 VSS247 VSS_NCTF_4 BD3
AJ45 VSS68 VSS158 BA26 M11 VSS248 VSS_NCTF_5 BD59
AJ48 VSS69 VSS159 BA32 M15 VSS249 VSS_NCTF_6 BE4
AJ7 VSS70 VSS160 BA48 VSS_NCTF_7 BE58
AK1 VSS71 VSS161 BA51 VSS_NCTF_11 C58
AK52 VSS72 VSS162 BB53 VSS_NCTF_12 D59
AL10 VSS73 VSS163 BC13
AL21 BD12 IVY-BRIDGE-GP-NF
VSS76 VSS166
AL25 VSS77 VSS167 BD16 71.00IVY.A0U
AL28 VSS78 VSS168 BD19
AM13 VSS85 VSS175 BD48
AM30 VSS89 VSS179 BE5
AM34 VSS90 VSS180 BG13
A DMB40 A
Wistron Corporation
IVY-BRIDGE-GP-NF 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
71.00IVY.A0U Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU (VSS)
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
XDP
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C
(Blanking) C
B B
A DMB40 A
Wistron Corporation
Title
(Reserved)
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
X01 12/15
SSID = MEMORY X01 12/02
DM1
[6] M_A_A[15:0]
M_A_A0 98 NP1
M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2
96
M_A_A3 A2
95 110 M_A_RAS# [6]
M_A_A4 A3 RAS# SA0_DIMA
M_A_A5
92
A4 WE#
113 M_A_WE# [6]
SA1_DIMA
Note:
91 115 M_A_CAS# [6]
M_A_A6 A5 CAS# SA0 DIM0 = 0, SA1_DIM0 = 0
90
A6
X01 12/20
M_A_A7 86 114 M_A_DIMA_CS#0 [6] SO-DIMMA SPD Address is 0xA0
1
M_A_A8 A7 CS0#
89 121 M_A_DIMA_CS#1 [6]
A8 CS1#
M_A_A9 85
A9
R1401 R1402 SO-DIMMA TS Address is 0x30
M_A_A10 107 73 0R0402-PAD-2-GP 0R0402-PAD-2-GP
A10/AP CKE0 M_A_DIMA_CKE0 [6]
M_A_A11 84 74
A11 CKE1 M_A_DIMA_CKE1 [6]
M_A_A12 83
2
M_A_A13 A12
119 101 M_A_DIMA_CLK_DDR0 [6]
M_A_A14 A13 CK0
D 80 103 M_A_DIMA_CLK_DDR#0 [6] D
M_A_A15 A14 CK0#
78
A15
79 102 M_A_DIMA_CLK_DDR1 [6]
[6] M_A_BS2 A16/BA2 CK1
104 M_A_DIMA_CLK_DDR#1 [6]
CK1#
109
[6] M_A_BS0 BA0
108 11
DDR_VREF_S3 [6] M_A_BS1 BA1 DM0
[6] M_A_DQ[63:0] 28
M_A_DQ0 DM1
X03 2/6 5 46
Layout Note: M_A_DQ1 7
DQ0 DM2
63
1
M_A_DQ2 DQ1 DM3

Place these caps 15
DQ2 DM4
136
R1405 M_A_DQ3 17 153
0R0402-PAD-2-GP
close to VREF_CA M_A_DQ4 DQ3 DM5
4 170
M_A_DQ5 DQ4 DM6
6 187
M_VREF_CA_DIMMA M_A_DQ6 DQ5 DM7
16
2
M_A_DQ7 DQ6
18 200 PCH_SMBDATA [15,20,65,66,69]
M_A_DQ8 DQ7 SDA
21 202 PCH_SMBCLK [15,20,65,66,69]
M_A_DQ9 DQ8 SCL
23
M_A_DQ10 DQ9 3D3V_S0
33 198
1
M_A_DQ11 DQ10 EVENT#

35
M_A_DQ12 DQ11
C1427
C1426
EC1428
22 199
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_A_DQ13 DQ12 VDDSPD

24
2
M_A_DQ14 DQ13 SA0_DIMA

34 197
1
M_A_DQ15 DQ14 SA0 SA1_DIMA C1401
36 201
M_A_DQ16 DQ15 SA1 SCD1U10V2KX-5GP
39
M_A_DQ17 41
DQ16
77 DY
2
M_A_DQ18 DQ17 NC#1
51 122
M_A_DQ19 DQ18 NC#2 1D5V_S3
53 125
M_A_DQ20 DQ19 NC#/TEST
40
M_A_DQ21 DQ20
X03 2/16 42 75
M_A_DQ22 DQ21 VDD1
50 76
DDR_VREF_S3 M_A_DQ23 DQ22 VDD2
52 81
X03 2/6 Layout Note: M_A_DQ24 57
DQ23 VDD3
82
M_A_DQ25 DQ24 VDD4
Place these caps 59 87
1
M_A_DQ26 DQ25 VDD5

close to VREF_DQ 67 88
R1404 M_A_DQ27 DQ26 VDD6 1D5V_S3
69 93
0R0402-PAD-2-GP M_A_DQ28 DQ27 VDD7
56 94
M_A_DQ29 DQ28 VDD8
58 99 X03 2/21
M_VREF_DQ_DIMMA M_A_DQ30 DQ29 VDD9
68 100
2
M_A_DQ31 DQ30 VDD10

70 105
M_A_DQ32 DQ31 VDD11
129 106
ST330U2VDM-4-GP
SC10U6D3V5KX-1GP
M_A_DQ33 DQ32 VDD12
TC1401
C1404
131 111
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1
1
M_A_DQ34 DQ33 VDD13
C 141 112 C
1
M_A_DQ35 DQ34 VDD14
C1403
C1405
EC1406
EC1407
EC1408
143 117
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_A_DQ36 DQ35 VDD15
C1411
C1423
C1429
130 118
DY DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
2
M_A_DQ37 DQ36 VDD16
132 123
2
M_A_DQ38 DQ37 VDD17

140 124
M_A_DQ39 DQ38 VDD18
142
M_A_DQ40 DQ39
147 2
M_A_DQ41 DQ40 VSS
149 3
M_A_DQ42 DQ41 VSS
157 8
M_A_DQ43 DQ42 VSS
159 9
M_A_DQ44 DQ43 VSS
146 13
0D75V_S0 M_A_DQ45 DQ44 VSS
148 14
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_A_DQ46 DQ45 VSS
C1414
C1415
C1416
C1417
158 19
1
M_A_DQ47 DQ46 VSS
160 20
M_A_DQ48 DQ47 VSS
163 25
M_A_DQ49 DQ48 VSS
165 26
2
M_A_DQ50 DQ49 VSS
175 31
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
M_A_DQ51 DQ50 VSS

C1419
C1420
C1418
177 32
1
M_A_DQ52 DQ51 VSS

164 37
Layout Note: M_A_DQ53 166
DQ52 VSS
38
DY Place these caps M_A_DQ54 174
DQ53 VSS
43
2
M_A_DQ55 DQ54 VSS

close to VTT1 and 176 44
M_A_DQ56 DQ55 VSS
181 48
VTT2. M_A_DQ57 DQ56 VSS
183 49
M_A_DQ58 DQ57 VSS
191 54
M_A_DQ59 193
DQ58 VSS
55
Layout Note:
M_A_DQ60 DQ59 VSS
180
DQ60 VSS
60 Place these Caps near SO-DIMMA.
M_A_DQ61 182 61
M_A_DQ62 DQ61 VSS
192 65
M_A_DQ63 DQ62 VSS
194 66
DQ63 VSS
[6] M_A_DQS#[7:0] 71
M_A_DQS#0 VSS 1D5V_S0 1D5V_S3
10 72
M_A_DQS#1 DQS0# VSS
27 127
M_A_DQS#2 DQS1# VSS
45 128
M_A_DQS#3 DQS2# VSS
62 133 1 2
M_A_DQS#4 DQS3# VSS
135 134
M_A_DQS#5 152
DQS4# VSS
138
DY
M_A_DQS#6 DQS5# VSS C1421
169 139
M_A_DQS#7 DQS6# VSS SCD1U10V2KX-5GP
186 144
DQS7# VSS
[6] M_A_DQS[7:0] 145
M_A_DQS0 VSS
12 150 1 2
B M_A_DQS1 DQS0 VSS B
29 151
M_A_DQS2 47
DQS1 VSS
155
DY
M_A_DQS3 DQS2 VSS C1424
64 156
M_A_DQS4 DQS3 VSS SCD1U10V2KX-5GP
137 161
M_A_DQS5 DQS4 VSS
154 162
M_A_DQS6 DQS5 VSS
171 167
M_A_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
Layout Note:
VSS
[6] M_A_DIMA_ODT0
116
ODT0 VSS
173 For S3 reduction circuit's 1D5V return pass.
120 178
[6] M_A_DIMA_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMMA 126 184
VREF_CA VSS
1 185
Layout Note: M_VREF_DQ_DIMMA VREF_DQ VSS
189
VSS
All VREF traces should [15,37] DDR3_DRAMRST#
30
RESET# VSS
190
have width=20mil; 195
VSS
196
spacing=20 mil VSS
0D75V_S0 203 205
VTT1 VSS
204 206
VTT2 VSS
DDR3-204P-73-GP
62.10017.U81
2nd = 62.10017.P31
3rd = 62.10017.K11
4th = 62.10017.N91
A A
<Core Design>
Wistron Corporation
Title
DDR3-SODIMM1
A2 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
X01 12/13 X01 12/15

SSID = MEMORY DM2
[6] M_B_A[15:0]
M_B_A0 98 NP1
M_B_A1 A0 NP1
97 NP2
M_B_A2 A1 NP2
96
M_B_A3 A2
95 110 M_B_RAS# [6]
M_B_A4 A3 RAS#
92 113 M_B_WE# [6]
M_B_A5 A4 WE#
M_B_A6
91
A5 CAS#
115 M_B_CAS# [6] Note:
90
M_B_A7 A6 SO-DIMMB SPD Address is 0xA4
86 114 M_B_DIMB_CS#0 [6]
M_B_A8 A7 CS0#
89 121 M_B_DIMB_CS#1 [6] SO-DIMMB TS Address is 0x34
M_B_A9 A8 CS1#
85
M_B_A10 A9
107 73 M_B_DIMB_CKE0 [6]
M_B_A11 A10/AP CKE0
84 74 M_B_DIMB_CKE1 [6]
M_B_A12 A11 CKE1
83
M_B_A13 A12
119 101 M_B_DIMB_CLK_DDR0 [6]
M_B_A14 A13 CK0
80 103 M_B_DIMB_CLK_DDR#0 [6]
DDR_VREF_S3 M_B_A15 A14 CK0#
D 78 D
A15
79 102 M_B_DIMB_CLK_DDR1 [6]
[6] M_B_BS2 A16/BA2 CK1
X03 2/6 CK1#
104 M_B_DIMB_CLK_DDR#1 [6]
109
1
[6] M_B_BS0 BA0

108 11
R1505 [6] M_B_BS1 BA1 DM0
[6] M_B_DQ[63:0] 28
0R0402-PAD-2-GP M_B_DQ0 DM1
5 46
M_B_DQ1 DQ0 DM2
7 63
M_VREF_CA_DIMMB M_B_DQ2 DQ1 DM3
15 136
2
M_B_DQ3 DQ2 DM4

17 153
M_B_DQ4 DQ3 DM5 3D3V_S0
4 170
Layout Note: M_B_DQ5 6
DQ4 DM6
187
M_B_DQ6 DQ5 DM7
Place these caps 16
1
M_B_DQ7 DQ6
close to VREF_CA 18 200 PCH_SMBDATA [14,20,65,66,69]
1
M_B_DQ8 DQ7 SDA
C1523
C1522
EC1524
21 202
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DQ8 SCL PCH_SMBCLK [14,20,65,66,69]

M_B_DQ9 23 R1501
2
M_B_DQ10 DQ9 3D3V_S0 10KR2J-3-GP

33 198
M_B_DQ11 DQ10 EVENT#
35
M_B_DQ12 DQ11
22 199
2
M_B_DQ13 DQ12 VDDSPD
24
1
M_B_DQ14 DQ13 SA0_DIMB
34 197
M_B_DQ15 36
DQ14 SA0
201 SA1_DIMB C1501 DY
M_B_DQ16 DQ15 SA1 SCD1U10V2KX-5GP SA1_DIMB
39
2
M_B_DQ17 DQ16
41 77
M_B_DQ18 DQ17 NC#1 SA0_DIMB
X03 2/16 51
DQ18 NC#2
122 X01 12/20
M_B_DQ19 53 125 1D5V_S3
DDR_VREF_S3 M_B_DQ20 DQ19 NC#/TEST
40
1
M_B_DQ21 DQ20
42 75
M_B_DQ22 DQ21 VDD1 R1502
X03 2/6 50 76
M_B_DQ23 DQ22 VDD2
52 81 0R0402-PAD-2-GP
1
M_B_DQ24 DQ23 VDD3

57 82
R1503 M_B_DQ25 DQ24 VDD4
59 87
2
0R0402-PAD-2-GP M_B_DQ26 DQ25 VDD5
67 88
Layout Note: M_B_DQ27 69
DQ26 VDD6
93
M_VREF_DQ_DIMMB M_B_DQ28 DQ27 VDD7
Place these caps 56 94
2
M_B_DQ29 DQ28 VDD8

close to VREF_DQ 58 99
M_B_DQ30 DQ29 VDD9
68 100
M_B_DQ31 DQ30 VDD10 1D5V_S3
70 105
M_B_DQ32 DQ31 VDD11
129 106 X01 01/09
1
M_B_DQ33 DQ32 VDD12

131 111
M_B_DQ34 DQ33 VDD13
C1515
C1516
C1517
141 112
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
M_B_DQ35 DQ34 VDD14

C 143 117 C
2
M_B_DQ36 DQ35 VDD15

130 118
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
M_B_DQ37 DQ36 VDD16
C1503
C1504
C1507
C1509
132 123
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1
1
M_B_DQ38 DQ37 VDD17
C1510
140 124
1
M_B_DQ39 DQ38 VDD18
C1508
142
M_B_DQ40 147
DQ39
2
DY DY DY
DY
2
M_B_DQ41 DQ40 VSS
149 3
2
M_B_DQ42 DQ41 VSS
157 8
M_B_DQ43 DQ42 VSS
159 9
M_B_DQ44 DQ43 VSS
146 13
M_B_DQ45 DQ44 VSS
148 14
M_B_DQ46 DQ45 VSS
158 19
0D75V_S0 M_B_DQ47 DQ46 VSS
160 20
M_B_DQ48 DQ47 VSS
163 25
Layout Note:
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_B_DQ49 DQ48 VSS
C1511
C1512
C1513
EC1514
165 26
1
M_B_DQ50 DQ49 VSS
Place these caps 175
DQ50 VSS
31
M_B_DQ51 177 32
close to VTT1 and M_B_DQ52 DQ51 VSS
C1518
C1519
C1521
164 37
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
2
1
VTT2. M_B_DQ53 DQ52 VSS

166 38
M_B_DQ54 DQ53 VSS
174 43
DY M_B_DQ55 176
DQ54 VSS
44
2
M_B_DQ56 DQ55 VSS

181 48
M_B_DQ57 DQ56 VSS
183 49
M_B_DQ58 DQ57 VSS
191
DQ58 VSS
54 X03 02/16
M_B_DQ59 193 55
M_B_DQ60 DQ59 VSS
180 60
M_B_DQ61 DQ60 VSS
182 61
M_B_DQ62 192
DQ61 VSS
65
Layout Note:
M_B_DQ63 DQ62 VSS
194
DQ63 VSS
66 Place these Caps near SO-DIMMA.
[6] M_B_DQS#[7:0] 71
M_B_DQS#0 VSS
10 72
M_B_DQS#1 DQS0# VSS
27 127
M_B_DQS#2 DQS1# VSS
45 128
M_B_DQS#3 DQS2# VSS
62 133
M_B_DQS#4 DQS3# VSS
135 134
M_B_DQS#5 DQS4# VSS
152 138
M_B_DQS#6 DQS5# VSS
169 139
M_B_DQS#7 DQS6# VSS
186 144
DQS7# VSS
[6] M_B_DQS[7:0] 145
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
29 151
B M_B_DQS2 DQS1 VSS B
47 155
M_B_DQS3 DQS2 VSS
64 156
M_B_DQS4 DQS3 VSS
137 161
M_B_DQS5 DQS4 VSS
154 162
M_B_DQS6 DQS5 VSS
171 167
M_B_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
116 173
[6] M_B_DIMB_ODT0 ODT0 VSS
120 178
[6] M_B_DIMB_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMMB 126 184
VREF_CA VSS
M_VREF_DQ_DIMMB 1 185
VREF_DQ VSS
189
Layout Note: 30
VSS
190
[14,37] DDR3_DRAMRST# RESET# VSS
All VREF traces should VSS
195
have width=20mil; 196
VSS
0D75V_S0 203 205
spacing=20 mil VTT1 VSS
204 206
VTT2 VSS
DDR3-204P-75-GP
62.10017.Z81
2nd = 62.10017.N41
3rd = 62.10017.P61
4th = 62.10017.P41
A A
<Core Design>
Wistron Corporation
Title
DDR3-SODIMM2
A2 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH
D D
3D3V_S0
RN1701 4 OF 10 3D3V_S0
PCH1D
1 4 L_CTRL_DATA [27] L_BKLT_EN J47 AP43
L_CTRL_CLK L_BKLTEN SDVO_TVCLKINN
2 3 [49] LVDS_VDD_EN M45 L_VDD_EN SDVO_TVCLKINP AP45
SRN2K2J-1-GP [49] L_BKLT_CTRL P45 L_BKLTCTL SDVO_STALLN AM42
3
4
SDVO_STALLP AM40
LVDS_DDC_CLK_R T40 RN1706
[49] LVDS_DDC_CLK_R
[49] LVDS_DDC_DATA_R LVDS_DDC_DATA_R K47 L_DDC_CLK
AP39 SRN2K2J-1-GP
Layout Note:
L_DDC_DATA SDVO_INTN
SDVO_INTP AP40 Close HDMI port
RN1702 L_CTRL_CLK T45
L_BKLT_EN L_CTRL_DATA L_CTRL_CLK
2 3 P39
2
1
LVDS_VDD_EN L_CTRL_DATA
1 4
LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK PCH_HDMI_CLK [51]
SRN100KJ-6-GP TPAD14-OP-GP TP1701 1 LVDS_VBG AF36 M39
LVD_VBG SDVO_CTRLDATA PCH_HDMI_DATA [51]
1
AE48 LVD_VREFH
R1701 AE47 AT49
Layout Note: 2K37R2F-GP LVD_VREFL DDPB_AUXN
AT47
DDPB_AUXP
Place near PCH; DDPB_HPD AT40 HDMI_PCH_DET [51]
trace to trace spacing=20mil 2 [49] LVDSA_CLK# AK39 LVDSA_CLK#
LVDS
[49] LVDSA_CLK AK40 LVDSA_CLK DDPB_0N AV42 HDMI_DATA2_R# [51]
DDPB_0P AV40 HDMI_DATA2_R [51]
[49] LVDSA_DATA0# AN48 LVDSA_DATA#0 DDPB_1N AV45 HDMI_DATA1_R# [51]
C AM47 AV46 C
[49] LVDSA_DATA1# LVDSA_DATA#1 DDPB_1P HDMI_DATA1_R [51]
Digital Display Interface

[49] LVDSA_DATA2# AK47 LVDSA_DATA#2 DDPB_2N AU48 HDMI_DATA0_R# [51]
AJ48 LVDSA_DATA#3 DDPB_2P AU47 HDMI_DATA0_R [51]
DDPB_3N AV47 HDMI_CLK_R# [51]
[49] LVDSA_DATA0 AN47 LVDSA_DATA0 DDPB_3P AV49 HDMI_CLK_R [51]
[49] LVDSA_DATA1 AM49 LVDSA_DATA1
[49] LVDSA_DATA2 AK49 LVDSA_DATA2
AJ47 P46
LVDSA_DATA3 DDPC_CTRLCLK
P42
Layout Note:
DDPC_CTRLDATA
Layout Note: HDMI trace length to DC CAP. max 10000mil
AF40 LVDSB_CLK#
LVDS signal trace AF39 LVDSB_CLK DDPC_AUXN AP47
length max 4000mil DDPC_AUXP AP49
AH45 LVDSB_DATA#0 DDPC_HPD AT38
AH47 LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
3D3V_S0 AH43 AY45
LVDSB_DATA0 DDPC_1P
AH49 LVDSB_DATA1 DDPC_2N BA47
AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49
3
4
RN1707
SRN2K2J-1-GP N48 CRT_BLUE DDPD_CTRLCLK M43
P49 CRT_GREEN DDPD_CTRLDATA M36
T49 CRT_RED
2
1
B B
DDPD_AUXN AT45
CRT
CRT_DDCCLK T39 AT43
CRT_DDCDATA CRT_DDC_CLK DDPD_AUXP
M40 CRT_DDC_DATA DDPD_HPD BH41
DDPD_0N BB43
M47 CRT_HSYNC DDPD_0P BB45
M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
DDPD_2N BF42
DAC_IREF_R T43 BE42
DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
1
BG42
Layout Note: R1702 DDPD_3P
Place near PCH; 1KR2J-1-GP PANTHER-GP-NF
trace to trace spacing=30mil 71.PANTH.00U
2
A <Core Design> A
Wistron Corporation
Title
PCH (LVDS/CRT/DDI)
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = PCH
PCH1E 5 OF 10
RSVD1 AY7
RSVD2 AV7
BG26 TP1 RSVD3 AU3
BJ26 TP2 RSVD4 BG4
BH25 TP3
BJ16 TP4 RSVD5 AT10
D BG16 TP5 RSVD6 BC8 D
AH38 TP6
AH37 TP7 RSVD7 AU2
AK43 TP8 RSVD8 AT4
AK45 TP9 RSVD9 AT3
C18 TP10 RSVD10 AT1
N30 TP11 RSVD11 AY3
H3 TP12 RSVD12 AT5
AH12 TP13 RSVD13 AV3
AM4 TP14 RSVD14 AV1
AM5 TP15 RSVD15 BB1
Y13 TP16 RSVD16 BA3
K24 TP17 RSVD17 BB5
L24 TP18 RSVD18 BB3
AB46 TP19 RSVD19 BB7
AB45 TP20 RSVD20 BE8
RSVD
RSVD21 BD4
RSVD22 BF6
Layout Note: B21 AV5
Trace Length : M20
TP21
TP22
RSVD23
RSVD24 AV10 USB Table
PCH ~~9000mil~~Cap~~1000mil~~CONN AY16 TP23
BG46 TP24 RSVD25 AT8 Pair Device
RSVD26 AY5 0 USB3.0 port1, with Power Share
RSVD27 BA2
USB3_RX1_N BE28 1 USB3.0 port2
USB3.0/2.0 Mapping Table [62] USB3_RX1_N
[82] USB3_RX2_N
USB3_RX2_N BC30
USB3RN1
USB3RN2 RSVD28 AT12
BE32 USB3RN3 RSVD29 BF3 X01 12/20 2 NC
C USB 3.0 Port USB 2.0 port BJ32 USB3RN4
X01 12/13 C
USB3_RX1_P BC28 3 NC
[62] USB3_RX1_P USB3_RX2_P USB3RP1
Port 1 Port 0 BE30
[82] USB3_RX2_P
BF32
USB3RP2
USB3RP3
USB2.0 Signal Group 4 Touch Panel
Port 2 Port 1 BG32 USB3RP4 USBP0N C24 USB_PN0 [62]
[62] USB3_TX1_N USB3_TX1_N AV26 A24 USB_PP0 [62] 5 NC
USB3_TX2_N USB3TN1 USBP0P
Port 3 Port 2 [82] USB3_TX2_N BB26 USB3TN2 USBP1N C25 USB_PN1 [82]
AU28 USB3TN3 USBP1P B25 USB_PP1 [82] 6 NC
Port 4 Port 3 AY30 USB3TN4 USBP2N C26
[62] USB3_TX1_P USB3_TX1_P AU26 A26 7 NC
USB3_TX2_P USB3TP1 USBP2P
[82] USB3_TX2_P AY26 USB3TP2 USBP3N K28
AV28 USB3TP3 USBP3P H28 8 WWAN
AW30 USB3TP4 USBP4N E28 USB_PN4 [82]
3D3V_S0 NC
USBP4P D28 USB_PP4 [82] 9
RN1803 C28
SRN10KJ-6-GP USBP5N
USBP5P A28 10 Card reader
8 1 PCH_GPIO50 C29
PCH_GPIO54 USBP6N
7 2 USBP6P B29 11 WLAN
6 3 PCH_GPIO02 INT_PIRQA# K40 N28
INT_PIRQB# PIRQA# USBP7N
5 4 K38 PIRQB# USBP7P M28 12 CAMERA
PCI
INT_PIRQC# H38 L30 USB_PN8 [66]
INT_PIRQD# PIRQC# USBP8N
G38 PIRQD# USBP8P K30 USB_PP8 [66] 13 NC
USBP9N G30
PCH_GPIO50 C46 E30
REQ1#/GPIO50 USBP9P
USB
PCH_GPIO52 C44 C30 USB_PN10 [82] 1. USB Ext. port 9 (HS) External debug port
TPAD14-OP-GP TP1803 BBS_BIT1 PCH_GPIO54 REQ2#/GPIO52 USBP10N
1 E40 REQ3#/GPIO54 USBP10P A30 USB_PP10 [82] use on Chief River platform.
USBP11N L32 USB_PN11 [65]
TPAD14-OP-GP TP1804 1 BBS_BIT0 BBS_BIT1 D47 K32 USB_PP11 [65]
2. 2011 July; Microsoft will support USB3.0
BBS_BIT0 [21] TPAD14-OP-GP TP1801 PCH_GPIO53 GNT1#/GPIO51 USBP11P
B
1 E42 GNT2#/GPIO53 USBP12N G32 USB_PN12 [49] debug--> Port1 useable. B
PCI_GNT3# F46 E32 USB_PP12 [49]
GNT3#/GPIO55 USBP12P
USBP13N C32
USBP13P A32
PCH_GPIO02 G42 PIRQE#/GPIO2
[56] SATA_ODD_DA# G40 PIRQF#/GPIO3
C42 C33 USB_RBIAS 1 2
Boot Bios Strap
[65] BLUETOOTH_EN
PCH_GPIO05 D44
PIRQG#/GPIO4 USBRBIAS# R1811 Layout Note:
PIRQH#/GPIO5 22D6R2F-L1-GP 1. USBRBIAS/# use 50ohm single-ended impedance
USBRBIAS B33 spacing to other signal=15mil
GNT1#/GPIO51 SATA1GP/GPIO19 Boot BIOS Location TPAD14-OP-GP TP1802 1 PCI_PME# K10 PME# 2. Length < 500mil
PCI_PLTRST# C6 A14 USB_OC#0_1 USB_OC#0_1 [62,82]
PLTRST# OC0#/GPIO59
0 0 LPC OC1#/GPIO40 K20 USB_OC#2_3
B17 USB_OC#4_5
ER1807 1 OC2#/GPIO41
2 0R2J-2-GP CLK_PCI_LPC_R H49 C16 USB_OC#6_7
0 1 Reserved
[71] CLK_PCI_LPC
[20] CLK_PCI_FB R1805 1 DY 2 22R2J-2-GP CLK_PCI_FB_R H43
CLKOUT_PCI0 OC3#/GPIO42
L16 USB_OC#8_9
R1806 1 CLKOUT_PCI1 OC4#/GPIO43
[27] CLK_PCI_KBC 2 22R2J-2-GP CLK_PCI_KBC_R J48 CLKOUT_PCI2 OC5#/GPIO9 A16 USB_OC#10_11
K42 D14 USB_OC#12_13
CLKOUT_PCI3 OC6#/GPIO10
1 0 Reserved H40 CLKOUT_PCI4 OC7#/GPIO14 C14 PCH_GPIO14
2
EC1802 EC1804
1 1 SPI(Default) PANTHER-GP-NF RN1802
DY DY
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SRN8K2J-2-GP-U
USB_OC#2_3 1 10 3D3V_S5
PCH_GPIO14 2 9 USB_OC#12_13
USB_OC#6_7 3 8 USB_OC#8_9
2 1 PCI_GNT3# USB_OC#0_1 4 7 USB_OC#10_11
DY 3D3V_S5 5 6 USB_OC#4_5
A R1801 <Core Design> A
4K7R2J-2-GP
X02 2/13 RN1801

SRN8K2J-2-GP-U Wistron Corporation
A16 Swap Override jumper 1 2 PCI_PLTRST# PCH_GPIO52 1 10 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
[5,27,31,65,66,71] PLT_RST# 3D3V_S0
INT_PIRQB# 2 9 INT_PIRQD# Taipei Hsien 221, Taiwan, R.O.C.
1
R1823 SATA_ODD_DA# 3 8 PCH_GPIO05

1
PCI_GNT#3 Low = A16 swap override/Top-Block R1816 0R0402-PAD-2-GP INT_PIRQA# 4 7 INT_PIRQC# Title
100KR2J-1-GP BLUETOOTH_EN
Swap Override enabled
High = Default
DY DY 3D3V_S0 5 6
PCH (PCI/USB/NVRAM)
2

2
C1801 A3 A00
SC220P50V2KX-3GP
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = PCH
PCH1C 3 OF 10
[4] DMI_RXN[3:0] FDI_TXN[7:0] [4]
DMI_RXN0 BC24 BJ14 FDI_TXN0
DMI_RXN1 DMI0RXN FDI_RXN0 FDI_TXN1
BE20 DMI1RXN FDI_RXN1 AY14
DMI_RXN2 BG18 BE14 FDI_TXN2
DMI_RXN3 DMI2RXN FDI_RXN2 FDI_TXN3
BG20 DMI3RXN FDI_RXN3 BH13
D BC12 FDI_TXN4 D
[4] DMI_RXP[3:0] FDI_RXN4
DMI_RXP0 BE24 BJ12 FDI_TXN5
DMI_RXP1 DMI0RXP FDI_RXN5 FDI_TXN6
BC20 DMI1RXP FDI_RXN6 BG10
DMI_RXP2 BJ18 BG9 FDI_TXN7
DMI_RXP3 DMI2RXP FDI_RXN7
BJ20 DMI3RXP FDI_TXP[7:0] [4]
BG14 FDI_TXP0
[4] DMI_TXN[3:0] DMI_TXN0 FDI_RXP0 FDI_TXP1
AW24 DMI0TXN FDI_RXP1 BB14
DMI_TXN1 AW20 BF14 FDI_TXP2
DMI_TXN2 DMI1TXN FDI_RXP2 FDI_TXP3
BB18 DMI2TXN FDI_RXP3 BG13
DMI_TXN3 AV18 BE12 FDI_TXP4
DMI3TXN FDI_RXP4
DMI
FDI
BG12 FDI_TXP5
[4] DMI_TXP[3:0] DMI_TXP0 FDI_RXP5 FDI_TXP6
AY24 DMI0TXP FDI_RXP6 BJ10
DMI_TXP1 AY20 BH9 FDI_TXP7
DMI_TXP2 DMI1TXP FDI_RXP7
AY18
Layout Note: DMI_TXP3 AU18
DMI2TXP
DMI3TXP
DMI_ZCOMP keep W=4 mils and FDI_INT AW16 FDI_INT FDI_INT [4] DSWODVREN - On Die DSW VR Enable
routing length less than 500 1D05V_PCH
BJ24 AV12 FDI_FSYNC0 FDI_FSYNC0 [4] HIGH Enabled (DEFAULT)
mils. DMI_ZCOMP FDI_FSYNC0
DMI_IRCOMP keep W=4 mils and R1901 1 2 49D9R2F-GP DMI_COMP_R BG25 BC10 FDI_FSYNC1 FDI_FSYNC1 [4]
DMI_IRCOMP FDI_FSYNC1 LOW Disabled
routing length less than 500
mils. R1902 1 2 750R2F-GP RBIAS_CPY BH21 AV14 FDI_LSYNC0 FDI_LSYNC0 [4]
DMI2RBIAS FDI_LSYNC0
BB10 FDI_LSYNC1 FDI_LSYNC1 [4]
FDI_LSYNC1 RTC_AUX_S5
A18 DSW ODVREN RTC_AUX_S5 DSW ODVREN R1917 1 2 330KR2J-L1-GP

DSWVRMEN
C R1911 1 2 10KR2J-3-GP C
DY
System Power Management

3D3V_S0 TPAD14-OP-GP TP1907 1 SUSACK# C12 E22 PCH_DPW ROK R1927 1 2 0R0402-PAD-2-GP PM_RSMRST#
SUSACK# DPWROK
X03 2/13
R1905 1 2 10KR2J-3-GP
K3 B9 PCH_W AKE# R1910 1 2 0R2J-2-GP 3D3V_S0
[5] XDP_DBRESET# SYS_RESET# WAKE# DY PCH_W AKE#_EC [27]
X03 2/6
[36] SYS_PW ROK P12 N3 PM_CLKRUN# R1929 1 2 0R0402-PAD-2-GP PM_CLKRUN#_EC [27] PM_CLKRUN# R1919 1 2 8K2R2J-3-GP
SYS_PWROK CLKRUN#/GPIO32
X03 2/6
X03 2/6
[27,36] S0_PW R_GOOD 1 2 PW ROK L22 G8 PM_SUS_STAT# 1 TP1901 TPAD14-OP-GP
R1921 R1916 1 PWROK SUS_STAT#/GPIO61 X03 2/6
2 0R0402-PAD-2-GP
0R0402-PAD-2-GP
1 2 MEPW ROK L10 N14 SUS_CLK R1925 1 2 0R0402-PAD-2-GP PCH_SUSCLK_KBC
[45,46,47] RUNPW ROK
R1907 DY 0R2J-2-GP APWROK SUSCLK/GPIO62 PCH_SUSCLK_KBC [27]
2
[37] PM_DRAM_PW RGD B13 D10 PM_SLP_S5# 1 TP1902 TPAD14-OP-GP
DRAMPWROK SLP_S5#/GPIO63 EC1901
X02 2/6 SC4D7P50V2CN-1GP DY
1
[27] RSMRST#_KBC 1 2 PM_RSMRST# C21 H4 PM_SLP_S4# PM_SLP_S4# [27,46]
R1924 RSMRST# SLP_S4#
0R0402-PAD-2-GP
SUS_PW R_ACK K16 F4 PM_SLP_S3# PM_SLP_S3# [27,36,37,47]
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3#
[27] PM_PW RBTN# PM_PW RBTN# E20 G10 PM_SLP_A# 1 TP1903 TPAD14-OP-GP
PWRBTN# SLP_A#
[27] AC_PRESENT AC_PRESENT H20 G16 PM_SLP_SUS# 1 TP1904 TPAD14-OP-GP

B ACPRESENT/GPIO31 SLP_SUS# B
BATLOW # E10 AP14 H_PM_SYNC H_PM_SYNC [5]

BATLOW#/GPIO72 PMSYNCH
PM_RI# A10 K14 PM_SLP_LAN# 1 TP1905 TPAD14-OP-GP

RI# SLP_LAN#/GPIO29
PANTHER-GP-NF
Sequence: 71.PANTH.00U
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
3D3V_S5
RN1901
8 1 BATLOW #
7 2 PM_RI#
6 3 SUS_PW R_ACK
5 4 PCH_W AKE#
SRN10KJ-6-GP
R1909 1 2 100KR2J-1-GP AC_PRESENT

R1920 2 1 10KR2J-3-GPPM_SLP_LAN#
DY
A <Core Design> A
R1908 2 1 10KR2J-3-GP PM_RSMRST# Wistron Corporation

R1926 1 2 100KR2J-1-GP SYS_PW ROK
R1904 1
DY 2 100KR2J-1-GP PW ROK Title
PCH (DM I/FDI/PM)

A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = PCH S5 power rail CLKREQ#: 3D3V_S0

RN2018
X01 12/09 3D3V_S5
PCIECLKRQ[0]# 1 4 PCIE_CLK_REQ2# PCIE_CLK_RQ2# S0 power rail CLKREQ#: SMB_CLK 4 1 RN2003

2 3 CLK_PCIE_REQ1# PCIE_CLK_RQ1# 3D3V_S5 SMB_DATA 3 2 SRN2K2J-1-GP
3D3V_S5 PCIECLKRQ[7:3]# PCIECLKRQ[2:1]#
1
RN2001 SRN10KJ-5-GP
1 8 PCIE_CLK_REQ6# PCIE_CLK_RQ6# R2004 SML0_DATA 1 8 RN2004
2 7 CLK_PCIE_W LAN_REQ# PCIE_CLK_RQ3# PCH1B 2 OF 10 UMA 10KR2J-3-GP SML0_CLK 2 7 SRN2K2J-2-GP
3 6 PCIE_CLK_REQ0# PCIE_CLK_RQ0# SML1_CLK 3 6
4 5 PCIE_CLK_REQ4# PCIE_CLK_RQ4# BG34 SML1_DATA 4 5
2
PERN1 EC_SW I# PEG_CLKREQ#_R
BJ34 PERP1 SMBALERT#/GPIO11 E12 EC_SW I# [27]
SRN10KJ-6-GP X01 12/09 AV32 PETN1 NC
1
RN2002 AU32 H14 SMB_CLK
EC_SW I# PETP1 SMBCLK R2005 PCH_GPIO74 R2011 1 10KR2J-3-GP
D 1 8 2 D
2 7 PCIE_CLK_LAN_REQ# PCIE_CLK_RQ5# BE34 C9 SMB_DATA 10KR2J-3-GP
3 6 CLK_PCIE_REQ7# PCIE_CLK_RQ7# BF34
PERN2 SMBDATA SG DRAMRST_CNTRL_PCH 1 2
CLK_PEG_B_REQ# PERP2 R2009 1KR2J-1-GP
4 5 BB32 NC
2
PETN2
AY32 PETP2
SMBUS
SRN10KJ-6-GP A12 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH [37]
SML0ALERT#/GPIO60 3D3V_S0
BG36 PERN3
BJ36 C8 SML0_CLK RN2007
PERP3 SML0CLK
AV34 NC 2 3
AU34
PETN3
G12 SML0_DATA 1 4
CRB : 1K
PETP3 SML0DATA Layout Note:
[65] PCIE_RXN4 BF36 Can Place Far away PCH SRN2K2J-1-GP CEKLT: 10K
PERN4
[65] PCIE_RXP4 BE36 PERP4
C2005 1 2 SCD1U10V2KX-5GP PCIE_TXN4_C AY34 C13 PCH_GPIO74
[65] PCIE_TXN4
C2006 1 2 SCD1U10V2KX-5GP PCIE_TXP4_C BB34
PETN4 WLAN SML1ALERT#/PCHHOT#/GPIO74
[65] PCIE_TXP4 PETP4
E14 SML1_CLK
SML1CLK/GPIO58 SML1_CLK [27,28,85]
PCI-E*
BG37 PERN5
BH37 M16 SML1_DATA SMB_DATA 6 1
PERP5 SML1DATA/GPIO75 SML1_DATA [27,28,85] PCH_SMBDATA [14,15,65,66,69]
AY36 PETN5 NC
BB36 PETP5 5 2
84.2N702.A3F
[31] PCIE_RXN6 BJ38 PERN6 4 3 2nd = 84.DM601.03F
[31] PCIE_RXP6 BG38 PERP6 3rd = 84.2N702.E3F
C2001 2 SCD1U10V2KX-5GP PCIE_TXN6_C CL_CLK TP2001 TPAD14-OP-GP
Controller
[31] PCIE_TXN6 1 AU36 PETN6 LAN CL_CLK1 M7 1 Q2001 4th = 84.2N702.F3F
[31] PCIE_TXP6 C2002 1 2 SCD1U10V2KX-5GP PCIE_TXP6_C AV36 2N7002KDW -GP
PETP6
PCH_SMBCLK [14,15,65,66,69]
Link
BG40 T11 CL_DATA 1 TP2002 TPAD14-OP-GP
PERN7 CL_DATA1 SMB_CLK
BJ40 PERP7 NC
AY40
C Layout Note: BB40
PETN7
P10 CL_RST# 1 TP2003 TPAD14-OP-GP C
PETP7 CL_RST1# XTAL25_IN
Layout trace < 14000mil 1 2
BE38 X2001
BC38
PERN8 Layout Note: C2008
AW38
PERP8 NC R2003 CLKOUT termination 1 4 SC15P50V2JN-2-GP
PETN8
2
AY38 0R2J-2-GP place close to PCH <500mil
PETP8 R2006
M10 PEG_CLKREQ#_R 1 2 1M1R2J-GP
Y40
PEG_A_CLKRQ#/GPIO47 DY PEG_CLKREQ# [85]
2 3 C2007
CLKOUT_PCIE0N RN2016 SC15P50V2JN-2-GP
Y39 NC
1
CLKOUT_PCIE0P CLKOUT_PEG_A_N
CLKOUT_PEG_A_N AB37 1 4 CLK_PCIE_VGA# [83]
PCIE_CLK_REQ0# CLKOUT_PEG_A_P XTAL25_OUT XTAL-25MHZ-155-GP1
CLOCKS
J2 AB38 2 3 2
PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P SG CLK_PCIE_VGA [83]
RN
SRN0J-6-GP
AB49 AV22 CLKOUT_DMI_N 1 4 CLK_EXP_N [5] 82.30020.D41
CLKOUT_PCIE1N CLKOUT_DMI_N
X01 12/09 AB47 NC AU22 CLKOUT_DMI_P 2 3 CLK_EXP_P [5] 2nd = 82.30020.G61
CLKOUT_PCIE1P CLKOUT_DMI_P
Layout Note: CLK_PCIE_REQ1# M1 RN2017 0R4P2R-PAD
PCIECLKRQ1#/GPIO18
CLKOUT termination AM12 A00 3/23
CLKOUT_DP_N
place close to PCH <500mil CLKOUT_DP_P AM13
AA48 3D3V_S0
CLKOUT_PCIE2N
AA47 CLKOUT_PCIE2P NC
A00 3/23 CLKIN_DMI_N BF18 CLK_BUF_EXP_N 2 3
1
X02 2/6 PCIE_CLK_REQ2# V10 PCIECLKRQ2#/GPIO20 CLKIN_DMI_P BE18 CLK_BUF_EXP_P RN2019 1 4
RN
SRN10KJ-5-GP
R2013
1 4 CLK_PCH_SRC3_N Y37 BJ30 CLK_BUF_CPYCLK_N 2 3 10KR2J-3-GP UMA
[65] CLK_PCIE_W LAN#
2 3 CLK_PCH_SRC3_P Y36
CLKOUT_PCIE3N WLAN CLK CLKIN_GND1_N
BG30 CLK_BUF_CPYCLK_P RN2008 1 4
[65] CLK_PCIE_W LAN
2
CLKOUT_PCIE3P CLKIN_GND1_P SRN10KJ-5-GP
B RN2012 0R4P2R-PAD BOARD_ID1 B
[65] CLK_PCIE_W LAN_REQ# A8 PCIECLKRQ3#/GPIO25
G24 CLK_BUF_DOT96_N 2 3 [22] BOARD_ID2 BOARD_ID2
CLKIN_DOT_96N CLK_BUF_DOT96_P RN2020 1
CLKIN_DOT_96P E24 4
1
Y43 SRN10KJ-5-GP
CLKOUT_PCIE4N R2012 R2010
Y45 CLKOUT_PCIE4P NC AK7 CLK_BUF_CKSSCD_N 2 3 10KR2J-3-GP 10KR2J-3-GP
PCIE_CLK_REQ4# L12
CLKIN_SATA_N
AK5 CLK_BUF_CKSSCD_P RN2021 1 4 SG
PCIECLKRQ4#/GPIO26 CLKIN_SATA_P
RN
SRN10KJ-5-GP
2
1 4 CLK_PCH_SRC5_N V45 K45 CLK_BUF_REF14 R2008 1 2
[31] CLK_PCIE_LAN#
2 3 CLK_PCH_SRC5_P V46
CLKOUT_PCIE5N LAN REFCLK14IN 10KR2J-3-GP
[31] CLK_PCIE_LAN CLKOUT_PCIE5P
RN2014 0R4P2R-PAD
CLK CLK_PCI_FB Layout Note: BIOS UMA/DIS Strap pin
[31] PCIE_CLK_LAN_REQ# L14 PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK H45 CLK_PCI_FB [18]
1500mil < Layout trace < 10000mil
AB42 CLKOUT_PEG_B_N XTAL25_IN V47 XTAL25_IN BOARD_ID1 BOARD_ID2
X01 12/09 AB40 NC V49 XTAL25_OUT
CLKOUT_PEG_B_P XTAL25_OUT
CLK_PEG_B_REQ# E6 PX(AMD) 0 0
Layout Note: PEG_B_CLKRQ#/GPIO56 R2007
Layout trace < 14000mil XCLK_RCOMP Y47 XCLK_RCOMP 1 2 +VCCDIFFCLKN
V40 DIS 0 1
CLKOUT_PCIE6N 90D9R2F-1-GP
V42 CLKOUT_PCIE6P NC
PCIE_CLK_REQ6# T13 UMA 1 0
PCIECLKRQ6#/GPIO45
X01 12/09 V38 K43 JTAG_TCK 1 TP2004 TPAD14-OP-GP
FLEX CLOCKS
CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64 Optimus(NV) 1 1

V37 CLKOUT_PCIE7P NC
A F47 CARD_READER_48M 1 TP2005 TPAD14-OP-GP <Core Design> A
CLK_PCIE_REQ7# CLKOUTFLEX1/GPIO65
K12 PCIECLKRQ7#/GPIO46
H47 CLK_27M_VGA_R 1 TP2006 TPAD14-OP-GP
TPAD14-OP-GP TP2007 PCIE_CLK_XDP_N_R CLKOUTFLEX2/GPIO66
TPAD14-OP-GP TP2008
1
1 PCIE_CLK_XDP_P_R
AK14
AK13
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 K49 BOARD_ID1 Wistron Corporation
PANTHER-GP-NF
71.PANTH.00U Title
PCH (PCI-E/SMBUS/CLOCK/CL)
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = PCH Layout Note:

RTC_AUX_S5 Place it at the open door location.
RN2102
1 4
2 3 Integrated SUS 1V VRM Enable
2
1
SRN20KJ-1-GP C2104 G2101 Low = External VRs
INTVRMEN Layout Note:
SC1U6D3V2KX-GP
GAP-OPEN
High = Internal VRs*
Place near PCH
2
A00 3/27
1
D D
PCH1A 1 OF 10 LPC_AD[3..0]
LPC_AD[3..0] [27,71]
RTC_X1 A20 C38 LPC_LAD0_PCHR2116 1 0R0402-PAD-2-GP
2 LPC_AD0
Q2102 RTCX1 FWH0/LAD0 LPC_LAD1_PCHR2121 0R0402-PAD-2-GP LPC_AD1
FWH1/LAD1 A38 1 2
LPC
[27] RTCRST_ON G RTC_X2 C20 B37 LPC_LAD2_PCHR2127 1 0R0402-PAD-2-GP
2 LPC_AD2
RTCX2 FWH2/LAD2 LPC_LAD3_PCHR2128 0R0402-PAD-2-GP LPC_AD3
FWH3/LAD3 C37 1 2
D RTC_RST# D20 RTCRST#
1
FWH4/LFRAME# D36 LPC_LFRAME#_PCH 1 2 LPC_FRAME# [27,71]

R2122 S SRTC_RST# G22 R2136 0R0402-PAD-2-GP
R2104 SRTCRST#
10KR2J-3-GP LDRQ0# E36
RTC
2N7002K-2-GP C2103 2 1 SM_INTRUDER# K22 K36 KB_DET# [69]
SC1U6D3V2KX-GP 1M1R2J-GP INTRUDER# LDRQ1#/GPIO23
84.2N702.J31
2
2ND = 84.2N702.031 RTC_AUX_S5 1 2 PCH_INTVRMEN C17 V5 INT_SERIRQ [27]
2
INTVRMEN SERIRQ
3rd = 84.07002.I31
4th = 84.2N702.W31 R2105
330KR2F-L-GP AM3 SATA_RXN0 [56]
HDA_BITCLK SATA0RXN
N34 AM1
HDA_BCLK SATA0RXP SATA_RXP0 [56]
HDD1
SATA 6G
SATA0TXN AP7 SATA_TXN0 [56]
HDA_SYNC L34 AP5 SATA_TXP0 [56]
HDA_SYNC SATA0TXP
[82] HDA_SPKR T10 SPKR SATA1RXN AM10 SATA_RXN1 [66]

AM8
R2123 Layout Note: HDA_RST# K34 HDA_RST#

SATA1RXP
SATA1TXN AP11
SATA_RXP1
SATA_TXN1
[66]
[66] mSATA
SATA1TXP AP10 SATA_TXP1 [66]
33R2J-2-GP Place close together.
2 1 HDA_SDOUT For RNxxxx later. [82] HDA_SDIN0 E34 AD7
[82] HDA_CODEC_SDOUT HDA_SDIN0 SATA2RXN
SATA2RXP AD5
R2125 G34 AH5
C 33R2J-2-GP Layout Note: HDA_SDIN1 SATA2TXN
AH4 C
HDA_RST# SATA2TXP
[82] HDA_CODEC_RST# 2 1 HDA_SDO and HDA_BCLK must be C34 HDA_SDIN2
IHDA
length matched to within 500 mils SATA3RXN AB8
R2126 A34 AB10
33R2J-2-GP HDA_SDIN3 SATA3RXP
SATA3TXN AF3
2 1 HDA_BITCLK R2107 AF1
[82] HDA_CODEC_BITCLK 1KR2J-1-GP HDA_SDOUT SATA3TXP
A36 HDA_SDO
SATA
[27] ME_UNLOCK 1 2 SATA4RXN Y7 SATA_RXN4 [56]
SATA4RXP Y5 SATA_RXP4 [56]
TPAD14-OP-GP TP2101 1PCH_GPIO33 C36 AD3
3D3V_S5 TPAD14-OP-GP TP2102

HDA_DOCK_EN#/GPIO33 SATA4TXN
SATA4TXP AD1
SATA_TXN4
SATA_TXP4
[56]
[56] ODD
Flash Descriptor Security Overide/ 1PCH_GPIO13 N32 HDA_DOCK_RST#/GPIO13
Y3
Intel ME Debug Mode SATA5RXN
Y1
Layout Note:
SATA5RXP
Low = Default * SATA5TXN AB3 HDD < 6000mil, mSATA < 6000mil, ODD < 12500mil
HDA_SDOUT High = Enable R2111 1 2 51R2J-2-GP PCH_JTAG_TCK_BUF J3 AB1
DY JTAG_TCK SATA5TXP
Layout Note: R2118 1 2 210R2F-L-GP PCH_JTAG_TMS H7 Y11 1D05V_PCH
DY JTAG_TMS SATAICOMPO
JTAG
Place at the separated point
R2119 1 2 210R2F-L-GP PCH_JTAG_TDI K5 Y10 SATA_COMP R2112 1 2 37D4R2F-GP
DY JTAG_TDI SATAICOMPI
R2120 1 2 210R2F-L-GP PCH_JTAG_TDO H1 1D05V_PCH
DY JTAG_TDO
AB12
3D3V_S0 SATA3RCOMPO
AB13 SATA3_COMP R2113 1 2 49D9R2F-GP
SATA3COMPI
R2106 1 2 1KR2J-1-GP HDA_SPKR
DY [27,60] SPI_CLK_R 1 2 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 R2114 1 2 750R2F-GP
R2108 33R2J-2-GP SPI_CLK SATA3RBIAS
B B
No Reboot Strap [27,60] SPI_CS0#_R 1 2 PCH_SPI_CS0# Y14 SPI_CS0#
R2109 33R2J-2-GP
Low = Default * T1 SPI_CS1# Layout Note:
SPI
HDA_SPKR High = No Reboot P3 SATA_LED# SATA_LED# [68]
SATALED#
Place close PCH(<500mil)
[27,60] SPI_SI_R 1 2 PCH_SPI_SI V4 SPI_MOSI SATA0GP/GPIO21 V14 PCH_GPIO21
R2110 33R2J-2-GP
+3VS_+1.5VS_HDA_IO 1 2 PCH_SPI_SO U3 P1 BBS_BIT0
[27,60] SPI_SO_R SPI_MISO SATA1GP/GPIO19 BBS_BIT0 [18]
R2115 33R2J-2-GP
R2103 1 2 1KR2J-1-GP HDA_SYNC
X01 12/21 PANTHER-GP-NF
71.PANTH.00U
PLL ODVR VOLTAGE 3D3V_S0
RN2103
Low = 1.8V INT_SERIRQ 1 4
HDA_SYNC High = 1.5V Q2101 PCH_GPIO21 2 3
* [36,37] RUN_ENABLE G
SRN10KJ-5-GP
D HDA_SYNC
R2124
[82] HDA_CODEC_SYNC 2 1 HDA_CODEC_SYNC_R S
2
33R2J-2-GP 2N7002K-2-GP RTC_X1

R2117 84.2N702.J31
1M1R2J-GP 2ND = 84.2N702.031 1 2 RTC_X2
3rd = 84.07002.I31 R2101 10MR2J-L-GP
4th = 84.2N702.W31 X2101
1
A HDA_CODEC_BITCLK HDA_CODEC_SDOUT <Core Design> A

1 4
HDA_SYNC:
2
This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V
DY EC2102
DY EC2103 Wistron Corporation
SC15P50V2JN-2-GP
1
1
C2101
VccVRM supply mode. 1K external pull-up resistor is required on this 2 3

1
1
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
C2102 Taipei Hsien 221, Taiwan, R.O.C.

signal on the board. Signal may have leakage paths via powered off devices (Audio SC15P50V2JN-2-GP
2
2
Codec) and hence contend with the external pull-up. A blocking FET is X-32D768KHZ-65-GP Title
recommended in such a case to isolate HDA_SYNC from the Audio Codec device PCH (SPI/RTC/LPC/SATA/IHDA)
until after the Strap sampling is complete. 82.30001.A41 Size Document Number Rev
A3 A00
2nd = 82.30001.841 BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = PCH
PCH1F 6 OF 10
PCH_GPIO00 T7 C40 SATA_ODD_PW RGT SATA_ODD_PW RGT [56]

BMBUSY#/GPIO0 TACH4/GPIO68
[27] EC_SMI# EC_SMI# A42 B41 BOARD_ID2 BOARD_ID2 [20]

TACH1/GPIO1 TACH5/GPIO69
PCH_GPIO6 H36 C41 PCH_GPIO70 1 TP2201 TPAD14-OP-GP
3D3V_S0 TACH2/GPIO6 TACH6/GPIO70
D D
RN2203 [27] EC_SCI# EC_SCI# E38 A40 PCH_GPIO71 1 TP2202 TPAD14-OP-GP
SRN10KJ-5-GP TACH3/GPIO7 TACH7/GPIO71
1 4 H_A20GATE_PCH PCH_GPIO08 C10 GPIO8
2 3 H_RCIN# A00 3/23
[60] RTC_DET# RTC_DET# C4 R2205
LAN_PHY_PWR_CTRL/GPIO12 0R0402-PAD-2-GP
PCH_GPIO15 G2 P4 H_A20GATE_PCH 1 2 H_A20GATE [27]
3D3V_S0 GPIO15 A20GATE
AU16 H_PECI_R R2203 1 2 0R2J-2-GP
RN2205 [56] SATA_ODD_PRSNT# SATA_ODD_PRSNT# U2
PECI DY H_PECI [5,27] VCCP_CPU
SRN10KJ-5-GP SATA4GP/GPIO16 H_RCIN#
RCIN# P5 H_RCIN# [27]
1 4 SATA_ODD_PRSNT#
GPIO
2 3 PCH_GPIO00 [27,86,92,93] DGPU_PW ROK DGPU_PW ROK D40 AY11 H_CPUPW RGD H_CPUPW RGD [5] R2202 1 2 2K2R2J-2-GP
TACH0/GPIO17 PROCPWRGD
CPU/MISC
[49] DBC_EN DBC_EN T5 AY10 PCH_THERMTRIP_R R2204 1 2 390R2J-1-GP H_THERMTRIP# [5]
SCLOCK/GPIO22 THRMTRIP#
[49] COLOR_ENGINE COLOR_ENGINE E8 T14 INIT3_3V# 1 TP2213 TPAD14-OP-GP

3D3V_S0 GPIO24 INIT3_3V#
RN2206 TPAD14-OP-GP TP2209 1 PCH_GPIO27 E16 AY1 DF_TVS 1D8V_S0
SRN10KJ-6-GP GPIO27 DF_TVS
1 8 PCH_GPIO49 PLL_ODVR_EN P8 GPIO28
1
2 7 MSATA_DET# AH8
PCH_GPIO38 MSATA_DET# TS_VSS1 R2207
3 6 [66] MSATA_DET# K1 STP_PCI#/GPIO34
4 5 DBC_EN AK11 2K2R2J-2-GP
TPAD14-OP-GP TP2210 PCH_GPIO35 TS_VSS2
1 K4 GPIO35
AH10 R2209
2
PCH_GPIO36 TS_VSS3
V8 SATA2GP/GPIO36
3D3V_S0 AK10 DF_TVS 1 2
TS_VSS4 H_SNB_IVB# [5]
C RN2201 PCH_GPIO37 M5 1KR2J-1-GP C
SRN10KJ-6-GP SATA3GP/GPIO37 Layout Note:
1 8 EC_SMI# PCH_GPIO38 N2 P37 Check these fuor balls are connected firstly, then to GND
EC_SCI# SLOAD/GPIO38 NC_1
2 7
3 6 PCH_GPIO6 [83] DGPU_HOLD_RST# DGPU_HOLD_RST# M3
DGPU_PW ROK SDATAOUT0/GPIO39
4 5
[93] DGPU_PW R_EN# DGPU_PW R_EN# V13 BG2 PCH_NCTF_BG2 1 TP2203 TPAD14-OP-GP
SDATAOUT1/GPIO48 VSS_NCTF_15#BG2
PCH_GPIO49 V3 BG48 PCH_NCTF_BG48 1 TP2204 TPAD14-OP-GP
SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16#BG48
PCH_GPIO57 D6 BH3 PCH_NCTF_BH3 1 TP2205 TPAD14-OP-GP
GPIO57 VSS_NCTF_17#BH3
BH47 PCH_NCTF_BH47 1 TP2206 TPAD14-OP-GP
3D3V_S5 VSS_NCTF_18#BH47
A4 VSS_NCTF_1#A4 VSS_NCTF_19#BJ4 BJ4
NCTF
RN2204 A44 BJ44
SRN10KJ-5-GP VSS_NCTF_2#A44 VSS_NCTF_20#BJ44
1 4 RTC_DET# A45 BJ45
PCH_GPIO57 VSS_NCTF_3#A45 VSS_NCTF_21#BJ45
2 3
A46 VSS_NCTF_4#A46 VSS_NCTF_22#BJ46 BJ46
2 1 COLOR_ENGINE A5 BJ5
R2221 DY 10KR2J-3-GP VSS_NCTF_5#A5 VSS_NCTF_23#BJ5
A6 BJ6
DY VSS_NCTF_6#A6 VSS_NCTF_24#BJ6
A4,A44,A45,A46,A5,A6,B3,B47,
BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
2 1 PCH_GPIO08
BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
R2224 10KR2J-3-GP TPAD14-OP-GP TP2211 1 PCH_NCTF_B3 B3 C2 PCH_NCTF_C2 1 TP2207 TPAD14-OP-GP
PCH_GPIO15 VSS_NCTF_7#B3 VSS_NCTF_25#C2
2 1
R2201 DY 1KR2J-1-GP TPAD14-OP-GP TP2212 1 PCH_NCTF_B47 B47 C48 PCH_NCTF_C48 1 TP2208 TPAD14-OP-GP
B VSS_NCTF_8#B47 VSS_NCTF_26#C48 B
D49,E1,E49,F1,F49
BD1 VSS_NCTF_9#BD1 VSS_NCTF_27#D1 D1
X01 12/09
NCTF TEST PIN:

BD49 VSS_NCTF_10#BD49 VSS_NCTF_28#D49 D49
3D3V_S0 BE1 E1
VSS_NCTF_11#BE1 VSS_NCTF_29#E1
2 DY 1 DGPU_PW R_EN# BE49 E49
R2225 2 DY 110KR2J-3-GP DGPU_HOLD_RST#
VSS_NCTF_12#BE49 VSS_NCTF_30#E49
R2226 10KR2J-3-GP BF1 F1
DGPU_PW R_EN# VSS_NCTF_13#BF1 VSS_NCTF_31#F1
2 1
R2227 2 110KR2J-3-GP DGPU_HOLD_RST# BF49 F49
R2228 10KR2J-3-GP VSS_NCTF_14#BF49 VSS_NCTF_32#F49
PANTHER-GP-NF
71.PANTH.00U
RN2202
SRN10KJ-5-GP
1 4 PCH_GPIO36
2 3 PCH_GPIO37
2 1 PLL_ODVR_EN
R2212 DY 1KR2J-1-GP
A DMB40 A
Wistron Corporation
PLL ON DIE VR ENABLE Taipei Hsien 221, Taiwan, R.O.C.
Title
Weakly internal pull up 20k.
GPIO28 High - Enable PCH (GPIO/CPU)
(PLL_ODVR_EN) Size Document Number Rev
LOW - Disable A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH Voltage Rail Voltage(V) Iccmax(A)

V_PROC_IO 1.05 0.001
V5REF 5 0.001
V5REF_Sus 5 0.001
1D05V_PCH
PCH1G POWER 7 OF 10 3D3V_S0
Vcc3_3 3.3 0.228
1.7A 0.061A
AA23 U48 VccADAC 3.3 0.063
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
SCD01U16V2KX-3GP
VCCCORE1 VCCADAC
D AC23 VCCCORE2 D
1
C2301
C2302
C2303
C2304
C2315
AD21 C2313 C2314 VccADPLLA 1.05 0.08
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
CRT
VCCCORE3
1
AD23 U47
AF21
VCCCORE4 VSSADAC DY X03 2/6 VccADPLLB 1.05 0.08
2
VCC CORE
VCCCORE5
AF23
2
2
VCCCORE6 3D3V_S0
AG21 VCCCORE7 R2304
VccCore 1.05 1.7
AG23 VCCCORE8 0.001A
AG24 AK36 +3VS_VCCA_LVDS 1 2 VccDMI 1.1 0.047
VCCCORE9 VCCALVDS
AG26 VCCCORE10
AG27 VCCCORE11 VSSALVDS AK37 0R0603-PAD-2-GP VccIO 1.05 3.711
AG29 VCCCORE12
AJ23 VCCCORE13
VccASW 1.05 0.903
1D8V_S0
LVDS
AJ26 VCCCORE14 VCCTX_LVDS1 AM37 R2301
AJ27 VCCCORE15 0.04A VccSPI 3.3 0.01
AJ29 AM38 +1.8VS_VCCTX_LVDS 1 2
SC22U6D3V5MX-2GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
VCCCORE16 VCCTX_LVDS2
AJ31 VCCCORE17
VccDSW3_3 3.3 0.001
1D05V_PCH
C2316
C2317
C2318
AP36 0R0603-PAD-2-GP
VCCTX_LVDS3
1
VccDFTERM 1.8 0.002
VCCTX_LVDS4 AP37
AN19 VccRTC 3.3 6uA
2
VCCIO28
VccSus3_3 3.3 0.095
TPAD14-OP-GP TP2301 1 VCCAPLLEXP BJ22 3D3V_S0
VCCAPLLEXP
0.228A VccSusHDA 3.3 0.01
VCC3_3_6 V33
HVCMOS
AN16 VCCIO15
VccVRM 1.5 0.167
1
C2319
AN17 SCD1U10V2KX-5GP VccClkDMI 1.05 0.07
VCCIO16
V34
2
VCC3_3_7
C X03 2/6 VccSSC 1.05 0.095 C
AN21 VCCIO17 VccDIFFCLKN 1.05 0.055
1D05V_PCH VCCVRM R2307 1D5V_S0
3.711A AN26 VCCIO18
0.167A 0R0402-PAD-2-GP VccALVDS 3.3 0.001
AN27 VCCIO19 VCCVRM3 AT16 1 2
VccTX_LVDS 1.8 0.04
1D05VS_VCC_DMI VCCP_CPU
C2306
C2307
C2308
C2309
AP21 R2306
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VCCIO20
1
0.047A 0R0402-PAD-2-GP
EC2305
AP23 AT20 1 2 Refer to chipset EDS V.0.7

SCD1U10V2KX-5GP
VCCIO21 VCCDMI1
DY DY
2
1
DMI
AP24 VCCIO22
VCCIO
C2320
AP26 AB36 SC1U6D3V2KX-GP
2
VCCIO23 VCCCLKDMI
AT24 VCCIO24
X03 2/16 R2308 1D05V_PCH
0.07A 0R0402-PAD-2-GP
AN33 +1.05VS_VCC_DMI_CCI 1 2
VCCIO25
1
AN34 VCCIO26 VCCDFTERM1 AG16
3D3V_S0 C2321
0.228A SC1U6D3V2KX-GP
2
BH29 VCC3_3_3 VCCDFTERM2 AG17
DFT / SPI
1
VCCVRM
C2310
AJ16
SCD1U10V2KX-5GP
VCCDFTERM3 1D8V_S0
2
B
AP16 VCCVRM2 0.002A B
VCCDFTERM4 AJ17
1
TPAD14-OP-GP TP2302 1VCCFDIPLL BG6 C2322
VCCAFDIPLL SCD1U10V2KX-5GP
1D05V_PCH
2
AP17 VCCIO27
V1
FDI
1D05VS_VCC_DMI VCCSPI 3D3V_S5

AU20 VCCDMI2 0.01A
PANTHER-GP-NF 1
71.PANTH.00U C2323
SC1U6D3V2KX-GP
2
A <Core Design> A
Wistron Corporation
Title
PCH (POWER1)
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = PCH
PCH1J POWER 10 OF 10 1D05V_PCH
TPAD14-OP-GP TP2401 1 VCCACLK AD49 N26

3D3V_S5 VCCACLK VCCIO29
0.001A
1
VCCIO30 P26
DG: none 3D3V_S5 T16 C2438
VCCDSW3_3 SC1U6D3V2KX-GP
CRB: 10uH P28
2
VCCIO31
1
3D3V_S0 TP2402 1 DCPSUSBYP V12 T27
C2416 TPAD14-OP-GP DCPSUSBYP VCCIO32 3D3V_S5 5V_S5
D L2401 SCD1U10V2KX-5GP T29 D
2
+V3.3S_VCC_CLKF33 +V3.3S_VCC_CLKF33 VCCIO33 3D3V_S5
1 2 T38 VCC3_3_5
2
IND-10UH-218-GP 0.095A
1
68.10050.10Y 1D05V_PCH T23 D2401
C2402 TP2403 +VCCAPLL_CPY_PCH VCCSUS3_3_7
2nd = 68.1001E.10N DY 1 BH23 VCCAPLLDMI2 83.R0304.A8F CH751H-40PT-GP
1
C2401 SC1U6D3V2KX-GP TPAD14-OP-GP T24 C2424 2nd = 83.R2004.B8F
2
SC10U6D3V5KX-1GP VCCSUS3_3_8 SCD1U10V2KX-5GP R2408
AL29
1
VCCIO14
V23 1 2
2
VCCSUS3_3_9
USB
TP2404 1 +VCCSUS1 AL24 V24 3D3V_S5 10R2J-2-GP
DCPSUS3 VCCSUS3_3_10
1
TPAD14-OP-GP
P24 C2426
VCCSUS3_3_6 SCD1U10V2KX-5GP
(0.1uFx1)
2
1
1D05V_PCH AA19 VCCASW1 C2425
0.93A VCCIO34 T26 1D05V_PCH
SCD1U10V2KX-5GP
AA21
2
VCCASW2
0.001A
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
C2406
SC1U6D3V2KX-GP
C2405
SC1U6D3V2KX-GP
C2419
SC1U6D3V2KX-GP
AA24 M26 +5VA_PCH_VCC5REFSUS
VCCASW3 V5REF_SUS
1
1
3D3V_S0 5V_S0
C2403
C2404
AA26
DY
Clock and Miscellaneous

VCCASW4 +VCCA_USBSUS
AN23
DY DY
2
2
DCPSUS4
AA27 VCCASW5
2
VCCSUS3_3_1 AN24 3D3V_S5
AA29 VCCASW6 DY C2437
SC1U10V2KX-1GP 83.R0304.A8F
D2402
CH751H-40PT-GP
2
AA31 VCCASW7 2nd = 83.R2004.B8F
0.001A R2407
1
AC26 P34 +5VS_PCH_VCC5REF 1 2
X01 1/9 VCCASW8 V5REF
C AC27 10R2J-2-GP C
VCCASW9
1
1D05V_PCH N20 3D3V_S5
VCCSUS3_3_2 C2427
0.08A
PCI/GPIO/LPC
AC29 VCCASW10
L2402 N22 SC1U6D3V2KX-GP
2
+1.05VS_VCCA_A_DPL VCCSUS3_3_3
1 2 AC31 VCCASW11
1
IND-10UH-218-GP P20 3D3V_S0
VCCSUS3_3_4
1
1
C2408
68.10050.10Y AD29 C2428

SC10U6D3V5KX-1GP
C2407 VCCASW12 SC1U6D3V2KX-GP

2nd = 68.1001E.10N DY P22
2
VCCSUS3_3_5
SC1U6D3V2KX-GP AD31 Voltage Rail Voltage(V) Iccmax(A)
2
VCCASW13
1
W21 AA16 C2430 V_PROC_IO 1.05 0.001
VCCASW14 VCC3_3_1 SCD1U10V2KX-5GP
2
W23 W16 3D3V_S0 V5REF 5 0.001
VCCASW15 VCC3_3_8
0.08A
L2403 W24 VCCASW16 VCC3_3_4 T34 V5REF_Sus 5 0.001
1 2 +1.05VS_VCCA_B_DPL
1
IND-10UH-218-GP W26 VCCASW17
C2431 Vcc3_3 3.3 0.228
1
68.10050.10Y SCD1U10V2KX-5GP
C2410 3D3V_S0 VccADAC 3.3 0.063
EC2409
2nd = 68.1001E.10N W29

SCD1U10V2KX-5GP
2
VCCASW18
SC1U6D3V2KX-GP
2
W31 AJ2 VccADPLLA 1.05 0.08

VCCASW19 VCC3_3_2
1
W33 VCCASW20
VccADPLLB 1.05 0.08
AF13 C2429
VCCIO5 SCD1U10V2KX-5GP VccCore 1.05 1.7
2
+VCCRTCEXT N16 DCPRTC 1D05V_PCH
VCCIO12 AH13 VccDMI 1.1 0.047
1
X03 2/16 0.167A

C2411 VCCVRM Y49 VCCVRM4 VCCIO13 AH14 VccIO 1.05 3.711
1
B SCD1U10V2KX-5GP B
2
C2432 VccASW 1.05 0.903

AF14 SC1U6D3V2KX-GP DY
2
VCCIO6
+1.05VS_VCCA_A_DPL BD47 VccSPI 3.3 0.01
VCCADPLLA
SATA
VCCAPLLSATA AK1
+1.05VS_VCCA_B_DPL BF47 VCCADPLLB
VccDSW3_3 3.3 0.001
+V1.05S_VCCAPLL_SATA3 1 TP2406
1D05V_PCH +VCCDIFFCLKN TPAD14-OP-GP VccDFTERM 1.8 0.002
0.055A +VCCDIFFCLK VCCVRM1 AF11 VCCVRM
AF17 VCCIO7
1 2 AF33 VCCDIFFCLKN1
VccRTC 3.3 6uA
R2412 AF34 AC16
VCCDIFFCLKN2 VCCIO2
1
0R0603-PAD-2-GP AG34 VCCDIFFCLKN3

VccSus3_3 3.3 0.095
C2414 AC17 1D05V_PCH
VCCIO3
SC1U6D3V2KX-GP VccSusHDA 3.3 0.01
2
X03 2/6 +V1.05S_SSCVCC AG33 VCCSSC VCCIO4 AD17

VccVRM 1.5 0.167
1
+VCCSST V16 C2435 VccClkDMI 1.05 0.07
DCPSST
1
C2415 1D05V_PCH SC1U6D3V2KX-GP
2
SCD1U10V2KX-5GP VccSSC 1.05 0.095
T17 T21
2
DCPSUS1 VCCASW22
TP2405 1 DCPSUS V19 VccDIFFCLKN 1.05 0.055
X03 2/6 TPAD14-OP-GP DCPSUS2
MISC
VCCP_CPU V21 VccALVDS 3.3 0.001

1D05V_PCH R2403 VCCASW23
0.001A
CPU
0R0402-PAD-2-GP BJ8 VccTX_LVDS 1.8 0.04

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
V_PROC_IO
C2418
C2420
1 2 +VCCDIFFCLK T19
VCCASW21
1
+3VS_+1.5VS_HDA_IO
1
C2417 3D3V_S5 Refer to chipset EDS V.0.7

A DMB40 A
C2412 SC4D7U6D3V3KX-GP 0.01A
2
HDA
SC1U6D3V2KX-GP A22 P32 1 2

RTC
2
RTC_AUX_S5 VCCRTC VCCSUSHDA

Wistron Corporation
1
6uA R2402
1D05V_PCH R2404 PANTHER-GP-NF 0R0402-PAD-2-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
0R0402-PAD-2-GP
0.095A 71.PANTH.00U C2433 Taipei Hsien 221, Taiwan, R.O.C.
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
C2421
C2422
1 2 +V1.05S_SSCVCC SCD1U10V2KX-5GP X03 2/6

1
Title
1
C2436
C2413 SC1U6D3V2KX-GP VCCSUSHDA need to be at either 3.3V or 1.5V. PCH (POWER2)
2
SC1U6D3V2KX-GP All the CODEC I/O Voltages need to be at the same Size Document Number Rev
2
A3 A00
level either 3.3 V or 1.5 V. BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = PCH
PCH1I 9 OF 10
AY4 VSS159 VSS259 H46

AY42 VSS160 VSS260 K18
B11 VSS163 VSS263 K46
B15 VSS164 VSS264 K7
B19 VSS165 VSS265 L18
B23 VSS166 VSS266 L2
D B27 VSS167 VSS267 L20 D
PCH1H 8 OF 10 B31 L26
VSS168 VSS268
H5 VSS0 B35 VSS169 VSS269 L28
B39 VSS170 VSS270 L36
AA17 VSS1 VSS80 AK38 B7 VSS171 VSS271 L48
AA2 VSS2 VSS81 AK4 F45 VSS172 VSS272 M12
AA3 VSS3 VSS82 AK42 BB12 VSS173 VSS273 P16
AA33 VSS4 VSS83 AK46 BB16 VSS174 VSS274 M18
AA34 VSS5 VSS84 AK8 BB20 VSS175 VSS275 M22
AB11 VSS6 VSS85 AL16 BB22 VSS176 VSS276 M24
AC19 VSS13 VSS92 AL27 BC14 VSS183 VSS283 M46
AC2 VSS14 VSS93 AL31 BC18 VSS184 VSS284 M8
AC21 VSS15 VSS94 AL33 BC2 VSS185 VSS285 N18
AC24 VSS16 VSS95 AL34 BC22 VSS186 VSS286 P30
AC33 VSS17 VSS96 AL48 BC26 VSS187 VSS287 N47
AC34 VSS18 VSS97 AM11 BC32 VSS188 VSS288 P11
AC48 VSS19 VSS98 AM14 BC34 VSS189 VSS289 P18
AD10 VSS20 VSS99 AM36 BC36 VSS190 VSS290 T33
AD11 VSS21 VSS100 AM39 BC40 VSS191 VSS291 P40
AD19 VSS24 VSS103 AM46 BD46 VSS194 VSS294 P7
AD24 VSS25 VSS104 AM7 BD5 VSS195 VSS295 R2
C AD26 AN2 BE22 R48 C
VSS26 VSS105 VSS196 VSS296
AD27 VSS27 VSS106 AN29 BE26 VSS197 VSS297 T12
AD33 VSS28 VSS107 AN3 BE40 VSS198 VSS298 T31
AD34 VSS29 VSS108 AN31 BF10 VSS199 VSS299 T37
AD36 VSS30 VSS109 AP12 BF12 VSS200 VSS300 T4
AD37 VSS31 VSS110 AP19 BF16 VSS201 VSS301 W34
AD40 VSS35 VSS114 AP38 BF26 VSS205 VSS305 V11
AD43 VSS37 VSS116 AP42 BD3 VSS207 VSS307 V26
AD8 VSS40 VSS119 AR2 BF40 VSS210 VSS310 V31
AE2 VSS41 VSS120 AR48 BF8 VSS211 VSS311 V36
AE3 VSS42 VSS121 AT11 BG17 VSS212 VSS312 V39
AF10 VSS43 VSS122 AT13 BG21 VSS213 VSS313 V43
AF12 VSS44 VSS123 AT18 BG33 VSS214 VSS314 V7
AD14 VSS45 VSS124 AT22 BG44 VSS215 VSS315 W17
AD16 VSS46 VSS125 AT26 BG8 VSS216 VSS316 W19
AF16 VSS47 VSS126 AT28 BH11 VSS217 VSS317 W2
AF26 VSS50 VSS129 AT34 BH19 VSS220 VSS320 Y12
AF27 VSS51 VSS130 AT39 H10 VSS221 VSS321 Y38
B B
AF4 VSS55 VSS134 AU24 BH35 VSS225 VSS325 Y8
AF42 VSS56 VSS135 AU30 BH39 VSS226 VSS328 BG29
AF46 VSS57 VSS136 AV16 BH43 VSS227 VSS329 N24
AF5 VSS58 VSS137 AV20 BH7 VSS228 VSS330 AJ3
AF7 VSS59 VSS138 AV24 D3 VSS229 VSS331 AD47
AF8 VSS60 VSS139 AV30 D12 VSS230 VSS333 B43
AG19 VSS61 VSS140 AV38 D16 VSS231 VSS334 BE10
AG2 VSS62 VSS141 AV4 D18 VSS232 VSS335 BG41
AG31 VSS63 VSS142 AV43 D22 VSS233 VSS337 G14
AG48 VSS64 VSS143 AV8 D24 VSS234 VSS338 H16
AH11 VSS65 VSS144 AW14 D26 VSS235 VSS340 T36
AH3 VSS66 VSS145 AW18 D30 VSS236 VSS342 BG22
AH36 VSS67 VSS146 AW2 D32 VSS237 VSS343 BG24
AH39 VSS68 VSS147 AW22 D34 VSS238 VSS344 C22
AH40 VSS69 VSS148 AW26 D38 VSS239 VSS345 AP13
AH42 VSS70 VSS149 AW28 D42 VSS240 VSS346 M14
AH46 VSS71 VSS150 AW32 D8 VSS241 VSS347 AP3
AH7 VSS72 VSS151 AW34 E18 VSS242 VSS348 AP1
AJ19 VSS73 VSS152 AW36 E26 VSS243 VSS349 BE16
AJ21 VSS74 VSS153 AW40 G18 VSS244 VSS350 BC16
AJ24 VSS75 VSS154 AW48 G20 VSS245 VSS351 BG28
AJ33 VSS76 VSS155 AV11 G26 VSS246 VSS352 BJ28
AJ34 VSS77 VSS156 AY12 G28 VSS247
AK12 VSS78 VSS157 AY22 G36 VSS248
AK3 VSS79 VSS158 AY28 G48 VSS249
H12 VSS250
PANTHER-GP-NF H18 VSS251
71.PANTH.00U H22 VSS252
A H24 VSS253 DMB40 A
H26 VSS254
H30 VSS255
H32
H34
VSS256
VSS257
Wistron Corporation
F3 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
VSS258 Taipei Hsien 221, Taiwan, R.O.C.
Title
PANTHER-GP-NF
71.PANTH.00U PCH (VSS)
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3 A00
BMW Z4 DIS
5 4 3 2 1
SSID = KBC 5 4 3 2 1
VBAT PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE VBAT MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
A00 3/15 X00 100.0K 10.0K 3.0V TBD 100.0K 10.0K(64.10025.6DL) 3.0V
X03 2/16 TBD 100.0K 13.7K(64.13725.6DL) 2.902V
1
3D3V_AUX_KBC VBAT 3D3V_S0 X01 12/02 X01 100.0K 20.0K 2.75V TBD 100.0K 17.8K(64.17825.6DL) 2.801V
X03 2/6 R2724 R2710 TBD 100.0K 22.1K(64.22125.6DL) 2.702V
64K9R2F-1-GP X02 100.0K 33.0K 2.48V 10KR2F-2-GP TBD 100.0K 27.0K(64.27025.6DL) 2.598V
TBD 100.0K 32.4K(64.32425.6DL) 2.492V
R2702 X03 100.0K 47.0K 2.24V TBD 100.0K 37.4K(64.37425.6DL) 2.402V
2
1 2 VBAT TBD 100.0K 43.2K(64.43225.6DL) 2.304V
0R0603-PAD-2-GP PCB_VER_AD A00 100.0K 64.9K 2.0V TBD 100.0K 49.9K(64.49925.6DL) 2.201V
2
1
MODEL_ID_DET TBD 100.0K 57.6K(64.57625.6DL) 2.093V
1
R2771 C2702 C2703 Reserved 100.0K 76.8 1.87V TBD 100.0K 64.9K(64.64925.6DL) 2.001V
DY
1
2D2R3-1-U-GP SCD1U10V2KX-5GP SC2D2U10V3KX-1GP R2726 TBD 100.0K 73.2K(64.73225.6DL) 1.905V
2
100KR2F-L1-GP Reserved 100.0K 100.0K 1.65V R2739 TBD 100.0K 82.5K(64.82525.6DL) 1.808V
2
3D3V_AUX_KBC_VCC C2717 100KR2F-L1-GP TBD 100.0K 93.1K(64.93125.6DL) 1.709V
DY
1
SCD1U10V2KX-5GP Reserved 100.0K 143.0K 1.358V C2718 TBD 100.0K 107K(64.10735.6DL) 1.594V
DY
2
D SCD1U10V2KX-5GP TBD 100.0K 120K(64.12035.6DL) 1.499V
D
2
Reserved 100.0K 174.0K 1.204V TBD 100.0K 137K(64.13735.6DL) 1.392V
TBD 100.0K 154K(64.15435.6DL) 1.299V
EC_AGND Reserved 100.0K 215.0K 1.048V TBD 100.0K 200K(64.20035.6DL) 1.099V
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
C2704
C2705
C2706
C2707
C2708
3D3V_AUX_S5 EC_AGND TBD 100.0K 232K(64.23236.6DL) 0.994V
1
1
C2701
C2709
C2710
X03 2/6
EC_VBKUP 1 2
DY DY DY RTC_AUX_S5
2
2
R2794
0R0402-PAD-2-GP
115
102
114
X01 12/12 C2711
19
46
76
88
75
4
U2701A 1 0F 2 SC220P50V2KX-3GP
1 2 U2701B 2 0F 2
DY
VCC1
VCC2
VCC3
VCC4
VCC5
VSBY
VBKUP
AVCC
VDD
KCOL[0..16] [69]
EC_AGND X03 2/6 31 53 KCOL0
[28] FAN_TACH1 GPIO56/TA1 KBSOUT0/GPOB0/JENK#
R27780R0402-PAD-2-GP 63 52 KCOL1
[40] AD_IA [31] PCIE_WAKE# GPIO14/TB1 KBSOUT1/GPIOB1/TCK
104 7 PLT_RST#_EC 1 2 64 51 KCOL2
VREF LRESET#/GPIOF7 PLT_RST# [5,18,31,65,66,71] [19,36,37,47] PM_SLP_S3# GPIO1/TB2 KBSOUT2/GPIOB2/TMS
2 50 KCOL3
LCLK/GPIOF5 CLK_PCI_KBC [18] KBSOUT3/GPIOB3/TDI
EC_AGND C2714 1 2 SCD1U10V2KX-5GP 97 3 LPC_FRAME# [21,71] LPC_AD[3..0] [21,71] [68] PWRLED# 32 49 KCOL4
PCB_VER_AD GPIO90/AD0 LFRAME#/GPIOF6 LPC_AD3 GPIO15/A_PWM KBSOUT4/GPOB4/JEN0# KCOL5
98 1 [82] KBC_BEEP 118 48
GPIO91/AD1 LAD3/GPIOF4 LPC_AD2 GPIO21/B_PWM KBSOUT5/GPIOB5/TDO KCOL6
[38] PSID_EC 99 128 [82] INSTANT_LAUNCH#_LED# 62 47
AMB_TEMP GPIO92/AD2 LAD2/GPIOF3 LPC_AD1 GPIO13/C_PWM KBSOUT6/GPIOB6/RDY# KCOL7
100 127 [38] AC_IN_KBC# 65 43
GPIO93/AD3 LAD1/GPIOF2 LPC_AD0 GPIO32/D_PWM KBSOUT7/GPIOB7 KCOL8
[66] AOAC_WWAN_EN# 108 126 [82] AUDIO_PRESENT#_LED# 22 42
GPIO5/AD4 LAD0/GPIOF1 GPIO45/E_PWM KBSOUT8/GPIOC0 KCOL9
[28] VGA_THRM 96 125 INT_SERIRQ [21] [19] PCH_WAKE#_EC 81 41
GPIO4/AD5 SERIRQ/GPIOF0 GPIO66/G_PWM KBSOUT9/GPOC1/SDP_VIS# KCOL10
95 8 PM_CLKRUN#_EC [19] [82] MOBILITY_CENTER#_LED# 66 40
[62] USBCHARGER_CB0 MODEL_ID_DET GPIO3/AD6 GPIO11/CLKRUN# GPIO33/H_PWM KBSOUT10&P80_CLK/GPIOC2 KCOL11
94 9 L_BKLT_EN [17] [68] CHG_AMBER_LED# 16 39
GPIO7/AD7 GPIO65/SMI# ECSCI#_KBC GPIO40/F_PWM KBSOUT11&P80_DAT/GPIOC3 KCOL12
29 38
ECSCI#/GPIO54 KBSOUT12/GPIO64 KCOL13
101 124 MOBILITY_CENTER# [82] 37
[28] FAN1_DAC GPIO94/DA0 GPIO10/LPCPD# KBSOUT13/GPIO63 KCOL14
[40] AD_IA_HW 105 121 H_A20GATE [22] [21] ME_UNLOCK 23 36
GPIO95/DA1 GPIO85/GA20 GPIO46/CIRRXM/TRIST# KBSOUT14/GPIO62 KCOL15
[82] AUDIO_PRESENT# 106 122 H_RCIN# [22] [65,66] AOAC_PCIE_WAKE# 113 35
GPIO96/DA2 KBRST#/GPIO86 GPIO87/CIRRXM/SIN_CR KBSOUT15/GPIO61/XOR_OUT KCOL16
[36,42] IMVP_PWRGD 107 [65] E51_TxD 111 34
GPIO97/DA3 GP/I/O83/SOUT_CR/TRIST# GPIO60/KBSOUT16 USB_DET#
33
GPIO57/KBSOUT17
KROW[0..7] [69]
3G_EN 79 27 77 54 KROW0
[66] 3G_EN GPIO02 GPIO52/PSDAT3/RDY# BLON_OUT [49] [19] PCH_SUSCLK_KBC GPIO0/EXTCLK KBSIN0/GPIOA0/N2TCK
ECSMI#_KBC 6 25 AD_IA_HW2 30 55 KROW1
GPIO24 GPIO50/PSCLK3/TDO AD_IA_HW2 [40] [82] AMP_MUTE# GPIO55/CLKOUT/IOX_DIN_DIO KBSIN1/GPIOA1/N2TMS
[69] CAP_LED# 109 11 PWR_CHG_AD_OFF [38] 56 KROW2
GPIO30/F_WP# GPIO27/PSDAT2 ECRST# KBSIN2/GPIOA2 KROW3
[36] S5_ENABLE 14 10 INSTANT_LAUNCH# [82] 85 57
GPIO34/CIRRXL GPIO26/PSCLK2 VCC_POR# KBSIN3/GPIOA3 KROW4
15 71 58
[68] BATT_WHITE_LED#
[39] BAT_IN# 80
GPIO36
GPIO41/F_WP#
GPIO35/PSDAT1
GPIO37/PSCLK1
72
TPDATA [69]
TPCLK [69]
TP VCCP_CPU R2721 KBSIN4/GPIOA4
KBSIN5/GPIOA5
59 KROW5
17 1 43R2J-GP2 PECI 13 60 KROW6
C [70] LID_CLOSE#
[19] RSMRST#_KBC
[19,46] PM_SLP_S4#
20
21
GPIO42/TCK
GPIO43/TMS
70
[5,22] H_PECI
1 2 EC_VTT 12
PECI
VTT
KBSIN6/GPIOA6
KBSIN7/GPIOA7
61 KROW7 C
BAT_SCL [39,40]
Charger
1
GPIO44/TDI GPIO17/SCL1/N2TCK R2720
[62] USBCHG_EN 26 69 BAT_SDA [39,40]
ECSWI#_KBC GPIO51/N2TCK GPIO22/SDA1/N2TMS
C2716
123 67 0R0402-PAD-2-GP NPCE885PA0DX-1-GP
SCD1U10V2KX-5GP
[65] WIFI_RF_EN 82
GPIO67/N2TMS GPIO73/SCL2
68
SML1_CLK [20,28,85] PCH
2
GPIO75 GPIO74/SDA2 SML1_DATA [20,28,85]
[65] AOAC_WLAN_EN# 83
GPIO76 GPIO23/SCL3
119 PM_LAN_ENABLE [31] X03 2/6
84 120
Layout Note: [19,36] S0_PWR_GOOD GPIO77 GPIO31/SDA3
24 PROCHOT_EC
RTCRST_ON [21]
Need very close to EC GPIO47/SCL4
28 LCD_TST_EN [49]
Layout Note: X03 2/6
33R2J-2-GP R2736 2 EC_SPI_CS#_C GPIO53/SDA4
[21,60] SPI_CS0#_R 1 90 1 R2792 2 LCD_TST [49] Need very close to EC
33R2J-2-GP R2719 2 EC_SPI_CLK_C F_CS0# 0R0402-PAD-2-GP R2764 ECSCI#_KBC
[21,60] SPI_CLK_R 1 92 [22] EC_SCI# 1 2 0R0402-PAD-2-GP
33R2J-2-GP R2725 2 EC_SPI_DI_C F_SCK PSL_OUT#
[21,60] SPI_SO_R 1 86
F_SDI&F_SDIO1 PSL_OUT_GPIO71#
74 X03 2/6
33R2J-2-GP 1 R2722 2 EC_SPI_DO_C 87 93 PSL_IN2# R2723 1 2 0R0402-PAD-2-GP ECSMI#_KBC
[21,60] SPI_SI_R F_SDIO&F_SDIO0 PSL_IN2_GPI06# [22] EC_SMI#
91 73 PSL_IN1#
[68] TP_LOCK_LED# GPIO81/F_WP# PSL_IN1_GPI70# R2727 1 2 0R0402-PAD-2-GP ECSWI#_KBC
[20] EC_SWI#
[19] PM_PWRBTN# 117

GPIO20/TA2/IOX_DIN_DIO
[19] AC_PRESENT 112
GP/I/O84/IOX_SCLK/XORTR# KBC_VCORF
[82] USB_PWR_EN# 110 44 X01 12/02
GPO82/IOX_LDSH/TEST# VCORF
1
C2712 PM_CLKRUN#_EC R2730 1 2 0R2J-2-GP
DY BOOST_MODE# [40]
AGND
GND1
GND2
GND3
GND4
GND5
GND6
SC1U25V3KX-1-GP
2
For System Reset. H_A20GATE R2731 1 2 0R2J-2-GP
NPCE885PA0DX-1-GP DY DGPU_PWROK [22,86,92,93]
18
45
78
89
116
5
EC_AGND 103
Layout Note:
AOAC Ambient temperature detect Need very close to EC 3D3V_AUX_S5
X01 12/02
1
ECRST#
VBAT X03 2/6 Layout Note: R2705 3D3V_AUX_KBC
1 2 Connect GND and AGND planes via either 10KR2J-3-GP
RN2702
0R resistor or connect directly.
2
R2765 C2715 USB_DET# 1 8
2
1
1
0R0402-PAD-2-GP MOBILITY_CENTER# 2 7
SC1U6D3V2KX-GP
E
R2713 EC_AGND 6 5 INSTANT_LAUNCH# 3 6
10KR2B-GP
[28,36,85] PURE_HW_SHUTDOWN# B
DY AUDIO_PRESENT# 4 5
2
RSTSW1
Q2701 SW-TACT-130-GP-U SRN100KJ-5-GP
2
1
C
B AMB_TEMP
EC_GPIO47 High Active
MMBT3906-4-GP
84.T3906.A11
62.40009.731
2nd = 62.40089.441 B
2nd = 84.03906.F11
2
R2703 R2740
NTC-10K-27-GP C2726 C2725 0R2J-2-GP
1 2
DY
SCD1U10V2KX-5GP
69.60013.131
SC100P50V2JN-3GP
1
2nd = 69.60011.201 X03 2/6

3rd = 69.60037.011 Q2702
PROCHOT_EC G R2733
0R0402-PAD-2-GP 3D3V_AUX_KBC
D H_PROCHOT#_EC 1 2 X01 12/09
H_PROCHOT# [5,40] RN2701
1
EC_AGND
R2732 S BAT_SCL 3 2
1
100KR2J-1-GP C2713 BAT_SDA 4 1 3D3V_WLAN_AOAC

2N7002K-2-GP SC47P50V2JN-3GP
84.2N702.J31 SRN4K7J-8-GP
2
2ND = 84.2N702.031
2
3rd = 84.07002.I31
4th = 84.2N702.W31 ECRST# R2707 1 2 10KR2J-3-GP R2706
Power Switch Logic(PSL) 100KR2J-1-GP 3D3V_WLAN_AOAC
X01 12/20 D2702
X01 12/09 2
1
3D3V_AUX_S5 3D3V_AUX_S5 C2722 3D3V_AUX_S5 AOAC_PCIE_WAKE# 2 1AOAC_PCIE_WAKE#_R 3 3D3V_WWAN_AOAC
SCD1U10V2KX-5GP DY DY
2
R2701 1
2
R2734 1 2 100KR2J-1-GP
X03 2/6 R2704 X01 12/21 330KR2J-L1-GP 3D3V_AUX_KBC CH715FPT-GP
330KR2J-L1-GP X01 12/13 3D3V_LAN_S5
R2767 AC_IN_KBC# R2714 1 2 100KR2J-1-GP 83.R0304.B81
DY
S
1
R2716
0R0402-PAD-2-GP BAT_IN# R2715 1 2 100KR2J-1-GP 2nd = 83.00040.E81
1
1 2 PSL_IN2# PSL_OUT# 1 2 KBC_ON#_GATE_L 1 2 KBC_ON#_GATE G

[68] KBC_PWRBTN#
2
G
R2791
R2735 DY 0R2J-2-GP R2711
R2768 1KR2J-1-GP 20KR2J-L2-GP Q2703 D 3D3V_S0 100KR2J-1-GP
0R0402-PAD-2-GP DMP2130L-7-GP
1
D
[40] AC_IN# 1 2 PSL_IN1# 84.02130.031
1
2ND = 84.03413.A31 FAN_TACH1 R2708 1 2 10KR2J-3-GP PCIE_WAKE#
A 3D3V_AUX_KBC 3D3V_AUX_KBC
3D3V_S5
A
1
D2707 X01 12/21 R2709 3G_EN R2712 1 2 10KR2J-3-GP

1 USB_DET# X01 12/13 10KR2J-3-GP
DY <Core Design>
X01 12/02 Q2704
3 G LID_CLOSE# R2799 1 2100KR2J-1-GP
[62] USBDET_CON#
Wistron Corporation
2
2 KBC_ON#_GATE_L D S5_ENABLE 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

BAT54CPT-GP S
VGA_THRM C2720 2
83.R2003.E81
2ND = 83.00054.Q81 2N7002K-2-GP DY1SCD1U10V2KX-5GP Title
84.2N702.J31 KBC Nuvoton NPCE885

2ND = 84.2N702.031 Size Document Number Rev
3rd = 84.07002.I31 A2 A00
4th = 84.2N702.W31 EC_AGND BMW Z4 DIS
Date: Tuesday, April 03, 2012 Sheet 27 of 105
5 4 3 2 1
5 4 3 2 1
SSID = Thermal
3D3V_S0
RN2801
2 3
1 4 Fan controller
SRN2K2J-1-GP
R2802 U2802 5V_S0

3D3V_S0 0R2J-2-GP
1 2 FON# 1 8
D 5V_S0
DY 2
FON# GND
7 D
THM_SML1_DATA FAN_VCC VIN GND
[20,27,85] SML1_DATA 6 1 3 VO GND 6
1
[27] FAN1_DAC 4 5 C2803 C2804
VSET GND
C2814
5 2
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
1
1
C2813 84.2N702.A3F
2
SCD1U10V2KX-5GP 4 3 2nd = 84.DM601.03F G991P11U-GP
3rd = 84.2N702.E3F 74.00991.031
2
Q2804 4th = 84.2N702.F3F 2nd = 74.02793.A31
2N7002KDW -GP 3rd = 74.05606.A71
THM_SML1_CLK Layout Note:
Need 10 mil trace width.
[20,27,85] SML1_CLK
84.03904.L06
2ND = 84.03904.P11
NCT7718_DXP
U2801 X03 2/6
3
1
1 8 THM_SML1_CLK R2807 FAN1
C2816 C2812 VDD SCL THM_SML1_DATA 0R0402-PAD-2-GP
1 2 D+ SDA 7 4
Q2803 SC470P50V3JN-2GP SC2200P50V2KX-2GP 3 6 ALERT# 1 2 FAN_TACH1_C 1
DY [27] FAN_TACH1
2
2
PMBS3904-1-GP D- ALERT#
4 5
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
T_CRIT# GND
1
C2808
C2815
NCT7718_DXN 2
FAN_VCC 3
2.System Sensor, Put on palm rest NCT7718W -GP DY DY 5
2
74.07718.0B9
2
X03 2/13 ACES-CON3-11-GP
1
THERM_SYS_SHDN# 1 2 T_CRIT# C2809 D2802 C2810
Layout Note:
1
R2813 0R0402-PAD-2-GP SC4D7U6D3V3KX-GP
DY SC2200P50V2KX-2GP
C C
DY DY
CH551H-30PT-GP
3D3V_S0 Signal Routing Guideline: 20.F0772.003
2
Layout Note: Trace width = 15mil 2nd = 20.F1841.003
2
C2812 close U2801 ALERT# R2815 1 2 18K7R2F-GP
T_CRIT# R2814 1 2 2KR2F-3-GP
83.R5003.C8F
Layout Note: 2ND = 83.R5003.H8H
3rd = 83.5R003.08F
Both DXN and DXP routing 10 mil trace width and 10 mil spacing.
FAN_TACH1_C 1 AFTP2801
FAN_VCC 1 AFTP2802
3D3V_S0
EMI
GPU thermal sensor X01 12/02
1
C2817 FAN_VCC
B SCD1U10V2KX-5GPDY B
2
[85] P2800_VGA_DXP
1
U2803
VGA_THRM EC2801
DY
1
C2818 5 4 VGA_THRM [27] SCD1U16V2KX-3GP
2
VCC TDR
1
SC2200P50V2KX-2GP 6 3 MISC_THRM 1 TP2803 TPAD14-OP-GP
DXP TDL R2837
7 2
DY
2
DXN GND 402KR2F-GP

8 OTZ ADJ 1
[85] P2800_VGA_DXN DY DY
2
P2800EB0-GP
74.02800.B71
Layout Note:
Both DXN and DXP routing 10 mil trace width and 10 mil spacing.
Thermal Sensor
Q2802
ADJ Temp.(C)
A S THERM_SYS_SHDN# <Core Design> A
Pull high 95 [27,36,85] PURE_HW _SHUTDOW N# D
G 3D3V_S0
Wistron Corporation
Pull low 90 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1

SCD1U10V2KX-5GP 2N7002K-2-GP
Floating 85 DY 84.2N702.J31 Title
2
2ND = 84.2N702.031 Thermal NCT7718W/Fan Controllor P2793

3rd = 84.07002.I31 Size Document Number Rev
4th = 84.2N702.W31 A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = LOM
3D3V_LAN_S5 3D3V_LAN_S5 Q3106
PA102FMG-GP-U
3D3V_S5 84.00102.031 3D3V_LAN_S5
2nd = 84.02301.G31
1
2
1
RN3101
R3102 SRN10KJ-5-GP S D
10KR2J-3-GP DY
1
C3133 C3134
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
R3103 C3132 R3116
1Q402_14
3
2
SCD1U10V2KX-5GP 10KR2J-3-GP C3130
CLK_LAN_REQ#_EN
D 10KR2J-3-GP D
1
SC1U6D3V2KX-GP
2
LAN_ENABLE_R_C
2
1
1 2PM_LAN_ENABLE_R
2 3 PLT_RST#_LAN R3117
84.03904.L06
[5,18,27,65,66,71] PLT_RST# DY Q3105 20KR2J-L2-GP
Q3102
2ND = 84.03904.P11 [27] PM_LAN_ENABLE G
PMBS3904-1-GP
2
Q3101 D
PMBS3904-1-GP 1 2 R3122
[20] PCIE_CLK_LAN_REQ# 3 2 CLK_LAN_REQ#_R 100KR2J-1-GP S
R3113
R3106 0R0402-PAD-2-GP 2N7002K-2-GP
1
2
DY 1 84.2N702.J31
2ND = 84.2N702.031
0R2J-2-GP A00 3/23 3rd = 84.07002.I31
4th = 84.2N702.W31
3D3V_LAN_S5
3D3V_LAN_S5 U3101
1 VDD33 LED0 38
C3101 C3102 C3103 C3104 C3105 C3114 C3113 AVDDL 39
Layout Note: LED1
1
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
16 AVDD33 LED2 23 X03 2/6
1
3D3V_S0
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC1KP50V2KX-1GP
DY Close to pin16 13 AVDDL

31 26 LAN_SMDATA 1 TP3104 TPAD14-OP-GP
2
2
AVDDL SMDATA LAN_SMCLK
AVDDVCO 34 25
2
AVDDL SMCLK
1
6 AVDDL_REG
1
C
AVDDH 9 R3136 C
AVDDH_REG LAN_XTAL1 C3110 30KR2J-4-GP
22 8
AVDDH XTLI
7 LAN_XTAL0 DY SCD1U10V2KX-5GP
2
XTLO
DVDDL 37
2
DVDDL_REG RBIAS ISOLATn
RBIAS 10
2 PLT_RST#_LAN RBIAS
Layout Note: 33
PERST#
5 ISOLATn
[20] CLK_PCIE_LAN REFCLK_P ISOLAT#
Close to pin1 [20] CLK_PCIE_LAN# 32 REFCLK_N
2
AVDDL 24 LOM_PPS 1 TP3103 TPAD14-OP-GP
PPS R3131
[20] PCIE_TXP6 35 RX_P
[20] PCIE_TXN6 36 RX_N TESTMODE 27 2K37R2F-GP
C3107 C3106 C3119 C3112 C3118 1 2 SCD1U10V2KX-5GP PCIE_RXP6_L 30 40 LX
1
[20] PCIE_RXP6 TX_P LX
1
SCD1U10V2KX-5GP
C3117 1 2 SCD1U10V2KX-5GP PCIE_RXN6_L 29

Layout Note: Layout Note: [20] PCIE_RXN6 TX_N
1
1
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
NC#17 17
Close to pin13 Close to pin13 [59] LAN_MDI0P 11 18
2
TRXP0 NC#18
[59] LAN_MDI0N 12 19
2
TRXN0 NC#19
NC#20 20
[59] LAN_MDI1P 14 TRXP1 NC#21 21
[59] LAN_MDI1N 15 TRXN1 NC#28 28
[27] PCIE_W AKE# 3 WAKE#

CLK_LAN_REQ#_R 4 41
Layout Note: CLKREQ# GND
Close to pin31
AR8162-AL3A-R-GP
71.08162.A03
AVDDH
B B
DVDDL AVDDL AVDDVCO

C3109 C3108
C3116 X01 12/15 X03 1/30
Layout Note: Layout Note:
1
1
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
( (
Close to pin9 Close to pin22 LX 2 1 2 1 2 1
( (
2
C3127 C3126 C3125 C3123 C3124

SCD1U10V2KX-5GP
1
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
L3103 L3102 L3101
1
1
SC1KP50V2KX-1GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
IND-4D7UH-253-GP BLM18KG601SN1D-GP BLM18KG601SN1D-GP
DY DY
EC3101
DY 68.4R71E.10R 68.00084.G71 68.00084.G71
2
2
2
2nd = 68.4R71G.10G 2nd = 68.00335.091 2nd = 68.00335.091
3rd = 68.00230.131 3rd = 68.00230.131
AVDDVCO
Layout Note:
Close to pin37
EC3122 C3120 C3121
X01 12/15
1
1
SC4D7U6D3V3KX-GP
SCD1U10V2KX-5GP
SC1U10V2KX-1GP
DY Layout Note:
Close to pin34
2
X3101
LAN_XTAL1 1 4
A <Core Design> A
LAN_XTAL0
2 3
Wistron Corporation
1
C3128
SC18P50V2JN-1-GP 1 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
XTAL-25MHZ-155-GP C3129 Taipei Hsien 221, Taiwan, R.O.C.
2
SC18P50V2JN-1-GP
2
Title
82.30020.D41
2nd = 82.30020.G61 LOM
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C
(Blanking) C
B B
DMB40
A A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
A B C D E
4 4
3 3
(Blanking)
2 2
1 DMB40 1
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
A B C D E
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = Reset.Suspend
2
D3601
3 BAS16-6-GP
[19,27] S0_PW R_GOOD
2
1
3 PURE_HW _SHUTDOW N# [27,28,85]
D3602
D BAS16-6-GP [41] 3V_5V_EN 1 D
83.00016.K11 83.00016.K11
2ND = 83.00016.F11 X03 2/6 2ND = 83.00016.F11
1
1 2 S5_ENABLE [27]
R3614 R3602
0R0402-PAD-2-GP 200KR2J-L1-GP DY R3603
[27,42] IMVP_PW RGD 1 2 SYS_PW ROK [19] 1KR2J-1-GP
2
1
Q3603 C3612
PS_S3CNTRL G SCD01U50V2KX-1GP DY
2
D
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
ROSA Run Power
15V_S5
Rds(on) = 11 ~ 14mOhm
AO4468 MAX 11.6A
5V_S5 U3601 5V_S0
C 2 AO4468-GP C
R3604 8 D S 1
100KR2J-1-GP 7 D S 2
6 D
D
S
G
3 5V_S0
5 4
1
5V_S0 Comsumption
1
3D3V_AUX_S5
1 2 5V_RUN_ENABLE C3603 Peak current 6A
SC10U6D3V5KX-1GP
2
1
R3605
10KR2J-3-GP C3608
1 2 PS_S3CNTRL SCD01U50V2KX-1GP 84.04468.037
PS_S3CNTRL [37,93]
2
2nd = 84.04178.037
R3606 3rd = 84.02659.037
100KR2J-1-GP
D G S
6
Rds(on) =11 ~ 14mOhm

Q3602 AO4468 MAX 11.6A
2N7002KDW -GP
84.2N702.A3F 3D3V_S5 U3602 3D3V_S0
1
2nd = 84.DM601.03F AO4468-GP

S G D 3rd = 84.2N702.E3F 8 D S 1
4th = 84.2N702.F3F 7 D
D
S
S
2 3D3V_S0
6 3
5 D G 4
1
B [19,27,37,47] PM_SLP_S3# 3D3V_S0 Comsumption B
C3604
1 2 3.3V_RUN_ENABLE SC10U6D3V5KX-1GP Peak current 2.5A
[21,37] RUN_ENABLE
2
1
R3607
10KR2J-3-GP C3605 84.04468.037
SCD01U50V2KX-1GP 2nd = 84.04178.037
2
3rd = 84.02659.037
1D5V_S3 1D5V_S0
1D5V_S0
U3606
8 D S 1 TPCA8062-H-GP MAX 28A
7 D S 2
6 D S 3
Rds(on) = 4.1~5.6m Ohm
1
5 D G 4 MAX Current 6A
C3609
<Core Design>
A TPCA8062-H-GP SC10U6D3V5KX-1GP A
2
1 2 1.5V_RUN_ENABLE
R3630 84.08062.037 Wistron Corporation

1
10KR2J-3-GP 2nd = 84.00460.037 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
SCD01U50V2KX-1GP
2
Title
Power Plane Enable

A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = Reset.Suspend Close to DIMM

S3 Power Reduction Circuit PM_DRAM_PWRGD
0D75V_S0 1D5V_S0
Close to CPU
1
S3 Power Reduction Circuit Processor VREF_DQ Implementation
R3703 R3704
22R2J-2-GP 220R2J-L2-GP
D
R3707 DY D
0R2J-2-GP
Q3702_D2
1 2
DY
Q3701_D
M_VREF_DQ_DIMMA +V_SM_VREF_CNT
Q3708
S
D
D
D Q3702
2
Q3701 2N7002K-2-GP
G 2N7002K-2-GP
84.2N702.J31 DY 84.2N702.J31
R3705 2ND = 84.2N702.031
2N7002K-2-GP 100KR2J-1-GP 2ND = 84.2N702.031
1
84.2N702.J31 3rd = 84.07002.I31
S
2ND = 84.2N702.031 4th = 84.2N702.W31
S
3rd = 84.07002.I31
4th = 84.2N702.W31 [36,93] PS_S3CNTRL [36,93] PS_S3CNTRL
[21,36] RUN_ENABLE
X03 2/6
R3710
0R0402-PAD-2-GP
[45,48] 1D05V_VTT_PW RGD 1 2
C
Close to CPU C
1 2 0D75V_EN S3 Power Reduction Circuit SM_DRAMRST#
[19,27,36,47] PM_SLP_S3# R3716 DY 22R2J-2-GP 0D75V_EN [46]
1
C3705
SCD1U10V2KX-5GP 1D5V_S3
DY
1
Q3704 R3706
G 1KR2J-1-GP
[36,93] PS_S3CNTRL
D 0D75V_EN S3 Power Reduction Circuit
2
S Q3703 SM_DRAMRST#
[5] SM_DRAMRST# S
2N7002K-2-GP
84.2N702.J31 D SM_DRAMRST#_D 1 2 DDR3_DRAMRST# [14,15]
2ND = 84.2N702.031
3rd = 84.07002.I31 [20] DRAMRST_CNTRL_PCH G R3718
4th = 84.2N702.W31 1KR2J-1-GP
PM_DRAM_PWRGD must have a maximum of 15ns rise or fall time 2N7002K-2-GP
over VDDQ * 0.55 200mV and the edge must be monotonic 84.2N702.J31
2ND = 84.2N702.031
1
3rd = 84.07002.I31
C3703 4th = 84.2N702.W31 C3702
SCD047U10V2KX-2GP SC100P50V2JN-3GP
2
B B
Close to CPU
S3 Power Reduction Circuit PM_DRAM_PWRGD
3D3V_S0 1D5V_S0
1
X01 11/28 R3714

10KR2J-3-GP R3702
200R2F-L-GP
DY
U3701
2
[19] PM_DRAM_PW RGD PM_DRAM_PW RGD 1 X01 12/02

5
1D05V_VTT_PW RGD 2
4 VDDPW RGOOD_R 1 2 VDDPW RGOOD [5]
3
R3719
TC7SZ08FU-2-GP 910R2F-1-GP
1
73.7SZ08.EAH
2ND = 73.01G08.L04 R3722 R3720
750R2F-GP
3rd = 73.7SZ08.DAH DY 39R2J-L-GP
2
Q3709
A DMB40 A
[36,93] PS_S3CNTRL G
DY VDDPW RGOOD_D
D
Wistron Corporation
S 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2N7002K-2-GP Title
R3717 S3 Power Reduction

0R2J-2-GP Size Document Number Rev
PM_DRAM_PW RGD VDDPW RGOOD_R A3 A00
1
DY 2 BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Support 5V_S5
2
PR3802 84.03904.L06
1
15KR2J-1-GP 2nd = 84.03904.P11 3D3V_S5
PR3803
2
10KR2J-3-GP
1
PQ3802_1 1 PMBS3904-1-GP 3D3V_S5
1
D
PQ3802 D
2
2
PD3803
1
PR3811 PSID_DISABLE#_R_C BAV99-5-GP-U
100KR2J-1-GP PR3806
X03 2/6 2K2R2J-2-GP
83.00099.T11
G
1
3
X03 2/6 PQ3801 2nd = 83.3X101.011
2
FDV301N-NL-GP
PR3819 PR3807
PS_ID_R 1 2 PS_ID_R2 D S PS_ID 1 2
D
PSID_EC [27]
0R0603-PAD-2-GP
84.00301.A31 33R2J-2-GP
2nd = 84.3K329.031
2
PR3808
1 2
DY PD3804 DY
Layout Note: SM24DTCT-GP-U 33R2J-2-GP
3
PSID Layout width > 25mil
DCIN1
5
4 +DC_IN AD+
C 3 PU3801 X01 12/19 C
2 1 S D 8
S D
PC3805
PC3803
PC3804
1 2 7
SC1U25V5KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
1
X03 1/30 S D
PC3801
PC3806
240KR3-GP
3 6
SC10U25V5KX-GP
K
1
1
PR3816 G D
PR3809
6 4 5
7 PD3801 PC3802
8 3K3R6J-GP P6SBMJ24APT-GP SCD1U25V3KX-GP SI7121DN-T1-GE3-GP
2
9
2
83.P6SBM.AAG 84.06675.030
A
DC-JACK255-GP 2nd = 83.22R03.03G 2nd = 84.07121.037
PQ3809_D
PQ3805
22.10261.401
1
1
R2
PQ3804 E Id=-9.6A
D
PR3814 C AD_OFF_L B PR3810
100KR2J-1-GP PQ3809 B R1 R1
C AD_OFF_R 47KR3J-L-GP Qg=-25nC
DY 2N7002K-2-GP E Rdson=18~30mohm
R2 PDTA124EU-1-GP
84.2N702.J31
2
2
PDTC124EU-1-GP 84.00124.K1K
2ND = 84.2N702.031 84.00124.H1K 2nd = 84.05124.A11
3rd = 84.07002.I31 2nd = 84.05124.011
4th = 84.2N702.W31
G
S
X01 12/02
PQ3810 [27] PW R_CHG_AD_OFF

G AC_IN#_G
B B
[27] AC_IN_KBC# D
S
DY
2N7002K-2-GP
1
84.2N702.J31
PR3815
100KR2J-1-GP
DY
2
A <Core Design> A
Wistron Corporation
Title
Size Document Number

DCIN Rev
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Support
D D
BT+
Batt CONN
K
1
1
C3902 C3901 PD3903 X01 12/02
SCD1U50V3KX-GP DY SC2200P50V2KX-2GP DY 1SMA18AT3G-GP
2
BATT1
A
11
X01 12/20 9
8
R3902 1 2100R2J-2-GP PBAT_SMBCLK1 7
[27,40] BAT_SCL
R3903 1 2100R2J-2-GP PBAT_SMBDAT1 6
[27,40] BAT_SDA
R3904 1 2100R2J-2-GP PBAT_PRES1# 5
[27] BAT_IN#
A00 3/15 SYS_PRES1# 4
X01 12/02 3
2
1
EC3902
1 2 SYS_PRES1# SYS_PRES1# EC3901 SC10P50V2JN-4GP 1
DY SC10P50V2JN-4GP DY DY 10
2
R3901
0R2J-2-GP SYN-CON9-24-GP
20.81755.009
2nd = 20.81771.009
NP2
NP1
6
3
1
4
C C
7
BATSW 1 AFTP3902 1 PBAT_PRES1#

SW -SLIDE77-GP AFTP3903 1 PBAT_SMBDAT1
62.40068.021 AFTP3904 1 PBAT_SMBCLK1
2nd = 62.40018.641 AFTP3905 1 BT+
Note: Mark the ON/OFF on the MB. X01 12/02
BAT_SCL
BAT_IN#
BAT_SDA
3
DY
3
D3901
D3902 D3903
DY BAV99-5-GP-U
DY BAV99-5-GP-U
BAV99-5-GP-U
2
83.00099.T11
1
83.00099.T11 83.00099.T11 2nd = 83.00099.K11

2nd = 83.00099.K11 2nd = 83.00099.K11 3rd = 83.BAV99.D11
B
3rd = 83.BAV99.D11 3rd = 83.BAV99.D11 B
3D3V_AUX_KBC
Layout Note:
Place near Battery CONN
A <Core Design> A
Wistron Corporation
Title
BATT CONN
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = Charger
DCBATOUT
AD+_TO_SYS
AD+ BT+
PU4004 PR4002 PU4006

8 D S 1 1 2 1 S D 8
1
7 D S 2 2 S D 7
D S S D
PR4003
GAP-CLOSE-PWR-3-GP
6 3 D01R3721F-GP-U AD+ 3 6
100KR2J-1-GP
X03 1/30 5 D G 4 4 G D 5
1
PG4002
1
D D
1
SI7121DN-T1-GE3-GP PG4003 SI7121DN-T1-GE3-GP
2
PR4004 84.06675.030 AD+_G_2 GAP-CLOSE-PWR-3-GP 84.06675.030
1
PWR_CHG_REGN 3KR5J-GP 2nd = 84.07121.037 2nd = 84.07121.037
2
2
2
PR4025
10KR2F-2-GP
PR4006
PR4001
Id= -10A 470KR2J-2-GP
2
0R2J-2-GP
Qg= -22nC Id=-8.6A
1
2 1
DY
DC_IN_D
2
[5,27] H_PROCHOT# PR4032 Rdson=14~13mohm Qg=-65nC
1
100KR2J-1-GP 1 2 Rdson=15~18mohm
D
PQ4002
AD+_G_1
PQ4005
2N7002A-7-GP 2 3 4 PC4002
SCD1U25V2KX-GP
SC1U25V3KX-1-GP
84.2N702.E31 G PWR_CHG_CMPOUT PWR_CHG_ACOK 2 5
2nd = 84.2N702.J31
PC4003
1 6
1
PC4004
S
AD+ SCD1U25V3KX-GP PC4024

DY
SC2200P50V2KX-2GP
SC10U25V5KX-GP
SC10U25V5KX-GP
PR4015 2N7002KDW-GP SCD1U25V3KX-GP
SC10U25V5KX-GP
2
SCD1U25V2ZY-1GP
PC4008
PC4009
PWR_CHG_ACN
PWR_CHG_ACP
120KR2J-L-GP 84.2N702.A3F
PC4006
1
EC4001
EC4002
2nd = 84.DM601.03F 83.1R504.A8F
1
2nd = 83.1R504.B8F
1
3rd = 84.2N702.E3F PR4008 CHG_AGND

DY
2
CHG_AGND
1
4th = 84.2N702.F3F 20R5J-GP CHG_AGND PD4001
SCD47U25V3KX-1GP
2
1
9
PR4007 1 2 PWR_CHG_VCC PR4009 SD103AWS-1-GP
0R3J-0-U-GP
G1
D1
D1
D1
D1
316KR2F-GP
1 2CHG_PHASE
K A 1 2
PC4010
PC4007 PU4002
Q1
1 2
SCD047U25V2KX-GP
2
1
PR4010 20R5J-GP PU4001 SC1U25V3KX-1-GP FDMC7200S-GP
PC4011
84.07200.A37
Q2
ACP
ACN
2
10 D2/S1
1
PWR_CHG_IOUT 20 2nd = 84.05524.037
1
VCC
8 G2
7 S2
6 S2
5 S2
3D3V_AUX_KBC CHG_AGND
PR4011
2
19K1R2F-GP PWR_CHG_ACDET PWR_CHG_BTST
PR4031
6 17 X01 12/21
SCD01U50V2KX-1GP
1
ACDET BTST
Charger Current=1.25A
1
PC4012
PWR_CHG_CMPOUT 16 PWR_CHG_REGN
1
REGN
49K9R2F-L-GP
1
PR4021 PR4020 PR4014 3
2
PR4013 3K3R2F-2-GP 3K3R2F-2-GP 3D3MR2J-GP CMPOUT PWR_CHG_HIDRV PR4033 BT+

18
49K9R2F-L-GP HIDRV D01R3721F-GP-U
1 2
C DY DY 4
PL4001
C
DY
2
2
CMPIN PWR_CHG_PHASE PC4013 BT+_R
19 1 2 1 2
2
2
PWR_CHG_CMPIN PHASE SC3300P50V3KX-1GP
SCD1U25V2KX-GP
3D3V_AUX_KBC
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
IND-2D2UH-161-GP-U
SCD1U25V3KX-GP
CHG_AGND 2 1 PWR_CHG_BAT_SCL 9 15 PWR_CHG_LODRV
PC4025
PC4016
PC4017
2
1
SCL LODRV
PC4018
CHG_AGND PG4007 GAP-CLOSE-PWR-3-GP 68.2R210.20T
[27,39] BAT_SCL
1
PG4009
PG4012
PC4019
2nd = 68.2R21D.10Y
SCD1U25V2KX-GP
PR4017 2 1 PWR_CHG_BAT_SDA 8
2
[27,39] BAT_SDA SDA
100KR2J-1-GP PG4008 GAP-CLOSE-PWR-3-GP
1
PC4020
PR4019
13 PWR_CHG_SRP 1 2 10R2F-L-GP
2
PWR_CHG_ILIM SRP
10
1
ILIM PWR_CHG_SRN
12 1 2
1
PR4023 SRN PR4012 7D5R2F-GP

3D3V_AUX_KBC 2 1 PWR_CHG_IFAULT
11 DY
[27] BOOST_MODE# DY
2
NC#11
DY 32K4R2F-1-GP PR4018
1
0R2J-2-GP
2
DY PR4026 A00 3/23 CHG_AGND

10KR2F-2-GP
PQ4001 100KR2J-1-GP PWR_CHG_IOUT

5 7 1 2
SCD1U25V2KX-GP
PR4035
D
2N7002A-7-GP ACOK# IOUT AD_IA [27]

PWR_CHG_CSOP_1
DY
GND
GND
CHG_AGND PR4022
SC220P50V2JN-3GP
2
PC4021
0R0402-PAD-2-GP
DY 3D3V_AUX_KBC
1
G PWR_CHG_CMPOUT BQ24727RGRR-GP
8K45R2F-2-GP
1 PR4024
21
14
74.24727.073 X03 2/16
1
1 PC4022
X01 12/12
PG4011
S
1 2
2
PWR_CHG_CSON_1
SCD1U25V2KX-GP
3D3V_AUX_S5 GAP-CLOSE-PWR-3-GP
CHG_AGND
CHG_AGND DY
2
CHG_AGND
1
PC4023
2
1
PR4027
100KR2J-1-GP
3D3V_AUX_S5
2
PWR_CHG_REGN
2
1 CHG_AGND
1
[27] AC_IN# CHG_AGND

PR4039 PR4028
100KR2J-1-GP 100KR2J-1-GP
B DY B
2
2
PWR_CHG_ACOK
D
PQ4006
2N7002A-7-GP
1
PR4036 G AC_IN#
120KR2F-L-GP
DY
84.2N702.E31
2
2nd = 84.2N702.J31
EC Code for BQ24727

PR4030
PQ4004
54K9R2F-L-GP
H_PROCHOT# AD_IA_HW AD_IA_HW2 PWR_CHG_CMPIN 1 2 PQ4904_3 3 4 CHG_AGND
2 5
65W 0 0 [27] AD_IA_HW2 AD_IA_HW [27]
1 6 PQ4004_6 2 1 PWR_CHG_CMPIN
90W 1 0 PR4038
2N7002KDW-GP 19K6R2F-GP
A
130W 0 1 CHG_AGND 84.2N702.A3F A
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F
<Core Design>
Wistron Corporation
Title
CHARGER BQ24727
A2 A00
BMW Z4 DIS
5 4 3 2 1
A B C D E
SSID = PWR.Plane.Regulator_5v3p3v
X03 2/16 PWR_5V3D3V_VCLK
3D3V_AUX_S5 PC4104 PC4102 PC4103

DCBATOUT PWR_DCBATOUT_5V DCBATOUT PWR_DCBATOUT_3D3V
1
SC1KP50V2KX-1GP
SCD1U25V3KX-GP
SCD1U25V3KX-GP
1
1
PG4144 PG4111
2
1 2 1 2
2
PR4132 PD4102
3PC4102_2 2
3PC4103_2 2
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
PG4102 PG4112 DY 0R2J-2-GP BAT54-7-F-GP
1 2 1 2
DY
2
4 4
3
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP X03 2/10
PG4103 PG4113 PR4131
1 2 1 2 PR4127 0R2J-2-GP PD4103 PD4101
PWR_5V_EN1 1 2 PWR_5V_EN1_R 2 1 BAT54S-7F-GP BAT54S-7F-GP
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP 0R0402-PAD-2-GP X03 2/10 DY 83.00054.Y81 83.00054.Y81
PG4104 PG4114 2nd = 83.0R203.081 2nd = 83.0R203.081
1
1 2 1 2
1
PR4133 15V_S5 15V_PWR 5V_PWR
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP 0R0402-PAD-2-GP PG4105
PG4106 PG4115 X03 2/10 GAP-CLOSE-PWR-3-GP
1 2 1 2
2
PR4130 1 2 PC4108_1
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP PWR_3D3V_EN2 1 2
PG4107 PG4118 0R0402-PAD-2-GP 3V_5V_EN [36]
1
1 2 1 2 PC4106
PD4104 SC1U25V3KX-1-GP PC4108 PC4107
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP BZT52C15S-GP SCD1U25V3KX-GP SCD1U25V3KX-GP
2
PG4108 PG4135 83.15R03.C3F
1 2 1 2 2nd = 83.15R03.E3F
A
PG4109
1 2
GAP-CLOSE-PWR-3-GP
PG4110 DCBATOUT
1 2 PWR_DCBATOUT_3D3V
PC4112 PC4113 X01 12/12
SC10U25V5KX-GP
SCD01U50V2KX-1GP
GAP-CLOSE-PWR-3-GP
PC4109 PC4110 PC4111 PWR_DCBATOUT_5V X03 2/20
1
PU4102 X03 2/16
1
1
SC10U25V5KX-GP
SCD1U25V3KX-GP
SC10U25V5KX-GP
2
DY 3
2
D 84.08884.A37 1 4
2
D 8
D 7
D 6
D 5
2nd = 84.00412.037 10 PC4129 PC4130 PC4114 PC4115 PC4116 5V_PWR 5V_S5
9 PG4119
1
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U25V3KX-GP
PU4105
12
Design Current = 7.64A 7 1 2
SIS412DN-T1-GE3-GP PU4101 8 6
12.1A<OCP< 14.2A 5 GAP-CLOSE-PWR-3-GP
VIN
2
PG4120
PR4108 PR4109 SCD1U25V3KX-GP Design Current = 12A
S
S
S
G
3 1 2 3
3D3V_S5 3D3V_PWR PC4117 1D5R3F-GP 1D5R3F-GP PC4118
1
2
3
4
PG4136 1PWR_3D3V_VBST2_1 2 PWR_3D3V_VBST2 PWR_5V_VBST1 2PWR_5V_VBST1_1 1 FDMS3600-02-RJK0215-COLAY-GP 18A<OCP< 21.6A

1 2
S G 2
SCD1U25V3KX-GP
1 9
VBST2 VBST1
17 1 2
84.03664.037
GAP-CLOSE-PWR-3-GP
PG4121
3D3V_PWR PWR_3D3V_DRVH2 10 16 PWR_5V_DRVH1 2nd = 84.06920.037 5V_PWR 1 2
PL4102 DRVH2 DRVH1 PL4101
GAP-CLOSE-PWR-3-GP
PG4137 2 1 PWR_3D3V_LL2 8 18 PWR_5V_LL1 1 2 GAP-CLOSE-PWR-3-GP
IND-2D2UH-46-GP-U SW2 SW1 IND-1D5UH-34-GP PG4122
1 2
1
68.2R210.20B PWR_3D3V_DRVL211 15 PWR_5V_DRVL1 1 2
1
DRVL2 DRVL1
GAP-CLOSE-PWR-3-GP 2nd = 68.2R21B.10J 68.1R510.10J
PG4138 PR4110 2nd = 68.1R51A.10E
DY D GAP-CLOSE-PWR-3-GP
D 8
D 7
D 6
D 5
1 2 PC4119 PG4116 2D2R5F-2-GP 14 PWR_5V_VO1 PG4117 PC4120 PG4123

DY
SE220U6D3VM-30-GP
SE220U6D3VM-30-GP
1
1
VO1
PT4103
PT4104
PU4106 PR4111 1 2
SE220U6D3VM-30-GP
2
1
1
SCD1U10V2KX-4GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
SCD1U10V2KX-4GP
PT4101
GAP-CLOSE-PWR-3-GP PWR_3D3V_FB2 4 2 PWR_5V_FB1 2D2R5F-2-GP

SIS406DN-T1-GE3-GP
DY
2
PG4139 VFB2 VFB1
1PWR_3D3V_SNUB
GAP-CLOSE-PWR-3-GP
DY
2
1 2 PG4124
2
2
1 2
1PWR_5V_SNUB
PWR_3D3V_EN2 PWR_5V_EN1
GAP-CLOSE-PWR-3-GP S G
1 S
2 S
3 S
6 20
4 G
PG4140 EN2 EN1

GAP-CLOSE-PWR-3-GP
1 2 PG4125
PWR_3D3V_CS2 5 1 PWR_5V_CS1 1 2
CS2 CS1
GAP-CLOSE-PWR-3-GP
1
1
PG4141 77.52271.09L 77.52271.09L 77.52271.09L GAP-CLOSE-PWR-3-GP
3D3V_TER
1 2 2nd = 77.92271.03L PR4102 19 PWR_5V3D3V_VCLK PR4103 2nd = 77.92271.03L 2nd = 77.92271.03L PG4126
X01 12/02 PC4121 DY 84.07696.037 120KR2F-L-GP VCLK 33KR2F-GP PC4123 1 2
DY
2
GAP-CLOSE-PWR-3-GP SC330P50V3KX-GP 2nd = 84.00406.037 SC560P50V-GP X01 12/02
2
PG4142 7 21 GAP-CLOSE-PWR-3-GP
2
2
PGOOD GND PG4127
1 2 X01 12/12
VREG3
VREG5
1 2
GAP-CLOSE-PWR-3-GP
PG4143 GAP-CLOSE-PWR-3-GP
1
1
1 2 TPS51225RUKR-GP PG4128
3
13
PR4113 74.51225.073 5V_PWR_2 PR4114 1 2
1
GAP-CLOSE-PWR-3-GP PR4112 0R2J-2-GP 3D3V_PWR_2 0R2J-2-GP
DY DY
1PWR_5V3D3V_VREG3
6K65R2F-GP PG4101 PR4115 GAP-CLOSE-PWR-3-GP

1 2 15KR2F-GP PG4129
2
1 2
1 2
X03 2/16 PWR_3D3V_FB2_R PWR_5V_FB1_R 1 2
PC4124 GAP-CLOSE-PWR-3-GP
2
SC18P50V2JN-1-GP PC4125 GAP-CLOSE-PWR-3-GP
DY SC18P50V2JN-1-GP DY PG4130
2
2
X01 12/13 1 2
2 2
1
1
GAP-CLOSE-PWR-3-GP
1
PR4117 PC4127 PR4121 PG4131

SC1U6D3V2KX-GP
10KR2F-2-GP
PC4126
10KR2F-2-GP
DY PC4128 1 2
SC4D7U6D3V3KX-GP
SC22U6D3V5MX-2GP
3D3V_PWR_2 3D3V_AUX_S5
2
3D3V_S5 X03 2/13 GAP-CLOSE-PWR-3-GP

2
2
PG4132
1 2 1 2
1
PR4119 PR4116 GAP-CLOSE-PWR-3-GP

100KR2J-1-GP 0R0402-PAD-2-GP PG4133
1 2
2
PWR_5V3D3V_PGOOD GAP-CLOSE-PWR-3-GP
PG4134
1 2
GAP-CLOSE-PWR-3-GP
PG4145
1 2
GAP-CLOSE-PWR-3-GP
PG4146
1 2
GAP-CLOSE-PWR-3-GP
PG4147
1 2
GAP-CLOSE-PWR-3-GP
PG4148
1 2
GAP-CLOSE-PWR-3-GP
1 1
<Core Design>
Wistron Corporation
Title
TPS51123_5V/3D3V
A2 A00
BMW Z4 DIS
A B C D E
5 4 3 2 1
SSID = CPU.Regulator
VCCP_CPU
1 2 Volterra's suggestion:
[8] VR_SVID_ALERT# PR4224 DY 75R2F-2-GP
[8] H_CPU_SVIDDAT
H_CPU_SVIDDAT 1 2 VCC 26x22uF(0805) 1-PHASE VCC
PR4225 130R2F-1-GP
[8] H_CPU_SVIDCLK
H_CPU_SVIDCLK 1 2 boot voltage=0V VCCAXG 23x22uF(0805) for 1-PHASE VCCAXG
PR4226 54D9R2F-L1-GP
[48] D85V_PWRGD
PR4211
PR4201
PR4205
PR4262
PR4209
PR4210
X03 2/10 X03 2/10
PR4204
PR4208
1
PR4228
PR4207
1D8V_S0 3D3V_S5
1
825R2F-GP
5V_S5
21D5R2F-1-GP
61K9R2F-GP
280R2F-1-GP
20KR2F-L-GP
402R2F-GP
1
825R2F-GP
191R2F-GP
D D
1
PR4231
2
1
0R0402-PAD-2-GP
0R0402-PAD-2-GP
PC4211 10R2F-L-GP
2
PR4260 SC1U6D3V2KX-GP
PWR_VCORE_VR_ENABLE
866KR2F-GP
PWR_VCORE_R_OSC
PWR_VCORE_R_SEL0
PWR_VCORE_R_SEL1
2
PWR_VCORE_R_SEL6
PWR_VCORE_VR_READY2
PWR_VCORE_VR_READY1
PWR_VCORE_VR_TT#
PWR_VCORE_R_SEL4
1 2
PWR_VCORE_VIN_UVLO_R
PC4237 SCD1U10V2KX-5GP
1
PR4263 PC4214
100KR2F-L1-GP
SCD1U10V2KX-5GP
GND_1318
2
2
X03 2/13
1 2
GND_1318
PR4223
49
48
47
46
45
44
43
42
41
40
39
38
37
0R0402-PAD-2-GP PU4201
R_SEL6
VR_READY2
VR_READY1
VR_TT#
R_SEL4
ALERT#
VDIO
VCLK
VR_ENABLE
R_SEL0
R_SEL1
GND
R_OSC
1D8V_S0
PWR_VCORE_VDD3 1 36 PWR_VCORE_R_SEL2
VDD3 R_SEL2 PWR_VCORE_R_SEL3
2 35
VDD R_SEL3 PWR_VCORE_R_REF
3 34
PWR_VCORE_VIN_UVLO VDD R_REF
4 33
PWR_VCORE__PWM3 VIN_UVLO IPH2_2 PWR_VCORE_R_SEL5
5 32 PWR_AXG_IPH2_1_R [44]
PWR_VCORE__PWM2 PWM1_3 R_SEL5 PWR_AXG_PWM2_2
6 31
PWR_VCORE__PWM1 PWM1_2 PWM2_2 PWR_AXG_PWM2_1 PR4229
7 30
[43] PWR_VCORE__PWM1 PWR_VCORE__TP_FAULT#1 PWM1_1 PWM2_1 PWR_AXG_TS_FAULT#2 PWR_AXG_PWM2_1 [44] 1K96R2F-1-GP
8 29
[43] PWR_VCORE__TP_FAULT#1 TS_FAULT#1 TS_FAULT#2 PWR_AXG_IPH2_1 PWR_AXG_TS_FAULT#2 [44]
9 28 1 2 1 2
IPH1_3 IPH2_1 PWR_AXG_MRAMP2 PR4246
10
IPH1_2 MRAMP2
27 X03 2/10
1 2 1 2 PWR_VCORE_IPH1_1 11 26
1
IPH1_1 SENSE2+ 1KR2F-3-GP
PR4257
PC4201
PC4229 X02 2/13 PWR_VCORE_MRAMP1
SENSE1+
12 25
A2_OUT1
A3_OUT1
A3_OUT2
A2_OUT2
SENSE1-
MRAMP1 SENSE2-
A_ERR1
A_ERR2
PR4261
PR4219
PR4256 PR4216 PR4218 PR4212
DY
A2_IN1
A3_IN1
A3_IN2
A2_IN2
1
1
750R2F-GP 1K96R2F-1-GP PR4215 0R2J-2-GP
DY 0R0402-PAD-2-GP
2
1
1
SC10P50V2JN-4GP
PR4258
13KR2F-GP
15K4R2F-GP
SC10P50V2JN-4GP
C C
DY DY 0R2J-2-GP
2
[43] PWR_VCORE_IPH1_1_L
VT1318MFQX-1-GP
2
13
14
15
16
17
18
19
20
21
22
23
24
0R0402-PAD-2-GP
0R0402-PAD-2-GP
2
2
74.01318.B73
PWR_VCORE_A_ERR1
PWR_VCORE_A2_IN1
PWR_VCORE_A2_OUT1
PWR_VCORE_A3_IN1
PWR_VCORE_A3_OUT1
PWR_AXG_A3_OUT2
PWR_AXG_A3_IN2
PWR_AXG_A2_OUT2
PWR_AXG_A2_IN2
PWR_AXG_A_ERR2
PC4231
SC22P50V2JN-4GP GND_1318 X02 2/13
2 1 1 2
PR4252
PC4236 GND_1318 0R0402-PAD-2-GP
PC4232 PR4234 SC33P50V2JN-3GP PWR_AXG_SENSE2_P 1 2 VCC_AXG_SENSE [9]
2 1 VCORE_IN1_R0 2 1 1 2 VCORE_IN1_L0 1 2
DY DY PR4235 PWR_AXG_SENSE2_N 1 2 VSS_AXG_SENSE [9]
SC22P50V2JN-4GP 6K81R2F-1-GP PC4238 X03 2/10
X01 12/21 SC680P50V3JN-GP 15KR2F-GP PR4254
PR4251 0R0402-PAD-2-GP
1 2 1 2VCORE_IN1_R1 1 2 2 1 [8] VCCSENSE 1 2 PWR_VCORE_SENSE_P
PR4237 PR4264 0R0402-PAD-2-GP
487R2F-GP PR4236 PR4233 PC4235 SC22P50V2JN-4GP PC4233 SC22P50V2JN-4GP
953R2F-GP 7K5R2F-1-GP 10KR2F-2-GP
1 2 1 2
X03 2/21
PR4250
1 2 PWR_VCORE_SENSE_N
[8] VSSSENSE
0R0402-PAD-2-GP PC4218 PR4244 PC4234
1 2 AXG_IN2_L1 1 2 1 2 AXG_IN2_R0 1 2 1 2
DY DY
PR4255 SC1000P50V3JN-GP-U 6K81R2F-1-GP SC22P50V2JN-4GP PR4240
30K1R2F-L-GP 665R2F-2-GP
X01 12/21
X03 2/16 1 2 1 2AXG_IN2_R1 1 2
1 2VCORE_IPH1_R0 1 2 PR4245 10KR2F-2-GP
PG4201 PR4249 PR4239
1 2 PR4238 PC4213 7K68R2F-GP 300R2F-GP
2K7R2F-GP SC3300P50V2KX-1GP X03 2/21
GAP-CLOSE-PWR-3-GP
GND_1318
B B
1 2 AXG_IPH2_R0 1 2
PC4219 SCD01U16V2KX-3GP PR4243

3K24R2F-GP
3D3V_S0
VCC_CORE
PR4202
1 2 PWR_VCORE_MRAMP1 1 2 PWR_VCORE_VR_READY1
PR4222
10KR2F-2-GP X03 2/13
43KR2F-GP
PR4203
1 2
PWR_VCORE_VR_READY2 IMVP_PWRGD [27,36]
1 2
PR4253
10KR2F-2-GP 0R0402-PAD-2-GP
VCC_GFXCORE
1 2 PWR_AXG_MRAMP2
PR4227
56K2R2F-2-GP
VCCP_CPU
PR4206
1 2 PWR_VCORE_VR_TT#
62R2J-GP
1
PC4202
SC47P50V2JN-3GP
2
A A
<Core Design>
Wistron Corporation
Title
VT1318+1323_CPU_CORE1+1(1/3)
A2 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
X03 2/20
SSID = CPU.Regulator X03 2/16
X01 12/13
PW R_CPU 5V_S5
EG4301
1 2
GAP-CLOSE-PW R-3-GP
EG4302
1 2
D GAP-CLOSE-PW R-3-GP D
EG4303
PW R_CPU 1 2
GAP-CLOSE-PW R-3-GP
EG4304
Layout Note: 1 2
Small Cap close IC
PC4304
PC4305
PC4306
PC4307
GAP-CLOSE-PW R-3-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
EG4305
PC4308
PC4309
1
1
1 2
PC4310
SCD1U10V2KX-5GP GAP-CLOSE-PW R-3-GP
2
1D8V_S0 EG4306
1 2
GAP-CLOSE-PW R-3-GP
EG4307
C1
C2
C3
C4
X01 12/21 1 2
PU4301
1
GAP-CLOSE-PW R-3-GP
VDDH
VDDH
VDDH
VDDH
PC4302 A1 B4 PW R_CORE_BT1 EG4308
[42] PW R_VCORE__TP_FAULT#1 TS_FAULT# BST
SC4D7U6D3V3KX-GP 1 2
2
1
A4 PC4301 D.C. = 25A GAP-CLOSE-PW R-3-GP
VCC SCD22U10V3KX-2GP EG4309
D1
2
VX#D1 P.C. =33A
VX#D2 D2 1 2
VX#D3 D3
PW R_VCORE_PU4301_VDD B1 D4 PL4301 VCC_CORE GAP-CLOSE-PW R-3-GP
C VDD VX#D4 EG4310 C
VX#F1 F1
F2 PW R_CORE_VX1 1 2 1 2
VX#F2 IND-D1UH-26-GP X01 12/19
VX#F3 F3
[42] PW R_VCORE_IPH1_1_L B2 F4 X01 12/12 GAP-CLOSE-PW R-3-GP
ISENSE VX#F4 EG4311
VX#H1 H1 68.R1010.10T
1
1D8V_S0 B3 H2 2nd = 68.R1010.10X PR4303 1 2
[42] PW R_VCORE__PW M1 PWM VX#H2
VX#H3 H3
100R5F-2-GP
H4 GAP-CLOSE-PW R-3-GP
VX#H4
K1
DY
VX#K1
PR4301 K2
2
PC4303 VX#K2
VX#K3 K3
1 2 1 2 A2 GND VX#K4 K4
SCD1U25V2KX-GP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
10R2F-L-GP
VT1326SFCX-1-GP
E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4
L1
L2
L3
L4
74.01326.A7Z
X03 2/16
B PG4301 B
1 2
GAP-CLOSE-PW R-3-GP
GND_1323S_1
<Core Design>
A A
Wistron Corporation
Title
VT1318+1326_CPU_CORE2+1(2/3)
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = CPU.Regulator X03

X03
2/20
2/16
X01 12/20
X01 12/13
PW R_CPU 5V_S5
EG4401
1 2
GAP-CLOSE-PW R-3-GP
EG4402
D 1 2 D
GAP-CLOSE-PW R-3-GP
EG4403
1 2
GAP-CLOSE-PW R-3-GP
EG4404
1 2
X01 12/20
GAP-CLOSE-PW R-3-GP
EG4405
PW R_CPU 1 2
GAP-CLOSE-PW R-3-GP
EG4406
1 2
Layout Note:
Small Cap close IC
PC4403
PC4404
PC4405
PC4406
GAP-CLOSE-PW R-3-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC1U6D3V2KX-GP
EG4407
PC4407
1
1
PC4408 1 2
SCD1U10V2KX-5GP GAP-CLOSE-PW R-3-GP
2
1D8V_S0 EG4408
1 2
GAP-CLOSE-PW R-3-GP
X01 12/21 EG4409
C1
C2
C3
C4
1 2
C PU4401 C
1
GAP-CLOSE-PW R-3-GP
VDDH
VDDH
VDDH
VDDH
PC4401 A1 B4 PW R_AXG_BT3 EG4410
[42] PW R_AXG_TS_FAULT#2 TS_FAULT# BST
SC4D7U6D3V3KX-GP 1 2
2
D.C. = 22A
1
A4 GAP-CLOSE-PW R-3-GP
VCC PC4409 P.C. =33A EG4411
VX#H4 H4
H3 SCD22U10V3KX-2GP 1 2
2
VX#H3 VCC_GFXCORE
VX#H2 H2 PL4401
PW R_AXG_PU4401_VDD B1 H1 GAP-CLOSE-PW R-3-GP
VDD VX#H1
VX#F4 F4
F3 PW R_AVG_VX1 1 2
VX#F3 IND-D1UH-26-GP
VX#F2 F2
[42] PW R_AXG_IPH2_1_R B2 ISENSE VX#F1 F1
VX#D4 D4 68.R1010.10T
1
1D8V_S0 B3 D3 2nd = 68.R1010.10X PR4402
[42] PW R_AXG_PW M2_1 PWM VX#D3
VX#D2 D2
100R5F-2-GP
D1
PR4401
VX#D1 DY
PC4402
2
1 2 1 2 A2 GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SCD1U25V2KX-GP
10R2F-L-GP
VT1323SFCX-1-GP
E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4
74.01323.A7Z
X03 2/16
B PG4401 B
1 2
GAP-CLOSE-PW R-3-GP
GND_1323S_3
A <Core Design> A
Wistron Corporation
Title
VT1318+1323_CPU_CORE1+1(3/3)
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p05v
X03 2/16
1D05VTT_PW R 1D05V_PCH 1D05VTT_PW R VCCP_CPU
PG4501 PG4508
1 2 1 2
D D
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
3D3V_S0 PG4502 PG4509
1 2 1 2
2
PR4718 PG4503 PG4510
10KR2J-3-GP 1 2 1 2
X03 2/10
1
PR4523 PG4504 PG4511
1 2 PW R_1D05V_STAT 5V_PW R_1D05V A00 3/29 5V_S5 1 2 1 2
[37,48] 1D05V_VTT_PW RGD
0R0402-PAD-2-GP Layout Note: X03 2/16
140mil X03 2/16 GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
2
1 2 PG4506 PG4512
DY PC4531 1 2 1 2
SC22U6D3V5MX-2GP
SC2200P50V2KX-2GP EL4501
PC4515
PC4508
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
1
MPZ1608S300AT-GP
PC4514
EC4507
1
PG4507 PG4513
68.00212.051 1 2 1 2
2
PG4514
1 2
GAP-CLOSE-PW R-3-GP
PU4501 PG4515
1 2
Layout Note: B5 B2 PW R_1D05V_VX
VDD VX#B2
C Diff. pair C5 VDD VX#B3 B3 GAP-CLOSE-PW R-3-GP C
B4 D.C. =10.67A PG4516
VX#B4
1 2
PW R_1D05V_VSENSE+ A2 C2 16.77A < OCP < 19.82A
PW R_1D05V_VSENSE- SENSE+ VX#C2
1 2 2 1 A3 C3 GAP-CLOSE-PW R-3-GP
PR4506
SENSE- VX#C3
C4
Layout Note: 1D05VTT_PW R
VX#C4 PL4501
2K74R2F-GP PR4507 400mil
6K81R2F-1-GP X03 2/10 PW R_1D05V_STAT A4 STAT
PR4522 A1 1 2
PU4501_OE AGND
[19,46,47] RUNPW ROK 1 2 A5 OE
0R0402-PAD-2-GP B1 COIL-D2UH-2-GP X03 2/16
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
GND
PC4518
PC4519
C1
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
GND
PC4530
PC4529
68.R2010.20B
SCD1U10V2KX-5GP
1
1
EC4521
EC4528
2nd = 68.R2010.10Q
1
VT386FCX-ADJ-GP
PC4522
1
PC4539 X01 12/12
SCD1U10V2KX-4GP
2
DY
2
PR4515 2
150R2F-1-GP AGND_1D05V_386
1 2 1 2
DY
VCCIO_SENSE_1
1
PC4532
SC3300P50V2KX-1GP PR4501
25K5R2F-GP
1 2
VCCP_CPU
2
PC4501 X03 2/16
SC4700P50V2KX-1GP
PG4517
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
B B
PC4525
PC4520
PC4526
PC4527
1 2
SC22U6D3V5MX-2GP
PC4523
PC4509
PC4510
PC4512
PC4513
PC4516
PC4517
PC4511
SCD1U10V2KX-5GP
1
GAP-CLOSE-PW R-3-GP
1
1
1
PC4506
AGND_1D05V_386 DY DY DY
DY DY
2
2
2
2
2
X03 2/10
VCCIO_SENSE_C PR4510 1 2 0R0402-PAD-2-GP VCCIO_SENSE [8]
PR4511 1 2 0R0402-PAD-2-GP VSSIO_SENSE [8]
Layout Note:
Close CPU output
A <Core Design> A
Wistron Corporation
Title
1D05V_PCH & VCCP_CPU

A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p5v0p75v
3D3V_S0
2
PR4616 1D5V_S0
D X03 2/10 10KR2J-3-GP D
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PR4626
1
[19,45,47] RUNPW ROK 1 2 PW R_1D5V_STAT
1
0R0402-PAD-2-GP X01 12/13
PC4610
PC4622
PC4608
PC4624
5V_PW R_1D5V 5V_S5
2
1
PC4524 1 2
SC2200P50V2KX-2GP
SCD1U10V2KX-5GP
EL4601 68.00143.041
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC4D7U6D3V3KX-GP
2
BLM18PG330SN1D-GP 2nd = 68.00212.051
PC4617
PC4611
PC4607
PC4628
1
1
1 2
68.00143.041
UMA VT386 EL4602 2nd = 68.00212.051
2
BLM18PG330SN1D-GP
SG VT385
PU4602
X01 12/12 PW R_1D5V_VSENSE+ A2 SENSE+ VDD B5

PW R_1D5V_VSENSE- A3 C5 D.C. =13.7A
SENSE- VDD
D5
Layout Note:
VDD 21.6A < OCP < 25.4A 1D5V_S3
1 PR4609 2 1 2 PL4601 720mil
PW R_1D5V_STAT A4
4K7R2F-GP PR4612 PW R_1D5V_OE STAT PW R_1D5V_VX
A5 OE VX#B2 B2 1 2
C 4K53R2F-1-GP B3 C
VX#B3 COIL-D20UH-GP
VX#B4 B4
X01 12/15 C2 68.R2010.201
DY
SC6800P25V2KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VX#C2
1 2 1 2 A1 AGND VX#C3 C3 2nd = 68.R2010.10P
1
PR4614
PC4633
PC4609
PC4631
PC4632
VX#C4 C4
2
150R2F-1-GP PC4618 SC3300P50V2KX-1GP AGND_1D5V_385 PR4613
EC4638
PC4623
PC4619
PC4621
PC4627
B1 D2
SCD1U10V2KX-4GP
GND VX#D2 13KR2F-GP

C1 GND VX#D3 D3
1
D1 D4
1
GND VX#D4
DY
2
1 2
2
VT385FCX-ADJ-GP
PC4625
SC4700P50V2KX-1GP
PW R_1D5V_VSENSE-_R
X02 2/10
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PR4621
PW R_1D5V_VSENSE-_R_1
1
1 2
PC4620
PC4613
1
0R0402-PAD-2-GP
PC4616
PC4615
PC4612
PC4634
PC4635
PC4636
PC4637
PR4622 DY DY DY DY DY DY
2
X03 2/10 1 2
X03 2/16 0R0402-PAD-2-GP
PR4623
1 2 PG4601
[19,27] PM_SLP_S4# 0R0402-PAD-2-GP 1 2
GAP-CLOSE-PW R-3-GP
B B
AGND_1D5V_385
RT9026 for 0D75V_S0

5V_S5 X03 2/16 1D5V_S3
PG4602
0D75V_PW R_VLDOIN 1 2
PC4606
GAP-CLOSE-PW R-3-GP
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
1
PC4603
PC4605
1
SC1U6D3V2KX-GP
2
PU4601
D.C. =0.7A
X03 2/10 X03 2/16
10 1 0D75V_PW R 0D75V_S0
PR4611 VIN VDDQSNS
[19,27] PM_SLP_S4# 1 2 0R0402-PAD-2-GP 0D75V_PW R_S5 9 S5 VLDOIN 2 PG4603
8 GND VTT 3 1 2 <Core Design>
A PR4602 1 2 0R0402-PAD-2-GP 0D75V_PW R_S3 7 4 A
[37] 0D75V_EN S3 PGND
DDR_VREF_S3 6 5 GAP-CLOSE-PW R-3-GP
VTTREF VTTSNS PG4604
PC4604
PC4601
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
Wistron Corporation
GND
1
PC4629
PC4630
1 2
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
PC4602 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

1
SCD1U10V2KX-5GP RT9026PFP-GP GAP-CLOSE-PW R-3-GP Taipei Hsien 221, Taiwan, R.O.C.

11
DY
1
DY Title
2
VT385_1D5V_S3/RT9026_0D75V_S0
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p8v
D D
3D3V_S5
X03 2/16 RT8068A for 1D8V_S0
PG4701 D.C. =0.87A
1 2
1.29A < OCP <1.52A
GAP-CLOSE-PW R-3-GP PU4701
PG4702 1D8V_PW R X03 2/16 1D8V_S0
1 2 PW R_1D8V_PVDD 10 1
PVIN LX#1 PL4701
PR4701 PG4704
GAP-CLOSE-PW R-3-GP 1 2 PW R_1D8V_SVIN 9 2 PW R_1D8V_PHASE 1 2 1 2
PG4703 2D2R2F-GP PVIN LX#2 IND-1D5UH-71-GP-U
1
1 2 8 3 PR4703 GAP-CLOSE-PW R-3-GP
SVIN LX#3
1
PC4703 68.1R510.20J 102KR2F-GP PG4705
SC22P50V2JN-4GP
SC1U6D3V2KX-GP
PC4705
GAP-CLOSE-PW R-3-GP 7 2nd = 68.1R51B.10Q 1 2
2
PW R_1D8V_EN NC#7
5
R1
2
EN
1
1
PC4701 PC4702 6 PC4706 PC4707 GAP-CLOSE-PW R-3-GP
FB
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
4 PG4706
DY
2
PGOOD
11 1 2
2
2
GND
RT8068AZQW ID-GP-U PW R_1D8V_FB GAP-CLOSE-PW R-3-GP
74.08068.A43 PG4707
1 2
C C
1
GAP-CLOSE-PW R-3-GP
PR4704
51KR2F-L-GP
X03 2/11 R2
2
[19,27,36,37] PM_SLP_S3# 1 2
PR4702
1
0R0402-PAD-2-GP
PC4704
DY SC22P50V2GN-GP
2
Vo=0.6*(1+(R1/R2))
[19,45,46] RUNPW ROK
B B
A <Core Design> A
Wistron Corporation
Title
RT8068A_1D8V_S0
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_vccsa
X02 1/9
VCCP_CPU
X03 2/16
PG4801
D PW R_VCCSA_VIN 1 2 D
GAP-CLOSE-PW R-3-GP
PG4802
1 2
GAP-CLOSE-PW R-3-GP
PG4803
1 2
GAP-CLOSE-PW R-3-GP
PG4804
1 2
GAP-CLOSE-PW R-3-GP
5V_S5 PG4805
A00 3/23 1 2
2
GAP-CLOSE-PW R-3-GP
PR4801 PG4806
0R0402-PAD-2-GP 1 2
3D3V_S0
GAP-CLOSE-PW R-3-GP
1
PW R_VCCSA_VCNTL
1
PC4802 PC4803
Iomax=4A
1
PC4801
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
PR4802 SC1U6D3V2KX-GP OCP>9A
2
10KR2J-3-GP
C VCCSA=0.9V C
2
Note: LDO solution VCCSA is 0.9V.
2
6
PU4801
VCNTL
7 5 VCCSA_PW R 0D85V_S0
[42] D85V_PW RGD POK VIN
VIN 9 X03 2/16
A00 3/23 PG4807
1 2 PW R_VCCSA_EN 8 3 1 2
[37,45] 1D05V_VTT_PW RGD EN VOUT
VOUT 4 R1
1
PR4803 GAP-CLOSE-PW R-3-GP
1
1
0R0402-PAD-2-GP PR4804 PC4804 PG4808
1
PR4808 2 10KR2F-2-GP 1 2
GND FB
SC100P50V2JN-3GP
47KR2F-GP PC4809 PC4805 PC4806
DY DY
2
SC1U6D3V2KX-GP GAP-CLOSE-PW R-3-GP
2
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
PW R_VCCSA_FB PG4809
2
1 2
APL5916KAI-TRL-GP
R2
2
1
74.05916.031 GAP-CLOSE-PW R-3-GP
1
2nd = 74.00977.031 PR4806 PG4810
PR4805 160KR2F-GP DY 1 2
80K6R2F-GP
GAP-CLOSE-PW R-3-GP
2
PG4811
2
1 2
PWR_VCCSA_SEL1
GAP-CLOSE-PW R-3-GP
Vout=0.8*(1+R1/R2) PG4812
1 2
B B
GAP-CLOSE-PW R-3-GP
PQ4801
2N7002BK-GP
S DY D
84.07002.I31
2nd = 84.2N702.W31
G
3rd = 84.2N702.J31
PR4807
PW R_VCCSA_SEL0 1 2
DY VCCSA_SEL1 [9]
10KR2J-3-GP
1
DY PC4807
SCD1U10V2KX-4GP
2
A <Core Design> A
TPAD14-OP-GP TP4801 1 VCCSA_SEL0 [9]

Wistron Corporation
TPAD14-OP-GP TP4802 1 VCCSA_SENSE [9] Title
APL5916_VCCSA
A3 A00
BMW Z4 DIS
5 4 3 2 1
SSID = VIDEO SSID = VIDEO
X01 12/20
X01 12/02
LCD Power for ROSA
RN4901
LCD_TST_C 2 3 LCD_TST [27]
LVDS CONN BLON_OUT_C 1 4 BLON_OUT [27]
2
SRN100J-3-GP
LCD1
38 DCBATOUT_LCD R4908
X03 2/13 100KR2J-1-GP
31 39 68.00143.041 D4901
1
2nd = 68.00212.051 [17] LVDS_VDD_EN 1
1 LCD_POW ER 1 2
EL4901 BLM18PG330SN1D-GP R4902 3 LCDVDD_EN
2 33R2J-2-GP
32 3 BLON_OUT_C 2
[27] LCD_TST_EN
2
4 LCD_BRIGHTNESS 2 1 L_BKLT_CTRL [17] 3D3V_S0
5 DBC_EN_C BAT54CPT-GP R4909
6 3D3V_CAMERA_S0 100KR2J-1-GP
7 USB_CAMERA# 83.R2003.E81 U4901
8 USB_CAMERA 2ND = 83.00054.Q81 LCDVDD
1
9 COLOR_ENGINE_R 1 5
3D3V_S0 EN IN#5
10 AUD_DMIC_CLK [82] 2 GND
33 11 AUD_DMIC_IN0 [82] 3 OUT IN#4 4
12
1
13 LVDSA_CLK [17] C4907
1
2
14 LVDSA_CLK# [17] G5285T11U-GP SC4D7U6D3V3KX-GP
1
15 C4908
2
SC4D7U6D3V3KX-GP
16
17
LVDSA_DATA2 [17]
LVDSA_DATA2# [17] RN4903 Layout Note: DYEC4907
SCD1U25V3KX-GP 74.05285.07F
2
18 SRN2K2J-1-GP Trace width = 80mil 2nd = 74.09724.09F
34 19 LVDSA_DATA1 [17]
4
3
20 LVDSA_DATA1# [17]
21
22 LVDSA_DATA0 [17] A00 3/27
23 LVDSA_DATA0# [17]
24 LVDS_DDC_DATA_R_1 1 4 LVDS_DDC_DATA_R [17]
25 LVDS_DDC_CLK_R_1 2 3 LVDS_DDC_CLK_R [17]
26 LCD_TST_C
35 27 3D3V_LCD_ROM
28 RN4902
29 SRN100J-3-GP
30 3D3V_S0 3D3V_LCD_ROM
LCDVDD
1
36 40 C4901 C4902
SCD1U10V2KX-5GP SC1U6D3V2KX-GP R4901 1 2 0R3J-0-U-GP
37
DY
2
F4902 1 2 FUSE-2A32V-16-GP
FOX-CON30-4-GP DY
20.F2173.030
2nd = 20.F2089.030
X03 2/6
DBC_EN_C 1 2 DBC_EN [22]
R4912
0R0402-PAD-2-GP
COLOR_ENGINE_R 1 2 X03 2/16

DY COLOR_ENGINE [22]
R4913
0R2J-2-GP
LVDSA_CLK
A00 3/27 LVDSA_CLK#
X01 12/30 LVDSA_DATA0
LVDSA_DATA0#
LVDSA_DATA1
LVDSA_DATA1#
USB_CAMERA# LVDSA_DATA2
[18] USB_PN12
LVDSA_DATA2#
COLOR_ENGINE_R
TR4902
SC3D3P50V2CN-GP
SC3D3P50V2CN-GP
SC3D3P50V2CN-GP
SC3D3P50V2CN-GP
SC3D3P50V2CN-GP
SC3D3P50V2CN-GP
SC3D3P50V2CN-GP
SC3D3P50V2CN-GP
SC3D3P50V2CN-GP
1
1
2 1
EC4901
EC4902
EC4904
EC4905
EC4906
EC4908
EC4909
EC4910
EC4911
3 4
2
FILTER-4P-6-GP
69.10103.041
2nd = 68.00201.141
USB_CAMERA
[18] USB_PP12
Camera Power
DCBATOUT_LCD DCBATOUT
3D3V_S0 3D3V_CAMERA_S0
R4904 F4901 <Core Design>
1 2 2 1
1
0R3J-0-U-GP POLYSW -1D1A24V-GP-U

Wistron Corporation
C4905
1
SCD1U25V3KX-GP
C4904
69.50007.A31
SC1KP50V2KX-1GP
EC4903 C4903 2nd = 69.50007.A41 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
DY
2
SCD1U10V2KX-5GP SC10U6D3V5KX-1GP Taipei Hsien 221, Taiwan, R.O.C.

2
Title
LCD Connector
A3 A00
BMW Z4 DIS
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
CRT Connector
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
HDMI Level Shifter X03 2/6
R5101
C5103 1 2 SCD1U10V2KX-5GP HDMI_CLK_R_C# HDMI_CLK_R_C 1 2 HDMI_CLK_R_C_CON
[17] HDMI_CLK_R# C5104 SCD1U10V2KX-5GP HDMI_CLK_R_C 0R0603-PAD-2-GP
[17] HDMI_CLK_R 1 2
[17] HDMI_DATA0_R#
C5105 1 2 SCD1U10V2KX-5GP HDMI_DATA0_R_C# HDMI CONN
D C5106 1 2 SCD1U10V2KX-5GP HDMI_DATA0_R_C R5102 D
[17] HDMI_DATA0_R HDMI_CLK_R_C# HDMI_CLK_R_C#_CON
1 2
0R0603-PAD-2-GP HDMI1
22
20
C5110 1 2 SCD1U10V2KX-5GP HDMI_DATA1_R_C# R5103 HDMI_DATA2_R_C_CON 1
[17] HDMI_DATA1_R# C5107 SCD1U10V2KX-5GP HDMI_DATA1_R_C HDMI_DATA0_R_C HDMI_DATA0_R_C_CON
[17] HDMI_DATA1_R 1 2 1 2
0R0603-PAD-2-GP 2
C5108 1 2 SCD1U10V2KX-5GP HDMI_DATA2_R_C# HDMI_DATA2_R_C#_CON 3
[17] HDMI_DATA2_R# C5109 SCD1U10V2KX-5GP HDMI_DATA2_R_C HDMI_DATA1_R_C_CON
[17] HDMI_DATA2_R 1 2 4
R5104 5
HDMI_DATA0_R_C# 1 2 HDMI_DATA0_R_C#_CON HDMI_DATA1_R_C#_CON 6
0R0603-PAD-2-GP HDMI_DATA0_R_C_CON 7
8
8
7
6
5
8
7
6
5
HDMI_DATA0_R_C#_CON 9
RN5106 RN5107 R5105 HDMI_CLK_R_C_CON 10
SRN680J-GP SRN680J-GP HDMI_DATA2_R_C 1 2 HDMI_DATA2_R_C_CON 11
0R0603-PAD-2-GP HDMI_CLK_R_C#_CON 12
13
R5106 14
1
2
3
4
1
2
3
4
HDMI_PLL_GND HDMI_DATA2_R_C# 1 2 HDMI_DATA2_R_C#_CON DDC_CLK_HDMI 15
0R0603-PAD-2-GP 5V_HDMI_S0 DDC_DATA_HDMI 16
17
R5107 18
HDMI_DATA1_R_C 1 2 HDMI_DATA1_R_C_CON 19
0R0603-PAD-2-GP 21
1
C5102 23
D
R5108 SCD1U10V2KX-5GP
Q5103 HDMI_DATA1_R_C# 1 2 HDMI_DATA1_R_C#_CON SKT-HDMI19P-69-GP
2
C 2N7002K-2-GP 0R0603-PAD-2-GP 22.10296.211 C
2nd = 22.10296.431
HPD_HDMI_CON
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
5V_S0 3D3V_S0
4th = 84.2N702.W31
G
3
Q5102 1 HDMI_HPD_B 2 1
PMBS3904-1-GP 150KR2J-L1-GP R5111
1
X03 2/6
[17] HDMI_PCH_DET 1 2 HDMI_HPD_E 84.03904.L06 R5110
2nd = 84.03904.P11 DY 200KR2J-L1-GP
1
R5125
X03 02/14 0R0402-PAD-2-GP R5112
2
X03 01/09 5V_S0 10KR2J-3-GP
2
3
D5102
BAW 56-2-GP
83.00056.G11
1
2nd = 83.00056.E11
D5102_2
D5102_1
B B
X03 02/14
X01 12/27
X01 12/02
4
3 5V_S0 5V_HDMI_S0
3D3V_S0
F5101
RN5101
SRN2K2J-1-GP 1 2
FUSE-1D1A6V-4GP-U
Q5104
1
2
69.50007.691
4 3 DDC_CLK_HDMI 2nd = 69.50007.771
[17] PCH_HDMI_CLK
5 2
6 1
2N7002KDW -GP
[17] PCH_HDMI_DATA
DDC_DATA_HDMI
84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
DMB40
A 4th = 84.2N702.F3F A
Wistron Corporation
Title
HDMI Level Shifter/Connector

A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title

ITP/Fan Connector Rev
A3
BMW Z4 DIS A00
5 4 3 2 1
SSID = SATA
3D3V_S0 5V_S0 HDD CONN
X01 12/02
X01 12/15 5V_S5
1
C5604 EC5601 C5606
SC10U6D3V5KX-1GP SCD1U10V2KX-5GP C5605
DY SC10U6D3V5KX-1GP DY SCD1U10V2KX-5GP HDD1 Due to layout, HDD1 pin 23 modify 5V_S5
2
3D3V_S0 P1 V33 23 23
P2 V33 24 24
P3 V33
5V_S0 P7 V5
P8 V5
P9 V5
P13 V12 GND S1
P14 V12 GND S4
P15 V12 GND S7
GND P4
GND P5
SATA_TXP0_C S2 P6
SATA_TXN0_C A+ GND
S3 P10
Layout Note: A- GND
P12
SATA_RXP0_C GND
AC coupling Cap; S6 B+
place near CONN(<100mils) SATA_RXN0_C S5 P11
B- DAS/DSS
SKT-SATA7P-15P-85-GP
[21] SATA_TXP0 C5614 2 1 SCD01U16V2KX-3GP SATA_TXP0_C
[21] SATA_TXN0 C5613 2 1 SCD01U16V2KX-3GP SATA_TXN0_C
20.81599.022
2nd = 22.10300.C51
[21] SATA_RXP0 C5615 1 2 SCD01U16V2KX-3GP SATA_RXP0_C

[21] SATA_RXN0 C5616 1 2 SCD01U16V2KX-3GP SATA_RXN0_C
ODD CONN
5V_S0
Layout Note:
2
ODD1 SATA_RX- and SATA_RX+ Trace
15 AC coupling Cap; R5605
NP2
Length match within 20 mil 100KR2J-1-GP
place near CONN(<100mils)
S1
1
S2 SATA_TXP4_C C5612 1 2 SCD01U16V2KX-3GP SATA_TXP4 [21]
SATA_TXN4_C C5611 1 2 SCD01U16V2KX-3GP SATA_ODD_DA#_C
ODD_PWRGT#
S3 SATA_TXN4 [21]
S4
S5 SATA_RX4-_C C5607 1 2SCD01U16V2KX-3GP SATA_RXN4 [21]
S6 SATA_RX4+_C C5608 1 2SCD01U16V2KX-3GP SATA_RXP4 [21]
S7
3D3V_S0
4
1 SATA_ODD_PRSNT# [22] Q5601
2N7002KDW -GP
2 R5604 1 210KR2J-3-GP
ODD_PW R_5V DY
1
3 84.2N702.A3F
4 SATA_ODD_DA#_C 2 1 R5607 2nd = 84.DM601.03F
DY SATA_ODD_DA# [18]
3
5 10KR2J-3-GP 3rd = 84.2N702.E3F
6 R5602 4th = 84.2N702.F3F
0R2J-2-GP
2
NP1
14
SATA_ODD_PW RGT SATA_ODD_DA#
SKT-SATA7P+6P-77-GP-U
2nd = 20.81152.013
[22] SATA_ODD_PW RGT
Zero Power ODD Power Sequence

U5602 ODD_PW R_5V
5V_S0
4 EN OC# 5
3 6 ODD_PW R_5V 100 mil
VIN VOUT#6
2 VIN VOUT#7 7
1 GND VOUT#8 8
1
1
C5617 C5618
SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP
UP7534PRA8-15-GP
2
2
74.07534.D79
2nd = 74.00547.G79 <Core Design>
Wistron Corporation
1 2 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
R5606 DY 0R5J-6-GP Taipei Hsien 221, Taiwan, R.O.C.
Title
1
R5603
2
DY 0R5J-6-GP HDD/ODD
A3 A00
BMW Z4 DIS
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = LOM
D D
XF5901
1CT:1CT
16 1 MDO1-
[31] LAN_MDI1N
AVDD_CEN 14 3 XFR_CMT1 XFR_CMT2
15 2 MDO1+
[31] LAN_MDI1P
Tx Side
1CT:1CT
10 7 MDO0-
[31] LAN_MDI0N
AVDD_CEN 11 6 XFR_CMT0
C C
9 8 MDO0+
[31] LAN_MDI0P
Rx Side
1
C5905 C5904 C5903 C5901 XFR_CMT3

SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY DY XFORM-12P-36-GP
2
68.HD081.30B
8
7
6
5
2nd = 68.0NS14.30B
RN5901
SRN75J-1-GP
X03 2/29
1
2
3
4
LAN_TERMINAL 1 2
C5902
B SC1000P3KV8KX-L1-GP B
RJ45 Connector
RJ45
10
AFTP5901 1 XFR_CMT3 8
7
AFTP5903 1 MDO1- 6
AFTP5904 1 XFR_CMT2 5
4
AFTP5906 1 MDO1+ 3
AFTP5907 1 MDO0- 2
AFTP5908 1 MDO0+ 1 DMB40

9
A
RJ45-8P-28-GP-U
Wistron Corporation A
AFTP5909 1
22.10277.B61 Taipei Hsien 221, Taiwan, R.O.C.
Title
RJ45+Transfermer
A4
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = Flash.ROM
SPI Flash ROM(8M) for PCH
3D3V_S5
3D3V_S5
D D
1
C6001 C6002
SC10U6D3V5KX-1GP DY SCD1U10V2KX-5GP
2
2
4
3
R6003 RN6001
4K7R2J-2-GP SRN4K7J-8-GP
PCH
1
2
SPI_HOLD_0#
U6001 3D3V_S5 SPI

X01 12/21
[21,27] SPI_CS0#_R 1 CS# VCC 8
[21,27] SPI_SO_R 2 DO/IO1 HOLD#/IO3 7
SPI_W P# 3 6 SPI_CLK_R [21,27]
WP#/IO2 CLK
4 5 SPI_SI_R [21,27]
1
GND DI/IO0 KBC
1
W 25Q64CVSSIG-GP
EC6002 DY EC6001
SC4D7P50V2CN-1GP 72.25Q64.B01 DY DY SC10P50V2JN-4GP
2
2
2nd = 72.25640.D01 Layout Note:
3rd = 72.25Q64.F01 EC6003
4th = 72.25Q64.D01 SC4D7P50V2CN-1GP KBC----10"----PCH
C
KBC----1.5"~6.5"----SPI C
PCH----0.5"~6.5"----SPI
X01 12/02
SSID = RBATT
3D3V_AUX_S5
B B
RTC_AUX_S5 D6001
2 X01 12/02
+RTC_VCC
3 R6002 RTC1
1KR2J-1-GP 3
1 RTC_PW R 1 2 1
2
C6003 CH715FPT-GP 2
SC1U6D3V2KX-GP 4
1
83.R0304.B81
2nd = 83.00040.E81 TPAD14-OP-GP TP6001 1 ACES-CON2-11-GP
20.F0772.002
2nd = 20.F1035.002
TPAD14-OP-GP TP6002 1 +RTC_VCC
R6006
100R2J-2-GP
1 2
DY
Q6002
RTC_PW R G
1
A D RTC_DET# [22] <Core Design> A

R6007
10MR2J-L-GP S
2N7002K-2-GP Wistron Corporation

2
84.2N702.J31 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

2ND = 84.2N702.031 Taipei Hsien 221, Taiwan, R.O.C.
3rd = 84.07002.I31
4th = 84.2N702.W31 Title
Flash/RTC
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = USB
USB3.0 Port1 with power share
A00 3/27
X01 12/23
USB_PP0_RR USB20_DP0_C USB30_VCCA

USB1
D 1 5 USB30_RXDN1_C D
VBUS SSRX- USB30_RXDP1_C
SSRX+ 6
TR6204
4 3 USB20_DN0_C 2 8 USB30_TXDN1_C
USB20_DP0_C D- SSTX- USB30_TXDP1_C
3 D+ SSTX+ 9
1 2
10 10
11 4 USBDET
FILTER-4P-62-GP 11 PGND
12 12
69.10080.021 13 13 GND 7
2nd = 69.10103.061
USB_PN0_RR USB20_DN0_C SKT-USB13-70-GP-U
22.10341.691
A00 3/23
X01 12/15
X01 12/02
1 2 USB30_TXDN1_R 1 2 USB30_TXDN1_C [18] USB3_RX1_N 1 2 USB30_RXDN1_C
[18] USB3_TX1_N
C6223 R6281 R6283 USBDET
SCD1U10V2KX-5GP 0R0402-PAD-2-GP 0R0402-PAD-2-GP
C 1 2 C
USBDET_CON# [27]
R6208
0R2J-2-GP
U6204 USB30_VCCA
USB20_DN0_C 1 8
1 2 USB30_TXDP1_R 1 2 USB30_TXDP1_C [18] USB3_RX1_P 1 2 USB30_RXDP1_C
[18] USB3_TX1_P
C6222 R6282 R6284 USB20_DP0_C 2 7
SCD1U10V2KX-5GP 0R0402-PAD-2-GP 0R0402-PAD-2-GP
USB30_RXDP1_C 3 6 USB30_TXDP1_C
DY
USB30_RXDN1_C 4 5 USB30_TXDN1_C
X01 12/13 AZ1065-06Q-GP
B B
5V_S5
X03 01/30
USB Charger
1
C6201
SC1U25V3KX-1-GP
USB30_VCCA
2
U6201
1 IN OUT 12 TPS2541 charging type setting

13 11 USB_PN0_RR
SC10U6D3V5KX-1GP
[18,82] USB_OC#0_1 FAULT# DM_IN
1
C6203
DP_IN 10 USB_PP0_RR TC6201 CTL1 CTL2 CTL3
C6202
X03 2/6
SCD1U10V2KX-5GP
1 2 ILIM_SEL 4 2 80.10715.B1L
ST100U6D3VAM-3-GP
USB_PN0 [18]
2
2
ILIM_SEL DM_OUT CDP
R6202 0R0402-PAD-2-GP
DP_OUT 3 USB_PP0 [18] 2nd = 78.10710.52L 1 1 1
9 NC#9 3rd = 77.C1071.22L
X03 2/6 16 ILIM0 1 2
ILIM0 DCP
5 15 ILIM1 R6210 1 2 20KR2J-L2-GP 0 0 X
[27] USBCHG_EN
1 2 CTL1 6
DSC ILIM1 R6211 DY 20KR2J-L2-GP
R6203 1 CTL1
20R0402-PAD-2-GP CTL2 7 CTL2 GND 14
[27] USBCHARGER_CB0 R6204 1 20R0402-PAD-2-GP CTL3 8 17
R6205 0R0402-PAD-2-GP CTL3 GND
TPS2541RTER-GP
A 74.02541.A73 <Core Design> A
Wistron Corporation
Title
USB 3.0
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
(Reserved)
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title

Finger Printer Rev
A3 BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = Wireless
Mini Card Connector(802.11a/b/g/n)
WLAN CONN
D D
X03 2/6
1D5V_S0 3D3V_W LAN_AOAC 1D5V_S0
W LAN1
R6502 53
0R0402-PAD-2-GP NP1
[27,66] AOAC_PCIE_W AKE# 1 2 W LAN_W AKE# 1 2 C6505
SCD1U10V2KX-5GP
1
2
TPAD14-OP-GP TP6501 1 W LAN_ACT 3 4 C6502 C6503
SC10U6D3V5KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
TPAD14-OP-GP TP6502 1 BT_ACT 5 6 C6504
DY
2
CLK_PCIE_W LAN_REQ#_C 7 8 SC10U6D3V5MX-3GP
1
C6501
9 10
[20] CLK_PCIE_W LAN# 11 12
1
[20] CLK_PCIE_W LAN 13 14
15 16 A00 3/23
TPAD14-OP-GP TP6503 1 E51_RxD_R 17 18 X03 2/6
1 2 E51_TxD_R 19 20
[27] E51_TxD
R6504 DY 0R2J-2-GP 21 22 W LAN_22 1 2
W IFI_RF_EN [27]
R6505 PLT_RST# [5,18,27,31,66,71] USB_PP11_R
[20] PCIE_RXN4 23 24 [18] USB_PP11 1 2
[20] PCIE_RXP4 25 26 0R0402-PAD-2-GP R6503
27 28 0R0603-PAD-2-GP
29 30 PCH_SMBCLK
PCH_SMBCLK [14,15,20,66,69]
[20] PCIE_TXN4 31 32 PCH_SMBDATA
PCH_SMBDATA [14,15,20,66,69]
[20] PCIE_TXP4 33 34
35 36 USB_PN11_R
37 38 USB_PP11_R
C 39 40 C
3D3V_W LAN_AOAC
41 42
43 44 W LAN_LED# W LAN_LED# [68]
45 46 W PAN_LED# W PAN_LED# [68]
R6508 47 48
10KR2J-3-GP 49 50
1 2 51 52
5V_S5 DY NP2 [18] USB_PN11 1 2 USB_PN11_R
54 R6506
0R0603-PAD-2-GP
[18] BLUETOOTH_EN SKT-MINI52P-54-GP-U
62.10043.981
2nd = 20.F1764.052
3rd = 62.10043.F11
X01 12/15
X01 12/09
3D3V_W LAN_AOAC
3D3V_S5 3D3V_W LAN_AOAC
U6502
X01 12/02
3D3V_W LAN_AOAC AO3404A-GP
1
D S
R6507
100R2J-2-GP
84.03404.B31 DY
G
1
B B
2nd = 84.03404.C31
2
R6513
10KR2J-3-GP AO3404A MAX 4.9A
1

R6512
U6501_D
2 CLK_WLAN_REQ#_EN
10KR2J-3-GP
15V_S5 1 2 VAUX_G_SW
2
D
1
R6509
84.03904.L06 100KR2J-1-GP C6506
2ND = 84.03904.P11 SCD01U50V2KX-1GP
2
DY
1
Q6502 3D3V_S5
D
PMBS3904-1-GP
[20] CLK_PCIE_W LAN_REQ# 3 2 CLK_PCIE_W LAN_REQ#_C Q6503
2N7002K-2-GP
S
2
R6511
2 1 R6510 84.2N702.J31 AOAC_W LAN_EN#
DY 100KR2J-1-GP 2ND = 84.2N702.031
0R2J-2-GP 3rd = 84.07002.I31 U6501
4th = 84.2N702.W31 2N7002K-2-GP
S
84.2N702.J31
2ND = 84.2N702.031
[27] AOAC_W LAN_EN# AOAC_W LAN_EN#
A <Core Design> A
Wistron Corporation
Title
WLAN/BT
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = Wireless
WWAN CONN
X03 1/30
W W AN1
A00 3/23 53 R6615
NP1 0R2J-2-GP
2 1 W W AN_W AKE# 2 1
R6602 1D5V_S0 DY AOAC_PCIE_W AKE# [27,65]
0R0603-PAD-2-GP 4 3
D [18] USB_PP8 1 2 USB_PP8_R 6 5 D
UIM_PW R 8 7
1
C6602 C6603 UIM_DATA 10 9
SC33P50V2JN-3GP SCD047U10V2KX-2GP UIM_CLK_L R6604 1 2 33R2J-2-GP UIM_CLK 12 11
UIM_RESET 14 13
WWAN WWAN WWAN
2
UIM_VPP 16 15
18 17
3D3V_W W AN_AOAC 3G_EN 20 19
[27] 3G_EN
1 2 W W AN_22 22 21
[5,18,27,31,65,71] PLT_RST# SATA_RXP1_C C6612 SCD01U16V2KX-3GP
24 23 1 2
R6616 26 25 SATA_RXN1_C C6601 1
MSATA
2 SCD01U16V2KX-3GP
SATA_RXP1 [21]
MSATA SATA_RXN1 [21]
2
A00 3/23 0R0402-PAD-2-GP 28 27
30 29
MSATA_WWANC6604 [14,15,20,65,69] PCH_SMBCLK
32 31 SATA_TXN1_C C6613 1 2 SCD01U16V2KX-3GP
[14,15,20,65,69] PCH_SMBDATA MSATA SATA_TXN1 [21]
1
[18] USB_PN8 1 2 USB_PN8_R SCD1U10V2KX-5GP 34 33 SATA_TXP1_C C6615 1 2 SCD01U16V2KX-3GP SATA_TXP1 [21]
R6601 USB_PN8_R 36 35
0R0603-PAD-2-GP USB_PP8_R 38 37 MSATA
40 39 3D3V_W W AN_AOAC
[68] W W AN_LED# W W AN_LED# 42 41
44 43
46 45
3D3V_W W AN_AOAC 48 47
50 49 DAS 1 TP6601 TPAD14-OP-GP
EC6602 52 51 MSATA_DET# MSATA_DET# [22]
ST220U6D3VDM-20GP
TC6601
SC33P50V2JN-3GP
C6605
SC33P50V2JN-3GP
C6606
SCD047U10V2KX-2GP
C6607
SCD047U10V2KX-2GP
C6608
SC1U6D3V2KX-GP
MSATA_WWAN
MSATA_WWAN
MSATA_WWAN
NP2
SIM1 54
10 1 2
WWAN MSATA_WWAN
1
8
C C1 UIM_PW R C
77.22271.27L MSATA_WWAN SKT-MINI52P-54-GP-U
WWAN
2
C5 2nd = 79.22710.20L 62.10043.981
C2 UIM_RESET 2nd = 20.F1764.052
WWAN C6 UIM_VPP 3rd = 62.10043.F11
C3 UIM_CLK_L
C7 UIM_DATA
9 X01 12/09
11
SDCARD-10P-1-GP 3D3V_S5 3D3V_W W AN_AOAC 3D3V_W W AN_AOAC

U6607
62.10051.971
AO3404A-GP
1
D S
R6611
100R2J-2-GP
84.03404.B31 DY
Layout Note: DY
G
2nd = 84.03400.B37
2
DATA & CLK keep about 20mil
AO3404A MAX 4.9A
U6605_D
15V_S5 1 2 W W AN_G_SW
6 UIM_VPP 3D3V_S0 R6603 3D3V_W W AN_AOAC
UIM_RESET 1 0R3J-0-U-GP DY
DY
D
1
B R6612 B
1 2
MSATA_WWAN 100KR2J-1-GP C6609
2 5 UIM_PW R R6605
SCD01U50V2KX-1GP
2
0R3J-0-U-GP
DY 1 2 3D3V_S5 DY
MSATA_WWAN
D
UIM_CLK_L 3 4 UIM_DATA U6608
S
2
2N7002K-2-GP
SC10P50V2JN-4GP
SC33P50V2JN-3GP
EC6605 EC6601 U6601 R6613 AOAC_W W AN_EN#

1
1
SC33P50V2JN-3GP
SC33P50V2JN-3GP
EC6606
EC6607
SRV05-4-2-GP 100KR2J-1-GP
DY DY
1
U6605
WWAN WWAN
WWAN WWAN 2N7002K-2-GP
2
S
84.2N702.J31
2
2ND = 84.2N702.031
[27] AOAC_W W AN_EN# AOAC_W W AN_EN#
Layout Note:
Close to SIM1
A <Core Design> A
Wistron Corporation
Title
WWAN/MSATA
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface
PWRBTN
Front Power LED X01 12/02
LOW actived from KBC GPIO [27] KBC_PW RBTN# 1 2 KBC_PW RBTN#_C
5V_S5
Q6801 R6806 R6802
R2
E 680R2J-3-GP 100R2F-L1-GP-U
2
[27] PW RLED# B R1
C LED_PW R 1 2 FPOW ER_LED_A FPOW ER_LED_A [82]
D 6 5 D
1
PDTA144VT-GP PW LED1
SC220P50V2KX-3GP
2 POW ER_SW _LED_B
EC6801
84.00144.P11 DY 1 A K
2nd = 84.DT144.A11 R6808 1KR2J-1-GP
1
83.19213.H70 LED-W -45-GP
2nd = 83.00191.F70
PW LED2
1 2 POW ER_SW _LED_C A K
R6811 1KR2J-1-GP PW SW 1
5V_S0 83.19213.H70 LED-W -45-GP SW -TACT-130-GP-U
2nd = 83.00191.F70 62.40009.731
Q6805 2nd = 62.40089.441
R2
E
[21] SATA_LED# B R1
C SATA_LED_R 1 2 HDD_LED_A HDD_LED_A [82]
SATA HDD LED
1
PDTA144VT-GP R6812
EC6810
SC220P50V2KX-3GP
84.00144.P11 680R2J-3-GP
LOW actived from PCH GPIO 2nd = 84.DT144.A11 DY
2
C Battery LED2(White_LED) C
5V_S5
LOW actived from KBC GPIO Q6809 X01 12/02 X01 12/15 A00 3/22
R2
E
[27] BATT_W HITE_LED# B R1
C LED_BATCHG 1 2 BAT_W HITE_LED_A BAT_W HITE_LED_A [82]
PDTA144VT-GP R6804
SC220P50V2KX-3GP
1
680R2J-3-GP
EC6804
84.00144.P11
2nd = 84.DT144.A11 DY
2
5V_S5
Battery LED1(Amber_LED) Q6808
R2
E
LOW actived from KBC GPIO B
[27] CHG_AMBER_LED# R1
LED_BAT BAT_AMBER_LED_A
C 1 2 BAT_AMBER_LED_A [82]
SC220P50V2KX-3GP
PDTA144VT-GP R6805
EC6802
84.00144.P11 680R2J-3-GP
2nd = 84.DT144.A11 DY
2
TPLOCK LED
LOW actived from KBC GPIO
B B
5V_S0
Q6807
R2
E
[27] TP_LOCK_LED# B R1
C TP_LOCK_LED_R 1 2 TP_LOCK_LED_A TP_LOCK_LED_A [82]
1
PDTA144VT-GP R6818
SC220P50V2KX-3GP
680R2J-3-GP
EC6812
84.00144.P11 DY
2nd = 84.DT144.A11
2
X03 1/30 A00 3/22
WLAN LED
LOW actived from KBC GPIO
A00 3/22
83.R2003.P81 5V_S0
D6801 2nd = 83.00056.G11
A 1 Q6806 A
[66] W W AN_LED# R2 <Core Design>
E
3 AOAC_LED# B R1
C W LAN_LED_R 1 2 W LAN_LED_A
[65] W PAN_LED# 2
W LAN_LED_A [82]
Wistron Corporation
1
PDTA144VT-GP R6815 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

SC220P50V2KX-3GP
X03 01/30 680R2J-3-GP Taipei Hsien 221, Taiwan, R.O.C.

EC6811
BAT54A-7-F-1-GP 84.00144.P11 DY
2nd = 84.DT144.A11
2
D6803 Title
B0530W S-7-F-GP 83.R5003.G8H
[65] W LAN_LED# K A 2nd = 83.R5003.H8H LED Bar/Power Button
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = KBC SSID = Touch.Pad
Internal Keyboard Connector

KB1 1 AFTP6901
31
D 1 D
KB_DET# [21] Touch Pad Connector
2 KROW 7 1 AFTP6909
3 KROW 6 1 AFTP6910
4 KROW 4 1 AFTP6911
5 KROW 2 1 AFTP6913 TP_VDD A00 3/27 3D3V_S0
6 KROW 5 1 AFTP6912 TP_VDD TP_VDD
7 KROW 1 1 AFTP6914 R6909
8 KROW 3 1 AFTP6916 1 2
9 KROW 0 1 AFTP6915
10 KCOL5 1 AFTP6917 0R3J-0-U-GP
1
2
1
11 KCOL4 1 AFTP6919 C6901 X01 12/02
12 KCOL7 1 AFTP6918 KROW [0..7] [27] RN6901 SCD1U10V2KX-5GP
13 KCOL6 1 AFTP6920 SRN10KJ-5-GP 1
2
14 KCOL8 1 AFTP6922 AFTP6935
15 KCOL3 1 AFTP6921 KCOL[0..16] [27] TPAD1
16 KCOL1 1 AFTP6923 7
4
3
17 KCOL2 1 AFTP6925 1
18 KCOL0 1 AFTP6924
19 KCOL12 1 AFTP6926 [27] TPCLK R6911 1 2 0R2J-2-GP TPCLK_C 2
20 KCOL16 1 AFTP6928 [27] TPDATA R6910 1 2 0R2J-2-GP TPDATA_C 3
21 KCOL15 1 AFTP6927 4
22 KCOL13 1 AFTP6929 [14,15,20,65,66] PCH_SMBCLK 5 3D3V_S5
1
23 KCOL14 1 AFTP6931 [14,15,20,65,66] PCH_SMBDATA 6
24 KCOL9 1 AFTP6930 EC6917 EC6918 8
25 KCOL11 1 AFTP6932 SC33P50V2JN-3GP DY DY SC33P50V2JN-3GP
2
26 KCOL10 1 AFTP6934 PTW O-CON6-12-GP
27 CAP_LED CAP_LED
28 20.K0382.006
C 29 2nd = 20.K0320.006 C
30 1 AFTP6902
32 Due to layout, TPAD1 pin 8 modify to 3D3V_S5
ACES-CON30-14-GP
TP_VDD 1 AFTP6906
20.K0700.030 TPCLK_C 1 AFTP6907
2nd = 20.K0750.030 TPDATA_C 1 AFTP6908
PCH_SMBCLK 1 AFTP6933
PCH_SMBDATA 1 AFTP6937
CAP LED Control 5V_S0 CAP_LED

Q6902
LOW actived from KBC GPIO R2
E
B R6906
[27] CAP_LED# R1
CAP_LED_Q CAP_LED
C 1 2
PDTA144VT-GP 1KR2J-1-GP
84.00144.P11
2nd = 84.DT144.A11
B B
A DMB40 A
Wistron Corporation
Title
Key Board/Touch Pad

A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
D D
3D3V_S5
1
C7001
C SCD1U10V2KX-5GP LIDSW1 C
2
2 VDD
VSS 1
[27] LID_CLOSE# LID_CLOSE# 3 OUT
1
C7002 S-5711ACDL-M3T1S-GP
DY SCD047U16V2KX-1-GP
2 74.05711.07B
2nd = 74.05712.0BB
3rd = 74.01803.07B
B B
DMB40
A
Wistron Corporation A
Title
Hall Sensor
A4 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = DEBUG PORT

Debug Connector
A00 3/15
Layout Note:
Place near trace separated point 3D3V_S0
DB1
11
LPC_AD[3..0] RN7101 1
[21,27] LPC_AD[3..0]
SRN0J-7-GP
LPC_AD0 1 8 LPC_LAD0_R 2
D
LPC_AD3 4 LPC 5 LPC_LAD3_R 5
D
LPC_FRAME#_DEBUG 6
1 2 PLT_RST#_DEBUG 7
[21,27] LPC_FRAME#
R7101 1 LPC 2 0R2J-2-GP 8
[5,18,27,31,65,66] PLT_RST#
R7102 LPC 0R2J-2-GP 9
[18] CLK_PCI_LPC
10
12
PAD-10P-177042-GP
ZZ.00PAD.Y41
SSID = CPU
C C
CPU XDP
XDP_PREQ# 1 TP7101 TPAD14-OP-GP

[5] XDP_PREQ# XDP_PRDY# TP7102 TPAD14-OP-GP
[5] XDP_PRDY# 1
[5] XDP_BPM0 XDP_BPM0 1 TP7103 TPAD14-OP-GP




B CFG0 TP7111 TPAD14-OP-GP B
[7] CFG0 1
DMB40
A A
Wistron Corporation
Title
Dubug connector
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
DMB40
A A
Wistron Corporation
Title
(Reserved)
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface Due to layout, TPLED1 pin 5 modify 3D3V_S5

X01 12/02
5V_S5 3D3V_S5
MEDIA1
9 LEDBD1 TPLED1
1 7 5
1 FPOW ER_LED_A FPOW ER_LED_A [68]
2 INSTANT_LAUNCH#_LED_1 1 2 INSTANT_LAUNCH#_LED# [27] 1 TP_LOCK_LED_A [68]
3 AUDIO_PRESENT#_LED_1 R8201 1 21KR2J-1-GP AUDIO_PRESENT#_LED# [27] 2 HDD_LED_A HDD_LED_A [68]
4 MOBILITY_CENTER#_LED_1 R8202 1 21KR2J-1-GP MOBILITY_CENTER#_LED# [27] 3 BAT_W HITE_LED_A BAT_W HITE_LED_A [68] 2
D 5 R8203 1KR2J-1-GP INSTANT_LAUNCH# [27] 4 BAT_AMBER_LED_A BAT_AMBER_LED_A [68] 3 D
6 AUDIO_PRESENT# [27] 5 W LAN_LED_A W LAN_LED_A [68] 4
7 MOBILITY_CENTER# [27] 6
8 8 A00 3/15 6
10 X03 2/6
PTW O-CON6-12-GP
X01 12/20 ACES-CON4-10-GP-U
ACES-CON8-40-GP
3D3V_S0
20.K0382.006 20.K0320.004
20.K0667.008
2nd = 20.K0665.008 INSTANT_LAUNCH#_LED# 1 2 2nd = 20.K0320.006 2nd = 20.K0382.004
AUDIO_PRESENT#_LED# EC8203 1 2 SC470P50V-2-GP 5V_S0
MOBILITY_CENTER#_LED# EC8204 1 2 SC470P50V-2-GP R8205
EC8205 SC470P50V-2-GP AFTP8209 1 FPOW ER_LED_A TPAN1 1 2 0R3J-0-U-GP AFTP8215 1 TP_LOCK_LED_A
AFTP8210 1 HDD_LED_A 7
DY AFTP8214 1 GND
AFTP8211 1 BAT_W HITE_LED_A R8204
AFTP8212 1 BAT_AMBER_LED_A 1 TPAN_PW R 1 2 0R3J-0-U-GP
AFTP8201 1 INSTANT_LAUNCH#_LED_1 AFTP8213 1 W LAN_LED_A DY
AFTP8202 1 AUDIO_PRESENT#_LED_1 AFTP8216 1 GND 2
AFTP8203 1 MOBILITY_CENTER#_LED_1 3 USB_PN4 [18] A00 3/15
4 USB_PP4 [18]
AFTP8205 1 INSTANT_LAUNCH# 5 5V_S0
AFTP8206 1 AUDIO_PRESENT# DY 6 CRTBD1
AFTP8207 1 MOBILITY_CENTER# 11
AFTP8208 1 GND 8 1
ACES-CON6-39-GP 2 VGA_R [85]

3 VGA_G [85]
4 VGA_B [85]
A00 3/23 5
C X01 12/23 6 VGA_CRT_DDCCLK [85]
C
X01 12/13 7 VGA_CRT_DDCDATA [85]
8 VGA_CRT_HSYNC [85]
X03 1/30 9 VGA_CRT_VSYNC [85]
X01 12/20 USB_PP1_C ER8201 1 2 0R0603-PAD-2-GP USB_PP1 [18] 10 3D3V_VGA_S0
X01 12/02 12
IOBD1 PAD-10P-177042-GP
48
ZZ.00PAD.Y41
41 50
1 5V_S5
2
3
4
5 USB_PN1_C ER8202 1 2 0R0603-PAD-2-GP USB_PN1 [18]
42 6 5V_S0
7
8
9
10
11 3D3V_S0
12 AUD_PC_BEEP AUD_PC_BEEP C8253 1 2 SCD1U10V2KX-5GP SB_SPKR_R 1 2 HDA_SPKR [21]
43 13 C8254 1 2 SCD1U10V2KX-5GP KBC_BEEP_R R8233 1 2100KR2J-1-GP KBC_BEEP [27]
14 USB_PP1_C R8234 100KR2J-1-GP
15 USB_PN1_C
16
2
17 HDA_CODEC_SDOUT [21]
B R8230 R8231 B
18
19 HDA_SDIN0 [21] 10KR2J-3-GP 10KR2J-3-GP
44 20 A00 3/23
21 HDA_CODEC_SYNC [21] X01 12/23
1
22 AMP_MUTE# [27] X01 12/13
23 HDA_CODEC_RST# [21]
24
25 AUD_DMIC_CLK [49] USB_PP10_C ER8203 1 2 0R0603-PAD-2-GP USB_PP10 [18]
26 AUD_DMIC_IN0 [49] A00 3/23
45 27 USB_PW R_EN# [27] X01 12/23
28 USB_OC#0_1 [18,62] X01 12/13
29 USB_PP10_C
30 USB_PN10_C
31
32 HDA_CODEC_BITCLK_C 1 2 HDA_CODEC_BITCLK [21]
33 ER8205
46 34 HDA_CODEC_BITCLK_C 0R0402-PAD-2-GP
1
35
36 EC8206
USB3_TX2_P [18] USB_PN10_C ER8204 1 SC10P50V2JN-4GP
37 2 0R0603-PAD-2-GP USB_PN10 [18]
2
USB3_TX2_N [18]
38
39 USB3_RX2_N [18]
40 USB3_RX2_P [18]
47 51
5V_S5 5V_S0 3D3V_S0
49
FOX-CON40-2R-1-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
A 20.F2091.040 SC10U6D3V3MX-GP <Core Design> A

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2nd = 20.F2089.040
2
1
C8202
C8203
C8205
EC8201
EC8202
EC8207
DY DY DY Wistron Corporation
1

Title

IO Board Connector Rev
A3 BMW Z4 DIS A00
X01 12/09 Request by EMI A00 3/27
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
[4] PEG_TXP[7..0] VGA1A PEG_RXP[7..0] [4]
1 OF 7
[4] PEG_TXN[7..0] PEG_RXN[7..0] [4]
D D
PEG_TXP0 AF30 AH30 PEG_C_RXP0 C8318 1 SCD1U10V2KX-5GP PEG_RXP0
PEG_TXN0 AE31
PCIE_RX0P PCIE_TX0P
AG31 PEG_C_RXN0 C8317 1
SG22 SCD1U10V2KX-5GP PEG_RXN0
PCIE_RX0N PCIE_TX0N SG
PEG_TXP1 AE29 AG29 PEG_C_RXP1 C8320 1 SCD1U10V2KX-5GP PEG_RXP1
PEG_TXN1 AD28
PCIE_RX1P PCIE_TX1P
AF28 PEG_C_RXN1 C8319 1
PEG_TXP2 AD30 AF27 PEG_C_RXP2 C8321 1 SCD1U10V2KX-5GP PEG_RXP2
PEG_TXN2 AC31
PCIE_RX2P PCIE_TX2P
AF26 PEG_C_RXN2 C8322 1
PEG_TXP3 AC29 AD27 PEG_C_RXP3 C8323 1 SCD1U10V2KX-5GP PEG_RXP3
PEG_TXN3 AB28
PCIE_RX3P PCIE_TX3P
AD26 PEG_C_RXN3 C8328 1 SG22 SCD1U10V2KX-5GP PEG_RXN3
PEG_TXP4 AB30 AC25 PEG_C_RXP4 C8327 1 SCD1U10V2KX-5GP PEG_RXP4
PCIE_RX4P PCIE_TX4P SG22
PCI EXPRESS INTERFACE

PEG_TXN4 AA31 AB25 PEG_C_RXN4 C8326 1 SCD1U10V2KX-5GP PEG_RXN4
PEG_TXP5 AA29 Y23 PEG_C_RXP5 C8335 1 SCD1U10V2KX-5GP PEG_RXP5
PEG_TXN5 Y28
PCIE_RX5P PCIE_TX5P
Y24 PEG_C_RXN5 C8336 1
PEG_TXP6 Y30 AB27 PEG_C_RXP6 C8330 1 SCD1U10V2KX-5GP PEG_RXP6
PEG_TXN6 W31
PCIE_RX6P PCIE_TX6P
AB26 PEG_C_RXN6 C8329 1
X01 12/15
C PEG_TXP7 W29 Y27 PEG_C_RXP7 C8332 1 SCD1U10V2KX-5GP PEG_RXP7 C
PEG_TXN7 V28
PCIE_RX7P PCIE_TX7P
Y26 PEG_C_RXN7 C8331 1
V30 PCIE_RX8P PCIE_TX8P W24
U31 PCIE_RX8N PCIE_TX8N W23
U29 PCIE_RX9P PCIE_TX9P V27

T28 PCIE_RX9N PCIE_TX9N U26
T30 PCIE_RX10P PCIE_TX10P U24

R31 PCIE_RX10N PCIE_TX10N U23
R29 PCIE_RX11P PCIE_TX11P T26

P28 PCIE_RX11N PCIE_TX11N T27
P30 PCIE_RX12P PCIE_TX12P T24

N31 PCIE_RX12N PCIE_TX12N T23
N29 PCIE_RX13P PCIE_TX13P P27

M28 PCIE_RX13N PCIE_TX13N P26
M30 PCIE_RX14P PCIE_TX14P P24

B B
L31 PCIE_RX14N PCIE_TX14N P23
L29 PCIE_RX15P PCIE_TX15P M27

K30 PCIE_RX15N PCIE_TX15N N26
CLOCK X03 2/6

[20] CLK_PCIE_VGA AK30 PCIE_REFCLKP [22] DGPU_HOLD_RST# 1 2 VGA_RST# [85]
AK32 R8322 0R0402-PAD-2-GP
[20] CLK_PCIE_VGA# PCIE_REFCLKN
1V_VGA_S0
CALIBRATION
Y22 PCIE_CALRP 1 2
PCIE_CALRP R8326 SG 1K27R2F-L-GP
1 2 PW RGOOD N10 AA22 PCIE_CALRN 1 2
R8317 SG 10KR2F-2-GP PWRGOOD PCIE_CALRN R8318 SG 2KR2F-3-GP
VGA_RST# AL27
PERST#
SG
1
C8333
ROBSON-GP-U
SC47P50V2JN-3GP
DY
2
A <Core Design> A
Wistron Corporation
Title
GPU_PEG/STRAPPING(1/5)
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
VGA1C 3 OF 7
[88] DQA0_[31..0]
MAA0_8 MAA0_[8..0] [88]
DQA0_0 K27 K17 MAA0_0
DQA0_1 DQA_0 MAA_0 MAA0_1
J29 DQA_1 MAA_1 J20
DQA0_2 H30 H23 MAA0_2
H32 DQA_3 MAA_3 G23
DQA0_4 G29 G24 MAA0_4
F28 DQA_5 MAA_5 H24
DQA0_6 MAA0_6
MEMORY INTERFACE
D F32 DQA_6 MAA_6 J19 D
DQA0_7 F30 K19 MAA0_7
DQA0_8 DQA_7 MAA_7 MAA1_0 MAA1_[8..0] [89]
C30 DQA_8 MAA_8 J14
DQA0_9 F27 K14 MAA1_1
A28 DQA_10 MAA_10 J11
DQA0_11 C28 J13 MAA1_3
E27 DQA_12 MAA_12 H11
DQA0_13 G26 G20 MAA0_8
D26 DQA_14 MAA_14/BA0 J16
DQA0_15 F25 L15 MAA1_7
DQA0_16 DQA_15 MAA_15/BA1 MAA1_5
A25 DQA_16 MAA_BA2 G11
DQA0_17 C25 MAA1_8
DQA0_18 DQA_17
E25 DQA_18 DQMA_0 E32 W CKA0_0 [88]
DQA0_19 D24 E30
DQA_19 DQMA_1 W CKA0_0# [88]
DQA0_20 E23 A21
DQA_20 DQMA_2 W CKA0_1 [88]
DQA0_21 F23 C21
DQA_21 DQMA_3 W CKA0_1# [88]
DQA0_22 D22 E13
DQA0_23 F21 D12
DQA_23 DQMA_5 W CKA1#_0 [89]
DQA0_24 E21 E3
DQA0_25 D20 F4
DQA_25 DQMA_7 W CKA1#_1 [89]
DQA0_26 F19
DQA0_27 DQA_26
A19 DQA_27 RDQSA_0 H28 EDCA0_0 [88]
DQA0_28 D18 C27
DQA_28 RDQSA_1 EDCA0_1 [88]
DQA0_29 F17 A23
DQA0_30 A17 E19
DQA0_31 C17 E15
[89] DQA1_[31..0] DQA_31 RDQSA_4 EDCA1_0 [89]
DQA1_0 E17 D10
DQA1_1 D16 D6
DQA1_2 F15 G5
1D5V_VGA_S0 1D5V_VGA_S0 DQA_34 RDQSA_7 EDCA1_3 [89]
C DQA1_3 A15 C
DQA1_4 DQA_35
D14 DQA_36 WDQSA_0 H27 DDBIA0_0 [88]
DQA1_5 F13 A27
DQA_37 WDQSA_1 DDBIA0_1 [88]
1
DQA1_6 A13 C23

DQA_38 WDQSA_2 DDBIA0_2 [88]
SG R8410
40D2R2F-GP
R8411
40D2R2F-GP
DQA1_7
DQA1_8
C13
E11
DQA_39 WDQSA_3 C19
C15
DDBIA0_3 [88]
SG DQA1_9 A11
DQA_40 WDQSA_4
E9
DDBIA1_0
DDBIA1_1
[89]
[89]
DQA1_10 DQA_41 WDQSA_5
C11 C5 DDBIA1_2 [89]
2
MVREFDA MVREFSA DQA1_11 DQA_42 WDQSA_6

F11 DQA_43 WDQSA_7 H4 DDBIA1_3 [89]
DQA1_12 A9 DQA_44
1
C8402 C8403 DQA1_13 C9 L18

DQA_45 ODTA0 ADBIA0 [88]
R8414 SCD1U10V2KX-5GP R8415
SG
100R2F-L1-GP-U SG SCD1U10V2KX-5GP
100R2F-L1-GP-U
DQA1_14
DQA1_15
F9
D8
DQA_46 ODTA1 K16 ADBIA1 [89]
SG SG
2
DQA1_16 DQA_47
E7 DQA_48 CLKA0 H26 CLKA0 [88]
DQA1_17 A7 H25
2
DQA1_18 DQA_49 CLKA0# CLKA0# [88]

C7 DQA_50
DQA1_19 F7 G9
DQA1_20 DQA_51 CLKA1 CLKA1 [89]
A5 DQA_52 CLKA1# H9 CLKA1# [89]
DQA1_21 E5
DQA1_22 DQA_53
C3 DQA_54 RASA0# G22 RASA0# [88]
1D5V_VGA_S0 DQA1_23 E1 G17
Layout Note: DQA1_24 G7
DQA_55 RASA1# RASA1# [89]
DQA1_25 DQA_56
Place MVREF R & C close to GPU G6 DQA_57 CASA0# G19 CASA0# [88]
DQA1_26 G1 G16
DQA1_27 DQA_58 CASA1# CASA1# [89]
G3 DQA_59
R8403 1 2 240R2F-1-GP MEM_CALRN0 DQA1_28 J6 H22
R8406 1 SG 2 240R2F-1-GP MEM_CALRP0 DQA1_29 J1
DQA_60 CSA0#_0
J22
CSA0#_0 [88]
SG DQA1_30 J3
DQA_61 CSA0#_1
DQA1_31 DQA_62
J5 DQA_63 CSA1#_0 G13 CSA1#_0 [89]
B B
CSA1#_1 K13
MVREFDA K26
MVREFSA MVREFDA
J26 MVREFSA CKEA0 K20 CKEA0 [88]
J17 X01 11/28
MEM_CALRN0 J25 CKEA1 CKEA1 [89]
R8407 TESTEN MEM_CALRN0
[85] TESTEN K7 TESTEN WEA0# G25 W EA0# [88]
150R2F-1-GP H10 R8408
MEM_CALRP1/DPC_CALR WEA1# W EA1# [89] 0R2J-2-GP
1 2 J8
R8405 SG MEM_CALRP0 K25
MEM_CALRP1/DPC_CALR
AB16 PX_EN_R 1 2
51R2J-2-GP MEM_CALRP0 PX_EN DY PX_EN [86]
1
1 2 DRAM_RST_1 1 2 DRAM_RST L10
[88,89] MEM_RST SG R8402 SG DRAM_RST
X01 12/12
10R2J-2-GP TP8401 1CLKTESTA K8 G14 MAA1_8 R8412
CLKTESTA RSVD#G14 SG
1
TPAD14-OP-GP 1CLKTESTB L7 4K7R2J-2-GP

CLKTESTB SG
2
C8401 R8404
2
5K1R2F-2-GP TP8402
SG SG
SC120P50V2JN-1GP
TPAD14-OP-GP ROBSON-GP-U
1
25mm (Max) 5mm (Max) 25mm (Max)

A DMB40 A
Wistron Corporation
Layout Note:
Place all these components very close to GPU Title
(Within 25mm) and keep all component close
to each Other (within 5mm) except R_MEM_2
GPU Memory(2/5)
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
MEMORY ID Table
CONFIGURATION STRAPS RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR DVPDATA[3:0] Description
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, 1 = INSTALL 3K RESISTOR
X = DESIGN DEPENDANT
THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE 0011 GDDR5 1.25GHZ Hynix-H5GQ2H24AFR-T2C 128M*16 VGA1B 2 OF 7
PLATFORM
DESCRIPTION OF DEFAULT SETTINGS RECOMMEND 0001 GDDR5 1.25GHZ Hynix-H5GQ2H24MFR-T2C 128M*16
STRAPS PIN SETTING M93-S3/M92-S2 TXCAP_DPA3P
AF2
Transmitter Power Savings Enable AE9
DVCNTL_0/DVPDATA_18 TXCAM_DPA3N
AF4
TX_PWRS_ENB GPIO0 0: 50% Tx output swing 1: Full Tx output swing X 1 0000 GDDR5 1.25GHZ SAMSUNG-K4G20325FD-FC04 128M*16 L9
DVCNTL_1/NC#L9
N9 AG3
DVCNTL_2/TESTEN#2 TX0P_DPA2P
PCIE TRANSMITTER DE-EMPHASIS ENABLED AE8
DVDATA_12/DVPDATA_16 DPA TX0M_DPA2N
AG5
TX_DEEMPH_EN GPIO1 0:Tx de-emphasis disabled 1:Tx de-emphasis enabled X 1 DVPDATA[0:3] Default:Pull down AD9
DVDATA_11/DVPDATA_20
AC10 AH3
DVDATA_10/DVPDATA_22 TX1P_DPA1P
0:Advertises the PCIe device as 2.5GT/s capable at power on. AD7
DVDATA_9/DVPDATA_12 TX1M_DPA1N
AH1
BIF_GEN2_EN_A GPIO2 1:Advertises the PCIe device as 5.0GT/s capable at power on. 0 0 AC8
DVDATA_8/DVPDATA_14
AC7 AK3
DVDATA_7/DVPCNTL_0 TX2P_DPA0P
optional input allow the system to request a fast AB9 AK1
1D8V_VGA_S0 DVDATA_6/DVPDATA_8 TX2M_DPA0N
GPIO5_AC_BATT GPIO5 ? 0 AB8
power reduction by setting GPIO5 to low. DVDATA_5/DVPDATA_6
X01 12/02 AB7
DVDATA_4DVPDATA_4 TXCBP_DPB3P
AK5
AB4 AM3 3D3V_VGA_S0
D DVDATA_3/DVPDATA_19 TXCBM_DPB3N D
GPIO8_ROMSO GPIO8 RESERVED 0 0 AB2
R8519 HYNIX_RTS
1 2 10KR2J-3-GP MEM_ID1 Y8
DVDATA_2/DVPDATA_21
AK6
R8518 10KR2J-3-GP MEM_ID0 DVDATA_1/DVPDATA_2 TX3P_DPB2P
0:VGA Controller capacity enabled 1
HYNIX 2 Y7
DVDATA_0/DVPDATA_0 TX3M_DPB2N
AM5
VGA_DIS GPIO9 1:The device won't be recognized as the system's VGA controller 0 0 DPB
AJ7
TX4P_DPB1P
4
3
BIOS_ROM_EN=1, Config[2:0] defines the ROM type 0 0 1 DVO AH6
BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size X X X TX4M_DPB1N RN8504
ROMIDCFG[2:0] GPIO[13:11] (256MB) AK8 SRN4K7J-8-GP
1D8V_VGA_S0 TX5P_DPB0P
AL7
GPIO21_BB_EN GPIO21 RESERVED 0 0
TX5M_DPB0N SG
M93-S3/M92-S2
1
2
Q8503
0:Disable external BIOS ROM device W6
DPC_PVDD/DVPDATA_11
X GPIO_VGA_04_CLK
BIOS_ROM_EN GPIO_22_ROMCSB 1:Enable external BIOS ROM device 0 V6
DPC_PVSS/GND M92-S2/M93-S3 1 6 SML1_CLK [20,27,28]
V4
1V_VGA_S0 DVPDATA_3/TXCCP_DPC3P
VIP Device Strap Enable indicates to the software driver that it sense AC6
DPC_VDD18#1/DVPDAT10 DVPCNTL_2/TXCCM_DPC3N
U5 2 5
VIP_DEVICE_STRAP_EN V2SYNC X 0 AC5
whether or not a VIP device is connected on the VIP Host interface. DPC_VDD18#2/DVPDAT23
W3 3
SG 4
L8507 330mA AA5
DPC_VDD10#1/DVPDAT15
DVPDATA_7/TX0P_DPC2P
DVPDATA_1/TX0M_DPC2N
V2
1 2 DPC_VDD10 AA6
RSVD H2SYNC RESERVED 0 0 SG DPC_VDD10#2/DVPDAT17 2N7002KDW-GP
Y4 SML1_DATA [20,27,28]
BLM15BD121SS1D-GP DVPCNTL_MV1/TX1P_DPC1P
W5
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
DVPDATA_9/TX1M_DPC1N
C8527
C8528
68.00084.F81 3D3V_VGA_S0 GPIO_VGA_03_DATA
RSVD GENERICC RESERVED 0 0
1
2ND = 68.00217.701 U1
DPC_VSSR#1/DVPCLK DVPDATA_13/TX2P_DPC0P
AA3
DY DY W1
DPC_VSSR#2/DVPDAT5 DVPCNTL_1/TX2M_DPC0N
Y2 84.2N702.A3F
AUD[1] HSYNC X 1 U3 2nd = 84.DM601.03F
2
DPC_VSSR#3/GND
AUD[1:0]:11-Audio for both DisplayPort and HDMI Y6 AA12
DPC_VSSR#4/GND NC#AA12 3rd = 84.2N702.E3F
AA1
DPC_VSSR#5/DVPCNTL_MV0
4
3
AUD[0] VSYNC X 1 4th = 84.2N702.F3F
RN8505 X03 2/6
SRN4K7J-8-GP DPC
DY AVDD_A2VDDQ 1D8V_VGA_S0
Straps Pin R8504 70mA
1
2
BACO_SCL R1 1 2
BACO_SDA SCL 0R0603-PAD-2-GP
R3
SDA I2C
1
3D3V_VGA_S0 C8542 C8543
SCD1U10V2KX-5GP
AM26 C8536
GENERAL PURPOSE I/O R
AK26
VGA_R [82]
SC10U6D3V3MX-GP DY SC1U6D3V2KX-GP
DY DY
2
TX_PWRS_ENB R#
U6
3KR2J-2-GP R8537 TX_PWRS_ENB TX_DEEMPH_EN GPIO_0
2 1 U10 AL25
SG BIF_GEN2_EN_A T10
GPIO_1 G
AJ25
VGA_G [82]
AVSSQ
3KR2J-2-GP R8541 TX_DEEMPH_EN GPIO_VGA_03_DATA GPIO_2 G#
2 1 U8
SG GPIO_VGA_04_CLK U7
GPIO_3_SMBDATA
AH24 VGA_B [82] VDD1DI
10KR2J-3-GP R8535 BIF_GEN2_EN_A GPIO5_AC_BATT GPIO_4_SMBCLK B R8506
2 1 T9 AG25
SG TPAD14-OP-GP TP8501 1 GPIO6_VGA T8
GPIO_5_AC_BATT
DAC1
B#
1 2 45mA
GPIO_6
A00 3/15 1R8523 2 VGA_BLEN T7 AH26 0R0603-PAD-2-GP
SG GPIO_7_BLON HSYNC VGA_CRT_HSYNC [82]
1
TPAD14-OP-GP TP8502 1 10KR2J-3-GPGPIO_8_ROMSO P10 AJ27 C8502 C8544 C8545
SC1U6D3V2KX-GP
GPIO_8_ROMSO VSYNC VGA_CRT_VSYNC [82]
10KR2J-3-GP 2 1 R8533 VGA_DIS VGA_DIS P4 SC10U6D3V3MX-GP SCD1U10V2KX-5GP
DY TPAD14-OP-GP TP8503 1 GPIO_10_ROMSCK P2
GPIO_9_ROMSI DY DY
DY
2
CONFIG0 GPIO_10_ROMSCK GPU_RSET
N6 AD22 1 2
10KR2J-3-GP R8534 CONFIG0 CONFIG1 GPIO_11 RSET R8539 499R2F-2-GP
2 1 N5
SG CONFIG2 N3
GPIO_12
AG24 AVDD_A2VDDQ
SG
10KR2J-3-GP R8538 CONFIG1 GPIO_13 AVDD
2 1 Y9 AE22
DY [92] PWRCNTL_0 PWRCNTL_0 N1
GPIO_14_HPD2 AVSSQ
10KR2J-3-GP R8520 CONFIG2 TPAD14-OP-GP TP8504 GPIO16_SSIN GPIO_15_PWRCNTL_0
2 1 1 M4 AE23
DY GPIO17_VGA R6
GPIO_16_SSIN VDD1DI
AD23
VDD1DI
AVSSQ
TPAD14-OP-GP TP8505 GPIO18_VGA GPIO_17_THERMAL_INT VSS1DI
1 W10
10KR2J-3-GP GPIO_18_HPD3
2 1 R8503 GPIO17_VGA THERMTRIP_VGA M2 M92-S2/M93-S3 X03 2/6
C SG [92] PWRCNTL_1 PWRCNTL_1 P8
GPIO_19_CTF
AM12 C
GPIO_20_PWRCNTL_1 R2/NC#AM12 AVSSQ R8507
P7 AK12
10KR2J-3-GP GPIO_21_BB_EN R2#/NC#AK12
2 1 R8530 GPIO5_AC_BATT N8 1 2
DY [20] PEG_CLKREQ# PEG_CLKREQ# N7
GPIO_22_ROMCSB
AL11 0R0402-PAD-2-GP
GPIO_23_CLKREQB G2/NC#AL11
AJ11
10KR2J-3-GP 2
DY 1 R8540 VGA_CRT_VSYNC G2#/NC#AJ11 LVDS Interface
AK10 AVSSQ
10KR2J-3-GP B2/NC#AK10
2 1 R8542 VGA_CRT_HSYNC JTAG_TRST#_VGA L6 AL9
DY JTAG_TDI_VGA L5
JTAG_TRST# B2#/NC#AL9 VGA1F 6 OF 7
JTAG_TCK_VGA JTAG_TDI
L3
1D8V_VGA_S0 JTAG_TMS_VGA JTAG_TCK RN8502
L1 AH12
JTAG_TDO_VGA JTAG_TMS C/NC#AH12 SRN10KJ-5-GP
K4
JTAG_TDO DAC2 Y/NC#AM10
AM10
LVDS CONTROL
3KR2J-2-GP 2 1 R8545 PWRCNTL_0 TPAD14-OP-GP TP8506 1 RSVD AF24 AJ9 AB11 VARY_BL 1 4
SG RSVD#AF24 COMP/NC#AJ9 VARY_BL
AB12 DIGON 2 3
3KR2J-2-GP 2 1 R8544 PWRCNTL_1 TPAD14-OP-GP TP8507 1 GEN_A AB13
DIGON SG
SG TPAD14-OP-GP TP8508 1 GEN_B W8
GENERICA
AL13
GENERICB H2SYNC
W9 AJ13
GENERICC V2SYNC
W7
GENERICD
1
TP8509 1 GENERICE_HPD4
AD10 AH20
TPAD14-OP-GP GENERICE_HPD4 TXCLK_UP_DPF3P
R8515 AD19 AJ19
VDD2DI/NC#AD19 TXCLK_UN_DPF3N
SG 499R2F-2-GP TP8510
TPAD14-OP-GP
1HDMI_HPD_DET AC14
HPD1 VSS2DI/NC#AC19
AC19
AL21
1D8V_VGA_S0 DPLL_PVDD TXOUT_U0P_DPF2P
AK20
2
GPU_VREFG TXOUT_U0N_DPF2N
AE20
L8508 A2VDD/NC#AE20
AH22
TXOUT_U1P_DPF1P
1
1 2 AE17 A00 3/15 AJ21

SG A2VDDQ/NC#AE17 TXOUT_U1N_DPF1N
1
R8516 C8514 AC16

VREFG
1
BLM18PG471SN1D-GP C8515 C8516 249R2F-GP SCD1U10V2KX-5GP AE19 AL23

SG SG
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
A2VSSQ TXOUT_U2P_DPF0P
1
68.00143.181 C8505 AK22

DY
2
SC10U6D3V3MX-GP R8501 TXOUT_U2N_DPF0N

2nd = 68.00214.211 DY DY
2
AG13 R2SET 1 2 AK24

DY
2
R2SET/NC#AG13 TXOUT_U3P
AJ23
715R2F-GP TXOUT_U3N
M92-S2/M93-S3 M92-S2/M93-S3
AE6 LVTMDP
DDC1CLK VGA_CRT_DDCCLK [82]
PLL/CLOCK AE5
75mA AF14
DPLL_PVDD
DDC1DATA VGA_CRT_DDCDATA [82]
TXCLK_LP_DPE3P
AL15
AE14 AD2 AK14
1V_VGA_S0 DPLL_VDDC DPLL_PVSS AUX1P TXCLK_LN_DPE3N
AD4
L8512 DDC/AUX AUX1N
AH16
1
SG 2 125mA AD14
DPLL_VDDC DDC2CLK
AC11
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
AJ15
AC13
3D3V_VGA_S0 BLM18PG471SN1D-GP DDC2DATA
AL17
TXOUT_L1P_DPE1P
1
68.00143.181 C8518 C8519 R8525 XTALIN_R AM28 AD13 AK16

C8508 XTALIN_R XTALOUT_R XTALIN AUX2P TXOUT_L1N_DPE1N
2nd = 68.00214.211 DY DY DY 1
DY 2 AK28 AD11
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC10U6D3V3MX-GP 0R2J-2-GP XTALOUT AUX2N

AH18
2
R8508 1 TXOUT_L2P_DPE0P
2 10KR2J-3-GP JTAG_TDI_VGA AE16 AJ17
DY DDCCLK_AUX5P
AD16
TXOUT_L2N_DPE0N
R8517 1 DDCDATA_AUX5N
2 0R2J-2-GP XO_IN AC22 AL19
R8509 1 2 10KR2J-3-GP JTAG_TRST#_VGA R8526 1 DY 2 0R2J-2-GP XO_IN2 AB22
NC#AC22/XO_IN
AC1
TXOUT_L3P
AK18
DY DY NC#AB22/XO_IN2 DDC6CLK
AC3
SG TXOUT_L3N
DDC6DATA
[28] P2800_VGA_DXP X01 12/02
R8512 1 2 10KR2J-3-GP JTAG_TMS_VGA AD20
DY NC#AD20/DDCCLK_AUX3P
1
AC20
C8523 THERMAL NC#AC20/DDCDATA_AUX3N ROBSON-GP-U
R8513 1 2 10KR2J-3-GP TESTEN SC2200P50V2KX-2GP DY P2800_VGA_DXP T4
DY TESTEN [84]
2
P2800_VGA_DXN DPLUS
[28] P2800_VGA_DXN T2
1D8V_VGA_S0 DMINUS
B TSVDD B
L8509
R8543 1 2 5K11R2F-L1-GP TP8511 1 FAN_PWM_C R5
SG 1 2 5mA TPAD14-OP-GP AD17
TS_FDO
SG AC17
TSVDD SG
R8514 1 TSVSS
2 10KR2J-3-GP JTAG_TCK_VGA BLM15BD121SS1D-GP
DY
1
C8521 C8522 ROBSON-GP-U

68.00084.F81
2ND = 68.00217.701 C8509 SC1U6D3V2KX-GP SCD1U10V2KX-5GP
R8524 1 2 10KR2J-3-GP JTAG_TDO_VGA SC10U6D3V3MX-GP DY SG SG
DY
2
THERMTRIP_R
X8501
THERMTRIP_VGA
1
1 4
82.30034.651 R8522
2nd = 82.30034.681 10KR2J-3-GP
SG
2 3
2
6
SG Q8501
XTAL-27MHZ-84-GP
2N7002KDW-GP
DY
84.2N702.A3F
1
XTAL_X1 1 XTAL_X2 2nd = 84.DM601.03F

DY2
R8511
1MR2F-GP
2
SGC8524 C8525 R8521

PURE_HW_SHUTDOWN# [27,28,36]
SG 2 1 Q5801_2
SC18P50V2JN-1-GP SC18P50V2JN-1-GP [83] VGA_RST# DY
1
0R2J-2-GP C8529
DY SCD1U10V2KX-4GP
2
X01 11/28
3D3V_VGA_S0
1 2 XTALIN_R 1.8V
L8501 DY
2
1 2 R8529
SG 124R2F-U-GP R8527
DY
2
BLM18BD601SN1D-GP 150R2F-1-GP
C8533
68.00082.531
2nd = 68.00226.031
DY SG C8532 DY C8534 SG C8535
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
1
3rd = 68.00040.111
A U8506 A
X01 11/28 3D3V_S0_U8606 4 9 CLK_27R 1 2 XO_IN 3.3V

8
VDD_100M 27M R8502 SG 47R2J-2-GP
VDD_27M CLK_100R XO_IN2
5 1 2 3.3V
3D3V_VGA_S0 100M R8510 SG 33R2J-2-GP
XTAL_X1 1
XTAL_X2 10
XIN SG
XOUT
2
SS_SEL0 GND_27M
1 2 7 6
R8531 1 DY 2 10KR2J-3-GP SS_SEL1 3
SS_SEL0 GND_100M
11
R8532 DY 10KR2J-3-GP SS_SEL1 GND
1
R8528 R8536 6V40088DNBGI8-GP

10KR2J-3-GP 10KR2J-3-GP SG 71.64088.003
SG 2nd = 71.16020.003
DMB40
2
Wistron Corporation
Title
GPU_DP/LVDS/CRT/GPIO(3/5)
A1
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
VGA1D 4 OF 7 1D8V_VGA_S0
1D5V_VGA_S0
MEM I/O
1.2A PCIE 440mA
H13 AB23
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VDDR1 PCIE_VDDR
C8614
C8613
C8617
C8615
C8616
H16 AC23
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1
VDDR1 PCIE_VDDR
C8606
C8607
C8608
C8609
C8610
C8643
H19 AD24
DY
SC10U6D3V3MX-GP
1
1
VDDR1 PCIE_VDDR
J10 AE24
SG J23
VDDR1 PCIE_VDDR
AE25
SG DY SG SG SG
SG SG SG
2
VDDR1 PCIE_VDDR
J24 AE26
D
DY D
2
VDDR1 PCIE_VDDR
J9 AF25
VDDR1 PCIE_VDDR 1V_VGA_S0
K10 AG26
VDDR1 PCIE_VDDR
K23
K24
VDDR1
VDDR1
1.1A
K9 L23
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VDDR1 PCIE_VDDC
C8628
C8629
C8630
C8631
C8632
C8633
C8602
L11 L24
1
VDDR1 PCIE_VDDC
C8623
C8624
C8625
C8663
L12 L25
SG SG SG DY SG
SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1
1
VDDR1 PCIE_VDDC
C8621
C8648
C8644
L13 L26
SG SG
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
VDDR1 PCIE_VDDC
L20 M22
DY DY DY DY
2
VDDR1 PCIE_VDDC
L21 N22
DY DY DY
2
2
VDDR1 PCIE_VDDC
L22 N23
VDDR1 PCIE_VDDC
N24
PCIE_VDDC
R22
PCIE_VDDC
T22
1D8V_VGA_S0 VDDC_CT LEVEL PCIE_VDDC
U22
TRANSLATION PCIE_VDDC
V22
PCIE_VDDC VGA_CORE
AA20
AA21
VDD_CT 22A
L8601 17mA AB20
VDD_CT
VDD_CT VDDC
AA15
1 2 AB21 CORE N15
SG VDD_CT VDDC
C8681
C8678
C8652
C8653
N17
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1
1
VDDC
C8626
C8639
C8634
C8637
C8636
C8638
C8603
C8604
BLM15BD121SS1D-GP M93-S3/M92-S2 R13
DY
SC10U6D3V3MX-GP
POWER
1
VDDC
68.00084.F81 SG SG SG VDDC
R16
SG
2ND = 68.00217.701 DY DY AA17 R18
SG SG SG SG SG
2
2
VDDR3 VDDC
AA18 I/O Y21
2
3D3V_VGA_S0 VDDR3 VDDC
AB17 T12
VDDR3 VDDC
AB18 T15
VDDR3 VDDC
T17
60mA V12
VDDR4/VDDR5
VDDC
VDDC
T20
C8668
C8667
Y12 U13
SC1U6D3V2KX-GP
1
1
VDDR4 VDDC
C8618
U12 U16
SC10U6D3V3MX-GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VDDR4/VDDR5 VDDC
C8662
C8647
C8642
C8650
U18
DY DY
SC4D7U6D3V3KX-GP
1
1
VDDC
C8645
C8661
C8654
C8651
AA11 V21
DY DY
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
2
2
NC#AA11/VDDR4 VDDC
Y11 V15
DVCLK/VDDR4 VDDC
V17 DY DY DY DY SG
SG SG
2
VDDR4 VDDC
V11 V20
NC#V11/VDDR5 VDDC
L8602 U11 Y13
NC#U11 VDDC BIF_VDDC
Y16
1
SG 2 170mA VDDC
VDDC
Y18
R21
C BLM15BD121SS1D-GP C8674 VDDC/BIF_VDDC
U21 55mA C
1
MEM CLK VDDC/BIF_VDDC

68.00084.F81
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
C8641
C8640
2ND = 68.00217.701 MPV18 L17
150mA SG
1
L8603 VDDRHA
2
1 2 L16 ISOLATED
SG VSSRHA CORE I/O SG SG
C8622
C8619
C8691
C8690
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
1
1
C8620
BLM18PG471SN1D-GP MPV18 M13

SC10U6D3V3MX-GP
PLL VDDCI
68.00143.181 DY SG SG VDDCI
M15
2nd = 68.00214.211 DY DY AM30 M16
2
MPV18 PCIE_PVDD VDDCI

M17
VDDCI
M18
VDDCI VGA_CORE
L8 M20
SPV18 MPV18 VDDCI
VDDCI
M21 3.9A
N20
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VDDCI
C8659
C8660
C8658
1V_VGA_S0 H7
SC4D7U25V5KX-GP
SPV18
C8664
L8605
100mA
1
1 2 SPV10 H8 C8655 C8656 C8657
SG SPV10
SG SG
SG SG DY SG
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C8646
C8649
BLM18PG471SN1D-GP J7
DY
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
2
1
SPVSS
C8612
68.00143.181
SC10U6D3V3MX-GP
2nd = 68.00214.211 DY DY
DY
2
BACK BIAS
SPV18 M11
L8604
50mA M12
BBP#1
BBP#2
1 2
SG SG
C8692
C8694
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
1
1
C8611
BLM15BD121SS1D-GP
SC10U6D3V3MX-GP
ROBSON-GP-U
68.00084.F81 DY DY DY
2ND = 68.00217.701
2
VGA_CORE 2N7002K-2-GP
[84] PX_EN G
A00 3/27
D 8209A_EN/DEM_VGA [92,93]
BIF_VDDC VGA_CORE
R8612 S
0R0402-PAD-2-GP DY
1 2 Q8601
84.2N702.J31
B 2ND = 84.2N702.031 B
X01 12/15
X01 11/28 X01 11/28
BIF_VDDC U8601 U8603 VGA_CORE BIF_VDDC U8602 U8604 1V_VGA_S0

AO3400A-GP AO3400A-GP AO3418-GP AO3418-GP
S D BIF_VDDC_CORE D S S D BIF_VDDC_1V D S
DY 84.03400.B37 DY 84.03400.B37 3D3V_VGA_S0 DY DY
3D3V_VGA_S0 2nd = 84.03203.031 2nd = 84.03203.031 84.03418.031 84.03418.031
G
2nd = 84.P8503.031 2nd = 84.P8503.031

1
R8603 R8604
DY 1KR2J-1-GP
DY 1KR2J-1-GP
2
PX_EN_VDDC PX_EN_1V
X01 12/15
X01 11/28 X01 12/15
X01 11/28
Q8602
R8601 4 3
0R2J-2-GP
1 2 Q6802_5 5 2 PX_EN_1V
[22,27,92,93] DGPU_PWROK DY
PX_EN_VDDC 6 1
A DY A
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
<Core Design>
PX4.0
PX4.0 PX5.0 Wistron Corporation
Mode PX_EN PX_EN_1V PX_EN_VDDC BIF_VDDC Taipei Hsien 221, Taiwan, R.O.C.
POP Q8601, Q8602, R8601, U8601, U8602, U8603 POP R8612
U8604, R8603, R8604, R8408 Title
DIS Low Low High VGA_CORE
Q8601, Q8602, R8601, U8601, U8602, U8603 GPU_POWER(4/5)
DY U8604, R8603, R8604, R8605, R8408 Size Document Number Rev
BACO High High Low 1V_VGA_S0 DY R8612 A2
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
For Video output port power rail.
1D8V_VGA_S0
1D8V_VGA_S0 DPEF_VDD18 DPAB_VDD18
VGA1G 7 OF 7 330mA L8703
L8701 1 2
1 2 DP E/F POWER DP A/B POWER SG
SG
SCD1U10V2KX-5GP
1
1
C8714
C8712
C8734 BLM15BD121SS1D-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
D D
1
C8718
C8719
BLM18PG471SN1D-GP C8731 AG15 AE11 68.00084.F81
DY DY DY
SC10U6D3V3MX-GP
SC1U6D3V2KX-GP
DPE_VDD18 DPA_VDD18
68.00143.181 DY DY DY AG16 AF11 2ND = 68.00217.701
SC10U6D3V3MX-GP
2
DPE_VDD18 DPA_VDD18
2nd = 68.00214.211
2
DPEF_VDD10 DPAB_VDD10
1V_VGA_S0 AG20 AF6 1V_VGA_S0

DPE_VDD10 DPA_VDD10
AG21 AF7
L8702 DPE_VDD10 DPA_VDD10 330mA L8704
VGA1E 5 OF 7 1 2 1 2
SG AG14 AE1
SG
SCD1U10V2KX-5GP
DPE_VSSR DPA_VSSR
1
C8720
C8725
C8702
C8703
BLM15BD121SS1D-GP C8726 AH14 AE3 C8732 BLM15BD121SS1D-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
DPE_VSSR DPA_VSSR
68.00084.F81 DY DY DY AM14 AG1
DY DY DY 68.00084.F81
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
DPE_VSSR DPA_VSSR
AA27 A3 2ND = 68.00217.701 AM16 AG6 2ND = 68.00217.701
2
PCIE_VSS GND DPE_VSSR DPA_VSSR
AB24 PCIE_VSS GND A30 AM18 DPE_VSSR DPA_VSSR AH5
AB32 PCIE_VSS GND/EVDDQ AA13
AC24 AA16 DPEF_VDD18 DPAB_VDD18
PCIE_VSS GND
AC26 PCIE_VSS GND AB10
AC27 AB15 AF16 AE13
AD25
PCIE_VSS
PCIE_VSS
GND/EVDDQ
GND AB6 AG17
DPF_VDD18
DPF_VDD18
DPB_VDD18
DPB_VDD18 AF13 330mA
AD32 PCIE_VSS GND AC9
AE27 AD6 DPEF_VDD10 DPAB_VDD10
PCIE_VSS GND
AF32 PCIE_VSS GND AD8
AG27 AE7 AF22 AF8
AH32
PCIE_VSS
PCIE_VSS
GND
GND AG12 AG22
DPF_VDD10
DPF_VDD10
DPB_VDD10
DPB_VDD10 AF9 330mA
K28 PCIE_VSS GND AH10
K32 PCIE_VSS GND AH28
L27 PCIE_VSS GND B10 AF23 DPF_VSSR DPB_VSSR AF10
M32 PCIE_VSS GND B12 AG23 DPF_VSSR DPB_VSSR AG9
C N25 B14 AM20 AH8 C
PCIE_VSS GND DPF_VSSR DPB_VSSR
N27 PCIE_VSS GND B16 AM22 DPF_VSSR DPB_VSSR AM6
P25 PCIE_VSS GND B18 AM24 DPF_VSSR DPB_VSSR AM8
P32 PCIE_VSS GND B20
R27 PCIE_VSS GND B22
T25 PCIE_VSS GND B24
T32 B26
U25
PCIE_VSS GND
B6 1 2 DPCD_CALR AF17 AE10 DPAB_CALR 1 SG 2
U27
PCIE_VSS GND
B8
SG DPEF_CALR DPAB_CALR
PCIE_VSS GND R8701 DPEF_VDD18 DPAB_VDD18 R8703
V32 PCIE_VSS GND C1
W25 C32 150R2F-1-GP 150R2F-1-GP
PCIE_VSS GND DP PLL POWER
W26 PCIE_VSS GND E28 AG18 DPE_PVDD DPA_PVDD AG8
W27 PCIE_VSS GND F10 AF19 DPE_PVSS DPA_PVSS AG7
Y25 F12 DPEF_VDD18 DPAB_VDD18
PCIE_VSS GND
Y32 PCIE_VSS GND F14
GND F16
F18 AG19 AG10
GND
F2 AF20
DPF_PVDD SG DPB_PVDD
AG11
GND DPF_PVSS DPB_PVSS
GND F20
M6 GND GND F22
N11 GND GND F24
N12 F26 ROBSON-GP-U
GND GND
N13 GND GND F6
N16 F8
N18
N21
GND
GND
GND
GND GND
GND
GND
G10
G27
P6 GND GND G31
P9 GND GND G8
R12 GND GND H14
B B
R15 GND GND H17
R17 GND GND H2
R20 GND GND H20
T13 GND GND H6
T16 GND GND J27
T18 GND GND J31
T21 GND GND K11
T6 GND GND K2
U15 GND GND K22
U17 GND GND K6
U20 GND GND T11
U9 GND GND R11
V13 GND
V16 GND
V18 GND
Y10 GND
Y15 GND
Y17 GND VSS_MECH A32 VSS_MECH1 1 TP8701 TPAD14-OP-GP
Y20 GND VSS_MECH AM1 VSS_MECH2 1 TP8702 TPAD14-OP-GP
AM32 VSS_MECH3 1 TP8703 TPAD14-OP-GP
SG VSS_MECH
ROBSON-GP-U
DMB40
A A
Wistron Corporation
Title
GPU_DPPWR/GND(5/5)
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
1D5V_VGA_S0 VRAM2A 1 OF 2
SSID = VIDEO 1D5V_VGA_S0 VRAM1A 1 OF 2 C5
VDD VSS
B5
C10 B10
VDD VSS
C5 B5 D11 D10
VDD VSS VDD VSS
C10 B10 G1 G5
VDD VSS VDD VSS
D11 D10 G4 G10
VDD VSS VDD VSS
G1 G5 G11 H1
VDD VSS VDD VSS
G4 G10 G14 H14
VDD VSS VDD VSS
G11 H1 L1 K1
VDD VSS VDD VSS
G14 H14 L4 K14
VDD VSS VDD VSS
L1 K1 L11 L5
VDD VSS VDD VSS
L4 K14 L14 L10
VDD VSS VDD VSS
L11 L5 P11 P10
VDD VSS VDD VSS
L14 L10 R5 T5
VDD VSS 1D5V_VGA_S0 VDD VSS
P11 P10 R10 T10
VDD VSS VDD VSS
R5 T5
1D5V_VGA_S0 VDD VSS
R10 T10 B1 A1
VDD VSS VDDQ VSSQ
B3 A3
VDDQ VSSQ
D B1 A1 B12 A12 D
VDDQ VSSQ VDDQ VSSQ
B3 A3 B14 A14
VDDQ VSSQ VDDQ VSSQ
B12 A12 D1 C1
VDDQ VSSQ VDDQ VSSQ
B14 A14 D3 C3
VDDQ VSSQ VDDQ VSSQ
D1 C1 D12 C4
VDDQ VSSQ VDDQ VSSQ
D3 C3 D14 C11
VDDQ VSSQ VDDQ VSSQ
D12 C4 E5 C12
VDDQ VSSQ VDDQ VSSQ 1D5V_VGA_S0 1D5V_VGA_S0 1D5V_VGA_S0
D14 C11 E10 C14
VDDQ VSSQ VDDQ VSSQ
E5 C12 F1 E1
VDDQ VSSQ VDDQ VSSQ
E10 C14 F3 E3
VDDQ VSSQ VDDQ VSSQ
F1 E1 F12 E12
VDDQ VSSQ VDDQ VSSQ
F3 E3 F14 E14
2
VDDQ VSSQ VDDQ VSSQ
F12 E12 G2 F5
VDDQ VSSQ VDDQ VSSQ R8823
F14
G2
VDDQ VSSQ
E14
F5
G13
H3
VDDQ VSSQ
F10
H2 SGC8862 R8824
SGC8863 R8829
SGC8864
2K37R2F-GP
SG SC1U6D3V2KX-GP 2K37R2F-GP
SG SC1U6D3V2KX-GP
1
VDDQ VSSQ VDDQ VSSQ
G13 F10 H12 H13
VDDQ VSSQ VDDQ VSSQ
H3 H2 K3 K2
1
VDDQ VSSQ VDDQ VSSQ
H12 H13 K12 K13
VDDQ VSSQ VDDQ VSSQ VREFC_A0 VREFD1_A0 VREFD2_A0
K3 K2 L2 M5
VDDQ VSSQ VDDQ VSSQ
K12 K13 L13 M10
VDDQ VSSQ VDDQ VSSQ
L2 M5 M1 N1
2
VDDQ VSSQ VDDQ VSSQ
L13 M10 M3 N3
VDDQ VSSQ VDDQ VSSQ R8822 C8865 R8825 C8866 R8832 C8867
M1 N1 M12 N12
M3
VDDQ VSSQ
N3 M14
VDDQ VSSQ
N14 5K49R2F-GP
SG SG SC1U6D3V2KX-GP 5K49R2F-GP
SG SG SC1U6D3V2KX-GP
1
VDDQ VSSQ VDDQ VSSQ
M12 N12 N5 R1
VDDQ VSSQ VDDQ VSSQ
M14 N14 N10 R3
1
VDDQ VSSQ VDDQ VSSQ
N5 R1 P1 R4
VDDQ VSSQ VDDQ VSSQ
N10 R3 P3 R11
VDDQ VSSQ VDDQ VSSQ
P1 R4 P12 R12
VDDQ VSSQ VDDQ VSSQ
P3 R11 P14 R14
VDDQ VSSQ VDDQ VSSQ
P12 R12 T1 U1
VDDQ VSSQ VDDQ VSSQ
P14 R14 T3 U3
VDDQ VSSQ VDDQ VSSQ
T1 U1 T12 U12
VDDQ VSSQ VDDQ VSSQ
T3 U3 T14 U14
VDDQ VSSQ VDDQ VSSQ
T12 U12
VDDQ VSSQ VREFC_A1
T14 U14 J14 A5
VDDQ VSSQ VREFC VPP/NC#A5
U5
VREFC_A0 VREFD1_A1 VPP/NC#U5
J14 A5 A10
VREFC VPP/NC#A5 VREFD2_A1 VREFD
U5 U10
VREFD1_A0 A10
VPP/NC#U5 VREFD SG
VREFD2_A0 VREFD
U10
C
VREFD SG H5GQ1H24AFR-T2L-GP C
H5GQ1H24AFR-T2L-GP DQA0_[31..0] [84]

[84] MAA0_[8..0] VRAM2B 2 OF 2
[84] MAA0_[8..0] DQA0_[31..0] [84]
VRAM1B 2 OF 2 MAA0_0 K4 A4 DQA0_12
MAA0_6 A8/A7 DQ0 DQA0_13
H5 A2
MAA0_7 DQA0_22 MAA0_7 A9/A1 DQ1 DQA0_8
K4 A4 H4 B4
MAA0_1 A8/A7 DQ0 DQA0_20 MAA0_1 A10/A0 DQ2 DQA0_9
H5 A2 K5 B2
H4 B4 J5 E4
MAA0_6 A10/A0 DQ2 DQA0_21 A12/RFU#J5/NC#J5 DQ4 DQA0_11 1D5V_VGA_S0 1D5V_VGA_S0 1D5V_VGA_S0
K5 B2 E2
MAA0_8 A11/A6 DQ3 DQA0_19 MAA0_4 DQ5 DQA0_15
J5 E4 H11 F4
A12/RFU#J5/NC#J5 DQ4 DQA0_17 MAA0_3 BA0/A2 DQ6 DQA0_14
E2 K10 F2
MAA0_2 DQ5 DQA0_16 MAA0_2 BA1/A5 DQ7
H11 F4 K11 A11
1D5V_VGA_S0 MAA0_5 BA0/A2 DQ6 DQA0_18 MAA0_5 BA2/A4 DQ8
K10 F2 H10 A13
2
MAA0_4 BA1/A5 DQ7 BA3/A3 DQ9
K11 A11 B11
MAA0_3 BA2/A4 DQ8 DQ10 R8833
H10
BA3/A3 DQ9
A13
B11
[84] ADBIA0 J4
G3
ABI# DQ11
B13
E11
SGC8868 R8835
SGC8870 R8837
SGC8872
2K37R2F-GP
SG SC1U6D3V2KX-GP
1
DQ10 [84] CASA0# RAS# DQ12
[84] ADBIA0 J4 B13 [84] WEA0# G12 E13
1
ABI# DQ11 CS# DQ13

G3 E11 L3 F11
1
[84] RASA0# RAS# DQ12 [84] RASA0# CAS# DQ14
R8809 R8810 G12 E13 L12 F13
[84]
120R2F-GP CSA0#_0 CS# DQ13 [84] CSA0#_0 WE# DQ15
120R2F-GP L3 F11 U11 DQA0_29 VREFC_A1 VREFD1_A1 VREFD2_A1
SG SG [84] CASA0#
L12
CAS# DQ14
F13 J12
DQ16
U13 DQA0_31
[84] WEA0# WE# DQ15 [84] CLKA0 CK DQ17
U11 DQA0_0 J11 T11 DQA0_26
[84] CLKA0#
2
2
DQ16 DQA0_3 CK# DQ18 DQA0_30
[84] CLKA0 J12 U13 [84] CKEA0 J3 T13
CK DQ17 DQA0_1 CKE# DQ19 DQA0_27 R8834 C8869 R8836 C8871 R8838 C8873
J11 T11 N11
[84] CLKA0#
J3
CK# DQ18
T13 DQA0_2 D2
DQ20
N13 DQA0_28 5K49R2F-GP
1
[84] CKEA0 CKE# DQ19 [84] DDBIA0_1 DBI0# DQ21
N11 DQA0_6 D13 M11 DQA0_24
DQ20 1D5V_VGA_S0 DBI1# DQ22
D2 N13 DQA0_4 P13 M13 DQA0_25
[84] DDBIA0_2 [84] DDBIA0_3
1
DBI0# DQ21 DQA0_7 DBI2# DQ23
1D5V_VGA_S0 D13 M11 1D5V_VGA_S0 P2 U4
[84] DDBIA0_0 P13 M13 U2
DBI2# DQ23 DQ25
1D5V_VGA_S0 P2 U4 [84,89] MEM_RST J2 T4
DBI3# DQ24 RESET# DQ26
U2 T2
DQ25 DQ27
[84,89] MEM_RST J2 T4 J10 N4
RESET# DQ26 VRAM2_ZQ SEN DQ28
T2 J13 N2
DQ27 ZQ DQ29
J10 N4 1D5V_VGA_S0 J1 M4
VRAM1_ZQ SEN DQ28 MF DQ30
J13
ZQ DQ29
N2 MF=1 DQ31
M2
J1 M4 Mirror [84] WCKA0_0 D4
MF DQ30 WCK1
M2 [84] WCKA0_0# D5 C2 EDCA0_1 [84]
DQ31 WCK1# EDC0
[84] WCKA0_1 D4 C13
WCK1 EDC1
[84] WCKA0_1# D5 C2 EDCA0_2 [84] [84] WCKA0_1 P4 R13 EDCA0_3 [84]
B WCK1# EDC0 WCK23 EDC2 B
C13 P5 R2
P4
EDC1
R13 EDCA0_0 [84]
[84] WCKA0_1# WCK23# SG EDC3
[84] WCKA0_0 WCK23 EDC2
P5 R2
[84] WCKA0_0# WCK23# SG EDC3 H5GQ1H24AFR-T2L-GP
H5GQ1H24AFR-T2L-GP
Samsung = 72.20325.B0U
Hynix = 72.05224.00U
Hynix RTS = 72.05224.A0U
Use internal Vref memory voltage R8812 1 2 120R2F-GP VRAM2_ZQ

SG
R8811 1 2 120R2F-GP VRAM1_ZQ
SG
1D5V_VGA_S0
SC10U6D3V5KX-1GP
C8801
1
SG SG SG SG SG SG SG SG SG
C88382
C88392
C88402
C88412
C88422
C88432
C88442
C88452
2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
A A
DMB40
Wistron Corporation
Title

GPU-VRAM1,2 (1/4) Rev
A2
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
C5 B5
VDD VSS
C5 B5 C10 B10
VDD VSS VDD VSS
C10 B10 D11 D10
VDD VSS VDD VSS
D11 D10 G1 G5
VDD VSS VDD VSS
G1 G5 G4 G10
VDD VSS VDD VSS
G4 G10 G11 H1
VDD VSS VDD VSS
G11 H1 G14 H14
VDD VSS VDD VSS
G14 H14 L1 K1
VDD VSS VDD VSS
L1 K1 L4 K14
VDD VSS VDD VSS
L4 K14 L11 L5
VDD VSS VDD VSS
L11 L5 L14 L10
VDD VSS VDD VSS
L14 L10 P11 P10
VDD VSS VDD VSS
D P11 P10 R5 T5 D
VDD VSS 1D5V_VGA_S0 VDD VSS
R5 T5 R10 T10
1D5V_VGA_S0 VDD VSS VDD VSS
R10 T10
VDD VSS
B1 A1
VDDQ VSSQ
B1 A1 B3 A3
VDDQ VSSQ VDDQ VSSQ
B3 A3 B12 A12
VDDQ VSSQ VDDQ VSSQ
B12 A12 B14 A14
VDDQ VSSQ VDDQ VSSQ
B14 A14 D1 C1
VDDQ VSSQ VDDQ VSSQ
D1 C1 D3 C3
VDDQ VSSQ VDDQ VSSQ
D3 C3 D12 C4
VDDQ VSSQ VDDQ VSSQ
D12 C4 D14 C11
VDDQ VSSQ VDDQ VSSQ
D14 C11 E5 C12
VDDQ VSSQ VDDQ VSSQ 1D5V_VGA_S0 1D5V_VGA_S0 1D5V_VGA_S0
E5 C12 E10 C14
VDDQ VSSQ VDDQ VSSQ
E10 C14 F1 E1
VDDQ VSSQ VDDQ VSSQ
F1 E1 F3 E3
VDDQ VSSQ VDDQ VSSQ
F3 E3 F12 E12
VDDQ VSSQ VDDQ VSSQ
F12 E12 F14 E14
2
VDDQ VSSQ VDDQ VSSQ
F14 E14 G2 F5
VDDQ VSSQ VDDQ VSSQ R8946
G2
G13
VDDQ VSSQ
F5
F10
G13
H3
VDDQ VSSQ
F10
H2
SGC8936 R8952
SGC8914 R8954
SGC8916
2K37R2F-GP
SG SC1U6D3V2KX-GP
1
VDDQ VSSQ VDDQ VSSQ
H3 H2 H12 H13
VDDQ VSSQ VDDQ VSSQ
H12 H13 K3 K2
1
VDDQ VSSQ VDDQ VSSQ
K3 K2 K12 K13
VDDQ VSSQ VDDQ VSSQ VREFC_A2 VREFD1_A2 VREFD2_A2
K12 K13 L2 M5
VDDQ VSSQ VDDQ VSSQ
L2 M5 L13 M10
VDDQ VSSQ VDDQ VSSQ
L13 M10 M1 N1
2
VDDQ VSSQ VDDQ VSSQ
M1 N1 M3 N3
VDDQ VSSQ VDDQ VSSQ R8949 C8911 R8953 C8915 R8955 C8917
M3 N3 M12 N12
M12
VDDQ VSSQ
N12 M14
VDDQ VSSQ
N14 5K49R2F-GP
1
VDDQ VSSQ VDDQ VSSQ
M14 N14 N5 R1
VDDQ VSSQ VDDQ VSSQ
N5 R1 N10 R3
1
VDDQ VSSQ VDDQ VSSQ
N10 R3 P1 R4
VDDQ VSSQ VDDQ VSSQ
P1 R4 P3 R11
VDDQ VSSQ VDDQ VSSQ
P3 R11 P12 R12
VDDQ VSSQ VDDQ VSSQ
P12 R12 P14 R14
VDDQ VSSQ VDDQ VSSQ
P14 R14 T1 U1
VDDQ VSSQ VDDQ VSSQ
T1 U1 T3 U3
VDDQ VSSQ VDDQ VSSQ
T3 U3 T12 U12
VDDQ VSSQ VDDQ VSSQ
T12 U12 T14 U14
VDDQ VSSQ VDDQ VSSQ
T14 U14
VDDQ VSSQ VREFC_A3 J14 A5
VREFC_A2 VREFC VPP/NC#A5
C J14 A5 U5 C
VREFC VPP/NC#A5 VREFD1_A3 VPP/NC#U5
U5 A10
VREFD1_A2 VPP/NC#U5 VREFD2_A3 VREFD
A10 U10
VREFD2_A2 U10
VREFD VREFD SG
VREFD SG
H5GQ1H24AFR-T2L-GP
H5GQ1H24AFR-T2L-GP
[84] MAA1_[8..0] DQA1_[31..0] [84]
VRAM4B 2 OF 2
[84] MAA1_[8..0] DQA1_[31..0] [84]
VRAM3B 2 OF 2 MAA1_0 K4 A4 DQA1_0
MAA1_6 A8/A7 DQ0 DQA1_1
H5 A2
MAA1_7 DQA1_30 MAA1_7 A9/A1 DQ1 DQA1_2
K4 A4 H4 B4
H5 A2 K5 B2
H4 B4 J5 E4
MAA1_6 A10/A0 DQ2 DQA1_26 A12/RFU#J5/NC#J5 DQ4 DQA1_7 1D5V_VGA_S0 1D5V_VGA_S0 1D5V_VGA_S0
K5 B2 E2
MAA1_8 A11/A6 DQ3 DQA1_31 MAA1_4 DQ5 DQA1_6
J5 E4 H11 F4
A12/RFU#J5/NC#J5 DQ4 DQA1_28 MAA1_3 BA0/A2 DQ6 DQA1_5
E2 K10 F2
MAA1_2 DQ5 DQA1_24 MAA1_2 BA1/A5 DQ7
H11 F4 K11 A11
1D5V_VGA_S0 MAA1_5 BA0/A2 DQ6 DQA1_25 MAA1_5 BA2/A4 DQ8
K10 F2 H10 A13
2
MAA1_4 BA1/A5 DQ7 BA3/A3 DQ9
K11 A11 B11
MAA1_3 BA2/A4 DQ8 DQ10 R8939
H10
BA3/A3 DQ9
A13
B11
[84] ADBIA1 J4
G3
ABI# DQ11
B13
E11
SGC8974 R8941
SGC8976 R8943
SGC8978
2K37R2F-GP
SG SC1U6D3V2KX-GP
1
DQ10 [84] CASA1# RAS# DQ12
[84] ADBIA1 J4 B13 [84] WEA1# G12 E13
1
ABI# DQ11 CS# DQ13

G3 E11 L3 F11
1
[84] RASA1# RAS# DQ12 [84] RASA1# CAS# DQ14
R8918 R8917 G12 E13 L12 F13
[84] CSA1#_0 CS# DQ13 [84] CSA1#_0 WE# DQ15 DQA1_22 VREFC_A3 VREFD1_A3 VREFD2_A3
120R2F-GP 120R2F-GP L3 F11 U11
SG SG [84] CASA1#
L12
CAS# DQ14
F13 J12
DQ16
U13 DQA1_20
[84] WEA1# WE# DQ15 [84] CLKA1 CK DQ17
U11 DQA1_8 J11 T11 DQA1_23
[84] CLKA1#
2
2
DQ16 DQA1_9 CK# DQ18 DQA1_21
[84] CLKA1 J12 U13 [84] CKEA1 J3 T13
CK DQ17 DQA1_10 CKE# DQ19 DQA1_18 R8940 C8975 R8942 C8977 R8944 C8979
J11 T11 N11
[84] CLKA1#
J3
CK# DQ18
T13 DQA1_11 D2
DQ20
N13 DQA1_19 5K49R2F-GP
1
[84] CKEA1 CKE# DQ19 [84] DDBIA1_0 DBI0# DQ21
N11 DQA1_13 D13 M11 DQA1_17
DQ20 1D5V_VGA_S0 DBI1# DQ22
D2 N13 DQA1_14 P13 M13 DQA1_16
[84] DDBIA1_3 [84] DDBIA1_2
1
1D5V_VGA_S0 D13 M11 1D5V_VGA_S0 P2 U4
[84] DDBIA1_1 P13 M13 U2
DBI2# DQ23 DQ25
1D5V_VGA_S0 P2 U4 [84,88] MEM_RST J2 T4
DBI3# DQ24 RESET# DQ26
U2 T2
DQ25 DQ27
[84,88] MEM_RST J2 T4 J10 N4
RESET# DQ26 VRAM4_ZQ SEN DQ28
T2 J13 N2
DQ27 ZQ DQ29
J10 N4 1D5V_VGA_S0 J1 M4
B VRAM3_ZQ SEN DQ28 MF DQ30 B
J13
ZQ DQ29
N2 MF=1 DQ31
M2
J1 M4 Mirror [84] WCKA1_0 D4
MF DQ30 WCK1
M2 [84] WCKA1#_0 D5 C2 EDCA1_0 [84]
DQ31 WCK1# EDC0
[84] WCKA1_1 D4 C13
WCK1 EDC1
[84] WCKA1#_1 D5 C2 EDCA1_3 [84] [84] WCKA1_1 P4 R13 EDCA1_2 [84]
WCK1# EDC0 WCK23 EDC2
C13 P5 R2
P4
EDC1
R13 EDCA1_1 [84]
[84] WCKA1#_1 WCK23# SG EDC3
[84] WCKA1_0 WCK23 EDC2
P5 R2
[84] WCKA1#_0 WCK23# SG EDC3 H5GQ1H24AFR-T2L-GP
H5GQ1H24AFR-T2L-GP
Samsung = 72.20325.00U
Hynix = 72.05224.00U
Use internal Vref memory voltage R8914 1 2 120R2F-GP VRAM4_ZQ

SG
R8915 1 2 120R2F-GP VRAM3_ZQ
SG 1D5V_VGA_S0
SC10U6D3V5KX-1GP
C8804
1
SG SG SG SG SG SG SG SG SG
C89852
C89972
C89802
C89072
C89902
C89122
C89012
C88832
2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
A A
DMB40
Wistron Corporation
Title
GPU-VRAM3,4 (2/4)
A2 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_vga_core 3D3V_AUX_S5
2
5V_S5
DY PR9218
100KR2J-1-GP
PWR_VGA_CORE_EN_R#
1
X03 2/16
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SCD1U10V2KX-5GP
1
4
1
1
EC9203
PC9201
PC9203
PC9204
DY SG
SCD1U10V2KX-5GP
SCD01U16V2KX-3GP
VGA_CORE
PC9202
SG SG SG PQ9206
1
X01 11/28 DMN66D0LDW-7-GP DY
2
1
3
D D
PR9220
5V_S5
DY 100R2J-2-GP
1
8209A_EN/DEM_VGA PQ9206_3
1
PR9201
SG10R2J-2-GP
2
PWR_VGA_AVDD
PU9201
3D3V_VGA_S0
1
PR9203 1 44K2R2D-GP PWR_VGA_BIAS PC9205
PR9204 1
SG22 6K49R2F-1-GP PWR_VGA_R_SEL/ILOAD
A1
A2
BIAS VDD
C4
C5
SGSCD22U10V3KX-2GP
1 2
SG A3
R_SEL/ILOAD VDD
E5
SG 10KR2J-3-GP
2
PR9221 VDES VDD
A4 G4
8209A_EN/DEM_VGA VSENSE+ VDD
A5 E4
PWR_VGA_CORE_PGOOD OE VDD
B5 G5
STAT VDD AGND_VGA
PD9201 B4
PWR_VGA_IRIPL TEMP
2 X01 11/28
[93] DGPU_PWR_EN DY1 8209A_EN/DEM_VGA [86,93] 1
PR9205 SG 2 B2
IRIPL AVDD
B3
VGA_CORE
PL9201
CH551H-30PT-GP 36KR2F-GP
1
PC9216 B1
SCD1U10V2KX-4GP AGND PWR_VGA_VX
D1 1 2
DY C1
SG VX#D1
D2
SG
2
GND VX#D2
C2 D3
GND VX#D3 COIL-D2UH-1-GP
C3 D4
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
GND VX#D4
E1
GND VX#D5
D5 68.R2010.20A
E2 F1 2nd = 68.R2010.10P
SCD1U10V2KX-5GP
1
1
GND VX#F1
PC9264
PC9259
PC9262
PC9260
PC9261
PC9218
AGND_VGA E3 F2
SG SG
SC22U6D3V5MX-2GP
GND VX#F2
PC9206
PC9207
PC9208
PC9209
PC9210
PC9211
PC9213
G1 F3
DY DY SG SG SG DY DY
SC6800P25V2KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PC9212
GND VX#F3
G2 F4
SG SG SG SG SG
2
GND VX#F4
G3 F5
GND VX#F5
X02 2/10 VT358FCX-ADJ-007-GP

C 74.00358.A3Z C
PWR_VGA_CORE_PGOOD 1 2 X03 2/16
DGPU_PWROK [22,27,86,93]
PR9215 X03 2/16
1
0R0402-PAD-2-GP
PC9219 PG9201 PG9202
SC100P50V2JN-3GP SG 1 2 PWR_VGA_VSENSE+ 1 2 VGA_CORE
2
PWR_VGA_VDES
SC2200P50V2KX-2GP
PR92231
360KR2F-GP
PR9224
PC9214
330KR2J-L1-GP
1
AGND_VGA
DY
1
PR9206
SG SG SG 36K5R2F-GP
2
PWRCNTL_1#
PWRCNTL_0#
PG9203
PWR_VGA_VSENSE- 1 2
PQ9205 PQ9204 GAP-CLOSE-PWR-3-GP

PWRCNTL_0_0 6 1 1 6 PWRCNTL_1#
5 2 PWRCNTL_0 [85] PWRCNTL_1_R 2 5 PWRCNTL_0_R 5V_S5

[85] PWRCNTL_1
4 3 PWRCNTL_1_1 PWRCNTL_0# 3 4 X03 2/16
SG SG
2N7002KDW-GP 2N7002KDW-GP Layout Note: Close VGA output
SCD1U10V2KX-5GP
2
1
84.2N702.A3F 84.2N702.A3F
PC9215
SG
EC9201
2nd = 84.DM601.03F 2nd = 84.DM601.03F
14
DY
SCD1U10V2KX-5GP
3rd = 84.2N702.E3F 3rd = 84.2N702.E3F
2
4th = 84.2N702.F3F 4th = 84.2N702.F3F 2 PU9208A
1
3 5V_S5 VGA_CORE
SG
3D3V_VGA_S0
TSLVC02APW-GP
7
PU9202_1 X03 2/16
1
1
SCD1U10V2KX-5GP
B B
14
PD9202 PU9208B
2
PR9209 K PWRCNTL_1_D PR9217 PR9216
DYA 1
DY 2
PC9217
10KR2F-2-GP 3D3R5J-GP 3D3R5J-GP
EC9202
5
DY DY SG SG SG
SCD1U10V2KX-5GP
PR9219
B0530WS-7-F-GP PR9207 4 PQ9202_4
SG
1
5K1R2F-2-GP PWRCNTL_0_0 1 2 PU9202_6 6
SG
2
2
PR9208
2
PWRCNTL_1_1 1 2 PWRCNTL_1_R 52K3R2F-L-GP PQ9203_D
DY TSLVC02APW-GP
7
PC9220
SG
2
10K7R2F-GP SCD01U50V2KX-1GP
100KR2J-1-GP
SCD047U10V2KX-2GP
1
1
PR9202
PC9222
14
PU9208C PU9206
DY DY 1 5
D
2
B VCC
8
1
10 2 PQ9203
PWRCNTL_1_1 9
SG A AO3404A-GP
3
SG 4 PU9206_Y G
SG 84.03404.B31
GND Y
TSLVC02APW-GP 2nd = 84.03404.C31
7
3D3V_VGA_S0 83.R5003.G8H 74LVC1G32GW-1GP
S
2nd = 83.R5003.H8H PQ9202_10 73.01G32.AHH
PR9222
PD9203
14
PU9208D
1
B0530WS-7-F-GP
PR9213 K A PWRCNTL_0_D 1 2 1 2 PQ9202_11 11
10KR2F-2-GP SG SG SG 13 PQ9202_13
SG SG
2
PR9212 52K3R2F-L-GP 12
5K1R2F-2-GP PC9221
SG
2
PR9210
SCD01U50V2KX-1GP TSLVC02APW-GP
1
7
PWRCNTL_0_0 1 2 PWRCNTL_0_R
SG
2
10K7R2F-GP
100KR2J-1-GP
SCD047U10V2KX-2GP
1
73.07402.EHB
PR9211
PC9223
SG SG
2
1
A A
VID0
GPIO15 Voltage
<Core Design>
1 1V
0 0.9V Wistron Corporation
Title
VT357_+VGA_CORE
A2
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_3p3v_vga, 1p8v_vga, 1p5v_vga, 1v_vga 1D8V_S0 to 1D8V_VGA_S0 Transfer
3D3V_S0 to 3D3V_VGA_S0 Transfer AO4468, SO-8 1D8V_S0

Id=11.6A, Qg=9~12nC 1D8V_VGA_S0
1
DY 2 PR9301 Rdson=17.4~22m ohm PU9306
0R2J-2-GP 8 D
SGS 1
7 D S 2
3D3V_VGA_S0 X03 2/16 6 D S 3
1
5 D G 4
SG PC9331
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
PC9330
3D3V_S0 S
EC9302
D AO4468-GP SC10U6D3V3MX-GP
DY SG
2
D
SG 84.04468.037
2
G
PQ9302 2nd = 84.04178.037
2
1
D DMP2130L-7-GP 3rd = 84.02659.037 D
G
PR9316 84.02130.031
SG
SG 10KR2J-3-GP 2ND = 84.03413.A31
2
PC9324 3D3V_AUX_S5
SCD1U10V2KX-5GP
SG
1
PR9319 1 2 1D8V_VGA_EN# 1D8V_ENABLE_RC

PR9319_1 1 2 PR9319_2
SG DGPU_PWR_EN# [22] PR9334 D G S
PR9333
10KR2J-3-GP X03 2/13 100KR2J-1-GP 2 1
SG
4
5930_PGOOD_1V 1 2 1D8V_VGA_EN
1
PQ9306 15V_S5 20KR2F-L-GP
4
PR9320 PC9323 PC9329
2N7002KDW-GP
SG
SCD1U10V2KX-5GP
PQ9303 0R0402-PAD-2-GP SCD01U50V2KX-1GP
84.2N702.A3F SG
2
2N7002KDW-GP
DY
2
2nd = 84.DM601.03F
84.2N702.A3F SG
2
3rd = 84.2N702.E3F S G D PR9335
3
2nd = 84.DM601.03F 100KR2J-1-GP
3rd = 84.2N702.E3F
4th = 84.2N702.F3F SG
4th = 84.2N702.F3F
1
2 1 1D8V_ENABLE
[92] DGPU_PWR_EN SG
PR9305
PD9303
1 2 DGPU_PWR_EN CH551H-30PT-GP 83.R5003.C8F
3D3V_S0 SG DGPU_PWR_EN [92]
2nd = 83.R5003.H8H
X03 2/21 10KR2F-2-GP X01 11/28
X01 11/28
PQ9304
PS_S3CNTRL G
[36,37] PS_S3CNTRL
D
X01 12/15
S
SG Discharge Circuit 3D3V_VGA_S0
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
2
C 3rd = 84.07002.I31 C
4th = 84.2N702.W31 1D8V_VGA_S0 PR9314
SG 470R2J-2-GP
1
1
DGPU_PWR_EN# PR9337
SG 470R2J-2-GP
PQ9311
dGPU mode L 1 6 3.3V_RUN_VGA_1
2
IGPU H PR9319_1 2 5 1D8V_VGA_EN#
DIS_1D8V_VGA_S0 3 4
IGPU with BACO L SG
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F
1D5V_S3 to 1D5V_VGA_S0 Transfer APL5930 for 1V_VGA_S0

1D5V_S3 1D5V_VGA_S0
PU9305
AO4468, SO-8 8 D 1D5V_S3 1V_VGA_S0_LDOIN
7 D SG SS 1
2 X03 2/16
Id=11.6A, Qg=9~12nC 6 D S 3 PG9301
1
1D5V_ENABLE_RC
Rdson=17.4~22m ohm 5 D G 4 PC9332 1 2

1
PC9327
AO4468-GP
SG SC10U6D3V3MX-GP GAP-CLOSE-PWR-3-GP
1V_VGA
SG
2
84.04468.037 X01 11/28

Design current =2.2A
SC10U6D3V3MX-GP
2
2nd = 84.04178.037 PG9302

3rd = 84.02659.037 1 2
GAP-CLOSE-PWR-3-GP PU9303 1V_PWR X03 2/16 1V_VGA_S0
1
X01 11/28 PC9319 5 PG9303
B PR9330
SC10U6D3V5KX-1GP SG 5V_S5 6
VIN#5
4 1 2 B
2
VCNTL VOUT#4
1 2 7 3
SG X03 2/16 PC9313 8
POK VOUT#3
2 GAP-CLOSE-PWR-3-GP
1K27R2F-L-GP
SCD1U10V2KX-5GP
1
10KR2J-3-GP EN FB PG9304
9 1
SC1U6D3V2KX-GP
1
VIN#9 GND
EC9301
1 2
DY SG SG
1
3D3V_AUX_S5
PR9322
PC9326 PC9317 PC9316
SG
1
SCD1U25V2KX-GP APL5930KAI-TRG-GP PC9312 GAP-CLOSE-PWR-3-GP
2
1 2 1D5V_VGA_EN# 74.05930.03D
SG 100KR2J-1-GP DY DY SG
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PR9332
SG
SCD01U16V2KX-3GP
2
2
D G S
2
SG
6
X01 11/28 3D3V_VGA_S0 1 2 PWR_1V_PGOOD

PQ9305 15V_S5 PR9304 100KR2J-1-GP PR9315_2
2N7002KDW-GP X02 2/13
5930_PGOOD_1V 1 2
SG
4K99R2F-L-GP
84.2N702.A3F PR9312
1
2nd = 84.DM601.03F 100KR2J-1-GP PR9311
1
3rd = 84.2N702.E3F S G D PR9331 0R0402-PAD-2-GP
100KR2J-1-GP PWR_1V_EN
PR9315
X01 11/28 1 2
4th = 84.2N702.F3F SG [92] DGPU_PWR_EN SG Vout=0.8V*(R1+R2)/R2
PD9301 PD9302 X01 11/28 SG
1
CH551H-30PT-GP CH551H-30PT-GP PC9318
2
1
SCD1U10V2KX-5GP
2 1 1D5V_VGA_EN 1D5V_ENABLE 2 1
[92] DGPU_PWR_EN SG [22,27,86,92] DGPU_PWROK SG DY
2
83.R5003.C8F 83.R5003.C8F
1
PR9326 2nd = 83.R5003.H8H 2nd = 83.R5003.H8H

1 2 PC9328
[22,27,86,92] DGPU_PWROK DY
0R2J-2-GP SG SCD47U25V3KX-1GP
2
1 2 X01 11/28
[86,92] 8209A_EN/DEM_VGA SG Discharge Circuit
PR9327
20KR2J-L2-GP 1D5V_VGA_S0
X01 11/28 PR9302 Discharge Circuit

1
1 2 PWR_1V_EN#
PR9336
3D3V_AUX_S5 SG
A SG 470R2J-2-GP
A
100KR2J-1-GP
DIS_1D5V_VGA_S02
PQ9301
2N7002KDW-GP
<Core Design>
PQ9307
84.2N702.A3F SG
1
G 1D5V_VGA_EN# 2nd = 84.DM601.03F

3rd = 84.2N702.E3F Wistron Corporation
D 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
4th = 84.2N702.F3F
S
SG PR9303
Title
2N7002K-2-GP PWR_1V_EN PQ9311_3 2 1
84.2N702.J31 SG 1V_VGA_S0
DISCRETE VGA POWER
2ND = 84.2N702.031 470R2J-2-GP Size Document Number Rev
3rd = 84.07002.I31 A2 BMW Z4 DIS
4th = 84.2N702.W31 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
DMB40
A A
Wistron Corporation
Title
Reserved
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
DMB40
A A
Wistron Corporation
Title
Reserved
A3 A00
BMW Z4 DIS
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DMB40 A
Wistron Corporation
Title
Reserved
A3 A00
BMW Z4 DIS
5 4 3 2 1
A
B
C
D
2 1 2 1 2 1 2 1 2 1 RF
2 1
DCBATOUT
DCBATOUT
DCBATOUT
DCBATOUT
DCBATOUT
1D5V_S3
EC9751 EC9750 EC9749 EC9748 EC9747
EC9705 SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP
SC4D7P50V2BN-GP
X01 12/15 For RF

2 1 2 1 2 1 2 1
DY
DY
DY
3D3V_S5
3D3V_S5
3D3V_S5
3D3V_S5
EC9769 EC9753 EC9752 EC9746

SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
2 1
5
5
AVDDL
EC9770 2 1 2 1 2 1 2 1 2 1
DY
DY
DY
DY
5V_S5
5V_S5
5V_S5
5V_S0
5V_S0
SCD1U10V2KX-5GP
EC9763 EC9762 EC9761 EC9755 EC9754

SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
2 1
DY
DVDDL
EC9771
SCD1U10V2KX-5GP
2 1 2 1 2 1 2 1 2 1
DY
DY
DY
DY
DY
3D3V_S0
3D3V_S0
3D3V_S0
3D3V_S0
3D3V_S0
2 1
DY
EC9760 EC9759 EC9758 EC9757 EC9756
1D8V_S0
EC9772
SCD1U10V2KX-5GP
RF
2 1
5V_S5
2 1 EC9789
5V_S5
SCD1U10V2KX-5GP
X03 2/16
X03 1/30
EC9738
SCD1U10V2KX-5GP 2 1
EC9790
VGA_CORE
X01 12/09 For EMI

2 1 SCD1U10V2KX-5GP
5V_S5
EC9739
SCD1U10V2KX-5GP
X01 12/30
2 1
5V_S5
EMI
2 1 2 1 2 1
EC9741 2 1 2 1
DY
SCD1U10V2KX-5GP
DCBATOUT
DCBATOUT
DCBATOUT
4
4
EC9703 EC9702 EC9701

DCBATOUT
DCBATOUT
EC9709 EC9708 SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP

SCD1U25V2KX-GP SCD1U25V2KX-GP
2 1
X03 2/13
5V_S5
EC9743 2 1 2 1
5V_S5
5V_S5
DY
SCD1U10V2KX-5GP 2 1 2 1 2 1
5V_S5
5V_S5
5V_S5
DY
DY
EC9735 EC9734
2 1 EC9745 EC9737 EC9736 SCD1U10V2KX-5GP SCD1U10V2KX-5GP
A00 3/27
5V_S5
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
EC9744
SCD1U10V2KX-5GP
2 1 2 1 2 1
5V_S0
5V_S5
5V_S5
DY
2 1 EC9710 EC9742 EC9740

A00 3/29
5V_S5
EC9764
SCD1U10V2KX-5GP
2 1 2 1 2 1 2 1 2 1
DY
DY
DY
DY
3D3V_S5
3D3V_S5
3D3V_S5
3D3V_S5
3D3V_S5
2 1 EC9717 EC9721 EC9720 EC9715 EC9714

5V_S5
EC9765
SCD1U10V2KX-5GP
2 1 2 1 2 1 2 1
DY
DY
DY
3D3V_S0
3D3V_S0
3D3V_S0
3D3V_S0
2 1 EC9727 EC9723 EC9726 EC9725

5V_S5
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
EC9766
SCD1U10V2KX-5GP
2 1
5V_S5
5V_S5
2 1
DY
2 1
EC9767
1
DY
EC9731
1D05V_PCH
SCD1U10V2KX-5GP
EC9732 SCD1U10V2KX-5GP
3D3V_WWAN_AOAC
SCD1U10V2KX-5GP
EC9733
SG2
3
3
2 1
5V_S5
VGA_CORE
EC9768
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2 1
EMI
2 1 2 1 2 1 2 1
5V_S5
3D3V_S5
+DC_IN
3D3V_S0
EC9775
DCBATOUT
EC9773 SCD1U10V2KX-5GP EC9707 EC9716 EC9704

SCD1U10V2KX-5GP SCD1U25V2KX-GP SCD1U10V2KX-5GP SCD1U25V2KX-GP
X03 2/16
2 1 2 1 2 1 2 1
5V_S5
+DC_IN
2 1
3D3V_S5
3D3V_S0
EC9774 EC9776 EC9718 EC9706

SCD1U10V2KX-5GP SCD1U10V2KX-5GP EC9719 SCD1U10V2KX-5GP SCD1U25V2KX-GP
X03 2/21
3D3V_AUX_S5
SCD1U10V2KX-5GP
2 1
2 1
5V_S5
EC9722
EC9728
3D3V_AUX_S5
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2 1 2 1
5V_S5
5V_S5
2 1 2 1 2 1
1D5V_S3
1D5V_S3
1D5V_S3
EC9730 EC9724
SCD1U10V2KX-5GP SCD1U10V2KX-5GP EC9786 EC9782 EC9777
2 1 2 1
2
2
1D5V_S3
1D5V_S3
EC9787 EC9783
SCD1U10V2KX-5GP SCD1U10V2KX-5GP
2 1 2 1
1D5V_S3
1D5V_S3
EC9788 EC9784
2 1 2 1
1D5V_S3
1D5V_S3
EC9785 EC9781
A2
Title
Size
Date:
<Core Design>
HS4
HS3
HS2
HS1
SG
1 1 1 1 1 1
HS6
HS5
Document Number
Friday, March 30, 2012
1
1
STF237R128H42-3-GP
STF237R128H42-3-GP
STF237R128H42-3-GP
STF237R128H42-3-GP
STF237R148H67-GP
STF237R148H67-GP
On the TOP side
34.4UV01.001
34.4UV01.001
34.4UV01.001
34.4UV01.001
MSATA_WWAN
2nd = 34.4UV01.101
2nd = 34.4UV01.101
2nd = 34.4UV01.101
2nd = 34.4UV01.101
BMW Z4 DIS
Sheet
97
H5
H2
H1
H7
H6
H4
H3
1 1 1 1 1 1 1
of
X01 12/23
UNUSED PARTS/EMI Capacitors

SSID = Mechanical
HOLE256R115-GP
HOLE256R115-GP
HOLE335R115-GP
HOLE256R115-GP

HT85BE95R29-U-5-GP
HT85BE95R29-U-5-GP
HT85BE95R29-U-5-GP
105
Rev
Wistron Corporation
A00
A
B
C
D
5 4 3 2 1
Huron River Platform Power Sequence

(AC mode) red word: KBC GPIO
(DC mode) red word: KBC GPIO
+RTC_VCC
+RTC_VCC t01 >9ms
t01 >9ms
RTC_RST#
RTC_RST#
DCBATOUT
DCBATOUT
Within logic high level and disable if

3D3V_AUX_S5
D it is less than the logic low level.
3D3V_AUX_S5 D
KBC GPIO34 control power on by 3V_5V_EN
S5_ENABLE Sense the power button status
Press Power button
KBC_PWRBTN# Platform to KBC PSL_IN2
Ta 5V_S5
V5REF_Sus must be powered up before EC_ENABLE#_1(GPIO31) keep low
VccSus3_3, or after VccSus3_3 within 3D3V_S5 Ta 3D3V_AUX_KBC
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before KBC GPIO34 control power on by 3V_5V_EN
VccSus3_3 within 0.7 V.
+5VA_PCH_VCC5REFSUS S5_ENABLE
KBC GPIO43 to PCH
PM_RSMRST#(EC Delay 40ms) t05 >10ms 5V_S5
PCH to KBC GPIO00 V5REF_Sus must be powered up before
+5V_ALW & +3.3V_ALW need meet 0.7V difference
PCH_SUSCLK_KBC t07>5ms VccSus3_3, or after VccSus3_3 within 3D3V_S5
0.7 V. Also, V5REF_Sus must power
KBC GPO84 to PCH down after VccSus3_3, or before
+5V_ALW & +3.3V_ALW need meet 0.7V difference
Not floating. VccSus3_3 within 0.7 V.
AC_PRESENT 0ms<t08a<90ms +5VA_PCH_VCC5REFSUS Ta
KBC GPIO20 to PCH

Press Power button
3D3V_AUX_KBC PM_PWRBTN#
Platform to KBC PSL_IN2
Sense the power button status
AC KBC_PWRBTN#
KBC GPIO43 to PCH
This signal has an internal PM_RSMRST# t05 >10ms
pull-up resistor and has an KBC GPIO20 to PCH
internal 16 ms de-bounce on the PCH to KBC GPIO00
input. AC PM_PWRBTN#
PCH_SUSCLK_KBC t07>5ms
AC PM_PWRBTN# DC PCH_RSMRST#
PCH to KBC GPIO44 PCH to KBC GPIO44

PM_SLP_S4# PM_SLP_S4#
t10 PCH to KBC GPIO01 t10 PCH to KBC GPIO01
PM_SLP_S3# >30us PM_SLP_S3# >30us
KBC GPIO23 to LAN KBC GPIO23 to LAN
PM_LAN_ENABLE PM_LAN_ENABLE
Enable by PM_SLP_S4# Enable by PM_SLP_S4#
1D5V_S3 1D5V_S3
C C
DDR_VREF_S3(0.75V) DDR_VREF_S3(0.75V)
+5V_RUN & +3.3V_RUN need meet 0.7V difference +5V_RUN & +3.3V_RUN need meet 0.7V difference
5V_S0 5V_S0
Tb
V5REF must be powered up before 3D3V_S0 V5REF must be powered up before 3D3V_S0
Vcc3_3, or after Vcc3_3 within 0.7 V. Vcc3_3, or after Vcc3_3 within 0.7 V.
Also, V5REF must power down after Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V. Vcc3_3, or before Vcc3_3 within 0.7 V.
+5VS_PCH_VCC5REF Tb +5VS_PCH_VCC5REF Tb
1D5V_S0 1D5V_S0
1D8V_S0 1D8V_S0
0D75V_S0 0D75V_S0
1D8V_S0 & 1D5V_S3 power ready 1D8V_S0 & 1D5V_S3 power ready
RUNPWROK RUNPWROK
1D05V_PCH/VCCP_CPU 1D05V_PCH/VCCP_CPU
TPS51218 PGOOD TPS51218 PGOOD
1D05VTT_PWRGD 1D05VTT_PWRGD
0D85V_S0 0D85V_S0
VCCSA_S0 VCCSA_S0
TPS51461RGER PGOOD TPS51461RGER PGOOD
VCCSA_PWRGD VCCSA_PWRGD
SetVID ACK SetVID ACK

CPU SVID BUS 50us< t36 <2000us CPU SVID BUS 50us< t36 <2000us
VCC_CORE VCC_CORE
VCC_GFXCORE VCC_GFXCORE
t37 t37
<5ms
ISL95831 PGOOD to system <5ms
ISL95831 PGOOD to system
IMVP_PWRGD IMVP_PWRGD
CLK_EXP_P CLK_EXP_P
B B
ALL_SYS_PWRGD=VCCSA_PWRGD ALL_SYS_PWRGD=VCCSA_PWRGD
This signal represents the Power
t14 >99ms KBC GPIO77 to PCH This signal represents the Power
t14 >99ms KBC GPIO77 to PCH
Good for all the non-CORE and Good for all the non-CORE and
non-graphics power rails.
PWROK non-graphics power rails.
PWROK
t18 >0us t18 >0us
VCCSA_PWRGD VCCSA_PWRGD
2ms< t17 <650ms PCH to CPU 2ms< t17 <650ms PCH to CPU
VDDPWRGOOD VDDPWRGOOD
t19 >1ms t19 >1ms
t20 >2ms t20 >2ms
1D8V_S0 1D8V_S0
5ms< t13 <650ms PCH to CPU 5ms< t13 <650ms PCH to CPU
H_CPUPWRGD H_CPUPWRGD
SYS_PWROK SYS_PWROK
t21+t22 >1ms+60us t21+t22 >1ms+60us
1ms< t25 <100ms PCH to all system 1ms< t25 <100ms PCH to all system
PLT_RST# PLT_RST#
t39 <200us t39 <200us
DMI DMI
Thames PRO Power-Up/Down Sequence
3D3V_S0
DGPU_PWR_EN#(Discrete only)
PCH GPIO48 output
3D3V_VGA_S0(Discrete only)
3D3V_VGA_S0 above VT358 VIH
8209A_EN/DEM_VGA(Discrete only)
A
VGA_CORE(Discrete only) Ta >0ms A
1V_VGA_S0(Discrete only)
APL5930 PGOOD
5930_PGOOD_1V(Discrete only)
Tb >0ms
1D5V_VGA_S0(Discrete only)
Tc >0ms
VT358 PGOOD
DGPU_PWROK(Discrete only) DMB40
1D8V_VGA_S0(Discrete only) Td <20ms Wistron Corporation

Title
For power-down, reversing the ramp-up sequence is recommended.
Power Sequence
A1
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
Wistron CHIEF RIVER POWER UP SEQUENCE DIAGRAM

-6
AC AD+
Adapter in
Page38
-3a -3a -3a 5V_S5
PWR_5V3D3V_ENC 3V_5V_EN S5_ENABLE
D
3a D
VDD 1D5V_S3
VOUT
-3b -3c 3
PWR_CHG_ACOK
SWITCH ENC 5V_S5 15V_S5 PM_SLP_S4#
Page40 LL1 PUMP EN VT385
3D3V_S5 RUNPWROK
LL2 PGD
SWITCH Page46
Page40 5V_AUX_S5 5
TPS51125RGER VREG5
DC/DC 3D3V_AUX_S5 -4
-5 (3V/5V) VREG3 3
DCBATOUT 3V_5V_POK PM_SLP_S4# 5V_S5 1D5V_S3
VIN PGOOD
Page41
DC 4
BT+ BQ24727 PM_SLP_S3# 5V_S0 VDDP VIN 3b
Battery Charger SWITCH
Page39 -3 Page36 3 DDR_VREF_S3
VTTREF
3D3V_AUX_KBC -3a PM_SLP_S4#
Page40 ACOK 3D3V_S0 EN
S5_ENABLE SWITCH
-6a Page36
AC_IN# GPIO34
1D5V_S0
RT9026
GPIO70
SWITCH 4
Page36 0D75V_S0
VTT
C
1 SLP_S4# SLP_S3# PM_SLP_S3#
C
-1 KBC VTT_EN
KBC_PWRBTN#
GPIO6 NPCE885 -2 4a
9 AND GATE
Power Button PM_RSMRST# 0D75V_EN Page46
PM_SLP_S4# GPIO43 RSMRST# A VDDPWRGOOD
GPIO44 PM_PWRBTN# PM_DRAM_PWRGD Y SM_DRAMPWROK
PM_SLP_S3# GPIO20 PWRBTN# DRAMPWRGD B
GPIO01
2 H_CPUPWRGD H_CPUPWRGD_R
PROCPWRGD UNCOREPWRGOOD 5V_S5 3D3V_S5
Page27 Panther Point 10
GPIO77 PCH Ivy Bridge
8
15 CPU 4
VDD VIN
VOUT
1D8V_S0
S0_PWR_GOOD
Sequence: APWROK
PM_SLP_S3#
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
PWROK PLT_RST# BUF_CPU_RST# EN RT8068A
PLTRST# RSTIN# RUNPWROK
SYS_PWROK SVID PGD
SYS_PWROK Page47
5
SVID
14
11
B B
5V_S5
5V_S5 DCBATOUT
V5IN VIN 1D05_PCH/VCCP_CPU 5a

VOUT 11 VIN VCC_CORE
5 OUTPUT
SVID 12
RUNPWROK VT386 SVID VCC_GFXCORE
EN 1D05V_VTT_PWRGD OUTPUT
Page45 PGOOD
6 7 VT1318/VT1323/
5b VT1326 14
D85V_PWRGD IMVP_VR_ON 13
VR_ON IMVP_PWRGD SYS_PWROK
Page42 & 43 & 44 PGOOD
5V_S5 VCCP_CPU
-4
-7 3D3V_AUX_S5
5c RTC_AUX_S5
VCNTL VIN 0D85_S0
5b VOUT -8
A APL5916 +RTC_VCC A
1D05VTT_PWRGD
EN D85V_PWRGD
Page48 PGOOD
RTC battery
6 DMB40
Wistron Corporation
Power Up Sequence: -8 ~ 15 Title

Power Sequence Diagram

A2
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
Adapter AD+ SI7121DN DCBATOUT 3D3V_S5

TPS51225RUKR
SI7121DN
D D
Charger AO3404A AO4468 AO3404A RT8068AZQWID PA102FMG
BQ24727
Battery BT+
3D3V_S0 3D3V_WWAN_AOAC 1D8V_S0 3D3V_LAN_S5
3D3V_WLAN_AOAC
3D3V_AUX_S5 5V_PWR_2
15V_S5 (3D3V_PWR_2) G5285T11U RTS5179 DMP2130L AO4468 AR8162L
LCDVDD 3D3V_CARD_S0 3D3V_VGA_S0 1D8V_VGA_S0 DVDDL

DMP2130L
C C
For Discrete For Discrete
3D3V_AUX_KBC
5V_S5
VT1318MFQ +
TPS2541RTER+ VT1326SFCX + AO4468 VT358FCX VT385FCX
UP7534QRA8 VT386FCX
VT1323SFCX
USB30_VCCx 5V_S0 VGA_CORE 1D5V_S3

VCC_CORE VCC_GFXCORE 1D05V_PCH/VCCP_CPU
For Discrete
B B
APL5916 RT9026PFP TPCA8062 AO4468 APL5930KAI
0D85V_S0 0D75V_S0 DDR_VREF_S3 1D5V_S0 1D5V_VGA_S0 1V_VGA_S0
For Discrete
A Power Shape DMB40 A
Wistron Corporation
Regulator LDO Switch Taipei Hsien 221, Taiwan, R.O.C.
Title

Power Block Diagram Rev
A3
BMW Z4 DIS A00
5 4 3 2 1
A B C D E
PCH SMBus Block Diagram 3D3V_S5 3D3V_S0 KBC SMBus Block Diagram
TP_VDD

3D3V_S0
SRN2K2J-1-GP SRN2K2J-1-GP

DIMM 1 SRN10KJ-5-GP
SMBCLK SMB_CLK
PCH_SMBCLK SCL
1 SMBDATA SMB_DATA
PCH_SMBDATA SDA
GPIO37/PSCLK1
0R2J-2-GP
TouchPad Conn. 1
TPCLK
TPCLK_C TPCLK
3D3V_S5 0R2J-2-GP
SMBus Address:A0h GPIO35/PSDAT1 TPDATA
TPDATA_C TPDATA
2N7002KDW
3D3V_AUX_KBC
DIMM 2
SRN2K2J-1-GP PCH_SMBCLK SCL

PCH_SMBDATA SDA
SML0CLK SML0_CLK SRN4K7J-8-GP

SMBus Address:A4h
SML0DATA SML0_DATA
3D3V_S5 Minicard GPIO17/SCL1/N2TCK BAT_SCL

33R2J-2-GP
PBAT_SMBCLK1
Battery Conn.

PCH_SMBCLK
WLAN
SMB_CLK
GPIO22/SDA1/N2TMS BAT_SDA

33R2J-2-GP
PBAT_SMBDAT1
SMBus address:16h
PCH_SMBDATA SMB_DATA
SRN2K2J-1-GP
BQ24727
Minicard SCL
SML1CLK/GPIO58
SML1_CLK GPIO73/SCL2
To KBC W-WAN KBC SDA
SML1DATA/GPIO75 SML1_DATA
GPIO74/SDA2 PCH_SMBCLK
PCH_SMBDATA
SMB_CLK
SMB_DATA
NPCE885PA0DX 3D3V_S5 3D3V_S0 SMBus address:12h
3D3V_VGA_S0 SRN2K2J-1-GP

2
TouchPad 2
SRN2K2J-1-GP
Conn.
SRN4K7J-8-GP

PCH_SMBCLK SMB_CLK

PCH_SMBDATA SMB_DATA Thermal IC
GPIO73/SCL2 SML1_CLK THM_SML1_CLK
NCT7718W
SCL
THM_SML1_DATA SDA
GPIO_VGA_04_CLK GPIO_4_SMBCLK GPIO74/SDA2 SML1_DATA

To GPU
GPIO_VGA_03_DATA
GPIO_3_SMBDATA
2N7002KDW
SMBus address:99h/98h(R/W)
SMBus Address:41h
2N7002KDW
PCH 5V_S0
SML1_CLK SML1CLK/GPIO58
PCH
3D3V_S0 SML1_DATA SML1DATA/GPIO75

3D3V_S0
SRN2K2J-1-GP
SRN2K2J-1-GP
SDVO_CTRLCLK PCH_HDMI_CLK
DDC_CLK_HDMI
SDVO_CTRLDATA PCH_HDMI_DATA
DDC_DATA_HDMI HDMI CONN
3 3
2N7002DW-1-GP
3D3V_S0
SRN2K2J-1-GP
SRN0J-6-GP
L_DDC_CLK LVDS_DDC_CLK_R
LVDS_DDC_CLK_R_1
L_DDC_DATA LVDS_DDC_DATA_R
LVDS_DDC_DATA_R_1 LCD CONN
4 4
DMB40
Wistron Corporation
Title
SMBUS Block Diagram

A2 BMW Z4 DIS A00
A B C D E
A B C D E
Thermal Block Diagram Audio Block Diagram

3D3V_S5 3D3V_S0
1 1
SRN2K2J-1-GP PAGE28

CPU/SYSTEM
SRN2K2J-1-GP
PAGE29
D+ NCT7718_DXP
Thermal

PMBS3904-1-GP
SC2200P50V2KX-2GP SC470P50V3JN-2GP
NCT7718W

D- NCT7718_DXN PORTA_L MIC_IN_L_R MIC_JACK_R
THM_SML1_CLK
SML1_CLK
SCL
3D3V_S0 PORTA_R
SML1_DATA
THM_SML1_DATA SDA
VREFOUT_A AUD_VREFOUT_A
2K2R3F HP/MIC
2N7002KDW
2K2R2F-3-GP
PORTB_L AUD_HP1_JACK_L
Combo
PORTB_R AUD_HP1_JACK_R
2N7002K D PURE_HW_SHUTDOWN#
T_CRIT# THERM_SYS_SHDN#
S
3V_5V_EN
G 3D3V_S0
GPIO73/SCL2 GPIO74/SDA2
2
PAGE27 Codec DMIC_CLK/GPIO1 AUD_DMIC_CLK_R Digital 2
IDT DMIC_0/GPIO2 AUD_DMIC_IN0_R

MIC
KBC 92HD94
NPCE885P
GPIO4/AD5
PORTD_+L AUD_SPK_L+
PORTD_-L AUD_SPK_L-
GPIO94/DA0 GPIO56/TA1
FAN_TACH1
SPEAKER
FAN1_DAC
PORTD_+R AUD_SPK_R+
3 3
TACH PORTD_-R AUD_SPK_R-
FAN
5V_S0 VIN
FAN_VCC
VIN VSET VOUT
FAN CONTROL
G991P11U
PAGE28
4 DMB40 4
Wistron Corporation
Title
Size
Thermal/Audio Block Diagram
Document Number Rev
Custom
BMW Z4 DIS A00
A B C D E
5 4 3 2 1
DATE PAGE Change Iteam Owner Version DATE PAGE Change Iteam Owner Version
2011 11/28 92 Change VT358 AVDD power rail to 5V_S5 to avoide leakage Power X01 2011 12/09 27 Change AOAC_PCIE_WAKE# pull high to 3D3V_WLAN_AOAC and PCIE_WAKE# to 3D3V_LAN_S5 EE X01
2011 11/28 92 Re-name Cap PC4663 to PC9218. EE X01 2011 12/09 66 Change WWAN power to 3D3V_S0 EE X01
2011 11/28 85 Change U8506 power rail and select pin to 3D3V_VGA_S0 to avoid leakage EE X01 2011 12/09 8 Change VCC_CORE MLCC by power team request Power X01
D D
2011 11/28 93 Change PU9303 to 74.05930.03D by design EE X01 2011 12/09 9 Change AXG_CORE MLCC by power team request Power X01
2011 11/28 93 POP PD9301, PD9302, PD9303, PD9304, PC9328, change PR9327 to 20K, PR9330 to 10K, EE X01 2011 12/09 22 Reserved DGPU_HOLD_RST# & DGPU_PWR_EN# pull high and down EE X01
PC9326 to 0.1u, PR9312 to 100K, PR9312 re-connect to DGPU_PWR_EN,
PD9302 re-connect to DGPU_PWROK for GPU power sequence 2011 12/09 97 Follow EMI request added Cap. EMI X01
2011 11/28 37 Change R3714 to 10K to fix step-like waveform EE X01 2011 12/09 20 Rename PCIE request pin EE X01
2011 11/28 84 DY R8408 cause GPU support PX5.0 EE X01 2011 12/09 65 Add WLAN requirst circuit EE X01
2011 11/28 86 DY R8605, Q8602, R8603, R8604, U8601, U8602, U8603, U8604, cause GPU support PX5.0 EE X01 2011 12/12 40 design change PU4001 by Power team request Power X01
2011 12/02 27 Reserved DGPU_PWROK signal to inform KBC EE X01 2011 12/12 41 design change PU4106 by Power team request Power X01
2011 12/02 62 POP R6208, DY R6201 for USB charging function. EE X01 2011 12/12 41 Change PU4102 to colay symbol by Power team request Power X01
2011 12/02 85 Change VRAM type setting. EE X01 2011 12/12 45 Change PU4501to VT386 by Power team request Power X01
C 2011 12/02 41 Change PT4101, PT4103, PT4104 to 77.52271.09L for design change EE X01 2011 12/12 46 Change PR4609 and PR4612 by Power team request Power X01 C
2011 12/02 27 Add R2737 for avoiding KBC power drop. EE X01 2011 12/12 48 Change PU4801 by Power team request Power X01
2011 12/02 37 Change R3719 to 0402 type EE X01 2011 12/12 43 Reserved PT4301 by Power team request Power X01
2011 12/02 69 Change TPAD1 conn by ME ME X01 2011 12/12 84 Change R8412 to 4.7k. EE X01
2011 12/02 82 Change LEDBD1 conn by ME ME X01 2011 12/12 27 Change U2701 to new P/N EE X01
2011 12/02 56 Change HDD1 conn by ME ME X01 2011 12/13 82 Add ER8201, ER8202, ER8203, ER8204 by EMI request. EMI X01
2011 12/02 68 Change PWSW1 conn by ME ME X01 2011 12/13 18 Reserved USB_PN13, USB_PP13 test point. EE X01
2011 12/02 27 Change RSTSW1 conn by ME ME X01 2011 12/13 62 Del USB3.0 Redriver circuit. EE X01
2011 12/02 39 Add BATSW1 and R3901 for avoiding MB crack on assembling. ME X01 2011 12/13 27 Change R2735 and R2737 to 20K for fix AUX power overshoot. EE X01
2011 12/02 60 Change RTC1 conn by ME ME X01 2011 12/13 41 Change PC4127 to 4.7uF for fix AUX power overshoot. EE X01
B B
2011 12/02 39 DY D3901, D3902, D3903 cause the battery is internal type. EE X01 2011 12/13 82 Add ER8205, EC8206 by EMI request. EMI X01
2011 12/02 51 Re-name D5001 and F5001 to D5101 and F5101, and DY F5101 and add R5109 EE X01 2011 12/13 46 Add EL4601, EL4602 by EMI request. EMI X01
due to no current leakage problem
2011 12/13 43 Add EG4301,EG4302EG4303,EG4304,EG4305,EG4306,EG4307 by EMI request. EMI X01
2011 12/02 14 Change DM1 conn by ME ME X01
2011 12/13 44 Add EG4401,EG4402,EG4403,EG4404,EG4405,EG4406,EG4407 by EMI request. EMI X01
2011 12/02 27 Change R2724 to 20K for X01 version EE X01
2011 12/13 15 Change DM2 conn by ME request ME X01
2011 12/02 85 DY C8523, cause VGA temp detect by SMBUS. EE X01
2011 12/15 97 Add EC9736, EC9726, EC9750 EC9708, EC9709, EC9770, EC9705, EC9769 by RF request. RF X01
2011 12/02 28 DY U2803, C2817, C2818 cause VGA temp detect by SMBUS. EE X01
2011 12/15 56 Add EC5601 by RF request. RF X01
2011 12/02 38 Del PR3812. EE X01
2011 12/02 49 Change LCD1 conn by ME ME X01
2011 12/02 60 POP U6001 and del ROMSK1 for X01 version EE X01
A <Core Design> A
2011 12/02 65 Change R6507 to J type EE X01
2011 12/02 39 Change BATT1 conn by ME ME X01 Wistron Corporation

2011 12/02 82 Change IOBD1 conn by ME ME X01
Title
2011 12/02 68 Add WLAN/WWAN LED power control circuit EE X01 Change History
A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
2011 12/15 14 Change DM1 P/N to 62.10017.S81 EE X01 2011 12/23 62 Swap USB0 signal to TR6204 for layout EE X01
2011 12/15 15 Change DM2 P/N to 62.10017.T01 EE X01 2011 12/23 97 Del H8. ME X01
2011 12/15 62 Del R6201 change by USB detect function EE X01 2011 12/27 51 Pop D5101, DY R5109. EE X01
D D
2011 12/15 65 DY R6507, U6501 for design change EE X01 2011 12/30 93 Change PD9301, PD9302, PD9303, PD9304's 2nd source to 83.R5003.H8H EE X01
2011 12/15 68 Add R6809, DY C6802, R6803, D6802, WLAN LED power control by AOAC_WLAN_EN#. EE X01 2011 12/30 31 Change U3101 to 71.08162.A03 due to vendor update new version. EE X01
2011 12/15 8 Change C825, C830, C831, C832 to 0805 type. EE X01 2011 12/30 97 Pop EC9738, EC9739, EC9741, EC9743, EC9744, EC9764, EC9765, EC9766, EC9767, EC9768 EMI X01
2011 12/15 9 Change C906, C907, C908, C909, C910 to 0805 type. EE X01 2011 12/30 36, 93 Change U3601 U3602 PU9305 PU9306 2nd to 84.04178.037 Power X01
2011 12/15 93 Del 1D8V_VGA_S0 power good circuit. EE X01 2011 12/30 49 Change TR4902 to 69.10103.041 EMI X01
2011 12/15 83 Del VGA_RST# circuit. EE X01 2012 01/09 15, 24 DY C1507 and C2403 by PI testing result. EE X01
2011 12/15 86 Del 1D5V_VGA_S0 power good circuit. EE X01

2012 01/09 48 Change VCCSA to LDO type. Power X02
2011 12/15 31 Reserved EC3101 by RF request. RF X01
2012 01/09 51 Change HDMI SMBUS pull up power to 5V_HDMI_S0_R EE X03
2011 12/15 97 Reserved EC9771, EC9772 by RF request. RF X01
2012 01/30 48 Reserved PC4818 PC4819 to prevent VCCSA power IC VID setting(PWM solution) EE X03
C 2011 12/16 86 Change C8642, C8650, C8647 to 22u 0805 size. EE X01 C
2012 01/30 68 Add D6803 to fix DW1703 BT LED behavior. and change WLAN LED power rail to 5V_S0. EE X03
2011 12/16 62 Pop TR6204, DY R6279, R6280. EMI X01
2012 01/30 97, 38 Take off EC9704, del PS_ID_R. EE X03
2011 12/16 49 Pop TR4902, DY R4903, R4906. EMI X01
2012 01/30 82 Move IO BD conn signal for coaxial cable EE X03
2011 12/16 8 Change C847 to 22u 0805 size. EE X01
2012 01/30 66 DY R6615. EE X03
2011 12/16 68 Pop C6802, for soft start. EE X01
2012 01/30 40, 38 Change PR4004 to 3K and PR3816 to 3.3K for hiccup mode adaptor. EE X03
2011 12/19 38 Change PC3806 to 0805 type Power X01
2012 01/30 62 Change U6201 to lastly version. EE X03
2011 12/19 43 Del PT4301 cause no layout area. Power X01
2011 12/20 44 Change PWR_GFX to PWR_CPU Power X01 2012 01/30 31 Change L3101 to prevent the shortage problem. EE X03
2011 12/20 18 Change touch panel USB signal to port 4. EE X01

2012 02/06 82 Change TPAN1 P/N by ME request and modify conn pin define. EE X03
2011 12/20 82 Reserved TPAN1, and swap IOBD1's main and 2nd source. EE X01
B
2012 02/06 31 Reserved C3110 for Lan IC. EE X03 B
2011 12/20 49 Swap LCD1's main and 2nd source. EE X01

2012 02/06 5, 8, 9, 14, Change R504, R812, R909, R1404, R1405, R1505, R1503, R1921, R1916, R1924, R1929,
15, 19, R1925, R2304, R2301, R2307, R2306, R2308, R2403, R2404, R2412, R2402, R2702, R2765,
2011 12/20 14 Change R1401, R1402 to short pad EE X01 EE X03
23, 24, 27, R2794, R2778, R2792, R2733, R2767, R2768, R2720, R2764, R2723, R2727, R2807, R3614,
28, 36, 37, R3710, PR3819, R4912, R4913, R5125, R5101,R5102, R5149, R5103, R5108, R5107, R5106,
2011 12/20 15 Change R1502 to short pad EE X01 38, 49, 51, R5105, R6202, R6203, R6204, R6205, R6505, R6502, R6616, R8322, R8504, R8506, R8507,
62, 65, 66, to short pad
2011 12/20 39 Change R3902, R3903, R3904 to 100 ohm to avoid break KBC when battery in. EE X01 83, 85
2011 12/20 27 Del RN2703, add R2714, R2715. EE X01 2012 02/10 41, 42, 45, Change PR4127, PR4130, PR4133, PR4116, PR4251, PR4250, PR4212, PR4207, PR4228, Power X03
46, 47, 95 PR4523, PR4522, PR4510, PR4511, PR4626, PR4621, PR4622, PR4623, PR4611, PR4602,
2011 12/21 48 POP PR4814, change PR4811 to 365ohm, PR4813 to 100Kohm Power X01 PR4702 ,PR9215 to short pad
2011 12/21 21 Add R2115 and del R6001 for SPI louting setting EE X01 2012 02/13 51 Change HDMI output power design EE X03
2011 12/21 8 DY C807, C843, C824. Power X01 2012 02/13 41, 42, 18 Change PR9311, PR9320, PR4116, PR4219, PR4223, PR4252, PR4254, PR4261, R1823, R1927 Power X03
19, 28, 93 R2813 to short pad
2011 12/21 42 Change PR4236 to 374ohm, PR4249 to 7.68Kohm. Power X01
2012 02/13 97 Add EC9704, EC9706, EC9716, EC9718, EC9722, EC9724, EC9728, EC9730, EC9775, EC9776, EMI X03
EC9773, EC9774,EC9701, EC9751, EL4901 by EMI required
A 2011 12/21 43 Change PU4301 IC to lastly version. Power X01 <Core Design> A
2011 12/21 44 Change PU4401 IC to lastly version. Power X01

Wistron Corporation
2011 12/21 40 Design change PU4002 by power request Power X01 Taipei Hsien 221, Taiwan, R.O.C.
Title
2011 12/21 27 Add R2716 to modify PSL circuit. EE X01
Change History
2011 12/23 82 Swap USB1, USB10 signal to TR8202 TR8201 for layout EE X01 A3
BMW Z4 DIS A00
5 4 3 2 1
5 4 3 2 1
2012 2/16 27 Change PCB version to X03, X02 is for VCCSA LDO version verify. EE X03
2012 2/16 97 Add EC9777, EC9778, EC9779, EC9780, EC9781, EC9782, EC9783, EC9784, EC9785, EC9786, EMI X03
EC9787, EC9788 by EMI required
D D
2012 2/16 8 Del C819, add C815 EE X03
2012 2/16 40, 41, 42 Change Pad type, change to green cover type. EE X03
43, 44, 45
46, 47, 48
92, 93
2012 2/16 45 Add EL4501, EL4502 by EMI required. EMI X03
2012 2/16 92, 93 Reserved EC9201, EC9202, EC9203, EC9301, EC9302, EC9303 by RF required. RF X03
2012 2/16 49 Add EC4901, EC4902, EC4904, EC4905, EC4906, EC4908, EC4909, EC4910, EC4911, EC1524, RF X03
EC1428, EC2409, EC2305, EC4528, EC4521, EC4507, EC9789, EC9790 by RF required.
2012 2/20 41, 43, 44 Add Power Gap PG4115, PG4116, PG4117 EG4308, EG4309, EG4310. EG4311, EG4408 Power X03
EG4409, EG4410, EG4411 for power team
2012 2/21 93 Add PQ9304 for fine tune GPU sequence EE X03
C C
2012 2/21 42 Change PR4236 to 953ohm, PR4239 to 300ohm Power X03
2012 2/21 14, 97 Change EC9778, EC9779, EC9780 to EC1406, EC1407, EC1408 by layout. EE X03
2012 2/29 59 Change C5902 P/N. EE X03
2012 3/15 82, 85, 39 DY R8501, R8204, TPAN1, R3901 EE A00
2012 3/15 27 Change R2724 to 64.9k for A00 PCB version EE A00
2012 3/15 71, 82 Change DB1 and CRTBD1 to green cover type symbol. EE A00
2012 3/15 85 Pop R8535 EE A00
2012 3/22 68 Del WLAN LED control power rail circuit. EE A00
2012 3/23 20, 22, 62 Change ER8201, ER8202, ER8203, ER8204, R6503, R6506, R6601, R6602, ER8205, R2205, R3113, EE A00
65, 48, 40 R6281, R6282, R6283, R6284, R6616, PR4022, PR4801, PR4803, RN2012, RN2014, RN2017,
B 66, 82 to short pad and del TR6501, TR6601, TR8201, TR8202, TR6205, TR6206. B
2012 3/27 82, 97 Pop EC8207, EC9734, reserved ER1807 by EMI request. EMI A00
2012 3/27 49, 62 Del R6279, R6280, R4903, R4906 by PSE request EE A00
2012 3/27 69 Change R6909 to 0603 type. EE A00
2012 3/27 49 Change RN4902 to 100 Ohm. EE A00
2012 3/27 21 Change R2136 R8612 to short pad, and change RN2101 to R2116, R2121, R2127, R2128 short pad EE A00
2012 3/29 45, 97 Del EL4502 and EC9729 for layout. EE A00
2012 3/30 8 Del C819 for layout. EE A00
A <Core Design> A
Wistron Corporation
Title
Change History
A3
BMW Z4 DIS A00
Date: Monday, April 02, 2012 Sheet 105 of 105
5 4 3 2 1

4327d Wistron DMB40 (BMW-Z4-DIS) 11289-1 Dell Inspiron 14z-5423

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4327d Wistron DMB40 (BMW-Z4-DIS) 11289-1 Dell Inspiron 14z-5423

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5 4 3 2 1

BMW Z4 14" Schematics Document

Intel CPU VT1318+VT1326 42,43

10/100 Lan High Definition Audio VGA DC/DC

USB3.0 / PowerShare USB3.0 Redriver Right side Switches

Fan Control NUVOTON SPI

Name Schematics Notes Pin Name Configuration Schematic Notes

PCI EXPRESS -- GRAPHICS

62R2J-GP H_PECI A48 AT30 SM_DRAMRST# SM_DRAMRST# [37]

R513 BF44 SM_RCOMP_0 R506 1 2 140R2F-GP

JTAG & BPM

R510 J61 XDP_BPM7 XDP_BPM7 [71]

DDR SYSTEM MEMORY B

M_A_DQ38 AT48 AK55 M_A_DQS#7 M_B_DQ39 BE53

TPAD14-OP-GP TP715 1VCC_VAL_SENSE H43

N50 CFG6 PCIE Port Bifurcation Straps

A00 3/30 8.5A

PEG IO AND DDR IO

+V_SM_VREF_CNT VCC_CORE(ULV) 0.3~1.52 33

BC43 TP_VDDQ_SENSE 1 TP901 TPAD14-OP-GP

BA43 TP_VDDQ_VSS 1 TP902 TPAD14-OP-GP

A13 VSS1 VSS91 AM38 BG17 VSS181 VSS250 M4

AE8 VSS36 VSS126 AU1 F19 VSS216 VSS285 T55

NCTF TEST PIN

M_A_DQ2 DQ1 DM3

M_A_DQ11 DQ10 EVENT#

M_A_DQ13 DQ12 VDDSPD

M_A_DQ14 DQ13 SA0_DIMA

M_A_DQ26 DQ25 VDD5

M_A_DQ31 DQ30 VDD10

M_A_DQ35 DQ34 VDD14

M_A_DQ38 DQ37 VDD17

M_A_DQ51 DQ50 VSS

M_A_DQ52 DQ51 VSS

M_A_DQ55 DQ54 VSS

X01 12/13 X01 12/15

[6] M_B_BS0 BA0

M_B_DQ3 DQ2 DM4

DQ8 SCL PCH_SMBCLK [14,20,65,66,69]

M_B_DQ10 DQ9 3D3V_S0 10KR2J-3-GP

M_B_DQ24 DQ23 VDD3

M_B_DQ29 DQ28 VDD8

M_B_DQ33 DQ32 VDD12

M_B_DQ35 DQ34 VDD14

M_B_DQ36 DQ35 VDD15

VTT2. M_B_DQ53 DQ52 VSS

M_B_DQ56 DQ55 VSS

SRN2K2J-1-GP [49] L_BKLT_CTRL P45 L_BKLTCTL SDVO_STALLN AM42

Digital Display Interface

X02 2/13 RN1801

R1823 SATA_ODD_DA# 3 8 PCH_GPIO05

Size Document Number Rev

A18 DSW ODVREN RTC_AUX_S5 DSW ODVREN R1917 1 2 330KR2J-L1-GP

System Power Management

[27] AC_PRESENT AC_PRESENT H20 G16 PM_SLP_SUS# 1 TP1904 TPAD14-OP-GP

BATLOW # E10 AP14 H_PM_SYNC H_PM_SYNC [5]

PM_RI# A10 K14 PM_SLP_LAN# 1 TP1905 TPAD14-OP-GP

R1909 1 2 100KR2J-1-GP AC_PRESENT

R1908 2 1 10KR2J-3-GP PM_RSMRST# Wistron Corporation

PCH (DM I/FDI/PM)

SSID = PCH S5 power rail CLKREQ#: 3D3V_S0

PCIECLKRQ[0]# 1 4 PCIE_CLK_REQ2# PCIE_CLK_RQ2# S0 power rail CLKREQ#: SMB_CLK 4 1 RN2003

CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64 Optimus(NV) 1 1