3.

8 Technology-related CAD issues

As the layout of an integrated circuit is being prepared, there are layout rules that must be
observed in order to ensure that the integrated circuit is manufacturable. Layout rules arise, in
part, from the fact that at each mask step in the process, features of the next photo mask must be
aligned to features previously defined on the integrated circuit. Even when using precision
automatic alignment tools, there is still some error in alignment. In some cases, alignment of two
layers is critical to circuit operation. As a result, alignment tolerances impose a limitation of
feature size and orientation with respect to other layers on the circuit.

Electrical performance requirements also dictate feature size and orientation with respect to other
layers. An example of this is the allowable distance between diffusions supporting a given
voltage difference. Understanding the rules associated with electrical performance is most
important to the designer if circuits are to be designed that challenge the limits of the technology.
The limits for these rules are constrained by the process conditions. Consider the example of
wire spacing; a designer wants wires close together that have denser layout. The fabrication
process may not be accurate to draw wires too close together. A general set of standard rules for
many processes is usually good enough. MOSIS is an economically viable integrated circuit
fabrication service where one can purchase prototype and small-volume production quantities of
integrated circuits. MOSIS Scalable CMOS (SCMOS) is a set of logical layers together with
their design rules, which provide a nearly process and metric independent interface to all CMOS
fabrication processes available through MOSIS. The designer works in the abstract SCMOS
layers and metric unit ("lambda"; not to be confused with the channel length modulation
parameter l ). Designer then specifies which process and feature size he wants the design to be
fabricated. MOSIS maps the SCMOS design onto that process, generating the true logical layers
and absolute dimensions required by the process vendor. The designer can often submit exactly
the same design, but to a different fabrication process or feature size. MOSIS alone handles the
new mapping. All lengths in the layout are in terms of multiples of 's. For example, minimum
transistor length is 2 , minimum wire spacing is 3 , etc. The actual value of can be chosen
later depending on the target technology (typically, feature size is 2 ).

The masks are the interface between a semiconductor manufacturer and the chip designer. In
design of a working chip, one should make sure that the mask is prepared according to specific
geometric design rules. In addition, interrelationship ship between masks must be ensured to
result the correct interconnected set of circuit elements. CAD tools are used to check these two
requirements and Magic is a very old layout tool released from Berkeley in 1986. Magic is
extraordinarily powerful, and today is still quite capable of large-scale designs, either analog or
digital. Magic is available in public domain and recent updates to Magic keep its features on par
with "industry standard" layout tools. Other industry standard layout tools come from Mentor
Graphics, Cadence, and from in-house CAD groups (e.g. Intel and DEC). Magic is an interactive
system for creating and modifying VLSI circuit layouts.

In Magic, one uses a color graphics display and a mouse to design basic cells and to combine
them hierarchically into larger structures. The Magic is more than just a color-painting tool: it
understands quite a bit about the nature of circuits and uses this information to provide additional
operations. For example, Magic has built-in knowledge of layout rules; as one is editing, it
continuously checks for rule violations. Magic also knows about connectivity and transistors, and
contains a built-in hierarchical circuit extractor. Magic also has a plow operation that one can use
to stretch or compact cells. Lastly, Magic has routing tools to make the global interconnections in
the circuits.

The only layers the designer needs to use are:

ndiff, pdiff, nwell

ndc, pdc, nwc, pwc, poly

nfet, pfet, m1, m2, via

Magic will automatically convert these paint layers to mask layers when it does CIF generation.
By restricting the designer to using these designated layers (called design paint layers), Magic
minimizes the trouble into which the designer can get. Magic allows faster Incremental Design
Rule Checking (Incremental DRC), Extraction and CIF Generation. All three of these tasks are
controlled by the technology file. The technology file is a set of rules that specify the fab
technology. The MOSIS fab uses "Scalable CMOS" (SCMOS) tech rules and the highlights are
given in Table 11.

Table 11 : Highlights of based S calable CMOS (SCMOS) technology rules

LAYER WIDTH SPACE

poly 2 3
Diff 3 3
metal1 3 3
metal2 3 4
nwell 10 9
cut 2 2
via 2 3
When a layout is made in Magic, the system automatically checks design rules. Every time the
layout is edited, Magic rechecks for any violation in any of the layout rules. In case of any
violation of rules, Magic will display little white dots in the vicinity of the violation. This error
paint will stay around until the problem is fixed and when the violation is corrected, the error
paint will go away automatically. To verify the layout, Magic creates an .ext netlist containing
transistors and capacitors. This can then be incorporated into Spice or sim netlists. All values
(cap per area for each layer) are defined in the techfile, so you need to specify for which process
you are extracting.

The most important characteristic of the SCMOS technology is that it is flavor-less and scalable:
layouts designed using the SCMOS rules may be fabricated in either N-well or P-well
technology at a variety of feature sizes. The lambda units used in Magic are dimensionless and
can be scaled to dimensions such as 0.6 microns/lambda, 1.0 microns/lambda, 1.5
microns/lambda, etc. In order for SCMOS designs to be fabricated with either N-well or P-well
technology, both p-well and n-well contacts must be placed, and where wells and rings are
specified explicitly (e.g. in pads) both flavors must be specified. When the circuit is fabricated,
one of the flavors of wells, rings, and substrate contacts will be ignored. The SCMOS technology
provides two levels of metal. All contacts are to first-level metal.

In most cases design rules are unique to each wafer manufacturer. Rules change from fab to fab,
process to process. The design rules for the particular wafer manufacturer should be obtained
before the design is begun and consulted during the design. This is especially important in the
design of state-of-the-art analog CMOS. However, the principles developed here should remain
unaltered while translated to specific processes.

Fig. 3.72: (a) CMOS inverter circuit

 Fig. 3.72 (b) : CMOS inverter magic layout

Fig. 3.72 (c) : CMOS inverter cross sectional view

The development of a CMOS inverter the circuit from circuit design, circuit layout and a
fabricated cross-sectional point of view is shown in Fig 3.72. The formation of the various levels
which make up the finished CMOS inverter has already been discussed in previous sections. A
circuit designer sees things from above, and only worries about the placement of transistors, and
how they will be connected together. In fact, the only factor in the actual design of the layout
engineer has any choice on is the transistor width, W. All other parameters are decided before
hand by the process engineer.