ELECTRICAL POWER DISTRIBUTION SYSTEM MODELING WITH VHDL-
AMS FOR THE CONSTRUCTION OF A REAL-TIME DIGITAL SIMULATOR
USING FPGAS DEVICES
Frank Alberto Ibarra Hernndez, Carlos Alberto Canesin
Power Electronics Laboratory Electrical Engineering Department So Paulo State University UNESP FE/IS
Av. Jos Carlos Rossi, 1370, 15385-000, Ilha Solteira-SP, Brazil
canesin@dee.feis.unesp.br, faihee@gmail.com
Abstract This paper presents a distribution feeder
simulation using VHDL-AMS, considering the standard
IEEE 13 node test feeder admitted as an example. In an
electronic spreadsheet all calculations are performed in
order to develop the modeling in VHDL-AMS. The
simulation results are compared in relation to the results
from the well knowing MatLab/Simulink environment, in
order to verify the feasibility of the VHDL-AMS
modeling for a standard electrical distribution feeder,
using the software SystemVision. This paper aims to
present the first major developments for a future Real-
Time Digital Simulator applied to Electrical Power
Distribution Systems.
Keywords - Distribution power systems, FPGA devices,
Hardware description languages, Real-time digital
simulation, VHDL-AMS.
I. INTRODUCTION
The software commonly used for load flow and fault
analysis of an electrical distribution feeder often has no
capability for user-defined models. Such models may
become necessary, with the recent widespread penetration on
the feeders of new rotating machine types, modern power
electronics devices (like FACTS controller devices, static
power converters, active power filters and other devices for
applying technology for ubiquitous sensing and data
communication), and distributed alternative generator
resources. In this context, the software developer must
implement a new amount of models for the final user, who
may not then use the models to someone using different
software [1]. Therefore, for this and others reasons, it was
proposed the use of the VHDL-AMS in this paper.
On the other hand, the paper presents the development of
a power system that will be the start point of a real-time
simulator based on FPGA. The simulator will be developed
using the language of description of the hardware VHDL-
AMS, allowing fast response and exactness in the processing,
making possible the interaction with peripheral systems of
control and consisting in HIL (Hardware in the Loop)
simulation platform.
II. VHDL-AMS MODELING LANGUAGE
In summary, VHDL-AMS is required to be a superset of
VHDL 1076-1993, supporting the hierarchical description
and simulation of continuous and mixed-continuous/discrete
system with conservative and non conservative semantics.
The language must support modeling at various abstraction
levels in electrical and non-electrical energy domains. The
systems to be modeled are lumped systems that can be
described by ordinary differential equations and algebraic
equations; the solution of the equations describing the
behavior of the system may include discontinuities [2]. On
the other hand, experimental analysis alone is often
impractical or non-sufficient for thorough characterization;
furthermore, the interfacing of discipline-specialized
simulation programs is not trivial, costly and time
consuming. Thus, the availability of a unified comprehensive
simulation platform is gaining high interest [3].
Although designed with analog electronic circuits in mind,
VHDL-AMS is general enough to handle other types of
systems. VHDL-AMS also provides mixed-discipline
modeling, wherein different domains such as electrical,
physical, and thermal, can be described and simulated in a
single entity. Any problem that can be defined by a
combination of event queues (digital) or simultaneous
differential algebraic equations (analog) can be simulated
with VHDL-AMS [4].
In order to evaluate the performance of a VHDL-AMS
simulator, three fundamental properties have to be
considered: Correctness, Efficiency and the Capability to
perform the simulation [5]. Correctness is defined by the
semantics of VHDL-AMS language and has to be ensured by
the implemented algorithms. Efficiency is measured in terms
of simulation speed. Performance capability includes issues
such as resource requirements and language support.
III. TEST FEEDER AND COMPONENT MODELS
In 1991 a paper was published by [6] that presented the
complete data for three-phase four-wire wye and three-phase
three-wire delta radial electrical distribution test feeders. The
purpose of publishing the data was to make available a
common set of data that could be used by program
developers and users, in order to verify the correctness of
their solutions. In this way, this paper uses the IEEE 13 Node
Test Feeder to illustrate the VHDL-AMS models. This feeder
is very small and yet displays some very interesting
characteristics:
1) Short and relatively highly loaded for a 4.16 kV
feeder (where zero power single-phase loads are Short
Circuit); 2) One substation voltage regulator consisting of
three single-phase units connected in wye; 3) Overhead
and underground lines with variety of phasing; 4) Shunt
capacitor banks; 5) In-line transformer, and 6) Unbalanced
spot and distributed loads; as shown in Fig. 1.
 68.21 kW;
Y-PQ Load 60.55 kVAr Y-PQ Load Constant
Power Loads
Constant 42.63 kW; a Constant 486.02 kW; 289.91 kW;
189.07 kVAr 212.65 kVAr Shunt Capacitors Connected Delta
20.18 kVAr Power Loads
Power Loads
34a 34b 34c 34n
75a
71c
33a 33b 33c 33n 75a 75b 75c 75n 75b
383.70 kW; 383.70 kW; 75c 0.0000306558F 0.0000306558F
D-PQ Load

0.05610; 0.00022721

0.05610; 0.00022721

0.05610; 0.00022721
0.05610; 0.00022721

0.0388; 0.00010993

0.0388; 0.00010993
200 kVAr 200 kVAr

0.0388; 0.00010993
219.95 kVAr 219.95 kVAr

R[ohm]; L[H]

R[ohm]; L[H]

R[ohm]; L[H]
R[ohm]; L[H]

R[ohm]; L[H]

R[ohm]; L[H]

R[ohm]; L[H]
0.0000306558F

ELECTRICAL SUBSTATION 71a 71b 200 kVAr

383.70 kW;
219.95 kVAr

R[ohm]; L[H] R[ohm]; L[H] R[ohm]; L[H]

Phase A 92a
50A 50a 0.07040; 0.00074543 32a 32a 0.0352; 0.00037272 0.0352; 0.00037272 71a
Phase B D-I Load

1e
9
Voltage Constant

O
hm
R[ohm]; L[H] R[ohm]; L[H] R[ohm]; L[H] 170.53 kW;
Phase C Regulator with 92b
151.38 Current
50B 122V Voltage 50b 0.07040; 0.00074543 32b 32b 0.0352; 0.00037272 0.0352; 0.00037272 71b kVAr
Loads

hm
Level

O
9
1e
A B C R[ohm]; L[H] R[ohm]; L[H] R[ohm]; L[H]
92c
50C 50c 0.07040; 0.00074543 32c 32c 0.0352; 0.00037272 0.0352; 0.00037272 71c
150a 150b 150c 150n In the 150 node there is no load.
R[ohm]; L[H] R[ohm]; L[H] R[ohm]; L[H]
5000 kVA Transformer;
115 kV D / 4160 kV Y 50n 32n 32n
R[ohm]sec = 0.0346
0.2242; 0.00090885 0.1121; 0.00045443 0.1121; 0.00045443 71n
Substation - 115000 V
3f balanced phase L[H]sec = 0.0007345

0.0636; 0.00015630
0.1061; 0.00026050

0.1061; 0.00026050

0.1061; 0.00026050

0.1061; 0.00026050

0.0636; 0.00015630

0.0636; 0.00015630

0.0636; 0.00015630
voltages: 66,395.3 V
R[ohm]; L[H]

R[ohm]; L[H]

R[ohm]; L[H]

R[ohm]; L[H]

R[ohm]; L[H]

R[ohm]; L[H]

R[ohm]; L[H]
Voltage L-L: 115 kV

R[ohm]; L[H]
127.90 kW;
Y-PQ Load 85.79 kVAr
45a 84a R[ohm]; L[H] 52a R[ohm]; L[H]

Constant 45b Constant

0.0920; 0.00009818 31.11; 0.055332869

45c a b c 84b R[ohm]; L[H] 52b
Power Loads b Power Loads
0.0920; 0.00009818
45n R[ohm]; L[H]
Y-Z Load
16.48 kW; 116.97 kW; 84c 52c
Y-PQ Load 9.45 kVAr 67.05 kVAr
0.0636; 0.00015630
0.0636; 0.00015630

0.0636; 0.00015630

0.0920; 0.00009818
170.53 kW;
R[ohm]; L[H]

R[ohm]; L[H]

R[ohm]; L[H]

66.40 kW;
125.09 kVAr
38.06 kVAr 84n R[ohm]; L[H] 52n
0.0920; 0.00009818

0.0636; 0.00015015

0.0636; 0.00015015

0.0636; 0.00015015

0.0636; 0.00015015
R[ohm]; L[H]

R[ohm]; L[H]

R[ohm]; L[H]

R[ohm]; L[H]

46a 46b 46c
R[ohm]; L[H]

1e9 Ohm 56.58; 0.08602325 1e9 Ohm 911a 911b 911c 911n
230.22 kW; 0.0000459837 F
131.97 kVAr 100 kVAr

D-Z Load 170.53 kW;

80.74 kVAr

Constant
Y-I Load
Current Loads

Fig. 1. IEEE 13 Node Test Feeder, as example for modeling with VHDL-AMS.

architecture of v_sine is
Considering that the above IEEE 13 Node Test Feeder function calc_limit(freq : real) return real is
was developed using the software SystemVision (Provided variable lim : real;
by the Mentor Graphics Company), VHDL-AMS basic begin
models of electric components, which will serve to build up if freq = 0.0 then
the real-time simulator, are presented as follows: lim := 1.0e12; -- A large value
elsif freq < 0.0 then
A. Single-Phase Voltage Source Model lim := 1.0 / (-20.0 * freq);
The distribution feeder substation was modeled using three else
single-phase voltage sources wye connected and three single- lim := 1.0 / (20.0 * freq);
phase transformer 115 kV delta - 4.16 kV grounded wye, in end if;
addition to a voltage regulator with 122 V voltage level. return lim;
The used Single-Phase Voltage Source VHDL-AMS end function;
Model is given by: constant v_limit : real := calc_limit(freq);
quantity v across i through pos to neg;
library IEEE; limit v : voltage with v_limit;
use IEEE.MATH_REAL.all; quantity phase_rad : real;
-- Use IEEE natures and packages quantity ac_spec : real spectrum ac_mag,
use IEEE.ELECTRICAL_SYSTEMS.all; math_2_pi*ac_phase/360.0;
entity v_sine is begin
generic ( phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
freq : real:= 60.0; -- frequency [Hertz] if domain = quiescent_domain or domain = time_domain
amplitude : voltage:= 115000.0; -- amplitude [Volts] use
phase : real:=0.0; -- initial phase [Degrees] v == offset + amplitude * sin(phase_rad) * exp(-now * df);
offset : voltage := 0.0; -- DC value [Volts] else
df : real := 0.0; -- damping factor [1/second] v == ac_spec;
ac_mag : voltage := 0.0; -- AC magnitude [Volts] end use;
ac_phase : real := 0.0); -- AC phase [Degrees] end architecture;
port (terminal pos, neg : electrical);
end entity v_sine;
B. Single-Phase Transformer Model port (terminal pos, neg : electrical);
In this paper was used an formulation similar to [1], with end entity i_sine;
an ideal n:1 transformer on the secondary side, and the r+j.l architecture of i_sine is
impedance on the primary side. The primary voltage on each function calc_limit(freq : real) return real is
winding, e.g. va1, is equal to the secondary winding voltage variable lim : real;
referred to the primary, plus a voltage drop of r.i+l.(di/dt). begin
The secondary current is equal to the primary winding if freq = 0.0 then
current, referred to the secondary side, because this model lim := 1.0e12; -- A large value
ignores the exciting impedance. elsif freq < 0.0 then
The used Single-Phase Transformer VHDL-AMS Model is lim := 1.0 / (-20.0 * freq);
given by: else
lim := 1.0 / (20.0 * freq);
library IEEE; end if;
use IEEE.electrical_systems.all; return lim;
use IEEE.fundamental_constants.all; end function;
entity transformer is constant i_limit : real := calc_limit(freq);
generic ( quantity v across i through pos to neg;
kv1: Kilo voltage := 115.0; limit i : current with i_limit;
kv2: Kilo voltage := 2.401; quantity phase_rad : real;
mva: real := 1.667; quantity ac_spec : real spectrum ac_mag,
freq: real := 60.0; math_2_pi*ac_phase/360.0;
x_pct : real := 8.0; begin
r_pct : real := 1.0); phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
port (terminal a1, b1, a2, b2); if domain = quiescent_domain or domain = time_domain
end entity transformer_phy; use
architecture transfomer is i == offset + amplitude * sin(phase_rad) * exp(-NOW *
constant omega : real := freq*math_2_pi; df);
constant n : real := kv1 / kv2; else
constant zbase : real := kv1 * kv1 / mva; i == ac_spec;
constant r : resistance := 0.01 * r_pct * zbase; end use;
constant l : inductance := 0.01 * x_pct * zbase / omega; end architecture;
quantity mmf across flux through mag1 to mag2;
quantity va1 across ia1 through a1 to electrical_ref;
quantity vb1 across ib1 through b1 to electrical_ref; D. Resistor Model
quantity va2 across ia2 through a2 to electrical_ref;
quantity vb2 across ib2 through b2 to electrical_ref; library IEEE;
begin use IEEE.electrical_systems.all;
va1 == n * va2 + r * ia1 + l * ia1'dot; entity resistor is
vb1 == n * vb2 + r * ib1 + l * ib1'dot; generic (
ia2 == -n * ia1; res : resistance); -- resistance (no initial value)
ib2 == -n * ib1; port (terminal p1, p2 : electrical);
end architecture; end entity resistor;
architecture of resistor is
The following general VHDL-AMS basic models of quantity v across i through p1 to p2;
electric components were used several times in the modeling begin
of the circuit shown in Fig. 1. v == i*res; -- Fundamental equation
end architecture;
C. Single-Phase Current Source Model
E. Inductor Model
library IEEE;
use ieee.math_real.all; library IEEE;
use IEEE.electrical_systems. all; use IEEE.electrical_systems.all;
entity i_sine is entity inductor is
generic ( generic (
freq : real; -- frequency [Hertz] ind : inductance; -- Nominal inductance
amplitude : current; -- amplitude [Amps] i_ic : real := real'low); -- Initial current
phase : real := 0.0; -- initial phase [Degrees] port (terminal p1, p2 : electrical);
offset : current := 0.0; -- DC value [Amps] end entity inductor;
df : real := 0.0; -- damping factor [1/second] architecture of inductor is
ac_mag : current := 0.0; -- AC magnitude [Amps] quantity v across i through p1 to p2;
ac_phase : real := 0.0); -- AC phase [Degrees] begin
 if domain = quiescent_domain and i_ic /= real'low use Based on the above and on the specifications of selected
i == i_ic; feeder, all engineering calculations (Resistances,
else Inductances, capacitances and types of loads) were made
v == ind * i'dot -- Fundamental equation with a degree of appropriate accuracy, in an electronic
end use; spreadsheet, for after to implement the modeling in VHDL-
end architecture; AMS. These simulations were confronted using the highly
customizable industry-standard MATLAB/SIMULINK
F. Capacitor Model environment (Library SimPowerSystems). Some significant
results from the simulations are shown in Figs. 2 until 5.
library IEEE; The following five tables contain a qualitative and
use IEEE.electrical_systems.all; quantitative description of the simulation results shown in
entity capacitor is Figs. 2 until 5. Table I apply to all subsequent four figures,
generic ( but the tables II until V, are directly related to each of the
cap : capacitance; -- Capacitance [F] four figures as well: Table II with Fig. 2, Table III with Fig.
v_ic : real := real'low); - Initial voltage 3 and so on.
port (terminal p1, p2 : electrical); TABLE I
end entity capacitor; Captions Fig. 2 until Fig. 5
architecture of capacitor is Color and Style Meaning
quantity v across i through p1 to p2; Va (Ia) Matlab Simulink
begin Vb (Ib) Matlab Simulink
if domain = quiescent_domain and v_ic /= real'low use Vc (Ic) Matlab Simulink
Va (Ia) VHDL-AMS Simulation
v == v_ic; Vb (Ib) VHDL-AMS Simulation
else Vc (Ic) VHDL-AMS Simulation
i == cap * v'dot; -- Fundamental equation
end use; TABLE II
end architecture. Three-phase voltages at the output of the voltage
regulator (phase voltages)
IV. VHDL-AMS SIMULATION FOR THE DESCRIPTION
RMS Value
OF THE ELECTRICAL DISTRIBUTION FEEDER %Error
Phase

Steady State
Simulation
Measurement at 5 seconds
Methods
Modeling is at the core of any design process. This task VHDL-AMS SIMULINK
essentially consists in developing abstract descriptions of A 2,522.16 2,523.11 0.038%
some physical reality in such a way that they are useful for B 2,522.28 2,522.34 0.002%
C 2,522.30 2,522.32 0.001%
the design process. Models may be used to validate
characteristics of some part of or the whole designed system,
e.g., its functionality or its performances. Such models are TABLE III
simulation models, or executable models that produce a Line currents flowing through the voltage regulator
response when acted upon by stimuli. Models may describe RMS Value
%Error
Phase

Steady State
the behavior and/or the structure of the designed system at Simulation
Measurement at 5 seconds
various levels of details, or levels of abstraction. Selecting Methods
VHDL-AMS SIMULINK
the appropriate level is, on the other hand, a matter of A 21,289.26 21,332.1 0.201%
compromise between model accuracy and model B 21,106.13 21,089.3 0.080%
performance, and furthermore, a means to cope with system C 21,366.97 21,412.1 0.211%
complexity [7].
Digital simulation of power systems is essentially a step- TABLE IV
by-step numerical solution of the system's differential Three-phase voltages at node 75 (phase voltages)
equations. Hence, digital simulators cannot give a continuous RMS Value
%Error
Phase

Steady State
history of the system's variables, e.g. voltages and currents, Measurement at 5 seconds
Simulation
but rather a sequence of snapshots at discrete time intervals. Methods
VHDL-AMS SIMULINK
The simulation time-step (t) directly defines the fastest A 143.50 143.25 0.173%
transient that can be accurately represented. However, as the B 383.07 390.22 1.831%
time-step is decreased the computation time required to C 144.61 145.25 0.439%
complete the required calculations increases. A primary
distinction between different types of digital simulators is the TABLE V
speed at which the calculations are performed to generate Three-phase voltages at node 71 (phase voltages)
corresponding data points of the waveforms. If the time RMS Value
%Error
Phase

Steady State
required for computation of each data point is less than the Measurement at 5 seconds
Simulation
time-step, the computation is said to be in real-time, and if Methods
VHDL-AMS SIMULINK
the computation time is greater than the simulation time-step, A 208.19 207.34 0.409%
the waveforms are generated off-line [8]. B 404.15 400.12 1.007%
C 275.78 270.56 1.929%
 3000

2000

1000
Voltage (V)

-1000

-2000

-3000
4.9 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 5
Time (s)
Fig. 2. Three-phase voltages at the output of the voltage regulator (phase voltages).
4
2.5 x 10
2
1.5
1
Current (A)

0.5
0
-0.5
-1
-1.5
-2
-2.5
4.9 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 5
Time (s)
Fig. 3. Line currents flowing through the voltage regulator.

400

300

200

100
Voltage (V)

-100

-200

-300

-400
4.9 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 5
Time (s)
Fig. 4. Three-phase voltages at node 75 (phase voltages).
 500
400
300
200
Voltage (V)
100
0
-100
-200
-300
-400
-500
4.9 4.91 4.92 4.93 4.94
Fig. 5. Three-phase voltages at node 71 (phase voltages).
V. CONCLUSIONS AND FUTURE WORK
In this paper was used the VHDL-AMS to model the
standard IEEE 13 node test electrical feeder.
From the results, considering the comparisons with a well
knowing simulation platform (MatLab/Simulink), one can
conclude: 1) The output voltages from the transformer are
balanced three-phase of 1.00 per unit; 2) The three-phase
feeder is unbalanced and includes three types of loads:
Constant kW and kVAr, Constant Impedance (Z) and
Constant Current (I); and 3) According to the steady state
RMS value measured at 5 second, the greatest error among
the results from the two simulation methods was observed in
the C phase at node 71, and its value was equal to 1.929%. It
should be pointed out that, with the same simulation tool, we
can optimize the system to fulfill the national criteria for
voltage regulation.
Finally, it should be informed that this paper is as part of
initial development for a real-time digital simulator that will
allow the simulation of electrical power distribution feeders
(low and medium voltage levels), considering its typical
physical and operational aspects (sources, lines of
distribution, transformers, linear and non-linear loads,
devices of regulation and compensation), using structures
with description of the hardware in software through FPGAs
devices. In this context, the simulator will be developed
using the language VHDL-AMS, allowing fast response and
exactness in the processing, making possible the interaction
with peripheral systems of control and consisting in HIL
(Hardware in the Loop) simulation platform.
Based on the above and on the exposed in [8], we intend
that our future real-time digital simulator will include the
following attributes:
It will make an effort to introduce and develop a
reconfigurable hardware simulator using FPGAs to
simulate power systems that contains power
electronic switching elements.
4.95 4.96 4.97 4.98 4.99 5
Time (s)
Typically uses a 50 s simulation time-step, or less.
Reducing the simulation time-step improves the
accuracy of the simulator as the error due to inter-
simulation time-step switching is reduced. If the
simulation time-step is hundred times less than the
switching period, there is no need to synchronize the
simulator and the controller under test, as the error
due to asynchronous operation can be neglected.
Due to the sequential nature of processors (either
General Purpose Processors or Digital Signal
Processors), the simulation time-step of the existing
processor-based real-time digital simulators cannot be
small enough to simulate switching networks with the
desired accuracy. However, the simulation time can
be greatly reduced if the simulator's hardware is
custom configured.
The modeled power system will be implemented in an
FPGA chip such that the calculation time is smaller
than the simulation time-step.
FPGA devices are very efficient in performing
mathematical operations, and especially
multiplication operations. Parallel hardware
multipliers can be implemented as required, allowing
simultaneous calculations. FPGAs have also the
advantage of flexible word size, therefore precision is
not lost and no extra resources are consumed.
ACKNOWLEDGEMENT
The authors gratefully acknowledge the So Paulo
Research Foundation FAPESP for financial support to
development a digital simulator in real time that allows the
simulation of distribution electric energy systems.
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