CXA2104S

US Audio Multiplexing Decoder

Description
The CXA2104S is an IC designed as a decoder for 30 pin SDIP (Plastic)
the Zenith TV Multi-channel System and also
corresponds with I2C BUS. Functions include stereo
demodulation, SAP (Separate Audio Program)
demodulation, dbx noise reduction. Various kinds of
filters are built in while adjustment and mode control
are all executed through I2C BUS.

Features
Adjustment free of VCO and filter. Absolute Maximum Ratings (Ta = 25C)
Audio multiplexing decoder and dbx noise Supply voltage VCC 11 V
reduction decoder are all included in a single chip. Operating temperature Topr 20 to +75 C
Almost any sort of signal processing is possible Storage temperature Tstg 65 to +150 C
through this IC. Allowable power dissipation
All adjustments are possible through I2C BUS to PD 1.35 W
allow for automatic adjustment.
Various built-in filter circuits greatly reduce external Range of Operating Supply Voltage
parts. 9 0.5 V
There is an additional SAP output.
Applications
Standard I/O Level TV, VCR and other decoding systems for US audio
Input level multiplexing TV broadcasting
COMPIN (Pin 11) 100mVrms
245mVrms (Selected by INSW) Structure
Output level Bipolar silicon monolithic IC
TVOUT-L/R (Pins 2 and 1) 490mVrms

A license of the dbx-TV noise reduction system is

Pin Configuration (Top View)
required for the use of this device.
NOISETC
VCAWGT

SUBOUT
SAPOUT
VEWGT
VEOUT
VCATC

VCAIN

SAPIN
SOUT

VETC

STIN

VCC
NC

VE

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MAINOUT
DGND
SDA

GND
TVOUT-R

VGR
PLINT
PCINT1
MAININ
SCL

SAPTC
TVOUT-L

IREF
COMPIN
PCINT2

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

1
E97726B96-PS
 Block Diagram

PCINT2
SUBOUT
MAINOUT
MAININ

PLINT

PCINT1
8 9 10 17 7 6
STLPF

LFLT VCO 1/4 1/2

2 TVOUT-L
MATRIX
1 TVOUT-R
FLT LPF VCA

"STEREO" WIDEBAND
COMPIN 11 VCA LPF DeEm LPF NRSW/FOMO/SAPC

(+6dB)
ATT/INSW STIND
VCC 16
LOGIC

2
GND 14
BPF SAPVCO LPF LPF 30 SOUT

DeEm VE VCA

NOISETC 19 NOISE
DET "NOISE"

HPF RMSDET
"SAP"
SAPTC 15 SAPIND

SPECTRAL
AMP RMSDET
LPF LPF
(+4dB)

IREF I2C BUS I/F

SW
"PONRES"

12 13 5 4 3 20 21 18 22 23 24 25 26 28 27
VE

SCL
SDA

VGR
IREF
STIN
VETC

SAPIN
VCAIN

DGND
VCATC

VEOUT

VEWGT

SAPOUT
VCAWGT
CXA2104S
 CXA2104S

Pin Description (Ta = 25C, VCC = 9V)

Pin Pin
Symbol Equivalent circuit Description
No. voltage
VCC
3k
1 TVOUT-R 4.0V TVOUT right channel output
pin.

580
1
2 580

TVOUT left channel output

2 TVOUT-L 4.0V pin.

VCC
7.5k

35
2.1V
4k
2 Serial data I/O pin.
3 SDA VIH > 3.0V
4.5k 5
7.5k 3k VIL < 1.5V

VCC
7.5k

35
2.1V
4k
Serial clock input pin.
4 SCL VIH > 3.0V
10.5k 4 3k VIL < 1.5V

5
5 DGND Digital block GND.

VCC
10k

VCC
Input the (L + R) signal from
6 MAININ 4.0V
MAINOUT (Pin 7).
147
6
53k

4V

3
 CXA2104S

Pin Pin
Symbol Equivalent circuit Description
No. voltage

VCC
15k
4
VCC

147
7 MAINOUT 4.0V 7
(L + R) signal output pin.

1k
200

VCC

147
8
30k
8 PCINT1 4.0V

22k

Stereo block PLL loop filter

VCC integrating pin.

147
9

9 PCINT2 4.0V 10k 10k

2k

2
4k

VCC
20k 20k

147 Pilot cancel circuit loop filter

10 integrating pin.
10 PLINT 5.1V
(Connect a 1F capacitor
20k 20k between this pin and GND.)

20k 10k
26 50

4
 CXA2104S

Pin Pin
Symbol Equivalent circuit Description
No. voltage
VCC
24k 24k

14k 147
11
Audio multiplexing signal
11 COMPIN 4.0V input pin.
34k

4V
24k

3k 147 Band gap reference output

pin.
12 VGR 1.3V 9.7k 19.4k VCC
11k (Connect a 10F capacitor
11k 11k
between this pin and GND.)
4
12
2.06k

VCC
40k 40k 30k 30k 15k 30k

2
Set the filter and VCO
reference current. The
reference current is adjusted
VCC with the BUS DATA based on
13 IREF 1.3V the current which flows to this
pin.
30p 1.8k
(Connect a 62k (1%)
13
147
resistor between this pin and
GND.)
6.3k
16k

14
14 GND Analog block GND.

VCC
8k

10k

3k 1k Set the time constant for the

SAP carrier detection circuit.
15 SAPTC 4.5V VCC
(Connect a 4.7F capacitor
4k
between this pin and GND.)
50
15

5
 CXA2104S

Pin Pin
Symbol Equivalent circuit Description
No. voltage

16 VCC 16 Supply voltage pin.

Vcc
2k 2k

10P
4k

580
17 SUBOUT 4.0V 17 (LR) signal output pin.
14.4k 580 147
2k 2k

2k 4k 1k

VCC

18 STIN
23k 23k Input the (L-R) signal from
4.0V
SUBOUT (Pin 17).
11.7k

147 147
18 21
Input the (SAP) signal from
21 SAPIN 4.0V 18k 18k
SAPOUT (Pin 20).
4V 20k 4V

Vcc

8k 3.3k

10k
Set the time constant for the
1k 2k
4k noise detection circuit.
19 NOISETC 3.0V 2 (Connect a 4.7F capacitor
4V between this pin and GND.)
3k Vcc 3k

200k
19

6
 CXA2104S

Pin Pin
Symbol Equivalent circuit Description
No. voltage
Vcc
5P

580

20 SAPOUT 4.0V 580 10k SAP FM detector output pin.

20
147

24k 4k
10 50

VCC
7.5k

Variable de-emphasis
integrating pin.
147
22 VE 4.0V 22
(Connect a 2700pF capacitor
and a 3.3k resistor in series
between this pin and GND.)

Vcc

Weight the variable

2.9V de-emphasis control effective
580 4V
23 value detection circuit.
23 VEWGT 4.0V 147 36k (Connect a 0.047F capacitor
580
and a 3k resistor in series
between this pin and GND.)

8k 30k 4k
8 50

Vcc

Determine the restoration

time constant of the variable
de-rmphasis control effective
24
4 4 value detection circuit.
24 VETC 1.7V
(the specified restoration time
constant can be obtained by
20k connecting a 3.3F capacitor
7.5 between this pin and GND.)
4k
50

7
 CXA2104S

Pin Pin
Symbol Equivalent circuit Description
No. voltage

Vcc

5P
Variable de-emphasis output
580
pin.
25 VEOUT 4.0V 25 (Connect a 4.7F non-polar
10k
580 capacitor between Pins 25
and 26.)

VCC

47k 47k
VCA input pin.
20k
Input the variable
26 VCAIN 4.0V VCC de-emphasis output signal
from Pin 25 via a coupling
26
capacitor.

VCC
Determine the restoration
time constant of the VCA
4 27 control effective value
detection circuit.
4
27 VCATC 1.7V (the specified restoration
time constant can be
obtained by connecting a
10F capacitor between this
4k 20k pin and GND.)

50 7.5

VCC
40k 40k 3p

Weight the VCA control

580 effective value detection
28 circuit.
28 VCAWGT 4.0V 2.9V 580 147 (Connect a 1F capacitor
36k
and a 3.9k resistor in series
between this pin and GND.)

4k 30k 8k
50 8

29 NC 29

8
 CXA2104S

Pin Pin
Symbol Equivalent circuit Description
No. voltage
VCC
15k

30 SOUT 4.0V 30 Additional SAP output pin.

200 1k

9
 Electrical Characteristics
INSW = 0 INSW = 1
COMPIN input level
(100% modulation level) Main (L + R)
= 245mVrms = 100mVrms
(Pre-Emphasis: OFF)
SUB (L R) (dbx-TV: OFF) = 490mVrms = 200mVrms
Pilot = 49mVrms = 20mVrms
SAP Carrier = 147mVrms = 60mVrms

fH = 15.734kHz
(Ta = 25C, VCC = 9V)

Measurement Output
No. Item Signal Mode Input pin Input signal conditions Filter Min. Typ. Max. Unit
pin

1 Current consumption Icc No signal 22 32 42 mA

Mono 1kHz 100% mod.

2 Main output level Vmain MONO 11 1/2 440 490 540 mVrms
Pre-em. ON
Main de-emphasis Mono 5kHz 30% mod. 20 log
3 FCdeem MONO 11 1/2 1.2 0 1.0 dB
frequency characteristic Pre-em. ON ('5k'/'1k')
Main LPF frequency Mono 12kHz 30% mod. 20 log
4 FCmain MONO 11 1/2 3.0 1.0 1.0 dB

10
characteristic Pre-em. ON ('12k'/'1k')
Mono 1kHz 100% mod.
5 Main distortion THDm MONO 11 15kLPF 1/2 0.1 0.5 %
Pre-em. ON
Mono 1kHz 200% mod.
6 Main overload distortion THDmmax MONO 11 15kLPF 1/2 0.15 0.5 %
Pre-em. ON
Mono 1kHz, 20 log
7 Main S/N SNmain MONO 11 15kLPF 1/2 61 69 dB
Pre-em. ON ('100%'/'0%')
SUB (L-R) 1kHz,
8 Sub output level Vsub ST 11 17 150 190 230 mVrms
100% mod., NR OFF
Sub LPF frequency SUB (L-R) 12kHz, 20 log
9 FCsub ST 11 17 3.0 0.5 1.0 dB
characteristic 30% mod., NR OFF ('12k'/'1k')
SUB (L-R) 1kHz,
10 Sub distortion THDsub ST 11 15kLPF 17 0.1 1.0 %
100% mod., NR OFF
SUB (L-R) 1kHz,
11 Sub overload distortion THDsmax ST 11 15kLPF 17 0.2 2.0 %
200% mod., NR OFF
SUB (L-R) 1kHz, 20 log
12 Sub S/N SNsub ST 11 15kLPF 17 56 64 dB
NR OFF ('100%'/'0%')
SUB (L-R) 1kHz, 20 log
ST SAP
13 CTst SAP 11 100% mod., NR ON, ('NRSW = 0'/ 1kBPF 2 60 70 dB
CXA2104S

Crosstalk
SAP Carrier (5fH) 'NRSW = 1')
 Measurement Output
No. Item Signal Mode Input pin Input signal Filter Min. Typ. Max. Unit
conditions pin

14 Sub pilot leak PCsub ST 11 PILOT (fH) 0dB 0dB = 49mVrms fH BPF 42 30 dB
17

15 Stereo ON level THst 0dB = 49mVrms 9.0 6.0 3.0 dB

ST 11 Change BUS
Stereo ON/OFF PILOT (fH) Level 20 log (on RETURN
16 HYst 2.0 6.0 10.0 dB
hysteresis level'/'off level')
SAP 1kHz 100% mod. 190
17 SAP output level Vsap SAP 11 20 150 230 mVrms
NR OFF
SAP LPF frequency SAP 10kHz 30% mod. 20 log 3.0 0
18 FCsap SAP 11 20 2.5 dB
characteristic NR OFF ('10k'/'1k')
SAP 1kHz 100% mod. 2.5
19 SAP distortion THDsap SAP 11 15kLPF 20 6.0 %
NR OFF
20 log 46 55
20 SAP S/N SNsap SAP 11 SAP 1kHz, NR OFF 15kLPF 20 dB
('100%'/'0%')
SAP ST SAP 1kHz 100% mod. 20 log ('NRSW 60 70
21 CTsap ST 11 1kBPF 2 dB
Cross talk NR ON, Pilot (fH) = 1'/'NRSW = 0')

22 SAP ON level THsap Change 0dB = 147mVrms 12.0 9.0 6.5 dB

SAP 11 BUS
SAP Carrier (5fH)
RETURN

11
Level 20 log (on 4.0
23 SAP ON/OFF hysteresis HYsap 2.0 6.0 dB
level/off level)
ST-L 300Hz 30% mod. 35
24 ST separation 1 L R STLsep1 ST 11 15kLPF 1/2 23 dB
NR ON
ST-R 300Hz 30% mod. 23 35
25 ST separation 1 R L STRsep1 ST 11 15kLPF 1/2 dB
NR ON
ST-L 3kHz 30% mod. 23 35
26 ST separation 2 L R STLsep2 ST 11 15kLPF 1/2 dB
NR ON
ST-R 3kHz 30% mod. 23 35
27 ST separation 2 R L STRsep2 ST 11 15kLPF 1/2 dB
NR ON
CXA2104S
 Electrical Characteristics Measurement Circuit

S5
S4
BUFF
S3
FILTERS MEASURES
S2
S1 15kHz LPF
fH BPF
1kHz BPF

C2 R2 R5 R7 C17 C20
3.9k C5 C6 C8 3k 3.3k C14 C18
4.7 4.7 100
10 4.7 3.3 4.7 4.7
C4 C9 C12

TANTALUM
TANTALUM
1 0.047 2700P

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VCC

VE

NC
VCC

V2

STIN

VETC

SOUT
SAPIN

VCAIN
9V

VCATC
VEOUT
VEWGT
SAPOUT
SUBOUT

VCAWGT
NOISETC

12
GND

COMPIN

PCINT2

MAINOUT

DGND
GND

SDA
VGR

TVOUT-R
PLINT

PCINT1

MAININ
SAPTC

SCL
IREF

TVOUT-L
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

C1 C3 R1 R3 R6 C13 C15 C16 C19

R8
4.7 4.7 220 220 1MEG 1 4.7 10 62k 4.7
C7
METAL
I2C BUS DATA 4.7 C10 1%
5600p

SIGNAL
GENERATOR
DGND R4 C11 V1
100k 0.012 GND
AC

GND
CXA2104S
 CXA2104S

Adjustment Method (This is the case when standard input level is 245mVrms.)
1. ATT adjustment
1) TEST BIT is set to TEST1 = 0 and TEST-DA = 0.
2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level. Then,
adjust the ATT data for ATT adjustment so that the TVOUT-L output goes to the standard value
(490mVrms).
3) Adjustment range: 30%
Adjustment bits: 4 bits

2.Separation adjustment
1) TEST BIT is set to TEST1 = 0 and TEST-DA = 0.
2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz
NR-ON) to COMPIN. At this time, adjust the WIDEBAND adjustment data to reduce TVOUT-R output
to the minimum.
3) Next, set the frequency only of the input signal to 3kHz and adjust the SPECTRAL adjustment data to
reduce TVOUT-R output to the minimum.
4) The adjustments in 2 and 3 above are performed to optimize the separation.
5) WIDEBAND SPECTRAL
Adjustment range: 30% Adjustment range: 15%
Adjustment bits: 6 bits Adjustment bits: 6 bits

Adjust this IC through Tuner and IF when this IC is mounted in the set.

13
 CXA2104S

Description of Operation

The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.
PEAK DEV
kHz AM-DSB-SC
50 50

L-R
dbx-TV
25 25 NR
PILOT

15
SAP
dbx-TV NR TELEMETRY
L+R 5 FM 10kHz FM 3kHz
50 15kHz 50 10kHz 3

fH 2fH 3fH 4fH 5fH 6fH 6.5fH f

fH = 15.734kHz
Fig. 1. Base band spectrum

2
I C BUS
2fHL0 DECODER
PLL PILOT
fHL90 MODE
(VCO 8fH) DET
fHL0 CONTROL

STEREO LPF MAIN LPF DE.EM (MAIN OUT)

(COMPIN) (MAIN IN)
PILOT
11 MVCA
CANCEL
7 6
4.7
L+R
SUB LPF WIDEBAND
(SUBOUT) (ST IN) MATRIX
L-R (DSB)
DET SUBVCA 17 18 (Lch)

L R 4.7
NR SW to
SAP (FM) A dbx-TV B (Rch) TVSW
SAP BPF DET SAP LPF BLOCK
(SAP OUT) (SAP IN)
INJ.
LOCK 20 21
4.7

NOISE I 2C BUS
DET DECODER LPF
(SOUT) MODE
CONTROL
I 2C BUS 30
SAP DECODER
DET MODE
CONTROL

Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)

(ST IN) FIXED VARIABLE

NR SW DEEMPHASIS DEEMPHASIS
18 (VE OUT) (VCA IN)
A B
26 to
(SAP IN) 25 VCA
MATRIX
4.7
21
HPF
LPF RMS
DET

LPF
RMS
DET

Fig 3. dbx-TV block

14
 CXA2104S

(1) L + R (MAIN)
After the audio multiplexing signal input from COMPIN (Pin 11) passes through MVCA, the SAP signal
and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the
L R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened
(de-emphasized) and input to the matrix.

(2) L R (SUB)
The L R signal follows the same course as L + R before the pilot signal is canceled. L R has no
carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM
modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)
to be used for the demodulation of the L R signal. In the last stage, the residual high frequency
components are removed by SUB LPF and the L R signal is input to the dbx-TV block via the NRSW
circuit after passing through SUBVCA.

(3) SAP
SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is
extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency
components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal
is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 20 output is
soft muted.

(4) Mode discrimination

Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is
performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the
noise near 25kHz after FM detection of SAP signal.

(5) dbx-TV block

Either the L R signal or SAP signal input respectively from ST IN (Pin 18) or SAP IN (Pin 21) is
selected by the mode control and input to the dbx-TV block.
The input signal then passes through the fixed de-emphasis circuit and is applied to the variable de-
emphasis circuit. The signal output from the variable de-emphasis circuit passes through an external
capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a
current to a voltage using an operational amplifier and then input to the matrix.
The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of
effective value detection circuits. Each of the effective value detection circuits passes the input signal
through a predetermined filter for weighting before the effective value of the weighted signal is
detected to provide the control signal.

(6) Matrix
The signals (L + R, L R, SAP) input to MATRIX become the outputs for the ST-L, ST-R, MONO and
SAP signals according to the mode control and whether there is ST / SAP discrimination.

(7) Others
MVCA is a VCA which adjusts the input signal level to the standard level of this IC.
Bias supplies the reference voltage and reference current to the other blocks. The current flowing to
the resistor connecting IREF (Pin 13) with GND become the reference current.

15
 CXA2104S

Register Specifications

Slave address

SLAVE RECEIVER SLAVE TRANSMITTER

84H (1000 0100) 85H (1000 0101)

Register table

SUB ADDRESS DATA

MSB LSB BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0000 TEST-DA TEST1 ATT (4)
0001 SPECTRAL (6)
0010 WIDEBAND (6)
0011 DATA1 DATA2 NRSW FOMO SAPC M1
0100 INSW DATA5 ATTSW FST DATA3 DATA4
: Don't Care

Status Registers

STA1 STA2 STA3 STA4 STA5 STA6 STA7 STA8

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
POWER
STEREO SAP NOISE
ON RESET

16
 CXA2104S

Description of Registers

Control registers

Number Classifi- Standard

Register Contents
of bits cation1 setting
ATT 4 A 9 Input level adjustment
SPECTRAL 6 A 1F Adjustment of stereo separation (3kHz)
WIDEBAND 6 A 1F Adjustment of stereo separation (300Hz)
TEST-DA 1 T 0 Turn to DAC test mode by means of TEST-DA = 1.
TEST1 1 T 0 Turn to test mode by means of TEST = 1.
FST 1 T 0 Turn to forced stereo by means of FST = 1.
NRSW 1 U Selection of the output signal (Stereo mode, SAP mode)
Turn to forced MONO by means of FOMO = 1.
FOMO 1 U
(Left channel only is MONO during SAP output.)
Selection of TVOUT mute ON/OFF
M1 1 U 1
(0: mute ON, 1: mute OFF)
ATTSW 1 S Turn the input stage MVCA off when ATTSW = 1.
INSW 1 S Selection of standard input level
Selection of SAP mode or L + R mode according to the
SAPC 1 S
presence of SAP broadcasting
DATA1 1 T 0
DATA2 1 T 0
DATA3 1 T 0 Test mode (Normal standard setting value)
DATA4 1 T 0
DATA5 1 T 0
1 Classification U: User control
A: Adjustment
S: Proper to set
T: Test

Status registers

Register Number of bits Contents

PONRES 1 POWER ON RESET detection; 1: RESET
STEREO 1 Stereo discrimination of the COMPIN input signal; 1: Stereo
SAP 1 SAP discrimination of the COMPIN input signal; 1: SAP
NOISE 1 Noise level discrimination of the SAP signal; 1: Noise

17
 CXA2104S

Description of Control Registers

ATT (4): Adjust the signal level input to COMPIN (Pin 11) to the standard input level.
Variable range of the input signal: standard input level 5.0dB to +3.0dB
0 = Level min.
F = Level max.

SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment.

0 = Level max.
3F = Level min.

WIDEBAND (6): Perform low frequency (fs = 300Hz) separation adjustment.

0 = Level min.
3F = Level max.

TEST-DA (1): Set DAC output test mode.

0 = Normal mode
1 = DAC output test mode
In addition, the following output are present at Pin 2.
TVOUT-L (Pin 2): DA control DC level

TEST1 (1): Monitor SAPBPF and NRBPF output

0 = Normal mode
1 = SAPBPF, NRBPF output
In addition, the following outputs are present at Pins 1 and 2.
TVOUT-L (Pin 2): SAP BPF OUT
TVOUT-R (Pin 1): NR BPF OUT

FST (1): Select forced STEREO mode

0 = Normal mode
1 = Forced stereo mode

NRSW (1): Select stereo mode or SAP mode

0 = Stereo mode
1 = SAP mode

18
 CXA2104S

FOMO (1): Select forced MONO mode

0 = Normal mode
1 = Forced MONO mode

M1 (1): Mute the TVOUT-L and TVOUT-R output.

0 = Mute ON
1 = Mute OFF

ATTSW (1) Select BYPASS SW of MVCA

0 = Normal mode
1 = MVCA is passed

INSW (1): Select standard input level of COMPIN (Pin 11).

0 = 245mVrms
1 = 100mVrms

SAPC (1): Select the SAP signal output mode

When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC.
0 = L + R output is selected
1 = SAP output is selected

19
 CXA2104S

Description of Mode Control

Mode control SAPC = 0 SAPC = 1

Select dbx input and TV decoder output Select dbx input and TV decoder output
Conditions: FOMO = 0 Conditions: FOMO = 0
NRSW = 0 (MONO or ST output) NRSW = 0 (MONO or ST output)
During ST input: left channel: L, As on the left
right channel: R
During other input: left channel: L + R,
NRSW right channel: L + R
NRSW = 1 (SAP output) NRSW = 1 (SAP output)
When there is SAP during SAP Regardless of the presence of SAP
discrimination discrimination,
left channel: SAP, right channel: SAP dbx input: SAP
When there is No SAP, output is the left channel: SAP, right channel: SAP
same as when NRSW = 0. However, when there is no SAP, SAPOUT
output is soft muted (7dB)

Forced MONO

FOMO FOMO = 1
During SAP output: left channel: L + R, right channel: SAP
During ST or MONO output: left channel: L + R, right channel: L + R

Change the selection conditions for MONO or ST output and SAP output.
SAPC = 0: Switch to SAP output when there is SAP discrimination.
SAPC
Do not switch to SAP output when there is no SAP discrimination.
SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination.

MUTE
M1
M1 = 0: TVOUT output is muted.

20
 CXA2104S

Decoder Output and Mode Control Table 1 (SAPC = 1)

Mode detection Mode control Output

Input signal mode dbx
ST SAP NOISE NRSW FOMO SAPC input Lch Rch
0 0 0 0 1 MUTE L+R L+R
0 0 0 1 0 1 SAP SAP SAP
0 0 0 1 1 1 SAP L+R SAP
MONO 1
0 1 0 1 MUTE L+R L+R
0 1 1 0 1 (SAP) (SAP) (SAP)
0 1 1 1 1 (SAP) L+R (SAP)
1 0 0 0 1 LR L R
1 0 0 1 1 MUTE L+R L+R
1 1 1 0 0 1 LR L R
1 1 1 0 1 1 MUTE L+R L+R
STEREO 1
1 0 0 1 0 1 SAP SAP SAP
1 0 0 1 1 1 SAP L+R SAP
1 1 1 0 1 (SAP) (SAP) (SAP)
1 1 1 1 1 (SAP) L+R (SAP)
0 1 0 0 1 MUTE L+R L+R
0 1 0 1 1 MUTE L+R L+R
0 1 0 1 0 1 SAP SAP SAP
MONO & SAP
0 1 0 1 1 1 SAP L+R SAP
0 1 1 1 0 1 (SAP) (SAP) (SAP)
0 1 1 1 1 1 (SAP) L+R (SAP)
1 1 0 0 1 LR L R
1 1 0 1 1 MUTE L+R L+R
1 1 0 1 0 1 SAP SAP SAP
STEREO & SAP
1 1 0 1 1 1 SAP L+R SAP
1 1 1 1 0 1 (SAP) (SAP) (SAP)
1 1 1 1 1 1 (SAP) L+R (SAP)

Note
(SAP) : The SAPOUT output signal is soft muted (approximately 7dB).
The signal is soft muted when NOISE = 1.
: Dont care.
1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
inputted in the weak electric field.
Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

21
 CXA2104S

Decoder Output and Mode Control Table 2 (SAPC = 0)

Mode detection Mode control Output

Input signal mode dbx
ST SAP NOISE NRSW FOMO SAPC input Lch Rch
0 0 0 MUTE L+R L+R
0 1 1 0 0 0 MUTE L+R L+R
MONO 1 0 1 1 0 1 0 MUTE L+R L+R
0 1 1 1 0 0 (SAP) (SAP) (SAP)
0 1 1 1 1 0 (SAP) L+R (SAP)
1 0 0 0 0 LR L R
1 0 0 1 0 MUTE L+R L+R
1 0 1 0 0 LR L R
1 0 1 1 0 MUTE L+R L+R
STEREO 1
1 1 1 0 0 0 LR L R
1 1 1 0 1 0 MUTE L+R L+R
1 1 1 1 0 0 (SAP) (SAP) (SAP)
1 1 1 1 1 0 (SAP) L+R (SAP)
0 1 0 0 0 0 MUTE L+R L+R
0 1 0 0 1 0 MUTE L+R L+R
0 1 0 1 0 0 SAP SAP SAP
0 1 0 1 1 0 SAP L+R SAP
MONO & SAP
0 1 1 0 0 0 MUTE L+R L+R
0 1 1 0 1 0 MUTE L+R L+R
0 1 1 1 0 0 (SAP) (SAP) (SAP)
0 1 1 1 1 0 (SAP) L+R (SAP)
1 1 0 0 0 0 LR L R
1 1 0 0 1 0 MUTE L+R L+R
1 1 0 1 0 0 SAP SAP SAP
1 1 0 1 1 0 SAP L+R SAP
STEREO & SAP
1 1 1 0 0 0 LR L R
1 1 1 0 1 0 MUTE L+R L+R
1 1 1 1 0 0 (SAP) (SAP) (SAP)
1 1 1 1 1 0 (SAP) L+R (SAP)

Note
(SAP) : The SAPOUT output signal is soft muted (approximately 7dB).
The signal is soft muted when NOISE = 1.
: Dont care.
1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
inputted in the weak electric field.
Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
22
 CXA2104S

I2C BUS block items (SDA, SCL)

No. Item Symbol Min. Typ. Max. Unit
1 High level input voltage VIH 3.0 5.0
2 Low level input voltage VIL 0 1.5 V

3 High level input current IIH 10

A
4 Low level input current IIL 10
5 Low level output voltage SDA (Pin 3) during 3mA inflow VOL 0 0.4 V
6 Maximum inflow current IOL 3 mA
7 Input capacitance CI 10 pF
8 Maximum clock frequency fSCL 0 100 kHz
9 Minimum waiting time for data change tBUF 4.7
10 Minimum waiting time for start of data transfer tHD: STA 4.0
11 Low level clock pulse width tLOW 4.7
s
12 High level clock pulse width tHIGH 4.0
13 Minimum waiting time for start preparation tSU: STA 4.7
14 Minimum data hold time tHD: DAT 0
15 Minimum data preparation time tSU: DAT 250 ns
16 Rise time tR 1 s
17 Fall time tF 300 ns
18 Minimum waiting time for stop preparation tSU: STO 4.7 s

I2C BUS load conditions: Pull-up resistor 4k (Connect to +5V)

Load capacity 200pF (Connect to GND)

I2C BUS Control Signal

SDA

tBUF tR tF tHD: STA

SCL

tSU: STA tSU: STO

P S tHD: STA tLOW tHD: DAT tHIGH tSU: DAT Sr P

23
 CXA2104S

I2C BUS Signal

There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal.
Accordingly there are 3 values outputs, H, L and HIZ.

H L HIZ L

I2C transfer begins with Start Condition and ends with Stop Condition.

Start Condition S Stop Condition P

SDA

SCL

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 CXA2104S

I2C data Write (Write from I2C controller to the IC)

L during Write
MSB MSB LSB
HIZ HIZ
SDA

SCL 1 2 3 4 5 6 7 8 9 1 8 9

S
Address ACK Sub Address ACK

MSB LSB
HIZ HIZ

1 8 9 1 8 9

DATA (n) ACK DATA (n+1) ACK DATA (n + 2)

HIZ HIZ

8 9 1 8 9 Data can be transferred in 8-bit units to be

P set as required.
DATA ACK DATA ACK Sub address is incremented automatically.

I2C data Read (Read from the IC to I2C controller)

H during Read

HIZ
SDA

SCL 1 6 7 8 9 1 7 8 9

S P
Address ACK DATA ACK

Read timing
MSB LSB
IC output SDA

SCL 9 1 2 3 4 5 6 7 8 9

Read timing
ACK DATA ACK

Data Read is performed during SCL rise.

25
 CXA2104S

Input level vs. Distortion characteristics 1 (MONO) Input level vs. Distortion characteristics 2 (Stereo)

Input signal: MONO (Pre-emphasis on), 1kHz Input signal: Stereo L = R

0dB = 100% modulation level (dbx-TVNR ON), 1kHz
VCC = 9V, 30kHz using LPF 0dB = 100% modulation level
1.0 10
Measurement point: TVOUT-L/R VCC = 9V, 30kHz using LPF, ST mode
Measurement point: TVOUT-L/R
Distortion [%]

Distortion [%]
0.1 1.0

Standard level (100%)

10 0 10
Input level [dB] Standard level (100%)

10 0 10
Input level [dB]

Input level vs. Distortion characteristics 3 (SAP)

Input signal: SAP (dbx-TVNR ON)

1kHz, 0dB = 100% modulation
10 level
VCC = 9V, 30kHz using LPF, SAP mode
Measurement point: TVOUT-L/R
Distortion [%]

1.0

Standard level (100%)

10 0 10
Input level [dB]

26
 CXA2104S

Stereo LPF frequency characteristics Main LPF and Sub LPF frequency characteristics
10
30

20

Gain (FC main and FC sub) [dB]

5
10

0
Gain [dB]

0
10

20
5

30

10 40

50
0 20 40 60 80 100 1 2 5 7 10 20 50 70 100
Frequency [kHz] Frequency [kHz]

SAP frequency characteristics and group delay Additional SAP frequency characteristics
100

20 90
5fH 500
80
Gain
Output level [mVrms]

10 70 100% modulation
Group delay [s]

60
Gain [dB]

30% modulation
0 50 100
10% modulation
40

10 30

20 1% modulation
Group delay
20 3.8fH 10
6.2fH
0 10
20 40 60 80 100 120 0.1 1.0 10
Frequency [kHz] Frequency [kHz]

27
 CXA2104S

Package Outline Unit: mm

30PIN SDIP (PLASTIC)

.05
+ 0.1
+ 0.4

0.25 0
26.9 0.1

30 16

+ 0.3
8.5 0.1
0 to 15

10.16
1 15

1.778

+ 0.4
3.7 0.1
0.5 MIN

Two kinds of package surface:

1.All mat surface type.
2.All mirror surface type.
3.0 MIN

0.5 0.1

0.9 0.15

PACKAGE STRUCTURE
MOLDING COMPOUND EPOXY RESIN

SONY CODE SDIP-30P-01 LEAD TREATMENT SOLDER/PALLADIUM

PLATING
EIAJ CODE SDIP030-P-0400 LEAD MATERIAL COPPER ALLOY

JEDEC CODE PACKAGE MASS 1.8g

NOTE : PALLADIUM PLATING

This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).

28
This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.