DIGITAL

SARANATHAN COLLEGE OF ENGINEERING
DEPARTMENT OF ECE
CS 2207-DIGITAL LAB
LAB MANUAL
CS 2207 DIGITAL LABORATORY LTPC
(Common to CSE & IT) 0032
LIST OF EXPERIMENTS
1. Verification of Boolean theorems using digital logic gates

2. Design and implementation of combinational circuits using basic gates for
arbitrary
functions, code converters, etc.
3. Design and implementation of 4-bit binary adder / subtractor using basic gates
and
MSI devices
4. Design and implementation of parity generator / checker using basic gates and
MSI
devices
5. Design and implementation of magnitude comparator
6. Design and implementation of application using multiplexers/ Demultiplexers
7. Design and implementation of Shift registers
8. Design and implementation of Synchronous and Asynchronous counters
9. Simulation of combinational circuits using Hardware Description Language
(VHDL/
Verilog HDL software required)
10. Simulation of sequential circuits using HDL (VHDL/ Verilog HDL software
required)
INDEX
S.NO DATE NAME OF THE EXPERIMENT SIGNATURE

DATE:
EX.NO: 1(a)
VERIFICATION OF LOGIC GATES
AIM:
To verify the functions of the basic logic gates.
COMPONENTS REQUIRED:
S.NO APPARATUS QUANTITY
Digital Trainer kit

1 1
IC 7432, IC 7408, IC 7400, IC 7402, IC7404 ,
2 1 each
IC 7486
3 1 each
IC 7411, IC 7410
4 As Required
Patch cords
5 As Required
Connecting wires
THEORY:
The basic elements that make up a digital system are Logic Gates. The
most common gates are AND, OR, NOT, NAND, NOR, EX-OR and EX-NOR
gates. The NAND and NOR gates are called as the universal gates because all the
other gates can be implemented using these two gates. A simple logic element
whose binary output is a Boolean function (AND, OR...) of the input is known as a
GATE.
AND GATE:
In AND gate, the output Y is the product of the two inputs A and B.
Hence, even if one input is zero, the output becomes zero. If both the inputs
are equal to one then the output is also one.
Y=A B
OR GATE:
In OR gate, the output Y is the sum of the two inputs A and B.Hence,
even if any one of the input is one or both the input is one the output
becomes one. The output becomes zero only when both the inputs are zero.
Y = A+B
NOT GATE:
In NOT gate, the output Y is the complement of the input A. Hence,
the output is one when the input is zero and vice versa.
Y = A'
NAND GATE:
In NAND gate, the output Y is the complement of the product of two
inputs A and B. Hence, the output is one if any one of the input is zero. The
output is zero if both the inputs are one.
Y = (A B)'
NOR GATE:
In NOR gate, the output Y is the complement of the sum of two inputs
A and B. Hence, if any one of the input is one, the output is zero and if both
inputs are zero, the output is one.
Y = (A+B)'
EXCLUSIVE OR GATE:
In EX-OR gate, the output Y is zero when both the inputs A and B are
same (Both are zero or both are one) otherwise the output is one.
Y=A B
EXCLUSIVE NOR GATE:
In EX-NOR gate, the output Y is one when both the inputs A and B
are same (Both are zero or both are one) otherwise the output is zero.
Y = (A B)'
PROCEDURE:
1. Make connections as per the logic diagram.
2. Give inputs as per truth table. For logic 1, connect the input pin to +5V and
for logic zero connect the input pin to Ground.
3. Verify the corresponding outputs for the given inputs, using the truth table of
AND gate.
4. Verify the truth tables for all the other gates.
AND GATE:
SYMBOL: PIN DIAGRAM:
OR GATE:
NOT GATE:
X-OR GATE:
NAND GATE:
NOR GATE:
3-INPUT AND GATE:
3-INPUT NAND GATE:
RESULT:
DATE
EX NO: 1(b)
APPLICATIONS OF BOOLEAN ALGEBRA AND DE-MORGANS

THEOREM
AIM:
To draw the logic diagram and write the truth table for the following laws
and rules of Boolean algebra and verify the truth table
APPARATUS REQUIRED:
1 Digital Trainer kit

1
2 IC 7432, IC7408, IC7404 , IC 7486,IC
1 each
7400,IC 7402,IC 7410
As Required
3 Patch cords
As Required
4 Connecting wires
1) Laws of Boolean Algebra

i. Commutative Law
Addition: X+Y=Y+X
Multiplication: XY=YX
ii. Associative Law

Addition: A+ (B+C) = (A+B) + C
Multiplication: A (BC) = (AB) C
iii. Distributive Law
A+ (B+C) = (AB+AC)
A+ (BC) = (A+B) (A+C)
2) Rules of Boolean Algebra

i. A+0=A
ii. A+1=A
iii. A.0=0
iv. A+A=A
v. A+A=1
vi. A.A=0
vii. A.A=A
viii. A=A
ix. A+AB=A
x. A+AB=A+B
xi. AB+AB=A
xii. (A+B)(A+B)=A
xiii. A(A+B)=A
xiv. (A+B)B=AB
xv. AB+B=A+B
xvi. (AB+AB)=((A+B).(A+B))
xvii. (A+B)(A+C)=(AC+AB)
xviii. AB+AC=(A+C)(A+B)
xix. AB+BC+AC=AB+AC
xx. (A+B)(B+C)(A+C)=(A+B)(A+C)
PROCEDURE:
1. Give connections as per the logic diagram.
2. Give inputs as per truth table. For logic 1, connect the input pin
to +5V and for logic zero; connect the input pin to Ground.
3. Verify the corresponding truth table.

RESULT:
DATE:
EX.NO:2 (a)
DESIGN AND IMPLEMENTATION OF COMBINATIONAL
CIRCUITS USING BASIC GATES FOR ARBITRARY FUNCTIONS
AIM:
To design and implement the following Combinational circuits using logic
gates.
A. Half Adder
B. Half Subtractor
C. Full Adder and
D. Full Subtractor.
1 Digital Trainer kit 1

2 IC 7432, IC7408, IC7404 , IC 7486 1 each
3 Patch cords As Required
4 Connecting wires As Required
THEORY:
COMBINATIONAL CIRCUIT:
A Combinational circuit is a circuit in which the output is a direct immediate
response of the input stimuli. Each combination of these inputs is known as a
minterm and can be plotted on a truth table or Karnaugh map. Maps can be
reduced by combining minterms into 2n squares and then reading the results either
in Sum of product (SOP) form or in Product of Sum (POS) form.
A. HALF ADDER:
Half adder is combinational circuit which is capable of adding two
binary bits producing SUM (S) and CARRY(C) outputs. The disadvantage
of this circuit is that it can add only 2 bits.
S=X'Y+XY'
C=XY
B. FULL ADDER:
Full adder is a combinational circuit which is capable of adding three
binary bits producing SUM(S) and CARRY(C) outputs.
S=X'Y'Z+X'YZ'+XY'Z'+XYZ
C=XY+YZ+ZX
C. HALF SUBTRACTOR:
Half Subtractor is a combinational circuit which is capable of
subtracting two binary bits producing DIFFERENCE (D) and BORROW (B)
outputs.
D=X'Y+XY'
B=X'Y
D. FULL SUBTRACTOR:
Full Subtractor is a combinational circuit which is capable of
subtracting three binary bits producing DIFFERENCE (D) and BORROW
(B) outputs.
D=X'Y'Z+X'YZ'+XY'Z'+XYZ
B=X'Y+YZ+X'Z'
PROCEDURE:
HALF ADDER
TRUTH TABLE:
A B CARRY SUM
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
K-Map for SUM: K-Map for CARRY:
SUM = AB + AB CARRY = AB
=A B
LOGIC DIAGRAM:
FULL ADDER
TRUTH TABLE:
A B C CARRY SUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
K-Map for SUM:
SUM = ABC + ABC + ABC + ABC

=A B C
K-Map for CARRY:
CARRY = AB + BC + AC
=AB+C( A B)
LOGIC DIAGRAM:
HALF SUBTRACTOR
TRUTH TABLE:
A B BORROW DIFFERENCE
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
K-Map for DIFFERENCE:
DIFFERENCE = AB + AB
=A B
K-Map for BORROW:
BORROW = AB
LOGIC DIAGRAM:
FULL SUBTRACTOR
TRUTH TABLE:
A B C BORROW DIFFERENCE
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
K-Map for Difference:
Difference = ABC + ABC + ABC + ABC

=A B C
K-Map for Borrow:
Borrow = AB + BC + AC
LOGIC DIAGRAM:
RESULT:
DATE:
EX.NO: 2 (b)
DESIGN AND IMPLEMENTATION OF CODE CONVERTERS USING

LOGIC GATES
AIM:
To design and implement the following code converters using logic gates.
a. BINARY code to GRAY code and vice versa.
b. BCD to EXCESS-3 code and vice versa.

2 IC 7432, IC 7408, IC 7404 , IC 7486 1 each
THEORY:
BINARY CODE:
Any discrete element of information distinct among a group of quantities
can be represented with a binary code. The code must be in binary because
computers can hold only 0s and 1s. Binary codes merely change the symbol and
not the meaning of the elements of information that they represent. An n-bit binary
code is a group of n bits that assumed up to 2n distinct combinations of 0s and
1s with each representing one element of the set that is being coded. In general, a
set of 2n elements can be coded with n bits. The bit combination of n-bit code is
determined from the count in binary form 0 to 2n-1.
GRAY CODE:
It is convenient to use gray code to represent the digital data when it is
converted from analog data. The advantage of the Gray code over the straight
binary number sequence is that only one bit in the code group changes when going
from one number to the next. The gray code is used in applications where the
normal sequence of binary numbers may produce error or ambiguity during the
transition from one number to the next. A typical application occurs when the
analog data are represented by continuous change in the shaft position.
BCD CODE:
It is possible to perform arithmetic operations directly with decimal numbers
when they are stored in the computer in a coded form. Different binary codes can
be obtained by arranging four bits in 10 distinct combinations. The code most
commonly used for the decimal digits is the straight binary assignment. This is
called Binary coded decimal (BCD). It is a weighted code.
EXCESS-3 CODE:
The excess-3 code has been used in some older computers because of its
self-complementing property. Such codes have the property that the 9s
complement of a decimal number is obtained directly by changing 1s to 0s and
0s to 1s in the code. This is an un-weighted code where each coded combination
is obtained from the corresponding binary value added with 3.
PROCEDURE:

LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR
K-Map for G3:
G3 = B3
K-Map for G2:
K-Map for G1:

K-Map for G0:
TRUTH TABLE:
| Binary input | Gray code output |
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR
K-Map for B3:

B3 = G3
K-Map for B2:
K-Map for B1:

K-Map for B0:
TRUTH TABLE:
| Gray Code | Binary Code |
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR
K-Map for E3:
E3 = B3 + B2 (B0 + B1)
K-Map for E2:

K-Map for E1:
K-Map for E0:

TRUTH TABLE:
| BCD input | Excess 3 output |
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTOR
K-Map forA:
A = X1 X2 + X3 X4 X1
K-Map for B:
K-Map for C:
K-Map for D:
TRUTH TABLE:
| Excess 3 Input | BCD Output |
B3 B2 B1 B0 G3 G2 G1 G0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
0 1
1 0 0 0 0 1 1 0
1 0 0 1 0 1 1 1
1 0 1 0 0 1 0 0
1 0 1 1 1 0 0 1
1 1 0 0 1 0
RESULT:
DATE:
EX.NO: 3 (a)
DESIGN AND IMPLEMENTATION OF 4-BIT BINARY

ADDER/SUBTRATOR USING MSI DEVICES(IC 7483)
AIM:
To design and implement 4-bit binary Adder/Subtractor using IC7483.
1
3 IC 7483 2
4 IC 7486, IC 7432, IC 7408 1 each
Patch cords
As Required
Connecting wires
5 As Required
THEORY:
4 BIT BINARY ADDER:
A binary adder is a digital circuit that produces the arithmetic sum of two
binary numbers. It can be constructed with full adders connected in cascade, with
the output carry from each full adder connected to the input carry of next full adder
in chain. The augends bits of A and the addend bits of B are designated by
subscript numbers from right to left, with subscript 0 denoting the least significant
bits. The carries are connected in chain through the full adder. The input carry to
the adder is C0 and it ripples through the full adder to the output carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed
between each data input B and the corresponding input of full adder. The input
carry C0 must be equal to 1 when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with
one common binary adder. The mode input M controls the operation. When M=0,
the circuit is adder circuit. When M=1, it becomes subtractor.
PROCEDURE:

PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:
4-BIT BINARY ADDER
LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR
LOGIC DIAGRAM:
4-BIT BINARY ADDER/SUBTRACTOR
TRUTH TABLE:
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
RESULT:
DATE:
EX.NO: 3 (b)
DESIGN AND IMPLEMENTATION OF BCD ADDER USING MSI DEVICES

(IC 7483)
AIM:
To design and implement BCD adder using IC7483.

2 IC 7483 2
3 IC 7486, IC 7432, IC 7408 1 each
BCD ADDER:
A BCD adder is a circuit that adds two BCD digits in parallel and produces a
SUM digit which is also BCD. A BCD adder must include the correction logic in
its internal construction. A BCD circuit must be able to do the following
i. Add two 4-bit BCD numbers using straight binary addition.
ii. If the 4-bit SUM is less than or equal to 9, the SUM is in proper BCD form And
no correction is needed.
iii. If the 4-bit sum is greater than 9 or if a carry is generated from the SUM, the
SUM is not in BCD form. Then the BCD result is produced by adding 6 to the
obtained SUM.
PROCEDURE:

2. Give inputs as per truth table. For logic 1, connect the input pin to +5V and
for logic zero; connect the input pin to Ground.
3. Verify the corresponding truth table
LOGIC DIAGRAM:
BCD ADDER
TRUTH TABLE:
Input Data A Input Data B OUTPUT

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1
1 0 0 0 0 0 1 0 1 0 0 0 0
1 0 0 0 1 0 0 0 1 0 1 1 0
0 0 1 1 1 0 0 1 1 0 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0
0 1 1 0 0 1 1 1 1 0 0 1 1
1 0 0 1 0 1 0 1 1 0 1 0 0
0 0 1 0 0 1 0 1 0 0 1 1 1
K-MAP
Y = S4 (S3 + S2)
TRUTH TABLE:
BCD SUM CARRY

S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
RESULT:
DATE:
EX.NO: 4
DESIGN AND IMPLEMENTATION OF 16-BIT ODD/EVEN

PARITY CHECKER/GENERATOR USING IC 74180
AIM:
To design and implement 16-bit odd/even parity checker/generator using IC
74180.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.

1. NOT GATE IC 7404 1
1. IC 74180 2
2. IC TRAINER KIT - 1
3. PATCH CORDS - 30
THEORY:
A parity bit is used for detecting errors during transmission of binary

information. A parity bit is an extra bit included with a binary message to make the
number is either even or odd. The message including the parity bit is transmitted
and then checked at the receiver ends for errors. An error is detected if the checked
parity bit doesnt correspond to the one transmitted. The circuit that generates the
parity bit in the transmitter is called a parity generator and the circuit that checks
the parity in the receiver is called a parity checker.
In even parity, the added parity bit will make the total number is even
amount. In odd parity, the added parity bit will make the total number is odd
amount. The parity checker circuit checks for possible errors in the transmission. If
the information is passed in even parity, then the bits required must have an even
number of 1s. An error occur during transmission, if the received bits have an odd
number of 1s indicating that one bit has changed in value during transmission.
EVEN PARTITY GENERATOR

TRUTH TABLE
A B C PO
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
ODD PARITY GENERATOR

TRUTH TABLE
A B C P0
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
EVEN PARITY CHECKER

ODD PARITY CHECKER
TRUTH TABLE
PE/P0 A B C PC(Odd) Pc(even)

0 0 0 0 1 0
1 0 0 0 0 1
0 0 0 1 0 1
FUNCTION TABLE:
1 0 0 1 1 0
INPUTS OUTPUTS
0 0 1 0 0 1
Number of High Data PE PO E O
1 0 1 0 1 0
Inputs (I0 I7)
0 0 1 1 1 0
EVEN 1 0 1 11 0 0 1 1 0
ODD 0 1 0 10 0 0 1 0 1
EVEN 1 1 0 00 1 1 0 0 1
ODD 0 1 0 01 1 1 0 1 0
X 1 1 0 11 0 1 1 0 0
X 0 1 1 00 1 0 0 1 1
1 1 1 0 0 1
0 1 1 1 0 1
1 1 1 1 1 0
LOGIC DIAGRAM:
ODD/EVEN PARITY CHECKER
LOGIC DIAGRAM:
ODD/EVEN PARITY GENERATOR
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
DATE:
EX.NO: 5
DESIGN AND IMPLEMENTATION OF MAGNITUDE

COMPARATOR
AIM:
To design and implement magnitude comparator using logic gates.

2 IC 7486 1
3 IC 7404 , IC 7408, IC 7485, IC 7432 2 each
THEORY:
A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitude. The comparison of two
numbers is an operation that determines whether one number is greater than, less
than or equal to the other number.
The circuit for comparing two n-bit numbers has 2 2n entries in the truth table
and becomes too cumbersome even when n=3. On the other hand as one may
suspect, a comparator circuit possess a certain amount of regularity.
Digital functions that possess an inherent well-defined regularity can usually
be designed by means of an algorithm procedure. The equality of two numbers, A
and B is displayed in a combinational circuit by an output binary variable that we
designate by symbol. This binary variable is equal to 1 if the input numbers A and
B are equal and it is zero otherwise.
To determine if A is greater or lesser than B we inspect the relative
magnitude of pairs of significant bits starting from the most significant bit position.
If MSB of both A and B are equal we compare the next lower significant pair of
bits.
PROCEDURE:
2. Give inputs as per truth table. For logic 1, connect the input pin to +5V
and for logic zero; connect the input pin to Ground.

2-BIT MAGNITUDE COMPARATOR
TRUTH TABLE
A1 A0 B1 B0 A>B A= B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
SIMPLIFICATION USING K MAP
= A0B0 (B1+A1) +A1B1
= A0B0 (A1+B1) +A1B1

LOGIC DIAGRAM:
8-BIT MAGNITUDE COMPARATOR

TRUTH TABLE:
A B A>B A=B A<B
0000 0000 0000 0000 0 1 0
0001 0001 0000 0000 1 0 0
0000 0000 0001 0001 0 0 1
LOGIC DIAGRAM:
RESULT:
DATE:
EX.NO: 6
DESIGN AND IMPLEMENTATION OF MULTIPLEXERS/DE-

MULTIPLEXERS
AIM:
To design and implement multiplexer and De-multiplexer using logic gates
and study of IC 74150 (Multiplexer IC), IC 74154 (De-Multiplexer IC).

2 IC 7404 1
3 IC 7411 4
4 IC 7432, IC 74150, IC 74154 1 each
THEORY:
MULTIPLEXER:
A multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Normally there are 2 n
input lines and n selection lines whose bit combinations determine which input is
selected.
A multiplexer function like an electronic switch that selects one of the
multiple sources. It suggests visually how a selected one of multiple data source is
directed into a single destination.
In a 4-to-1 line multiplexer, each of the four input lines (I 0 to I3) is applied to
one input of AND gate. Selection lines A and B are decoded to select a particular
AND gate. The outputs of the AND gates are applied to a single OR gate that
provides the one output line. As a multiplexer selects one of many input lines and
steers the binary information to the output line, it is also called as Data selector.
The AND gates and inverters in the multiplexer resemble a decoder circuit and
indeed they decode the selection input lines.
IC 74150 is 16-to-1 Multiplexer IC. It has 16 input lines (E 0 to E15), 4
selection lines (A, B, C, D) and 1 output line. The output of IC 74150 is active
low.
DE-MULTIPLEXER:
A De-multiplexer is a combinational logic circuit that receives information
on a single input line and transmits it through anyone of the 2n output lines (where
n is the number of selection lines).The word de-multiplexer means one into
many. De-multiplexing is a process of taking information from one input line and
transmitting the same over one of the several output lines.
The operation of a de-multiplexer is opposite to that of a multiplexer. The
circuit has one input line, n selection lines and 2 n output lines. The selection inputs
determine to which output line the input data will be connected. As the serial data
is changed to a parallel data , i.e. the input caused to appear on any one of the 2n
output lines, the de-multiplexer is also called as a Distributor or a serial-to-
parallel convertor.
1-to-4 De-multiplexer can be implemented using four 3-input NAND gates
and two NOT gates. Here the input data line is connected to all the AND gates. The
two selection lines enable only one gate at a time and the data that appears on the
input line passes through the selected gate to the associated output line.
PROCEDURE:
2. Give inputs as per truth table. For logic 1, connect the input pin to +5V
and for logic zero; connect the input pin to Ground.

4:1 MULTIPLEXER USING LOGIC GATES:
BLOCK DIAGRAM:
TRUTH TABLE:
S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3
CIRCUIT DIAGRAM FOR MULTIPLEXER:

1:4 DEMULTIPLEXER USING LOGIC GATES:
BLOCK DIAGRAM:
TRUTH TABLE:
DATA SELECT OUTPUTS

S1 S0 D0 D1 D2 D3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D
LOGIC DIAGRAM FOR DEMULTIPLEXER:
PIN DIAGRAM FOR MULTIPLEXER IC 74150:
E0-E15 are inputs, ABCD are selection lines & Q is output. ST is enable input.
TRUTH TABLE:
ST D C B A Q
1 X X X X 0
0 0 0 0 0 E0
0 0 0 0 1 E1
0 0 0 1 0 E2
0 0 0 1 1 E3
0 0 1 0 0 E4
0 0 1 0 1 E5
0 0 1 1 0 E6
0 0 1 1 1 E7
0 1 0 0 0 E8
0 1 0 0 1 E9
0 1 0 1 0 E10
0 1 0 1 1 E11
0 1 1 0 0 E12
0 1 1 0 1 E13
0 1 1 1 0 E14
0 1 1 1 1 E15
PIN DIAGRAM FOR DEMULTIPLEXER IC 74154:
Q0-Q15 are outputs, ABCD are selection inputs and Data is input. ST is enable
signal.
TRUTH TABLE:
S D D C B A Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
T at 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
a
1 0 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
0 0 0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
RESULT:
DATE:
EX.NO: 7
DESIGN AND IMPLEMENTATION OF SHIFT REGISTER
AIM:
To implement SIPO, SISO, PISO and PIPO shift registers using D-flip flop.

2 IC 7474, IC 7408 2 each
3 IC 7404, IC 7432 1 each
THEORY:
A register that is used to store binary information is known as a memory
register. A Shift register is a register which is capable of shifting binary
information either to right or to the left.
SERIAL IN SERIAL OUT SHIFT REGISTER (SISO):
This type of shift register accepts data serially i.e. one bit at a time on a
single input line. It produces the store information on its single output also in serial
form. Data may be shifted left (from low to higher order bits) or right (from high to
lower order bits) using shift left and shift right registers respectively.
a) SHIFT LEFT REGISTER:
Using D-flip flops input of the rightmost flip flop is used as a
serial input line. For input data 1, one is applied at the D input and
for input data 0, a zero is applied at the D input. The clock pulse is
applied to all the flip flops simultaneously. When the shift or clock
pulse occurs each flip flop is set or reset according to the data at the
respective flip flop input.
b) SHIFT RIGHT REGISTER:
A shift right register can also be constructed using D-flip flop.
Entry of 4-bits 1101 into the register, beginning with the right most
bit. One is applied at the serial input line i.e. at Delay input of the first
flip flop. When the first clock pulse is applied, flip flop A is set storing
1. Then a zero is applied to the serial input, making D = 0 for flip flop
A and D = 1 for flip flop B because D input of flip flop B is connected
to qA output. Similarly every bit is shifted right serially.
SERIAL IN PARALLEL OUT SHIFT REGISTER (SIPO):
It consists of one serial input and the outputs taken from all the flip flops are
parallel. In this register data is shifted in serially but shifted out in parallel. In order
to shift the data out in parallel it is necessary to have all the data available at the
outputs at the same time. One the data is stored, each bit appears on its respective
output line and all the bits are available simultaneously.
PARALLEL IN SERIAL OUT SHIFT REGISTER (PISO):

A 4-bit parallel in serial out register has four parallel input data lines (A, B,
C, D) and a control input (SHIFT/LOAD') that allows the four bits of data at the
input lines to enter into the register in parallel or shift the data in serial. When
SHIFT/LOAD' is low, AND gates G1 through G3 are enabled allowing the data at
the parallel inputs B,C and D to the Delay input of its respective flip flop. The A
input is directly connected to the Delay input of the first flip flop. When the clock
pulse is applied, the flip flops with D = 1 will be set and the flip flops with D = 0
will be reset, there by restoring all 4-bits simultaneously.
When SHIFT/LOAD' is high, AND gates G1 through G3 are disabled and the
remaining AND gates G4 through G6 are enabled allowing the data bits to shift
right from one stage to the next. The OR gates allow the normal shifting operation
depending on which the AND gates are enabled by the level on the SHIFT/LOAD'
input.
PARALLEL IN PARALLEL OUT SHIFT REGISTER (PIPO):
In this type of register, data inputs can be shifted in or out of the register in
parallel. The parallel entry of the data is carried out and the output is also taken
parallel. In this register, there is no interconnection between successive flip flops
since no serial shifting is required. Therefore the moment the parallel entry of the
input data is accomplished, the respective bits will appear at the parallel output.
PROCEDURE:

2. Give input signals. For logic 1, connect the input pin to +5V and for
logic zero; connect the input pin to Ground.
3. Give Clock pulse one by one and verify the corresponding outputs for
the given inputs using the indication lamps.
IC 7474:
SERIAL IN SERIAL OUT:

TRUTH TABLE:
CLK DATA IN DATA

OUTPUT
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
LOGIC 7 X 1 DIAGRAM:
SHIFT RIGHT
SHIFT LEFT
SERIAL IN PARALLEL OUT:

TRUTH TABLE:
OUTPUT
CLK DATA Q3 Q2 Q1 Q0
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 0
4 1 1 0 0 1
LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:

TRUTH TABLE:
SHIFT/ CLK A B C D O/P

LOAD
1 0 1 1 0 1 0
0 1 X X X X 1
0 2 X X X X 0
0 3 X X X X 1
0 4 X X X X 1
LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:
TRUTH TABLE:
DATA INPUT OUTPUT

CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
LOGIC DIAGRAM:
RESULT:
DATE:
EX.NO: 8 (a)
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS AND
ASYNCHRONOUS COUNTERS
i. 4-BIT RIPPLE,MOD-10 RIPPLE COUNTER AND MOD-12

RIPPLE COUNTER
AIM:
To construct and verify 4-bit ripple counter, MOD-10 and MOD-12 ripple
counters using flip flop.

2 IC 7476 2
3 IC 7400 1
THEORY:
RIPPLE COUNTER:
A register that goes through a prescribed sequence of states upon the
application of input pulses is called counter. The input pulses may be clock pulses
or they may originate from external source. The sequence of states may follow the
binary number sequence or any other sequence of states. A counter that follows the
binary number is called binary counter.
Counters are available in two categories
Ripple counter
Synchronous counter
In a Ripple counter, the flip flop output transition serves as the source of
triggering the flip flop.
4-BIT RIPPLE COUNTER:
It refers to first nine binary numbers. The count starts with binary 0 and
increments by one with each clock pulse input. After the count 15, the counter goes
to 0. The least significant bit is complemented at each clock pulse input. Every
time A0 goes from 1 to 0, A1 is complemented.
MOD COUNTERS:
Counters can be designed to generate any desired sequence of states. A
divide by N counter is also known as Modulo-N counter, a counter that goes
through a repeated sequence of N states. The sequence may follow the binary count
or may be any other arbitrary sequence. Counters are used to generate timing
signals to control the sequence of operations in a digital system. Counters can also
be constructed using shift registers.
PROCEDURE:

IC 7676:
4 BIT RIPPLE COUNTER:
TRUTH TABLE:
CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

QA,QB,QC AND QD are OUTPUTS
MOD - 10 RIPPLE COUNTER:
TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0
LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

QA,QB,QC AND QD are OUTPUTS
MOD - 12 RIPPLE COUNTER:
TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0
LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:

RESULT:
DATE:
EX.NO: 8(b)
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS AND
ASYNCHRONOUS COUNTERS
ii. 3-BIT SYNCHRONOUS UP/DOWN COUNTER

AIM:
To design and implement a 3-bit synchronous up/down counter.

2 IC 7476 2 each
3 IC 7432, IC 7486, IC 7411, IC 7404 1 each
THEORY:
To design a 3-bit up/down counter, the control inputs (count-up and count-
down) are used to allow either the normal output or the inverted output of the flip
flop o the J and K inputs of the flip flop. A 3-bit up/down counter will count from
000 to 111 when the count-up = 1 and when count-down = 0. When count-down =
1 and count-up = 0, it counts from 111 to 000.
A logical 1 on the count-up line while count-down = 0 enables AND gates
1,3 and disables AND gates 2 and 4. This allows the q A and qB outputs through the
AND gates to J and K inputs of the following flip flop. So the counter counts up
when clock pulses are applied. The reverse action takes place when count-up = 0
and count-down = 1.
PROCEDURE:

SYNCHRONOUS UP/ DOWN COUNTER:
STATE DIAGRAM:
CHARACTERISTICS TABLE:
Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
TRUTH TABLE:
Input Present Next State A B C

Up/Down(UD) State QA+1 Q B+1 QC+1 JA KA JB KB JC KC
QA QB QC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 0 X X 1
X
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
SIMPLIFICATION USING K MAP:
LOGIC DIAGRAM:
RESULT:
DATE:
EXNO: 9
SIMULATION OF COMBINATIONAL CIRCUITS USING HARDWARE

DESCRIPTION LANGUAGE
AIM:
To Design combinational and sequential circuits using Verilog HDL.
APPARATUS REQUIRED:
Personal computer & Xilinx 8.1 Software
THEORY:
HDL is a language that describes the hardware of Digital system in a text
form. It resembles a programming language, but it is specifically oriented to
describing hardware structure and behavior. It can be used to represent logic
diagrams, Boolean expressions and other more complex digital circuits.
There are two standard HDL; they are Verilog HDL & VHDL.
VHDL is very high speed integrated circuit hardware description language. It was
formulated by IEEE Engineers and it is not user friendly. But, Verilog HDL is user
friendly and uses three modeling methods to write coding.
They are Gate level or structural modeling, dataflow modeling and
behavioural modeling.
PROCEDURE:
1. Start the Xilinx project navigator tag by using the desktop shortcut Xilinx
Icon.
2. Create a new project by selecting file---New project. Specify the project
name and location and click Next
3. Open the device property & check for necessary conditions. Click Next upto
finish.
4. To create new Verilog files select new source and then Verilog module. Give
the appropriate name to the file.
5. The program is entered and saved.
6. To check whether the program is correct go to process---synthesis---check
syntax. If errors occur debug it.
7. A test bench file is created by selecting new source---test bench waveform.
Give the appropriate name and give the values of the input and save the file.
8. The mode is changed to Behavioral simulation for creating a test bench file.
9. Now select .tbw file and then go to process---Xilinx ISE simulator---
Simulate behavioral module. The simulated waveform appears on the screen.
10.The markers are placed at different location and the output is verified.
CODINGS:
1. Half Adder
A B CARRY SUM
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
module ha(a,b,sum,carry);
input a,b;
output sum,carry;
xor x1(sum,a,b);
and a1(carry,a,b);
endmodule
2. Full Adder
A B C CARRY SUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
module fa(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire w1,w2,w3;
xor x1(w1,a,b,);
xor x2(sum,w1,c);
and a1(w2,a,b);
and a2(w3,w1,c);
or o1(carry,w3,w2);
endmodule
3. Half Subtractor
A B BORROW DIFFERENCE
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
module hs(a,b,di,bo);
input a,b;
output di,bo;
wire w1;
not n1(w1,a);
xor x1(di,a,b);
and a1(bo,w1,b);
endmodule
4. Full Subtractor
A B C BORROW DIFFERENCE
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
module fs(a,b,c,di,bo);
input a,b,c;
output di,bo;
wire w1,w2,w3,w4,w5;
xor x1(w3,a,b);
xor x2(di,w3,c);
not n1(w1,a);
not n2(w2,w3);
and a1(w4,b,w1);
and a2(w5,c,w2);
or o1(bo,w4,w5);
endmodule
5. Multiplexer(4:1)
S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3
module mux(s1,s0,i0,i1,i2,i3,y);
input i0,i1,i2,i3,s0,s1;
output y;
wire y0,y1,y2,y3,s0bar,s1bar;
not n1(s0bar,s0);
not n2(s1bar,s1);
and a1(y0,i0,s1bar,s0bar);
and a2(y1,i1,s1bar,s0);
and a3(y2,i2,s1,s0bar);
and a4(y3,i3,s1,s0);
or o1(y,y0,y1,y2,y3);
endmodule
6. De-multiplexer(1:4)
DATA SELECT OUTPUTS

S1 S0 D0 D1 D2 D3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D
module demux(s1,s0,d,y0,y1,y2,y3);
input d,s0,s1;
output y0,y1,y2,y3;
wire s0bar,s1bar;
not n1(s0bar,s0);
not n2(s1bar,s1);
and a1(y0,d,s1bar,s0bar);
and a2(y1,d,s1bar,s0);
and a3(y2,d,s1,s0bar);
and a4(y3,d,s1,s0);
endmodule
RESULT:
DATE:
EXNO: 10
SIMULATION OF SEQUENTIAL CIRCUITS USING HARDWARE
DESCRIPTION LANGUAGE
AIM:
To Design combinational and sequential circuits using Verilog HDL.
APPARATUS REQUIRED:
Personal computer & Xilinx 8.1 Software
THEORY:
HDL is a language that describes the hardware of Digital system in a text
form. It resembles a programming language, but it is specifically oriented to
describing hardware structure and behavior. It can be used to represent logic
diagrams, Boolean expressions and other more complex digital circuits.
There are two standard HDL; they are Verilog HDL & VHDL.
VHDL is very high speed integrated circuit hardware description language. It was
formulated by IEEE Engineers and it is not user friendly. But, Verilog HDL is user
friendly and uses three modeling methods to write coding.
They are Gate level or structural modeling, dataflow modeling and
behavioural modeling.
PROCEDURE:
1. Start the Xilinx project navigator tag by using the desktop shortcut Xilinx
Icon.
2. Create a new project by selecting file---New project. Specify the project
name and location and click Next
3. Open the device property & check for necessary conditions. Click Next upto
finish.
4. To create new Verilog files select new source and then Verilog module. Give
the appropriate name to the file.
5. The program is entered and saved.
6. To check whether the program is correct go to process---synthesis---check
syntax. If errors occur debug it.
7. A test bench file is created by selecting new source---test bench waveform.
Give the appropriate name and give the values of the input and save the file.
8. The mode is changed to Behavioral simulation for creating a test bench file.
9. Now select .tbw file and then go to process---Xilinx ISE simulator---
Simulate behavioral module. The simulated waveform appears on the screen.
10.The markers are placed at different location and the output is verified.
CODINGS:
1. 4-Bit Binary counter

module counter(clk,rst,q);
input clk,rst;
output [3:0]q;
reg [3:0]q;
always @(posedge clk or posedge rst)
begin
if(rst)
q=4b0000;
else
q=q+1;
end
endmodule
2. MOD-10 Counter
input clk,rst;
output [3:0]q;
reg [3:0]q;
begin
if(rst)
q=4b0000;
elseif (q= = 4b1001)
q=4b0000;
else
q=q+1;
end
endmodule
3. MOD-12 Counter
input clk,rst;
output [3:0]q;
reg [3:0]q;
begin
if(rst)
q=4b0000;
elseif (q= = 4b1011)
q=4b0000;
else
q=q+1;
end
endmodule
4. Serial in serial out(SISO)

module siso(clk,rst,d,q);
input clk,rst,d;
output q;
reg q; reg [3:0]x;
begin
if(rst)
x=4b0000;
else
begin
x[3:0]={d,x[3:1]}; q=x[0];
end
end
endmodule
5. Serial in parallel out(SIPO)

module sipo(clk,rst,d,q);
input clk,rst,d;
output [3:0]q;
reg [3:0]q;
reg [3:0]x;
begin
if(rst)
x=4b0000;
else
begin
x[3:0]={d,x[3:1]};
q=x;
end
end
endmodule
6. Parallel in parallel out(PIPO)
module pipo(clk,rst,d,q);
input clk,rst;
input [3:0]d;
output [3:0]q;
reg [3:0]q;
begin
if(rst)
q=4b0000;
else
q=d;
end
endmodule
7. Parallel in serial out(PISO)

module piso(clk,rst,d,load,shift,q);
input clk,rst,load,shift;
input [3:0]d;
output q;
reg q;
reg [3:0]x;
begin
if(rst)
begin
q=4b0000;
x=4b0000;
end
elseif (load)
x=d;
elseif (shift)
begin
q=x[0];
x[3:0]={0,x[3:1]};
end
end
endmodule
RESULT:

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SARANATHAN COLLEGE OF ENGINEERING

1. Verification of Boolean theorems using digital logic gates

S.NO DATE NAME OF THE EXPERIMENT SIGNATURE

VERIFICATION OF LOGIC GATES

S.NO APPARATUS QUANTITY

Digital Trainer kit

3-INPUT NAND GATE:

APPLICATIONS OF BOOLEAN ALGEBRA AND DE-MORGANS

S.NO APPARATUS QUANTITY

1 Digital Trainer kit

1) Laws of Boolean Algebra

ii. Associative Law

2) Rules of Boolean Algebra

1. Give connections as per the logic diagram.

3. Verify the corresponding truth table.

S.NO APPARATUS QUANTITY

1 Digital Trainer kit 1

1. Give connections as per the logic diagram.

3. Verify the corresponding truth table.

K-Map for SUM: K-Map for CARRY:

K-Map for SUM:

SUM = ABC + ABC + ABC + ABC

K-Map for CARRY:

K-Map for DIFFERENCE:

K-Map for BORROW:

K-Map for Difference:

Difference = ABC + ABC + ABC + ABC

DESIGN AND IMPLEMENTATION OF CODE CONVERTERS USING

S.NO APPARATUS QUANTITY

1 Digital Trainer kit 1

1. Give connections as per the logic diagram.

3. Verify the corresponding truth table.

K-Map for G3:

K-Map for G1:

| Binary input | Gray code output |

K-Map for B3:

K-Map for B2:

K-Map for B1:

K-Map for E2:

K-Map for E0:

| BCD input | Excess 3 output |

| Excess 3 Input | BCD Output |

DESIGN AND IMPLEMENTATION OF 4-BIT BINARY

S.NO APPARATUS QUANTITY

4 BIT BINARY ADDER:

4 BIT BINARY SUBTRACTOR:

4 BIT BINARY ADDER/SUBTRACTOR:

1. Give connections as per the logic diagram.

3. Verify the corresponding truth table.

PIN DIAGRAM FOR IC 7483:

Input Data A Input Data B Addition Subtraction

DESIGN AND IMPLEMENTATION OF BCD ADDER USING MSI DEVICES

S.NO APPARATUS QUANTITY

1 Digital Trainer kit 1

1. Give connections as per the logic diagram.

3. Verify the corresponding truth table

Input Data A Input Data B OUTPUT

BCD SUM CARRY

DESIGN AND IMPLEMENTATION OF 16-BIT ODD/EVEN

Sl.No. COMPONENT SPECIFICATION QTY.

A parity bit is used for detecting errors during transmission of binary

EVEN PARTITY GENERATOR

ODD PARITY GENERATOR