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How to write to two output ports from inside architecture in VHDL?
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I encountered a problem when trying to connect a component to two output ports of parent hierarchy in
VHDL. Since the physical connection can be done only via "port map" statement, there is no way to
0 connect local signal to more than one output port. Here is an example:
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Linked
1
[VHDL]Using signal to drive output ports,why are
the output ports not visible?
entity HIER is 5
port (
IN1 : in bit;
OUT1, OUT2 : out bit); How to specify an integer array as generic in
end hier; VHDL?
Wouldn't it be better to have just one OUT port and connect OUT to both ports where OUT1 and OUT2 are
connected to? simon Aug 28 '12 at 7:10 [VHDL]Using signal to drive output ports,why are
the output ports not visible?
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1 Answer active oldest votes How to map a port in VHDL?
3
Is there a reason why you cannot create an internal signal and use that signal to drive the two output
ports like this? VHDL - Port mapping - Map different ports of a
7 component into different entities
entity HIER is
port (
IN1 : in bit; 0
OUT1, OUT2 : out bit);
end hier; Warning of an unconnected output port in UART's
VHDL code
architecture HIER_IMPL of HIER is
signal temp : bit;
component BUF is 1
port (a : in bit; o : out bit);
end component;
How to implement a 4 bit ALU in VHDL using an
begin
opcode
BUF1 : BUF port map (a => IN1, o => temp);
OUT1 <= temp;
OUT2 <= temp; Hot Network Questions
end HIER_IMPL; Remove spaces from macro argument
share improve this answer answered Aug 27 '12 at 14:50 Covfefify a string
Thanks! My intension was assignment-free solution. It looks like it is impossible to do it without assignments. Sum of Squares of odd numbers
The second option is not acceptable as it involves two buffers. mkostya Aug 28 '12 at 10:18
Worth writing, if end is obvious
@mkostya Please accept this answer if it solves your problem. Josh Aug 31 '12 at 12:40
Wife agrees with parenting, but is less strict on
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