ISRA UNIVERSITY

Department of Electrical Engineering

Course Code Course Name Credit Hours

ESVD-451 Very Large Scale Integration Technology 4 (3 + 3)
Objectives:
At the end of this course, the student will be able to:
1. Understand and Experience VLSI Design Flow.
2. Learn Transistor-Level CMOS Logic Design.
3. Understand VLSI Fabrication and Experience CMOS Physical Design.
4. Learn to Analyze Gate Function and Timing Characteristics .
5. Study High-Level Digital Functional Blocks.
6. Visualize CMOS digital chip design.

Chapters (Theory) Hours

1. MOS/CMOS Transistor Logic 10
1.1. The inverter, The NAND gate, Combinational Logic
1.2. The NOR gate, Compound gates, Pass Transistors and Transmission gates
1.3. Tristates, Multiplexer
1.4. Latches and Flip Flop
1.5. CMOS Fabrication and Layout, Inverter cross section
1.6. Fabrication Process, Layout design rules
1.7. VLSI Design Flow, Design Specification/Entry
1.8. Functional Simulation, Timing Simulation
1.9. Fusion/Fabrication into Chip, Packaging and Testing

Test#01 1

2. MOS Transistor Theory 7

2.1. Ideal I-V Characteristics, Non-Ideal I-V Effects
2.2. Channel Length Modulation, Junction Leakage
2.3. Tunneling, Temperature Dependence
2.4. DC Transfer Characteristics
2.5. Noise Margin
2.6. Switch Level RC Delay Model

3. CMOS Processing Technology 4

3.1. CMOS Technologies
3.2. Wafer formation, Photolithography
3.3. Well and Channel formation, Isolation
3.4. Gate/Source/Drain Formation

Test#02/Mid Term Review 2

MID Term
4. FPGA Based System 5
 4.1. Basic Concept
4.2. Boolean Algebra
4.3. Schematic and Logical Symbol
4.4. Digital design and FPGA (FPGA Role, Types, FPGA Vs custom VLSI)
4.5. FPGA based system design (Goals and techniques, Hierarchical design, Design
abstraction).

5. VLSI Technology 3
5.1. Wires (Structure, Parasitic, Models, Delay through RC transmission wire)
5.2. Registers and RAM
5.3. Packages and Pads

Test#03 1

6. FPGA Fabrics 3
6.1. FPGA Architecture
6.2. SRAM based FPGA (overview, logic elements, interconnection networks)
6.3. Permanently Programmed FPGA
6.4. Circuit design of FPGA fabric

7. Combination Logic 4
7.1. The logic design Process
7.2. Hardware description language (HDL, Verilog, VHDL)
7.3. Combinational network delay
7.4. Power and energy optimization

8. VHDL 6
8.1. Introduction
8.2. Behavioral Modeling
8.3. Basic Construct
8.4. Library
8.5. Functions

Test#04/Final Term Review 2

Total Chapters: 08 Total Hours: 48

Recommended Textbook:
1. CMOS VLSI Design- A Circuits and Systems prospective, by Neil H.E Weste
2. VLSI Design by Pucknell

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