ENGR 271 HW #5 NAME____SOLUTIONS__________

1.) Design a digital circuit to control the process described below by designing a
finite state machine (FSM).

The prototype of an electrically controlled

pneumatically operated domestic trash compactor is
equipped with a pre-compactor (1A) and a main
compactor (2A).
When the start button is pressed, the pre-compactor
advances and then retracts. After the pre-compactor
fully retracts, the main compactor can extend and
retract. The pre-compactor cannot start unless the
main compactor is fully retracted. Limit switches
sense cylinder positions. In the event that the main
compactor does not reach its forward end position
(bin full) the return stroke is initiated by a pressure
switch.

Inputs:
Start Button (PB1)
Limit Switch indicating that 1A is in the retracted position (LS1R)
Limit Switch indicating that 1A is in the extended position (LS1E)
Limit Switch indicating that 2A is in the retracted position (LS2R)
Limit Switch indicating that 2A is in the extended position (LS2E)
Pressure switch Bin Full (PW1)

Outputs:
Pre-compactor Cylinder 1A Extend (1AE)
Pre-compactor Cylinder 1A Retract (1AR)
Main compactor Cylinder 2A Extend (2AE)
Main compactor Cylinder 2A Retract (2AR)

Process Steps:
Both cylinders start in the retracted position.
o LS1R and LS2R will be indicating the cylinders are retracted.
When the button (PB1) is pressed the Pre-compactor Cylinder 1A will
extend.
When (LS1E) indicates that cylinder 1A is fully extended the cylinder will
retract.
When (LS1R) indicates that cylinder 1A is fully retracted the Main
compactor Cylinder 2A will extend.

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ENGR 271 HW #5 NAME____SOLUTIONS__________

When (LS2E) indicates that cylinder 2A is fully extended or that the

Pressure switch (PW1) indicates that the bin is full cylinder 2A will retract.
When (LS2R) indicates that cylinder 2A is fully retracted the system will be
ready to begin again.

a. Make a state diagram for the process using the Moore Machine model
b. Make a next state table using D flip-flops
c. Solve for Boolean expressions for the outputs and the inputs to the flip-flops
d. Draw out the circuit

Current State Input Next State Outputs Flip Flop Inputs

State Name Q2 Q1 Q0 PB1 LS1E LS1R LS2E PW1 LS2R Q2(t+1) Q1(t+1) Q0(t+1) 1AE 1AR 2AE 2AR D2 D1 D0
A 0 0 0 0 X X X X X 0 0 0 0 0 0 0 0 0 0
A 0 0 0 1 X X X X X 0 0 1 0 0 0 0 0 0 1
B 0 0 1 X 0 X X X X 0 0 1 1 0 0 0 0 0 1
B 0 0 1 X 1 X X X X 0 1 0 1 0 0 0 0 1 0
C 0 1 0 X X 0 X X X 0 1 0 0 1 0 0 0 1 0
C 0 1 0 X X 1 X X X 0 1 1 0 1 0 0 0 1 1
D 0 1 1 X X X 0 0 X 0 1 1 0 0 1 0 0 1 1
D 0 1 1 X X X 0 1 X 1 0 0 0 0 1 0 1 0 0
D 0 1 1 X X X 1 0 X 1 0 0 0 0 1 0 1 0 0
D 0 1 1 X X X 1 1 X 1 0 0 0 0 1 0 1 0 0
E 1 0 0 X X X X X 0 1 0 0 0 0 0 1 1 0 0
E 1 0 0 X X X X X 1 0 0 0 0 0 0 1 0 0 0

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ENGR 271 HW #5 NAME____SOLUTIONS__________

From Logic Friday

1AE = Q2' Q1' Q0;

1AR = Q2' Q1 Q0';
2AE = Q2' Q1 Q0;
2AR = Q2 Q1' Q0';
D2 = Q2' Q1 Q0 LS2E + Q2' Q1 Q0 PW1 + Q2 Q1' Q0' LS2R';
D1 = Q2' Q1 Q0' + Q2' Q1' Q0 LS1E + Q2' Q1 LS2E' PW1';
D0 = Q2' Q1' Q0' PB1 + Q2' Q1' Q0 LS1E' + Q2' Q1 Q0' LS1R + Q2' Q1 Q0 LS2E'
PW1';

2.) Design a Sequence Recognizer that will recognize the sequence 11011 by
designing a finite state machine (FSM). The input will be (X) and when the
pattern is seen the output (Z) will be 1.

Example:

X=101011011011

Z=000000001001

a. Make a state diagram for the process using the Moore Machine model
b. Make a next state table using D flip-flops
c. Solve for Boolean expressions for the outputs and the inputs to the flip-flops
d. Draw out the circuit

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ENGR 271 HW #5 NAME____SOLUTIONS__________

Current State Input Next State Outputs Flip Flop Inputs

State Name Q2 Q1 Q0 X State Name Q2(t+1) Q1(t+1) Q0(t+1) Z D2 D1 D0
A 0 0 0 0 A 0 0 0 0 0 0 0
A 0 0 0 1 B 0 0 1 0 0 0 1
B 0 0 1 0 A 0 0 0 0 0 0 0
B 0 0 1 1 C 0 1 0 0 0 1 0
C 0 1 0 0 D 0 1 1 0 0 1 1
C 0 1 0 1 C 0 1 0 0 0 1 0
D 0 1 1 0 A 0 0 0 0 0 0 0
D 0 1 1 1 E 1 0 0 0 1 0 0
E 1 0 0 0 A 0 0 0 0 0 0 0
E 1 0 0 1 F 1 0 1 0 1 0 1
F 1 0 1 0 D 0 1 1 1 0 1 1
F 1 0 1 1 C 0 1 0 1 0 1 0

Z = Q2 Q1 Q0;
D2 = Q2' Q1 Q0 X + Q2 Q1' Q0' X;
D1 = Q2 Q1' Q0 + Q2' Q1 Q0' + Q1' Q0 X;
D0 = Q1' Q0' X + Q2 Q1' Q0 X' + Q2' Q1 Q0' X';

3.) Exercise 3.30 Design an FSM with one input, A, and two outputs, X and Y. X
should be 1 if A has been 1 for at least three cycles altogether (not necessarily
consecutively). Y should be 1 if A has been 1 for at least two consecutive cycles.
Show your state transition diagram, encoded state transition table, next state and
output equations, and schematic.

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ENGR 271 HW #5 NAME____SOLUTIONS__________