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IRF9540NS/L
HEXFET Power MOSFET
l Advanced Process Technology
l Surface Mount (IRF9540S) D
VDSS = -100V
l Low-profile through-hole (IRF9540L)
l 175C Operating Temperature
RDS(on) = 0.117
l Fast Switching
G
l P-Channel
l Fully Avalanche Rated
ID = -23A
S
Description
Fifth Generation HEXFETs from International Rectifier utilize
advanced processing techniques to achieve extremely low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
HEXFET Power MOSFETs are well known for, provides the
designer with an extremely efficient and reliable device for
use in a wide variety of applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the highest
power capability and the lowest possible on-resistance in
any existing surface mount package. The D2Pak is suitable D 2 Pak TO-262
for high current applications because of its low internal
connection resistance and can dissipate up to 2.0W in a
typical surface mount application.
The through-hole version (IRF9540L) is available for low-
profile applications.
4/3/02
IRF9540NS/L
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage -100 V VGS = 0V, ID = -250A
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient -0.11 V/C Reference to 25C, ID = -1mA
RDS(on) Static Drain-to-Source On-Resistance 0.117 VGS = -10V, I D = -11A
VGS(th) Gate Threshold Voltage -2.0 -4.0 V VDS = VGS, I D = -250A
gfs Forward Transconductance 5.3 S VDS = -50V, ID = -11A
-25 VDS = -100V, V GS = 0V
IDSS Drain-to-Source Leakage Current A
-250 VDS = -80V, VGS = 0V, TJ = 150C
Gate-to-Source Forward Leakage 100 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage -100 VGS = -20V
Qg Total Gate Charge 97 ID = -11A
Qgs Gate-to-Source Charge 15 nC VDS = -80V
Qgd Gate-to-Drain ("Miller") Charge 51 VGS = -10V, See Fig. 6 and 13
td(on) Turn-On Delay Time 15 VDD = -50V
tr Rise Time 67 ID = -11A
ns
td(off) Turn-Off Delay Time 51 RG = 5.1
tf Fall Time 51 RD = 4.2, See Fig. 10
Between lead,
LS Internal Source Inductance 7.5 nH
and center of die contact
Ciss Input Capacitance 1300 VGS = 0V
Coss Output Capacitance 400 pF VDS = -25V
Crss Reverse Transfer Capacitance 240 = 1.0MHz, See Fig. 5
-23
(Body Diode) showing the
A
I SM Pulsed Source Current integral reverse G
-76
(Body Diode) p-n junction diode. S
Notes:
Repetitive rating; pulse width limited by Pulse width 300s; duty cycle 2%.
max. junction temperature. ( See fig. 11 )
Starting TJ = 25C, L = 7.1mH Uses IRF9540N data and test conditions
RG = 25, I AS = -11A. (See Figure 12)
ISD -11A, di/dt -470A/s, VDD V(BR)DSS,
TJ 175C
** When mounted on 1" square PCB (FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
IRF9540NS/L
100 100
VGS VGS
TOP - 15V TOP - 15V
- 10V - 10V
- 8.0V - 8.0V
- 7.0V
-ID , Drain-to-Source Current (A)
- 7.0V
10 10
-4.5V
100 2.5
I D = -19A
R DS(on) , Drain-to-Source On Resistance
-ID , Drain-to-Source Current (A)
TJ = 25C
2.0
TJ = 175C
10
(Normalized)
1.5
1.0
1
0.5
VDS = -25V
20s PULSE WIDTH VGS = -10V
0.1 0.0 A
A
4 5 6 7 8 9 10 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
20
3000 I D = -11A
V GS = 0V, f = 1MHz
C iss = Cgs + C gd , Cds SHORTED VDS = -80V
2000 Ciss
12
1500
8
Coss
1000
Crss
4
500
FOR TEST CIRCUIT
SEE FIGURE 13
0
0 A
A 0 20 40 60 80 100
1 10 100
-VDS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC)
100 1000
OPERATION IN THIS AREA LIMITED
-ISD , Reverse Drain Current (A)
BY R DS(on)
-I D , Drain Current (A)
10 100
TJ = 175C
TJ = 25C
100s
1 10
1ms
TC = 25C
TJ = 175C 10ms
VGS = 0V Single Pulse
0.1 A 1 A
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1 10 100 1000
-VSD , Source-to-Drain Voltage (V) -VDS , Drain-to-Source Voltage (V)
25
RD
V DS
20 V GS
D.U.T.
ID , Drain Current (A)
RG -
+ V DD
15
-10V
Pulse Width 1 s
10 Duty Factor 0.1 %
td(on) tr t d(off) tf
VGS
0
25 50 75 100 125 150 175 10%
TC , Case Temperature ( C)
1
D = 0.50
0.20
0.10 PDM
0.1
0.05 t1
0.02 SINGLE PULSE t2
0.01 (THERMAL RESPONSE)
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001 0.0001 0.001 0.01 0.1 1
t1 , Rectangular Pulse Duration (sec)
1200
ID
600
400
15V
0 A
25 50 75 100 125 150 175
I AS Starting TJ , Junction Temperature (C)
tp
V(BR)DSS
Current Regulator
Same Type as D.U.T.
50K
QG 12V .2F
.3F
-10V -
QGS QGD D.U.T. +VDS
VGS
VG
-3mA
IG ID
Charge Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit
IRF9540NS/L
Peak Diode Recovery dv/dt Test Circuit
+
- +
-
RG dv/dt controlled by RG +
ISD controlled by Duty Factor "D" V DD
-
D.U.T. - Device Under Test
VGS
[VGS=10V ] ***
Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
[VDD]
Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent
Ripple 5% [ISD]
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
4.10 (.161) 1.50 (.059)
3.90 (.153) 0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
30.40 (1.197)
NOTES : MAX.
1. COMFORMS TO EIA-418. 26.40 (1.039) 4
2. CONTROLLING DIMENSION: MILLIMETER. 24.40 (.961)
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 3
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.4/02