Escolar Documentos
Profissional Documentos
Cultura Documentos
QUITO-ECUADOR
NOVIEMBRE DE 1995
Certifico qu el- presente trabajo
tesis ha sidq^realizado -en: su totali
prSrta:. ,-
HELE50FiA~tBRRERA SAAVE
Dfreco de T
p jfud cfite es poderoso para hacer todas las
cosas mucho ms abundantemente de lo fue pedimos o
entendemos, segn el poder que acta en nosotros, kl
06g de los Obelos, inmortal invisible, al nico ^
sabio ^)ios sea honor p gloria por los siglos de los
siglos, 'A^mn. ((5if 3.- 20 -J^i J.-J7)
Pa
INTRODUCCIN
CAPITULO I
CAPITULO III
TCNICAS DE MODULACIN FM Y PM
Mtodo directo 13
Mtodo indirecto 14
CAPTULO V
5.3. Conclusiones 14
5.4. Recomendaciones 15
i
Anexo A: Hoja de datos de los principales elementos utilizadas1
Cuando los parmetros que varan en la seal portadora son el ngulo de fase
la frecuencia, ocurre el proceso de modulacin angular y como la onda pue
representarse en forma de un fasor porque es una funcin exponencial
mensaje, se le conoce tambin como modulacin exponencia!, esto es
= A eos 6(f) = Re [A
=A eos
T 2T t
A (\ VA A A f
i ]f
ui/u y
1 T
/ U Ui
Fig. No.1.1
donc/e 8() = co c f + Y0
dt
dt s
c,(f) = 2nf.(f)
Ec. 1.2
d9 A df(t) rad,
Ac L* . Ec. 1.3
dt dt s
Ec. 1.4
Fig,No.1.2
8(t) y u, en funcin dei tiempo para una seal PM
K, f(T) dr + 9D [rad]
f [t] '
A A A
FM W
Fig. No.1.3
8(t) y w, en funcin del tiempo para una seal FM
1.2.- ANLISIS ESPECTRAL:
f(f) = a eos co m f
y si se asume 8Q = O , se tiene:
a 2rr K,
$(t)FM = A cosfcoj + 1 sen u f ]
co m
2nAf Af o
Ec.
Las funciones;
f sen (m y s e n ^ sen (m
n
J (P,) A / e cfA Ec. 1.10
n ' 2n J-n
con A = comt
E
n=-
cos() Cjf
0.8
Portadora
la, frecuencia lateral
a i.Q n 12 13 u 15
Fig.No.1.4
Coeficientes de Bessel para las componentes espectrales
en la modulacin de fase y de frecuencia
f /
= P1 sen C1 t + P2 sen C2 t
(t)FM = A [eos 3cf eos (a1 + oc2) - sen (Oc sen (a1 + a2)
.8=1
A-Z A-Z
,3 = 5
= 20
au AW
ib]
Ec.1.11
fif = 1000Hz
= 500HZ
o.e -
0.4 -
i
0.2 -
J. f (KHz)
-4 -3 -2
1
0.4-
v
.2-
f (KHz)
1
varan de acuerdo al ndice de modulacin y por lo tanto dependen
de la amplitud y frecuencia de la seal modulante, aunque la
potencia total de la onda modulada permanece constante, en
contraste con la modulacin lineal.
Ec.1.12
si se reemplaza a Ae por p
Ec.1.12
12
de una sene! AM (m<1).
Fasor Portadora
u, % 2wm
Componentes fasj Fales
de.una seal modulada en ngulo
-2wra
0.4
a.1. Si pf es grande:
BW = 2 Af
BW =
p _ A 2
2 (t\
r FMIPM W
Ec. 1.13
pasa a travs de un dispositivo no lineal, la seal resultante contiene
misma informacin de frecuencia instantnea que la sea! FM origin
porque se comporta como si se tratara de una seal sinusoidal
frecuencia nica. La salida c|>0(t) de un circuito no lineal puede ser expandi
como una serie de Fourier de un conjunto de ondas FM de la forma:
E a n cos
Ec. 1.14
donde los coeficientes son exactamente los mismos que seran obtenid
si el circuito es alimentado por; A cos coct [2]. La expansin en esta serie
Fourier muestra que una seal proporcional a la seal FM original con
misma frecuencia instantnea, puede ser obtenida filtrando l
componentes de $0(t) que estn centradas alrededor de la frecuencia coc.
el circuito no lineal hace que a., sea independiente de A y de igual forma
salida del filtro de banda estrecha que se quiera utilizar, se tiene com
resultado un efectivo limitador FM. Si un filtro de banda estrecha
empleado para extraer las componentes de <J)0(t) centradas alrededor de
frecuencia ncoc se obtiene una seal FM con una frecuencia instantn
proporcional a f(t) pero con n veces la desviacin de frecuencia y n vec
la frecuencia portadora de
r fCr)cT
fc
Ec.1.16
/ -J cos
n=1
Ec. 1.17
,0 (w)
Desviacin: a w Desviacin : a w3 -
ndice de modulacin : J& ndice de modulacin : .3 =3.6
Fig. No.1.9
Espectro de una seal con modulacin angular a travs de una red no
lineal
1
fundamental FM de 4>0(t) puede ser filtrada siempre que
BW , ,
! + -- < Cu
Ec. 1.18
BW
2Ao1 2AX
'max
Relacin lmite para separar la componente
0.6 fundamental de la tercera armnica
0.5 -I
0.4
0.3
0.2 Relacin lmite para separar la componente
fundamental de la segunda armnica
0.1
1 2 3 4 5 6 7 8 9 10 11
Fig. No.1.10
Grfico de Dmx en funcin de p
Ec.1.19
=A cos [ U f + f ] =4 Re
IJJ(f) = AC f f ( T ) d T
donde
G = a=
LC
c/co
mx
Ac < 1
a2 P a a ~2
TIPOS DE MODULACIN FM Y PM
De acuerdo al valor del ndice de modulacin [3, las seales moduladas en fase
en frecuencia se definen como de banda ancha o de banda estrech
establecindose el lmite mximo para (5 entre estos dos tipos de modulacin igu
al valor de 0.6.
2
A partir de la Ec.1.6 que describe la sea! FM con un tono cosenoidal e
calidad de modulante se desarrolla la expresin de una seal de band
estrecha considerando las restricciones expuestas en la siguiente forma:
y sen ($fsen Cm f ) ~
$AM ^ ) =A ( C O S ^c t * m Sen m t C O S Wc f )
Ec.2.2
(J)(f ) = A (eos co t + K g (t ))
2
si $f 1 ** K g (f) 1
'-.. -fi/2
Portadora = 1
.& sen w m t
"\)
Resuftarite
(a) (b)
r
= A [eos tc f - -i- [eos (0)c - Cm )f - (Oc + Cm )f ] ]
= Re [A e J c (1 - e J m +
2 2
^ R e / l e " ( 1+ - e - e - ) ]
2 2
26
Fig. No. 2.2
Generacin de una seal NBFM
cj>(f )PM = A [eos u c t eos (Ae f ( t ) ) - sen coc f sen (AB f (t ))]
A 9 n/2 =- A e f ( f ) n/2
NBPM
= eos Cu f - Afi f (t) sen u t
Oscilador f = f c + M.f[t]
Controlado Filtro Salida
Pasabandas
por Voltaje Modulada
Seal modulante
pf i
GSO
29
Si se utiliza por ejemplo el VCO LM566 [13] para el diseo del circu
WBFM, el valor del resto de elementos se determina a continuacin.
v*-v. o
V+ RC
Ec.2,3
Seal de salida
Muestras Sinusoidales
M f; C p
Ec. 2.5
r
Mf,Cr I LJ
2TTC
CC 2TT
C, M
Ec. 2.6
Ec.2.7
3
Magnitud
Frecuencia
2n r, C,
Ec.2.8
1- f(t)
KV GSO
Ec.2.9
3
valores
- A9 < e. * AQ
puesto que
f(t) <1
3
M =P (X < x) = Fx (x)
X = AfZ
P (
Af z Af
Ec.2.15
donde -
P(f/) = P(f~fc)
/2noz
'c+Gf
nc(t) Y Hs(t) son seales de baja frecuencia de banda limitada a cm, siend
las potencias (valores cuadrticos medios) de n(t), r\(i) y ns(t) idnticas, est
es:
n 2 (0 = ni O = ni (O
para co > co
3
acompaar a la seal. Si se supone que es posible calcular la potencia
la seal a la'salida del demodulador independientemente de la potencia
ruido, esto es, asumir que el ruido es cero y que la seal f(t) es c
respectivamente se tiene;
A/,. = 2 N Af
2 a 2 N co^
3 A 2 TT
Po _ 3 2TTA2 A32 f ( f ) :
2 ' N
fm
considerando la condicin ms favorable para AM, cuando la modulacin
del 100% y la amplitud def(t) igual a A (la misma que la de la portadora),
tiene la siguiente expresin:
N FM _ A AOJ2 2
- - - o p FW
P '*
Jrct) at
3
Ui(f)es una funcin peridica con perodo T
m
=2n/r
3 r/4
Fn=~
" T J
-774
-/QTT/2]
- n)n/2 (P + n)n/2
PA
Las dos frecuencias utilizadas co1 para +1 y co2 para -1 de la seal modul
deben ser seleccionadas de tal forma que no produzcan distorsin e
proceso de demodulacin si estn muy prximas o no incrementen el an
de banda de transmisin si estn muy distantes.
nn
2AC = donde n = 2,4,...
T
-6-5
-S- 20
Ac T = o 2 AfT = -
co
Aoo =
donde r(0) es ia fase inicial que debe ser tal que evite discontinuidade
generalmente igual a cero.
Ec. 2.16
si cos AQ - m
COS ^ *m + ~m A COS
TCNICAS DE MODULACIN FM Y PM
Al final del Captulo se muestran los circuitos, de entre los cuales se escoge uno
que se debe aadir a un modulador para garantizar estabilidad en la seal FM.
4
generada inicialmente, la estabilidad de la seal FM resultante e
controlada por a estabilidad del oscilador a cristal.
con )(t) para cualquiera de las dos seales igual a coc+2nAf f(t).
' Ec.3.1
ufa
Ec.3.2
'
C0,(f) X(T
o
t
>/ (*) f w," (T) $("0 rfr + cj)(f) = o
o
4>(o) =
A = A^ x 1 + Az x O
A2 = O
Fg.No,3.1
Diagrama de bloques de un computador analgico
para la simulacin de la ecuacin diferencial FM
v.(t)
K,
o expresndolo en otra forma que
Ec.3.3
donde
v (t\ v (1 + f (f
Wc
U,(t)=KuK,V2V +^-
esto hace que la Ec.3.1 sea igual a a Ec.3.3, que da lugar a la portado
modulada en frecuencia d la forma:
Cf()
porque el trmino
), 3 (f)
L + 'C(0 =
-o
L J C.()
o 'x y
5
porque la frecuencia instantnea co(t) es igual a:
).() =
C (t) yL(Cc+AC(f))
1
AC(Q
c
C 2 C, 2! C
si se cumple que
3 AC(Q 2 rAC(Q.
' L J tt L .
4 C. C.
AC(f)
[1 -
2 C.
AC 'Ce
k f (t) = A C : Ce : (t)
Fig.No.3.2
Circuito resonante LC
di
AC
8(0 2n fc f + 2rr -=^ fc [ f ( T ) c / T
i e* j
donde
2C
5
Para generar seales FM directas, se utiliza un oscilador sintonizado don
la inductancia o capacitancia es variable y dependiente de la seal de aud
Existen algunas formas de obtener capacitancias o inductancias variabl
dependiendo del rango de frecuencias en el que se trabaje; por ejemplo
puede utilizar un diodo semiconductor inversamente polarizado cu
capacitancia varia ai cambiar la polarizacin inversa (se usa el dio
varactor) o un klystron, en el caso del diodo varactor, la desviacin
frecuencia no es pequea por lo que se lo utiliza para modulaciones co
portadoras de alta frecuencia y en el caso del klystron para trabajar en
rango de frecuencias portadoras mucho mas altas (en el orden de l
microondas) porque tiene las caractersticas de un oscilador line
controlado por voltaje sobre un intervalo de frecuencia de varios megaher
Otra forma de construir un modulador es en base a un tubo de reactanc
r
u
UD< -
C. diodo (pF)
30
20
MV2105
10
4 hti- ._.
3 "-
2
1
01 0.2 0.3 1 2 3 4 10
Fig.No.3.3
Capacitancia del diodo varactor en funcin
del voltaje reverso
C12 ACVVC
V1/C
/CHRF
Polarizacin de c,c.
ll" cristal
salida FH
CHRF
Cristal
1(
=p C s C
- ,- J Ls
= ACyU(, 4- Oscilador
" CP 5
> R
II
11
c,
(b)
Fig.No.3.4
(a) Oscilador a cristal modulado en frecuencia
(b) Circuito equivalente del modulador FM
con diodo varactor
AC. AC, c(
(C C vvc C
5
Cx i A
Cx /v rS r212
U uD(
AC X 2 C'x 2 (< "p c ^o
+ C ^/ ) CVV
Fig.No.3.5
Diagrama de bloques de un lazo asegurador de fase utilizado como
modulador en frecuencia
Fig.No.3.6
Diagrama de un modulador de corrimiento de fase
J9fR
R -
Vo COC
V,
COC
^ R/
R = d L R,
Si gfR 2 entonces:
COC
donde Q = arctan
CC
s(t)
Fig.No.3.7
Diagrama de bloques de un modulador por comparacin
a_z
V
Fig.No.3.8
Forma de onda de las seales a travs
del modulador por comparacin
6
3.5,- MTODO DE ARMSTRONG:
cos G c t sen Cu m
+ ' ~ sen
( c o c f + A e s e n Cm f)
75 KHz
= 375 = Factor de multDlicacin
200 Hz
Modulador Balanceado
con portadora suprimida
UAPS
Fig.No.3.9
Diagrama de bloques de un modulador FM utilizando el Mtodo de Armstrong
a. Reaiimentacin FM:
f
cj)(f) = A eos [ce f + ef + yf + Ac f f (T)C/ T]
v^ Generador FM w ff(t)dt]
-^ Desviacin: A W
ndice de modulacin :J5
salida FM
Ccos(wc-wd)t
w Jf(t)dtJ
Y - t/w] ( t + V - c/w-t-
Fig.No.3.10
Diagrama de bloques de un sistema de estabilizacin de frecuencia
Fig.No.4.1.1
Diagrama de bloques del modulador en frecuencia utilizando el mtodo directo
Ose. Interno
1 Seales de
fm = 1000Hz
1/L /W vV
Conlful
Externas
-ijijnj- mn-nn-ri
OUTPUT1
Ose. Externo
fmax-15 KHz
'w ..
Fg.No.4.1.2
Diagrama de bloques de la etapa de audio
MICRFONO
Fg.No.4.1.3
Amplificador de audio de bajo ruido
/ - 18 x 10
RA + R5 = 65.13 X 103
Con la expresin:
= 3 R
_
w _ 65.13 x 10
1.333
R4 = 48.86 x 103
RK = 15KD
Ve. x 107
- 910
2 6.05 x 103 + fc x 107
- 910
2 6.05 x 103 + 1.7 10
R 3 = 6.832KQ
= 6.8KQ
A.. = = 150
R2 = 45.63D
= 47O
R2
~
2n x 60 X 47
C =
Utilizando la expresin de la ganancia de la etapa de entrada
tenemos:
(2 105) R4
+ 2 x 105
A. =
. 0.026 4. 1
1 -f .
1 -f
1
I O4 R* R~
(2 x 10 5 )47 x 1Q 3
47 x 103 + 2 x 105
0.026 1
1.7 x 10~ 4 1 , 1 1
104 103 51
- 189.12
P.S.R.
20
10
2TT f Rc
100
10 20
C, =
1 - 4 x 10'12
a n x 15 x 103 - 026 10
1.7 x 1CT4
C, = 65.37 pF
C, = 68 pF
12 U O
Fig.No.4.1.4
Amplificador de audio de bajo ruido a implementarse
normalizada
C =
Z x FSF
P ~ p
^ ^ normalizada
Rg.No.4.1.5
Filtro de audio con fc=15KHz a implementarse
c. DISEO DE LOS OSCILADORES INTERNOS DE 400 Hz Y 1 KH
MEDIANTE EL USO DEL CIRCUITO INTEGRADO ICL3038 :
- . , - V CC(-)
R =
5 /
Ec.4.1.1
Fig.No.4.1.6
Oscilador interno a400Hzy lOOOHz
7
la Ec.No.4.1.1, se tiene:
para / = 100u,4
12
5 x 100uA
para f = 1000 Hz
Cg = - - = 12.5
24 x 103 x 1000
18
se same R17 = 15 KD = 1V = ^ 1.81/
17 + 18
R = 18.75
r
C nn
pp
R 21 = 2 KQ.
Fig.No.4.1.7
Oscilador interno a 400Hzy lOOOHza mplementarse
Seal de intermitencia
para la alarma audible
Fig.No.4.1.8
Diagrama de bloques del circuito de control de! Oscilador Externo
7
El TiMER 555 se disea como un circuito aestable que genera u
seal cuadrada de frecuencia igual a 10Hz, utilizando la aplicac
propuesta en el manual de operacin del chip [13], como se mues
en la Fig.No.4.1,9 y el valor de los elementos se calcula de
siguiente forma:
-t-S V
o
R2G RS7
i
1
ICS__
3 S
0 ? R5
S _ ._
Sen-a 1 de Contr-o 1
R
r=ana la ai ar-ma
T c
R V
U-1S55
2 s
_JiL_
~ CiS
0. i ul
Fig.No.4.1.9
Circuito aestable utilizando el LM555
C 15 =
C,, =
Se asume = 3.9/VfQ
R 27 = 3.05MQ
f? ?7 = 3.3ATQ
Este proceso se realiza para evitar el ruido que produciran los interruptor
durante la conmutacin.
Fg.No.4.1.11
Circuito de seleccin de la seal modulante
8
Seal Modulante (fm)
fr=8.33KHz
FM de
Detector de .7 MHz a 99.9 MHz
Kv
r &, Kf
Diviso r Circuito
Progr ama lies Sujetador
iz*f de 88 7 a 999
Fig.No. 4.1.12
Diagrama de bloques del circuito generador de la seal modulante
-C U 0 ,
111 1,1,1 1,
l3f1l 0 9 8 G 5 l3ia 019 SS43I2I1 0(3
R34 VDOOOCC VRCOJQPJ VRCOJQPJ
470 -iSDCiS KSS-R4 K554R-4
flftOOBB JJQQQU J JQOG.J
Yi U13 12Bi2G DX22J.33G
toWid^l-!3 ^D-J11 1234567 J.I23|.<US 617 9 lt2|3[4|S|6 7IB
?
ji
1 1 II T - - T * U ulsrj
CO-301B ]
^[^ _[__ 2.2M >R3H CD431S
-^p-Ci4 T^ C13 /S.2M 1__
j 27 f=F | 27 PF | 1^
. .. .
r
SEAL. DE REFERENCI
A e.
Fig.No.4.1.13
Circuito generador de la seal de referencia a 8.33 KHz
Fig.No.4.1.14
Oscilador Modulador FM
mx
min CD(min) + Cs
donde f mjn =
f (c D(mx) + cs
8
para fmax = 99.9 MHz
= 19-38 pF
__ p JL P
Dmax Vmax.E/V SERIE ' 2
C2 = 19.38 pF - 6 pF
C2 = 13.38 pF
= 26-.7S pF - 13.38 pF
Cv = 26.8 pF
IDO
Fig.No.4.1.15
Grfica de la capacidad del diodo MV2105
en funcin del voltaje reverso
Vmax - Vrnm
.
= 4 V
= 2 V
- 3 7 . 6 9 * 105 [rad!seg]IV
Fig.No.4.1.16
Oscilador Modulador FM a mplementarse
R , U1 PU UF
Detector de Fase
Charge Pump
V DI PD DF
Fig.No.4.1.17
Diagrama de bloques del circuito integrado MC4044
U-t
D1
Fig.No.4.1.18
Grfico a la salida del detector de fase del MC4044
2 e
(a) R2 > 50 Q
(b) R2/R1 < 10
(C) 1 KQ < R1 < 5 KQ y RL
riNPUT.~l_S
Fig.No.4.1.19
Detector de Fase y filtro pasabajos
fout = 87.9 MHz a 99.9 MHz
5 = 0-8
A/ = ^ = 99 ' 9 * 10
'
fref 8.3 * 103 Hz
N = 12036.145
v 5.5
10 * 10
0.1 [Virad]
= 37.69 * 10 S [rad!seg]!V
= 1
2 * 0.8
= 2.9 KQ
550 * 1 x 10
R7 = 2.7 KQ
Fig.No.4.1.20
Respuesta del filtro de segundo orden a la entrada paso
Fg.No.4.1.22
Diagrama de bloques de la etapa de potencia
Se 1 eccion d*
la f rec:urncia portador-*
Fis-No-l.1-2C
Grfico d lo di vi ore proor-omab 1 w s en 1 lazo de raal iinen-fcacion d I PLL
Af = 12 MHz
Af 12 MHz
Q = 7.83
Qc/c/r = 7'83
Fig.No.4.1.23
Amplificador clase B
Serval de Salida FM
de Q7 . SMHs: a 33. 3MH=
de enr"-ada
Fig.No.4.1.24
Amplificador clase B con elementos pasivos
El valor de las resistencias R,y R 2 se obtiene considerando un voltaj
en la base de 0.5 V y asumiendo un valor de corriente de salida.
R, = 50Q
P.,,f
; -
P
vo v
p0u, =- ~ donde Vam, = -SS.
O \J
97
/ c = 200 [mA]
n rr
s 63.33 = 0_633
B 100
sea Ir
R = 1.26 [mA]
2
Va 0-5 [VI
^2 =
IR 1.26 [mA]
= 390
B (12 - 0.5)
(1.89 * 10
R. = 6.1 KO.
2.lnr = 100
= 93.9
asumiendo L^ = 0.2yH
C? = 14.36 pF
G = 10 log
Pln
p = POU = 1
'" loq- 1 1 10
Pln = 100 mW
= 17 ; X.^.
CHRF = 1700
'a
= 2-8
. . . /~y
J_J_ Z.9UH _^
O
C3 -T- -J~ C4 -J- 1
_^. ^X- a * L
a.2 UJH ,/
Fig.No.4.1.25
Amplificador clase B (etapa de salida)
X-
X X2 = Xp
R
= +
1
X ;> A/316 * 78 = 160
se asume Xm = +280
316
(280 2 - 24648) = (280 2 -
78 \8316
Xp = 466.6 Xs = 115.2
RL.
7S
Fg. No.4.1.26
Red Transformadora de Impedancias de 78 O a 316 Q
10
Pout = 100 [mW]
Vout = 4 [V]
Z = 316 [Q]
= 12.66
P Z n 316 [Q]
I0 = op = 12.66 [mA]
n n
4.03 >3
oc
R, = 500 [Q]
= =
- o.5) [V] no - ou
4 =
= 12 [KQ]
1
En lugar del circuito tanque en el colector dei transistor, se coloca
choque de radio frecuencia, porque la red transformadora
impedancias que se disea a la entrada de la etapa anterior ya
selectiva:
= Zout
XCHRF 316 [D] w XCHRF = 3.16 [/CU]
= 5.3
Zin = 2 / n r u RB > RB = R3 i R4
G p = 10 [dB]
= 100 [mW]
P,n = 10
1
Vln =
= 2 * 12 * 10 X 10"3
V.lnn = 1.55
CHRF
C0 es ca B.3 u
100 UF 0.1 uF 100 pF
^OUTPUT IB
. QS
4 NTE311
|_XNPUT 1"
Fg.No.4.1.27
Amplificador clase B segunda etapa
v 2
B =
\/ G
m
1
>
1 1
480 * 120 240
1
se asume =
140
120 480
B = (
480 140 57600 120 140 57600'
B = 2.9 * 10 Xs = 0.011
+ s, =
o
= 2.9 * 10~ 3 + 7.14 * 10~3 = 10.04 * 10"3
fia = ," B^ = 0.01 + 7.14"3 = 0.01714
INPUT 1S~>
ra_
12E
Fig.No.4.1.28
Red Transformadora de Impedancias de 120 Q a 480 O
PDC2fj9lB
DC
= 70
AC2N918
A = - - 2 W = 2
= 6.25
RL 480[Q]
se asume lc - 7 [mA]
A =
(*5 + O
600
* re -
A
r - 26 [ _ _,
" -
1
R5 = (200 - 3.71) [Q] = 196.29 []
RR = 200 [D]
R - ^ = MJE. = 357_14
T /F 7 [mA]
= 1 5 0 [Q]
VB = 3.05 [V]
= 0.1
PDC 70
/ se asume ln = 1
B 3.05 [K]
R7 = 3 . 3 [ACQ]
1
1R = 1'1
R R = 8.2 [ACQ]
RB = 2.35 [Ki]
C 6 C^
CE = 165.78 pF C P = 180 pF
Se asume LK = 0 . 2
- 14.36 pF
10
Fig.No.4.1.29
Amplificador clase A y circuito fijador a implementarse
T = R * C
T T
1
T = 100 7 = 100 * = 1000 ns
93.9 * 106
R.'"MCHC404Q = 10KQ
- T _ 1000 [ns]
o 15
R 10 [KD]
El circuito total del mtodo directo de modulacin en frecuencia que incluye las tr
etapas diseadas se muestra en la Fig.No. 4.1.30.
1
4.2.- MODULADOR FM UTILIZANDO EL MTODO INDIRECTO
Se establecen tres bloques de diseo que cumplen con las siguientes condicion
y que se muestran en la Fig.No.4.2.1:
1
2.- SEAL FM A 31.25 MHz:
Multiplicador x 3
fp = 93.75 MHz
SEAL FM
Fig.No.4.2.1
Diagrama de bloques del mtodo indirecto de modulacin en frecuencia
4,2.1. - SEAL FM DE BANDA ESTRECHA.-
Sea! FM
de banda estrecha
Fig.No.4.2.2
Seal FM de banda estrecha
11
#2 del chip y de la salida serial desplazada en el pin #15 del chip,
74LS194 requiere de una seal de reloj de frecuencia igual al doble de
seal de entrada (125KHz) que se obtiene de la salida Q c del 74LS93. L
seales cuadradas son filtradas hasta obtener las seales de frecuen
fundamental. E grfico de! circuito que que defasa la seal portador y fi
las seales se muestra en la Fig.No.4.2.4.
l4l3(2 ais a
<, Rl -t- 1 SC > CIT J. 23
<' 470 Ui ,
A P l Q CS E3B LJ2
12AE 3 J- H C
123 4 se 7 OOQO :
S00KH3 ABCD
-1-
ifll i 23S1
'U1 " "
a.an >R2 OUTPUT 4")
M
ci -" "^
C
C2
i"
Fig.No.4,2,3
Seal portadora a 62.5 KHz
asumiendo C = 0.1
L = 64.8
Fg.No.4.2.4
Seal portadora filtrada y Seal portadora defasada y filtrada
R = R R = R , = 100 [KQ]
C, = 50
RS CJL0
100K 0. iuF
Fg.No,4.2.5
Generacin de ia seal modulante a 250 Hz
El mtodo requiere que la seal que acta como modulante sea en realid
la integral de la seal a ser recuperada en un demodulador.
2n *
f = 250 [Hz ]
= 27 [KQ]
1
muestra en la Fig.No.4.2.6.
Fg.No.4.2.6
Circuito ntegrador de la seal modulante
Fg.No.4.2.7
Modulador con portadora suprimida a 62.5 KHz
,/ AMPS ^ PORTADORA
V out
"30 R 31
D II D II O
~ K 30 II K31 II H32
r\"33
(1.8 || 1.8 || 1.8 ||) [KO] = 600 []
1
La sea! que se obtiene como resultado -de esta suma ingresa a
comparador que cuadra la seal para ser compatible con la entrada TTL
luego se somete a la divisin para ocho en el C.1.74LS197 que disminu
la frecuencia de la seal a 7.8125KHz . El circuito que realiza esta operaci
se muestra en la Fig.No.4.2.8.
Fg.No.4.2.8
Sumador de la seal FM de banda estrecha
Fig.No.4.2.9
Diagrama de bloques del modulador FM hasta 31.25MHz
1
El diagrama de bloques de esta etapa se muestra en la Fig.No.4.2.9.
se asume L7 = 0.8
c
^ , ,
(2TT * f) 2 * L
CTOTAL C s + CD
Cx = 6 pF
= 8.75 [pF]
C7 = 1 7 . 4 2 [pF]
Mientras que los valores del circuito tanque de salida son:
se asume CK = 8 [pF]
1
(217 * /)2 * C5
1
2n * 31.25 x 10T * 8 x 10\-12
1 1
7 = = 32 [ns]
f 31.25 x 106
T T T = 3200 [ns] ; T = R C
C, = 330 [pF]
kccsi
^KHM^
os oa
TJ =p U ^ _.
Fig.No.4.2,10
Circuito Oscilador controlado por voltaje a 31.25 MHz
1
El circuito fijador junto con el VCO se muestran en la Fig.No.4.2.10.
E, = 0.8
- = 5 x 103 \rzdlseg]
0.001
1
K =
0.1 * 37.69 X 10
= 37.69 [nF]
A/ 4000 * (5 x 10T * 1000
= 39 [nF]
p - 2 * 0.8
= 8205.13 [O]
* C 5 x 103 * 39 x 10 "9
j.ZNPUT_~ir>
Fig.No.4.2.11
Circuito detector de fase
Fg.No.4.2.12
Circuito divisor del lazo de realmentacin del PUL
1
Fig. No. 4.2.13
Diagrama de bloques del modulador FM a 93.75 MHz
Fg.No.4.2.14
Amplificador de salida clase C
Pout = 50 [mW]
f = 93.75 [MHz]
RL = 50 [Q]
Poc = 100
P,
MC.2,V3S6fi
Gp = 10 dB
v = 12 [VI
L J
f -}- 1 + -^X
Pr A
Asumiendo A = 2
^o P
( _ ?L\ P out
= 6 [V]
! =2 l = /. = 26.8
1
R =
CE..
=
12
l~
lc 26.8
3, = 447.74 [Q]
A =
_3
f * ac 447.74 [Q]
i '
Op c -) >
/e - - b.zl
n
a 4.99 [Q]
/E 5.21
R H = (223.87 - 5) [ Q] = 2 1 8.87 [ Q]
K P = R, = 220 [Q]
1
RB
O 2n
In -r
RD = R, = 22[KQ.]
[/CU]
R-il = RnQUl
,,t = 50 [LQlJ Yy c^
QUI = 8 [pF]
u- J
C2 = -1 . C, = 33.95 [pF]
1
1 C, = 102.45[pF]
2TT * 93.75 x 106 * 16.57
64.44
= 0.1
2T7 * 93.75 x 10e
"CHRF X, 'CHRF
= 6444
6444
CHRF = 10-9
2T7 * 93.75 x 10
Fig.No.4.2.15
Amplificador ciase C y red transformadora de mpedancias
1
b. Diseo de la etapa de preamplificacin a 93.75 MHz:
RL = Zout ; R L = 1.85 [K O]
Vop = 4 [V]
4 \V]
/ = L J = 2.2 [mA]
p 1.8 [KQ]
R.eq
A =
(RE + re)
RL I 1//7 oe ) ;
se asume A = 8
f a 26 ^ = 3_7
R, = 330[Q]
C7 = 750 [pF]
1
Se asume una ganancia alta porque la seal que ingresa a e
etapa es la salida del triplicador de frecuencia y mientras la se
armnica sea de mayor orden su amplitud es mucho menor.
^_^ = Q/|
Poc 70
R. = 2 . 7 [KQ]
= 1.1
= _cc
~ B r a
=
_ . = 826
/ 1.1 [mA]
R c = 8.2 [/en]
L. = 0.2
Ca = 14.41 [pF]
Fig.No.4.2.16
Preamplificador clase A
1
Los valores del tanque en el colector de este circuito son:
L* = 0-17
A = L , RE + r + ' = 600[Q]
[mA
p RLL 1.2 [K O]
= 5 [mA ]
/o = 5 * 10-
n n
^.59[mA]
1
v=2tv]
Fig.No.4.2.17
Multiplicador de frecuencia de 31.25MHza 93.75MHz
RL=1.3[KQ] , vop=2[V]
= 900 [Q]
A 2
r = 26 , = 6.5 [Q]
/c 4 [mA]
^ = V + - 6 = 4 - 24 [^
= o.05 [
Poc 70
9 = i -
" 4 ' 24 [^
= 4 ' 24
136
C17 se reemplaza por un condensador variable de 3 a 40 pF.
R10, GIS
V.SK, luH
1 nF
QUTPUT 13
j INPUT 12 C14
2N318
R3
3.SK
Fig.No.4.2.18
Amplificador ciase A a 31.25 MHz
Fig.No.4.3.1
Tarjetas construidas para el modulador en frecuencia
utilizando el mtodo directo
Fig.No.4.3.2
Tarjetas construidas para el modulador en frecuencia
utilizando el mtodo indirecto
1
6. Un led y una seal audible (ALARMA): que indican cualqui
exceso a 1V para la seal externa modulante proveniente d
osciiador.
Fig.No.4.3.3
Vista total del modulador en frecuencia
utilizando ei mtodo directo
MTODO INDIRECTO:
PS1: GND
PS2: Seal modulante a 250Hz
PS3: Seal integral de la seal modulante
PS4: Seal modulada en amplitud con portadora suprimid
PS5: Seal modulada en frecuencia de banda estrecha q
ingresa como referencia al detector de fase.
1
PS6: Seal portadora a 62.5KHz.
PS7: Seal portadora a 62.5KHz defasada 90.
PS8: Seal FM proveniente del lazo de realimentaci
debe ser enganchada para realizar la multiplica
PS9: Seal modulada en frecuencia a 31.25MHz.
PS10:Seal modulada en frecuencia a 93.75MHz sob
carga interna de 50Q.
Fg.No.4.3.4
Vista total del modulador en frecuencia
utilizando el mtodo indirecto
f.
Los moduladores didcticos estn montados en un gabinete met
y poseen un control de encendido del equipo, cable de alimentac
a AC (110V) y un fusible de proteccin de 1.5 A en el caso
modulador con mtodo directo y de 1 A en el caso del modulador c
mtodo indirecto.
Un diagrama esquemtico colocado sobre la tapa de cada uno de l
moduladores permite al usuario visualizar los bloques que form
parte de cada modulador, los puntos por donde se muestrea la se
monitoreada y los puntos por donde se puede ingresar la seal c
el mtodo que lo permite. Adjunto al diagrama esquemtico apare
una lista de pasos que se deben seguir para utilizar el equipo y l
precauciones en su manejo.
1
MANUAL DE OPERACIONES Y MANTENIMIENT
DEL EQUIPO, PRACTICAS SUGERIDAS PARA E
LABORATORIO, CONCLUSIONES Y
RECOMENDACIONES
5.3 Conclusiones
5.4 Recomendaciones
CAPITULO V
SEGUIMIENTO DE LA SEAL:
14
(e! NE564) que realicen la multiplicacin hasta los SOMHz sin ning
resultado positivo. El circuito que se implemento permite v
nicamente tres pasos de la modulacin y an as fueron necesario
muchos cambios y varias pruebas.
1
La respuesta de cualquier circuito en alta frecuencia depende e
gran parte de la tierra que posee y de la seal DC con que s
alimente, una buena tierra, es decir sin la presencia de seales
garantiza una salida con poco ruido y sin distorsiones, esto s
consigue colocando en cada etapa filtros de desacoplamiento en
fuente Vcc. A pesar de estas precauciones no es posible elimina
totalmente el ruido sino minimizarlo.
15
5.4.- RECOMENDACIONES
1
BIBLIOGRAFA
PHASE-FREQUENCY DETECTOR
PHASE-FREQUENCY
The MC4344/4044 consists of two digital phase detectors, a
charge pump, and an amplfier. In combinaton with a voltage DETECTOR
controlled multivibrator (such as the MC4324/4024 or MC1648),
it s useful in a broad range of phase-locked loop applications.
The circut accepts TTL waveforms at the R and V inputs and
generates an error voltage that s proportional to the frequency LSUFFIX
and/or phase difference of the nput signis. Phase detector #1 CERAMIC P A C K A G E
CASg 632
s ntended for use n systems requirng zero frequency and phase
(TO-116)
difference at lele. Phase detector #2 is used if quadrature lock s F SUFFIX
desred. Phase detector #2 can also be used to indcate that the CERAMIC PACKAGE
man loop, utzng phase detector #1, is out of lock. CASE 607
LOGIC D1AGRAM
PIN ASSIGNMENT
PU UF
Ul
Phase
Frequency 14
Detector
DI 13
,
v C 12
pu 11
U2 UF 10 DF
Phase
Frequency 02 C 9 Amp (n
Detector DZ
.2
Gnd 8 Ul Output
7-24
MC4344 MC4044
.i I -
i I I!!*
si <.,_. ie-,.i
i 11 !
7-25
MC4344 MC4044
APPLICATION
Operation of the MC4344/4044 is best explained by in- FIGURE i PHASE DETECTOR #1 FLOW TABLE
itially considering each section sepsrately. [f phase de-
tector #1 is used, loop lockup occurs when both outputs R o o ui
U1 and DI remain high. This occurs only when all the pt.a!e.
negative transitions on R, the reference input, and V, the _OeiBCtor
rraq
variable or feedback input, coincide. The circuit responds /i
only to transitions, henee phase error s independent of | \t waveform duty cycle or a
detector #1 consists of sequental logic crcuitry, there- R.V R.V fl-V R.V
fore operation prior to lockup is determinad by initial 0-Q 0-1 1-1 1-0
conditions. 11) 2 3 14) 0
When operation is nitiated, by either applying power 5 12) |3) 8 0
(5) 6 7 8 1
to the circuit or active input signis to R and V, the cir- 9 16) 7 12 1
cuitry can be in oneof several states. Gven a ny particular 5 2 17) 12. 1
starting conditions, the flow table of Figure 1 can be used 1 2 7 181 1
19) 110) 11 12 1 0
to determine subsequent operation. The flow table in- 5 6 (11) (12) 1 0
dicates the status of U1 and DI as the R and V inputs are
vared.The numbers in the able which are in parentheses
are arbitrarily assigned labels that correspond to stable Use of the table in determining circuit operaton is I-
states that can result for each inpu combination. The lustrated in Figure 2. In the timing diagram, ihe nput to
numbers wthout parentheses refer to unstable condi- R is the reference frequency; the input lo V s ihe same
tions. Input changes are trced by horizontal movement frequency but lags in phase. Stable state (4) s arbitrarily
n the table; after each input change, circuit operation assumed as the initial condition. From the timing diagram
will settle n the numbered state indicated by moving and flow table, when the circuit is n stable state (4),
horizontally to the appropriate R-V column. If the number outputs Ul and 01 are "0" an "1" respectively. The next
at that locaiion is not in parentheses, move vertically to input state is R-V = 1-1; moving horizontally from siable
the number of the same valu that is n parentheses, For state (4) under R-V = 1-0 to the R-V - 1-1 column, state
a given inputpar, any one of three stable states can exis. 3 is indicated. However, this is an unstable condition and
As an example, if R = 1 and V = 0, the circuit will be n the circuit will assume the state indicated by moving ver-
one of the stable states (4), (8), or (12). tically n the R-V = 1-1 column to stabie state (3). In this
(a) fl J 1 f | ! 1 1 1 1 I L_
fui v | j j ;j j
1) 13) 21 15) 18) [7] 12l| (5) (8) (7) |l2J S) J 1 8 1 (7) |l2l( 15} |(B)| 17) |2)| 15} 18][ 17) ,12))
ti M Ul ( 1 i LJ LJ n_r
'U- Id) 01 _
(el fl ( 1 j j j
1 1 i 1 1 I L
. 10 V J j j [ j _J 1 1 1 1 1 .
16) 17) (12) 15) (6) (7) 112) 15) (6) 171 [(12) (51 |[6) (71 (12JJ (51 I6)| 171 |(12J 15) 16] (7) (12)|
(a) ui
(hj Dr | 1 | 1 LJ LJ
<n R 1 1 1 [ 1 1 L_rn_r~i_rn_j~n_r-L_T~^L
ni v 1 [ ] '. 1 L i ii ii rL_
(7) (2) (5) (8) 12) (3) 13) (1) ( 3 ) 1 2 1 1 5 ) . . .
_T~
(1) 01 _
7-26
MC4344 MC4044
instance, outputs Ul and DI remain unchanged. The in- to the fixed phase difference case, bul now the duty cycle
put states nexl become R-V = 0-1; moving horizontally of he U1 waveform vares at a rate proportional to the
to the R-V = 0-1 column, stable state [2} s ndicated. At difference frequency of the two inputs, R and V. It is this
this point there is still no change in Ul or D1. The next characteristic that permits the MC4344/4044 to be used
Input change shfts operation to the R-V = 0-0 column as a frequency discriminator; if the sgnal on R has been
where unstable state 5 s ndicated. Moving venically to frequency modulated and f the loop bandv/jdth s se-
stable state (5), the outputs now change state lo Ul-Dl leced to pass the deviation frequency bui rject R and
= 1-1. The next input change, R-V = 1-0, drives the cr- V, the resulting error voltage applied to the VCO wll pe
cutry to stable state (8), with no change in Ul or DI. The the recovered modulation signa!.
next input, R-V = 1-1, leads to stable state (?) with no Phase detector #2 consists only of combinatoria! logic,
change in the outputs. The next two input state changes therefore ts characteristics can be determined from the
cause U1 o go low between the negative transitions of simple truth table of Figure 3. Since crcuit operation re-
R and V. As the inputs continu to change, the circuitry qures that both inputs to the charge pump either be high
moves repeatedly through stable states (2), (5), (8), (7}, or have the same duty cycle when lele occurs, using this.
(2), etc., as shown, and a periodic waveform is obtained phase detector leads to a quadrature relaionship be-
on the Ul terminal while DI remains hgh. tween R and V. This is llustrated in rows a-d of ihe tming
A similar resul s obtained f V is leading wth respect diagram of Figure 3. Note that any deviation from a ffty
to R, except that the periodic waveform now appears on percent duty cycle on the inputs would appear as phase
D1 as shown n rows e-h of the tmng diagram of Figure error.
2. In each case, the average valu of the resulting Waveforms showing the operation of phase detector
waveform is proportionai to the phase dfference be- #2 when phase detector #1 is being used In a closed
tween the two inputs. In a closed loop application, the loop are ndicated n rows e-j. When the main loop Es
error sgnal for controlling the VCO is derivad by trans- locked, U2 remains hgh. If the loop drifts out of lock n
[ating and filterng these waveforms. either direction a negative pulse whose width s propor-
The results obtaned when R and V are separated by tional to the amount of drift appears on U2. This can be
a fixed frequency difference are ndicated in rows -I of used to genrate a simple loss-of-lock ndicator.
the tmng system. For this case, the Ul output goes [ow Operation of the charge pump is besrexplainad by
when R goes low and stays in that state until a negative considering it n conjuncin wth the Darlington ampl-
transiton on V occurs, The resulting waveform is similar fer included n the package (see Figure 4], There will ba
R V U2 02
0 0 1 1
0 1 1 1
1 0 0 1
1 1 1 0
7-27
MC4344 MC4044'
a pulsed waveform on either PD or PU, dependng on the and down voltages nave equal effects, The pump signis
phase-frequency relationshi'p of and V. The charge are established by Vggs of transstors with millamperes
pump serves to inven one of the nput waveforms (01} of current flowing. On the other hand, the transistors
and translates the voltage levis before they are applied included for use as a filter amplifer will have ver/ small
to the loop filter. When PD is low and PU s high, Ql will currents flowing and will have correspondingly lower
be conducting in the normal directon and Q2 will be off. VBES on the order of 0.6 volt each for a threshold of
Current will be flowng through Q3 and CR2; the base of 1.2 volts. Any displacement of the threshold from 1.5
Q3 will be two VBE drops above ground orapproximately volts causes an ncrease n gan n one direction and a
1.5 volts, Since both of the resistors connected to the reduction in the other. The transistor configuraron pro-
base of Q3 are equal, the emtter of 04 (base of Q5) will vided is henee not optimum but does allow for the use
be approximately 3,0 volts. Forthis condion, the emitter oan additional transistor to improve filter response. Ths
of Q5 {DF} will be on Vgg below ths voltage, or about addtion also results n a non-symmetrical response since
2.25 volts. The PU nput to "the charge pump s hgh the threshold is now approximately 1.8 volts. The effec-
(> 2.4 volts} and CR1 will be reverse biased. Therefore tive postive swing s limited to 0.45 volt while the neg-
Q5 will be supplying current to Q6. This will tend to lower ative swing below threshold can be greater than 1.0 volt.
the voltage at the collector of Q7( resulting in an error This means that the loop gan when changing from a
signal that lowers the VCO frequency as required by a hgh frequency to a lower frequency is less than when
"pump down" signal. changing in the opposite directon. For type two loops
this tends to increase overshoot when going from low
to high and increases dampng in the other drection.
FIGURE 4 CHARGE PUMP OPERAT1ON
These problems and the selection of external filter com-
ponents are iruimaiety related to system requirements
and are discussed n detail n the flter design section.
7"28
MC4344 MC4044
Voltaga-
-
Amplifier/
-
ControUd Both wn (loop bandwidth or natural frequency) and
otar Filiar Otclllator (damping factor) are particularly mportant n the tran-
.sient response to a step input of phase orfrequency (Fig-
ure 9), and are defined as:
7-29
MC4344 MC4044
FIGURE 9 TYPE 2 SECOND ORDER STEP HESPONSE problems En linear loops when the system is out of lo
if the amplifier output swing is not adequately restrict
since integrating operational amplifier circuits will lat
up n time and effectvely open the loop.
The internal amplifier included in the MC4344/40
may be used effectvely if ts limits are observed. T
circuit configuracin shown n Figure 10 Ilstrales t
placement of R-}, RI- c- ano< 'oac resistor RL (1 kOJ. Du
to the non-Enfinite gain of ths stage (Ay = 30) and oth
non-ideal characteristcs, some restraim must be plac
on passfve component seiection. Foremost is a low
limit on the valu of R 2 and an upper limit on R-. Plac
in order of prorty, the recommendations are as follow
[a) R2 > 50 O, (b)'R2/Rl < 10, (c) 1 kO < R1 < 5 kfl.
(to V C O )
7-30
MC4344 MC4044
as C may approach this valu by themselves at the fre- DESIGN PROBLEMS AND THEIR SOLUTIONS
quency of nterest {w n j.
Pyriamicjange
Larger vales o R-; may be accommodated by either
usng an operational amplifier with a low bas current A source of trouble for all phase-Iocked loops, as well
(Ib < 1.0 *A) as shown in Figure 12 or by buffering the as most electrnica s simply overload orlackofsufficiem
interna! Darngton palr with an FET (Figure 13). It Es vitally dynamc range. One limit is the amplifier output drive to
important, however, that the added device be operated the VCO. Not only must a desgner note the outside limts
at zero VQS- Source resistor R4 should be adjusted for of the de control voltage necessary to give the output
this condition (which amounts to \QSS current for the frequency range, he must also account for the worst case
FET). Ths nsures that the overali amplifer input thresh- of overshoot expected for the system. Relatively large
od remalns at the proper potentia! of approximately two damping factors (C = 0.5) can comrbute significant
base-emirterdrops. Use of an additional emitterfollower amounts of overshoot (30%).To be prepared forthe worst
instead of the FET and R 4 (Figure 14) gives a threshold case output swing the amplifier should nave as mucn
near the upper limit of the phase detector charge pump, margin to postive and negatve lmits as the expected
resulting n an extremely unsymmetncal phase detector swing irself. That is, if a two-volt swing s suffcient to
gain in the pump up versus pump down mode. [t s not gve the desired output frequency excursin, there should
unusual to note a 5:1 difference in K< forcircuits having be at least a two-volt cushion above and below mximum
the bipolar bufferstage. If theintial designcan withstand expected steady-state vales on the control line.
this variation n loop gain and remain stable, the ap- This increase in range, in order to be effective, must
proach should be consdered since there are no crtica! of course by followed by an equivalen! range n the VCO
adjustments as in the FETcircuit. or there is linle to be gained. Any loss in loop gain will
n general cause a decrease in and a consequent in-
crease in overshoot and ringing. If the loss in gain s
FIGURE 12 USfNG AN OPERAT1ONAL AMPUHER
TO EXTENO THE VALU OF R1
caused by saturation or near saturation conditions, the
problem tends to accelerate towards a situacin where
thesystem senles n notonly a slowbutoscllatormanner
as wel.
Loss of amplifier gan may not be due entirely to nor-
mal system damping considerations, In loops employing
digital phase detecors, an additional problem is likely to
appear. This is due to amplifier saturation durng a step
input when there is a mximum phase detector output
simultaneous with a large transient overshoot. The phase
FIGURE 13 FET BUFFERING TO RAIS AMPUF1ER detector square wave rideson top of the normal transient
1NPUT1MPEDANCE and may even exceedthe amplifier output lmits imposed
above. Since the input frequency will exceed the R2C
time constant, gain Kp for these annoying pulses will be
RJ/RV Ordinarily this ratio will be less than 1, but soma
circumstances dctate a low loop gain commensurate
with a farly high tun. For these cases, Rj/Ri may be
higher than 10 and cause pulse-wise-saturation of the
amplifier.-Snce the de control voltage is an average of
phase detector pulses, clipping can be translated nto a
reduction in gain with all the "benefits" already outlined,
i.e,, poor settling time. An easy remedy to apply in many
cases s a simple RC low pass section preceding or to-
gether with the ntegrator-lag section. To make transient
FIGURE 14 EMITTEH FOU.OWEH BUFFERING OF suppression independen! of amplifier responso, the net-
AMPURER INPUT work may be mbedded within the Enput resistor R-j (Fig-
ure 15) or be mplemented by placing a feedback capac-
itor across R2 (Figure 16). Besides rounding off and
inhbiting pulses, these nerworks add an additional pole
to the loop and may cause further overshoot f the cutoff
frequency (ucj Is too cise to wn. If at all possible the
cutorf point should be fve to ten limes tun. How far UJG
can be placed from cun depends on the input frequency
MPS6S71 relationship to tun since fn s, after all, what is beng
Of Equiv. filtered. A side beneft of this simple RC pulsa "flartener"
s a reduction n fn sidebands around f out for synthe-
7-31
MC4344 MC4044
sizers wth N > 1, However, a series o RC lters is not ter. Although the filter does establish loop dynamic con
recommended for ether extended pulse suppression or ditions, it leaves somethng to be desred as a low pas
sideband mprovement as excess phase will begin to section for reference frequency components.
build up at the loop crossover (= ion} and tend to cause For the usual case where curef is higher than M^-> th
instabilty. Ths will be discussed in more detall later. Kp functon amounts to a simple resistor ratio:
V ref
(1
Vef
FIGURE 16 IMPROVED TRANSIENT SUPPRESSION
WITH R2 C c
where Vref = peak valu of reference voltage
the VCO input, and
V = peak valu of reference frequenc
voltage at the phase detector outpu
sdeband level _
~ < (16
fnnt evel JrefK</
Spurious Outputs
Although the mafor problem n phase-locked loop de- From Equation 16 we find that for a given phase de
sign is deining loop gain and phase margin under dy- tector, a given_vaue of R-| {which determines V<), an
namic operating condtions, high-qualty synthesizer de- gven basic system constraints' (N, f re f), only C and o)
signs aiso requre special consideraton to minimlze remain as variables to diminish the sidebands. If ther
spurious spectral components the worst of which is are few limits on Jn, t may be lowered indefinitely unt
reference-frequency sdebands. Requirements for good the desred degree of suppression is obtained. If w n i
sideband suppression often conflict wth other perfor- not arbitrary and the sidebands are stll objectionable
mance goals loop dynamic behavior, suppression of additonal filtering is indcated.
VCO nose, or suppression of other in-ioop noise. As a One tem worthy of note is the absence of Ky in Equa
result, most synthesizer designa requre compromised tion 16. From Equation 15 it might be concluded tha
specfications. For a given set of components and loop decreasing Kywould be anothermeans forreducing spu
dynamic condtions, reference sdebands should be pre- rious sidebands, but for constant vales of and iun this
diaed and checked against design specifications before is not a free variable. In a given loop, varying Ky wi
any hardware s built. ' certainly affect sideband voltage, but will also vary an
Any steady-state sgnal on the VCO control will produce jn.
sdebands n accordance with normal FM theory. For On the other hand, the cholee of tun may well affec
small spurious devaiions on the VCO, relative sideband- spectral purity near the carrier, ahhough referenc
to-carrier levis can be predicted by: sdeband levis may be quite acceptable.
In computing sideband levis, the valu of V,, must b
sidebands ___ V re fK\
(13) determined in relation to other loop components. Resid
carrier 2uref ual reference frequency components at the phase detec
tor output are related to the de error voltage necessar
where V re f = peak voltage valu of spurious frequency to supply charge purnp leakage current and amplifier bia
at the VCO input. current. From these average voltage figures, spectra
Unwanted control line modulation can come from a components of the reference frequency and its harmon
variety of sources, but the most likely cause s phase Ics can be computed using an approxmation that th
detector pulse components feedng through the loop fil- phase detectar output consists of square waves T second
7-32
MC4344 MC4044
wide repeated at t second intervals (Figure 17). A Fourier in a direction to deplensh the charge on filter capacitor
analysis can be summarized for smail ratios of 7/t by: C. A second charge pump leakage, IL', attributed by dode
CR1 flows out of pin 5. This current, however, s in a
(1)' the average voltage (Vavg) is A(T/I) direction to help supply IB and IL and thus tends to min-
(2) the peak reference voltage valu (V<) s twice V avg , mze the discharge of C. Typically IL' is much less than
and IL and, since t is also in a direction to minimize discharge
(3) the second harmona (2f re f) s raughly equal in am- of the flter capacitor, it will be gnored in the followng
plitude to the fundamental. discussion. The total charge removed from C must be
replaced by current supplied by the charge pump during
By knowing the requirements for (1) due to amplifer he next up-date opportunty. This current flows through
bias and leakage currents, vales for [2] and (3) are R1. To minimize the effects of IB and IL a relatve small
unquely determlned. valu of Rl should be chosen. A mnimum valu of 1 k!l
s a good choice.
FIGURE 17 PHASE DETECTOR OUTPUT
FIGURE 18 OUTPUT ERROR
CHARACTERISTICS
OUTY PHASE
CYCLE ERROR
IDegl ImV) tmV]
0.1 0.36 0S 12
0.2 0.72 12 2 4
0.3 i.as 1S 36
0.4 1.44 2 4 4 8
An example of this sdeband approxmaton technque
0.5 1.80 3 0 6 0
can be llustrated using the parametsrs specified for the 0.6 2.16 3 6 7 2
synthesizer design ncluded in the applications Infor- 0.7 2.52 42 S 4
0.8 2.88 48 9 6
mation secton. 0.9 3.24 5 4 10.9
1.0 3.60 6.0 12.0
Nmax = 30 Wn = 4500 rad/s 2.0 7.2 12.0 24.0
KV = 11.2 x lQ 6 rad/s/V R-, = 2 kl 3.0 10.8 18.0 35.9
4.0 14. d 24.0 47.9
K0 = 0.12 V/rad f re f = 100 kHz 5.0 18.0 30.0 59.8
= 0.8 6.0 21.6 36.0 71.6
7.0 25.2 .12.0 83.3
8.0 28.8 48.0 95.0
Substituting these numbers into Equation 16: 9.0 32.4 54.0 106.6
10.0 36.0 60.0 11S.O
sideband = (0.8K30}(4500)
(17)
~ *
(18)
After vales for C and 82 have been computed on the
basis of loop dynamic propenies, the overall sideband
to f0ut rat' computation can be simplified.
The result illustrates how much reference feedihrough
will affect sideband levis. If 1.0 mV peak of reference Snce
appears at the output of the phase detector, the nearest
= 2V
sideband will be down 56.2 dB.
V avg = Ub + 1
If the amplifier seciion included n the MC4344/4044 s
V = 2 (Ib -i-
used, with RL = 1 Jcfl, some approximations of the valu
of V0 can be made based on the input bias current and
the valu of R-j. The phase detector must provide suff-
cient average voltage to supply the amplifier bias curreni,
1^, through H-j," when the bias current is about 5.0 \iA and
RI is 2 kfl, V av g must be 10 mV. From the assumptions
earlier concerning the Fourer transform, and wth the
help of Figure 18, we can see that the phase detector duty
cycle will be about 1.7% (A = 0.6 V), givng a fundamental we fnd that
(reference) of 20 mV peak. If this valu for V< is substi-
sdejand _ V re fKy
tuted into Equation 18, the resulting sideband ratio rep- (19)
resants 30 dB suppression due to this componen! alone. . foout
7-33
MC4344 MC4044
current summing at the amplifier input (Figure 19). Ths more gradual phase shift at frequencies less than the
has ndeed proved to be the casa. Experimental results cutoff pont and still get nearly equal suppression at fre
indcate that greater than 60 dS rejection can routnely quencies above the cutoff poin. Sections designed with
be acheved at a constan! temperature. However when a sllght amoum of peaking ( = 0.5) show a good com
nullng farly large vales (> 100 nA}, the rejection be- promise between excess phsse below cutoff (ujc), without
comes quite sensitve since leakages are nherently a peaking enough to cause any danger of raising the loop
function of temperature. This technique has proved use- gan for frequencies above )n. A fairly non-critical section
ful n achieving improved system performance when may simply use an emitter follower as the active device
used n conjunction with goad crcut practice and ref- with two resistors and capacitors completing the circuit
erence flering. (Figure 21).Ths provides a -12 dB/octave (-40 dB/dec-
ade) rolloff characteristic above )n, though the atten-
FIGURE 19 CQMPENSATING FOR BIAS AND uation may be more accurately determned by Equation
LEAKAGE CURRENT 22. If the sideband probiem persists, an additional section
may be added in series with the first. No more than two
sections are recommended .since at that time either (1)
the constraint between cun and curef is too cise, or (2)
reference voltage s modulating the VCO from a source
other than the phase detector through the loop amplifier
rS.O to t-15 V
SB dB = n 20 (22}
ref-
7-34
MC4344 # MC4044
4044's transfer functon lnearity in the vcinity of FIGURE 23 LOOP RESPONSE TO VCO NOISE
zero phase error between he R and V inputs.
c. The filter ampJifer ground locationcan beseparated
from the phase detector ground.
d, An "optimum" filter amplifier nput threshold of
approxmately two diode drops need not be yl
established. TTF/T
The filter dlscussons and relationships developed for
integrator-log filter sectons can be appled to the system
of Figure 21 and the prevously derivad equations can be
used to determine vales for R1, R2 and C.
It may be desrable to split each of he R1 resstors and
incorprate a capacitor to ground in a manner similar to LOG FEQUENCY
thar shown in Figure 15. This should improve transient
suppression and provide integration of the Ul and DI
signis to better enable the operational amplifier to de- Other Spurious Responses
veiop corredive error information from very narrow Ul
and DI pulse widths. Spurious components appearing n the output spec-
Phase error for the circut n Figure 21 wll result from trum are seldom due to reference frequency feedthrough
nput offset voltage in the operational amplifier, resistor alone. Modulation of any kind appearing on the VCO con-
mismatch and mismatch between the phase detector trol une will cause Spurious side.bands and can come in
output sates appearng at U1 and D1. Phase error can through the loop amplifier supply, bias circuitry in the
be trimmed 10 zero initally by adjustng either the am- control path, a translator, or even the VCO supply tself.
plifier input offset or one of the Rl resstors, Some VCOs have a relatively hgh sensitivity to power
supply variaton. This should be investigated and its ef-
fects .considered. Problems of ths nature can be mn-
VCO Noise mized by operatng all devices except the phase detector,
charge pump, and VCO from a seprate and well isolated
Effecls of noise within the VCO itself can be evaluated supply. A common meihod uses a master supply of about
by consdering a closed loop situation with an external 10 or 12 volts and two regulators to produce voltages for
noise source, en, introduced at the VCO [Figure 22). Re- the PLL one for sil the logic (ncluding the phase de-
suitant modulation of he VCO by error voltage, E, s a tector) and the other for all circuitry associated with he
second order hgh pass function: VCO control Une.
Sideband and noise performance s also a function of
good power supply and regulator layout. As mentoned
earler, extreme care should be exercised in isolating the
T2N ' T2N 23) control lne voltageto the VCO from influences other than
the phase detector. This not only means good voltage
S2 regulation but ac bypassing and adherence to good
grounding techniques as well. Figure 24 shows two sep-
rate regulators and their respective loads. Resistor RS
FIGURE 22EFFECTS OF VCO NOISE s a small stray resstance due to a common thn ground.
return for both R[_i and RQ, Any noise in R[_2 is now
reproduced (n a suppressed form} across R^ . Load cur-
rent from RJJ does not affect the voltage across R^.
Even though the regulators may be quite good, they can
hold VQ constant only across their outputs, not neces-
sarly across the load (unless remote sensing is used).
FIGURE 24 LOOP VOLTAGE REGULATION
1
Ragulator
/fl Regul
Nat
7-35
MC4344 MC4044
One solutan to the ground-coupled noise problem is to Bypassing in a phase-locked loop must be effectve
lay out the return path with the most sensitive regulated both highfrequencesand lowfrequencies. One capaci
circut at the-farthest point-from power supply entry as n the l.O-to-10 p.F range and another between 0.01 a
shown in Figure 25. 0.001 p,F are usually adequate. These can be effective
Even for regulated subcircuits, accumulated noise on utilized boih at the immediaie crcuitry (between sup
the ground bus can pose major problems snce although and common ground) and the regulator if t is some d
the cross currents do not produce a differential load volt- tance away. When used at the regulator, a single el
age drectly, they do produce essentially common mode trolytic capacitor on the output and a capacitor par
noise on the regulators. Output differential load noise the input is most effective (Figure 28). It is importa
then is a function o the nput regulaton specfication. By again, to note that these bypasses go from he inp
far the best way to sdestep the problem s to connec: output pins to as near the regulator ground pin
each subcircut ground to the power supply entry return possble.
line as shown n Figure 26.
FIGURE 28 SUGGESTED BYPASSING PROCEDURE
FIGURE 25 REGULATOR LAYOUT
-,-.
APPUCAT10NS INFORMATION
JT&quency Syntheslzers
7-36
MC4344 MC4044
muncation use, this input frequency is called ihe "chan- Added sideband suppresson (dB) s:
nel spacng" or, n general, t is the reference frequency.
There is essentially no dfference in loop dynamc prob- 1
dS = 20 (B)
lems between the basfc PLL and synthesizers except that
synthesizer designers musfcontend wth" problems pe- 25(oJn)2
culiar to loops where N is variable and greater than 1.
Also, sidebands or speclral purity usually requre special 12. If step 11 still does not give the desired results, add
anention. These and other aspects are discussed n a second arder secton at a)c = 5 Ln using either
greater detail n AN-535. The steps fora sutable synthess the configuration o Figure 20 or 21. The expected
procedure may be summarized as follows: improvement stwicethat of the single pole in step
11.
Synthesis Procedure
1
dB = 40 log;0 (C)
1. Choose input frequency. {fref = channel spacing)
2. Compute the range o digital divisin:
I1I0A t
>ref Total sideband rejection is then the total of 20 log-jrj(A)
M - - frnin (B) -i- (C).
^min - f ,
T ref
2n 3. VCO range:
R2 = The VCO output frequency range should extend
WnC
beyond the specified mnimum-maximum limits to
accommodate the overshoot specificaton. In this
8. Compute C max :
nstance f ou t should be able to cover an additional
20% on either end. End limits on the VCO are:
4.5 4.5
= -T = ^r= (4.5)(1o3)rad/s
t 0.001
7-37
MC4344 MC4044
6. In order to compute C, phase detector gain and Rl If desired additional sideband filterng can be ob-
must be selected. Phase detector gain, K>, for the tained as noted n steps 11 and 12.
MC4344/4044 is approximately 0.1 volt/radian with
RI = 1 kfi. Therefore, ^- ^y splitting R- and Cc, further anenuaton can be
gained. The magntude of Cc s approximately:
u-
,
^max
. /Nmax
^mm ,/ w .
Y V mm
nqfl
u-Ja y- (2-T x 105)2
25(4.5 x 103)2
9. Figure 9 shows that C = 0.98 will meet the s ettling Nominal suppr assion is now - 63 dB. Worst-case is
time requirement. 6 d8 higher th 5n nominal suppression of - 57 dB
10. Sidebands may be computed fortwo cases: ( 1) with Ths s well witlin the -30 dB design requirement,
l(_ {charge pump leakage current) nominal (1 30 nA), step 12 s included for completeness only.
and (2) with l(_ mximum (5.0 iA). A valu c f 5 nA
will also be assumed for the amplifier bias c urrent, " 12. Anenuation of a second order filter s double that
ib- of thesingle ore er filter section described in stepll.
The calculation > for a second order filter indcate an
sideband (10 * 10"6J(200Hn x lO^) _ -iQ-3 additional-56cJB of sideband rejecton. Figures 20
f out max 6 -2S * 3 and 21 show tw o second order filier configura tions.
If R is assigneci a valu of 10 kl then C may be
The sideband-to-center frequency ratio ornnallV calculated.
wll be:
- c o.i
sideband 5.1 _ ^
mnR {4.5 x 103J{104) """"" >"'
'out^ nom 10
O 0
f <i k
C R2 f
" , I
!(
1.8| 12001 C = 120 PF
\f\\ d
,,-. MPS6571
1' | 1
13 10 3 _ 3 1 0 - 1
MC54J16
[MC4316) 1MC4316)
5 11 14 2 5 11 la 2
-n 1 1
DO DI D2 D3
un
DO O D2 O3
7-38
MC4344 MC4044
dock Recovery from Phase-Encoded Data consisted only of alternatmg "T's and "0"s, ihe phase-
encoded formal would resultin a waveform equal to one-
The electro-mechanical system used for recording dig- half the original clock frequency. If ths were applied d-
ital data on magnetic tape often introduces random var- recly to the loop, the VCM would of course move down
iations n tape speed and data spacing, Because of ths to that frequency. The encoding format nsures that there
and the encoding technque used, it is usually necessary wll be a transition n the middle of each data time. If only
to regenrate a synchronized clock from the data during trese transitions are sensed they can be used to regen-
this read cycle. One method for dojng ths is to phase- rate the clock. The schematic dagram of Figure 31 in-
lock a voltage controlled multivibrator to the data as it dcates one method of accomplishing this.
is read (Figure 31). The logic clrcutry generales a pulse at the midpoint
A typcal data block using the phase encoded format of each data cell which is then applied to the reference
is shown n row 1 of Figure 32. The standard format calis input of the phase detector. The loop VCM is deslgned
for recording a preamble of forty "0"s followed by a sin- to oprate at some mltiple of the basic clock rale. The
gle "1"; this is followed by from 19 to 2048 characters VCM frequency selected depends on the decoding res-
of data and a postamble consisting of a "1" followed by olution desired and other system timing requirements.
forty "0"s. The encoding format records a "O" as a tran- In this example, the VCM oprales at twenty-four times
sition from low to high n the middle of a data cell. A the clock rate (Figure 32, Row 12).
"1" s indicated by a transiran from hgh to low at the Referring to Figure 31 and the liming dagram of Figure
data cell mdpont. When required, phase transitions oc- 32, the phase-encoded data Figure 32, Row 1) is com-
curatthe end of data cells. If a string of eitherconsecutive bined with a delayed versin of itself (output of flp-flop
"0"s or consecutive "1"s s recorded, the format dupl- A row 3) to provide a poshve pulse out of G3 for every
cales the original clock; the clock s easily recovered by transltion of the input signa!. Portions of the data block
straght forward synchrontzation whh a phase-locked are shown expanded n row 2 of Figure 32. Flip-flop A
loop. In the general case, where the data may appear n delays the ncoming data of one-half of a VCM clock pe-
any order, the phase-encoded data must be processed riod. Gates Gl, G2, and G3 rnplement the logic Exclusive
to obtain a single pulse during each data cell before it s OR of waveforms 1 and 3 excepi when inhibited by
appled to the phase detector. For example, f the data DGATE [row4| or the output of G12 (row 7). DGATE and
7-39
MC4344 MC4044
its complement, DGATE, serve to initialize the circutry As a rougn check on acqustion time, assume that
and insure that the frst ransition of the data block [a lockup should occur not later than half-way through a 40-
phase transtion) s gnored. The MC7493 bnary counter bt preample, or for twenty 8,34 p.s data periods.
and the G5-G12 latch genrate a suitable sgnal for gating
out G3 pulses caused by phase transtions at the end of uint = {3.05)104(20)(8.34)10-6 = 5.1 (26)
a data cell, such as the one shown dashed in row 6.
The nitial data pulse from G3 sets GT2 low and is From Figure 3, the output wll be wthin 2 to 3% of its
combned with DGATE n G7 to reset the counter to ts final valu for w n t = 5 and = 0.707. The filter compo-
zero state. Subsequent VCM clock pulses now cycle the nents are calculated by:
counter and approximately one-third of the way through
the next data cell the counter's full state is decoded by K,KV (27)
Gil, generatng a negative transMon. This causes G12
to go high, removing the nhibit signal until it s again
and
reset by the next data ransition. Ths pulse a]so resets
the counter, continuing the cycle and generating a pos- (28)
tive pulse at the midpoint of each data cell as required.
Acquisiton time is reduced if the loop is locked to a where = 0.115 v/rad
frequency approximately the same as the expected data V= (18.2) 106rad/s/volt
rate durng inter-block gaps. In Figure 31, ths is achieved N = 24 = Feedback divider ratio
by operating the remaining half of the dual VCM at n = (3.05) 104 rad/s
sghtly less than the data rate and applying it to the S = 0.707
reference input of the phase detector va the G8-G9-G10 (0.1151(18.21106 _ 4
data selector. When data appears, DGATE and DGATE - 8.72)10
cause the output of G3 to be selected as the reference
nput to the loop. From Equation 27:
The loop parameters are selected as a compromise
between fast acquisiton and jitter-free racking once syn- (8.72)104
chronization s achieved. The resulting filter componen! -5
vales indicated in Figure 31 are suitable for recoverng
the clock from data recorded at a 120 kHz rate, such as
would result n a tape system operating at 75 .p.s. with From Equation 28:
a recording density of 1600 b.p.i. Synchronzation is
achieved by approximately the twenty-fourth bit time of R2 _ 2r.tunN _ 2[0.707)(3.05H04 _
the preamble. The relationship between system requre- [8.72J104
ments and the design procedure is illustrated by the fol-
lowng sample calcularon: Let R-, = 3.0 kTl; then R2 = 1.5 Wl and
Assume a 3.0 dB loop bandwdth much less than the
input data rate (= 120 kHz), say 10 kHz. Further, assume
a damping factor of - 0.707. From the expression for
loop bandwidth as a functon of damping factor and un-
damped natural frequency, ton, calclate Dn as: or using a cise standard valu, use C = 0.033 y.F. Now
add the additional prefiltering by splining R-j and select-
ing a time constant for the additonal secton so that t
+ 42 - 4{4j (24)
is large with respect to
wn = = (3.05)104 rad/s
n 2.06 10R-1 10(3.0)103
7-40
MC4344 MC4044
(1) "
(2) Data
(3) QA
(i)
15)
DGATE
DGATE
e 1
r t
L
i
(6) G3 (1 fl
i
17) G12
(8) G11
(9) G7
(10) G10
(lll 0B [VCM-7-24]
[121 VCM
7-41
MC1648/MC1648M
VOLTAGE-CONTROLLED
OSCILLATOR
-5.2 Vdc 1, 14 7, a
F I G U R E 1 - CIRCUITSCHEMATIC
4-3
O
I
CO
FIGURE 2 - SPECTRAL PURITY OF SIGfJAL AT OUTPLIT
ELECTRICAL CHARACTERISTICS
Supply Voltage = - 5.0 Volls
-55C ~30C -!2S0C -t-85C -M25C
Characterisiic Symbol Min Max Min Max Min Max Min Max Min Max Unil Conttions
_ _
Power Supply Diain Cuirun ~ - - - 41 - - - mAdc Inpuls and ouipuis opcn.
"E
Logic "1" Ouipui Voltnijc VOH 3.92 4.13 3.355 4.1B5 4.04 4.25 4.1 4.36 4. IR 4.40 Vdc vlLmin >opin 12,iL@Pin3.
Logic "0" Oulpul Voliagt VOL 3.13 3.38 3.16 3.40 3.20 3.43 3.22 3.475 3.23 3.51 Vdc vIHmax ' Pin 12, IL @ Pin 3.
Biis VoltnQc; v Bins' 1.6? 1.97 1.60 1.90 1.45 1.75 1.30 1.60 1.20 1.50 Vdc vlLminP'n12.
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Pcnk.o-Penk Tank Voliatjn VP.P - - - - - - - 400 - - - - - - - mV
_ _
Oulpul Duly Cycle - - - - - - 50 - - - - L. - % Scu Pigurii 3.
VDC
Oscillotion Frecjucncy 'mnx ' " - 225 - - 225 ~ 200 225 - - 225 - - 225 - MHz
'This rncnsurcmotil rjuoraniiJL's thtf de poicniin! o ihc hias poinl for puiposiis o ncotporaiintj a varnciat [urniny riiotlu ni ihis poini.
' 'Frcqucncy varisiion ovci lenipctlurc is a tirocl (uncion o he C/A Tmpuraiurc and A L / A Tcmpcraiuie.
o
i
CO
O
TEST V O L T A G E / C U R R E N T VALES
ELECTRICALCHARACTER1STICS
Supply Voltage = -5.2 Volts
Logic "0" Ompui Vohagc VOL -1.920 -1.670 -1.890 -1.650 -1.850 -1.620 -1.830 -1.575 -1.820 -1.540 Vdc ViHmaxtoPinlS.lL^Pina.
Bias Voliage v Bias- -3.53 -3.23 -3.60 -3.30 -3.75 -3.45 -3.90 -3.60 -4.00 -3.70 Vdc VlLmintopin 12 >
Mn Typ Max Mn Typ Max Min Typ Max Min Typ Max Min Typ Max
Pcak-to-Peak Tank Voliagc Vp.p - - - - - - - 400 - - - - - - - mV
_
Outpui Duty yele VDC - - - _ - - 50 - - - - - - - % Sei: Figure 3.
Oscllaiion Ficquency 'max" ' - 225 - - 225 - 200 225 " - 225 - - 225 - MHz
"This measufemenl guaranlees ihe de polenlial ai ihe bias point lor purposes o incorporang a varaclof turning diode ai ihis poini.
' 'Frequency vnation over lemperalure is a diit-ci lunclion o !he A C / A Tempera tute and L/A Tempera tur e.
MC1648/MC1648M FIGUR E 3 - TEST CIRCUIT AND WAVEFORMS
I r
OPERATING CHARACTERISTICS
Figure 1 Ilstralas trie circuit schernatic f o r the FIGURE 4 -THE MCI6Jfl OPERATING |N THE VOLTAGE
MC1648. The oscillator ncorporatas positiva feed- CONTROLLED MODE
taack by coupltng the base of transistor Q7 to the
collector of Q8. An autamatic gain control (AGC)
s Incorporated TO limit the current through the
emtter-coupled par of transistors (Q7 ana QS) and
allow optimurn frequancy response of the oscillator.
1
f, OPEHATING FEQUeNCY. (MHJ
MC1648
Fregusncy () 11
4-6
MC1648/MC1648M
z_
FIGURE?
9O
^SE 1 " V EE2 ' GnU
8 O
l.O 2.0 3.0 4.0 5.0 60 70 3 O 9.0 'The 1200 onn esistoi and me SCODB l
coniuiuie 3 25 t m
prob. Coa i l ae CT 070 5O or Hqu
Vin. INPUT V O L T A G E t V O L T S l
190
Miro MBUI Toroaial Core sT30-22,
iao 5 tutos f No 20 coppar wir.
170
160
150
14O
130
12O
1 10
1OO
z
90
ao
1.0 2.0 3.0 4.0 S.O 6.0 70 8.0 9 O 1O 1200 onrn itfs.iof jnd [he iCOe tBimn-
iiiipedance consiiiultt J 2S 1 Jllenuato
V,n. INPUT V O L T A G E IVOLTSl tf CoJ mu DP CT O70 50 or eyuwdleni
4-7
MC1648/MC1648M
Typlcal transfer characteristics for the Capacitor* |C1 and C2 of Figure 4) should
oscllator n the voltage contrallad mode are be used to bypass.the AGC point and the VCO
shown in Figures 6, 7\d 8. Figures 6 and 8 input [varactor diode), guaranteeng only
show transfer characteristics employing only de levis at trese points.
the capacitance of the varactor diode {plus the For output frequency operation between
input capacitance of the oscillator, 6 pF typi- 1 MHz and 50 MHz a 0.1 pF capacitor is s u f f i -
cal). Figure 7 illustrates the oscillator operating cent for C1 and C2. A t higher frequencies,
n a voltage controlled mode wjih the output smaller vales of capacitance should be used;
frequency range limited. This is acheved by at lower frequencies, larger vales of capaci-
addng a capacitor in parallel wth the tank tance. At high frequencies the valu of bypass
circuit as shown. The 1 kl resistor n Figures 6 capacitors depends directly upon the physical
and 7 s used to protect the varactor diode layout of ihe system. AII bypassing should be
during testing. It is not necessary as iong as cise to the package pins as possible to
as the de nput voltage does not cause the diode minimize unwanted lead nductance.
10 become forward based. The larger-valued The peak-to-peak swing of the tank circuit
resistor (51 kl~i) n Figure 8 is required to is set internally by the AGC circuitry. Since
provde sola t ion for the high-mpedance voltage swing of the tank circuit provides the
junctions of the two varactor diodes. drive for the output buffer, the AGC potential
The tunng range of the oscillator in the directly a f f e c t s the output waveform. !f t is
voltage controlled mode rnay be calculated as: desired to have a sine wave at the output of
the MCT648, a series resistor s tied from the
f
AGC point to he most negative power poten-
tial (ground if T-5.0 volt supply is used. 5.2
volts if a negative supply is used) as shown in
where f n
2JTs/L(C D (max) + C S J Figure 10.
At frequencies above 100 MHz typ, it may
Cg = shunt capacitance {input plus external be desirable to increase the tank circuit peak-
capacitance). to-peak voltage in order to shape the signal
CQ = varactor capacitance as a function at the output of the MC1648. This is accom-
of bas voltage. plished by tyng a series resistor (1 k! mni-
mum) from the AGC to the most positive
Good R F and low-frequency bypassng s power potential (-rS.O volts f a + 5.0 volt sup-
necessary on the power supply pins. (See ply is used, ground if a -5.2 volt suppiy is
Figure 2.) used). Figure 1 1 illustraces this principie.
APPLICATION INFORMATION
The phasa [ocked loop shown in Figure 9 (preferable over RF switching with a mltiple
illustrates the u s e ' o f the MC1648 as a voltage crystal system, and a broad range of tuning (up
controlled oscillator. The figure ilustra tes to 150 MHz, the range being set by the varactor
a frequency synthesizer useful n tuners for diode).
FM broadcast, general aviation, maritime and The output frequency of the synthesizer
[andmobile communicatons, amateur and loop is determined by the reference frequency
CS receivers. The system operates from a single and the number programmed ac the program-
t-5.0 Vdc supply, and requires no nternal trans- mable counter; f o u t = Nf r e f. The channei
lations, since all components are compatible. spacing is equal to frequency ( f r e f ) .
Frequency gen era ti on of this type offers For additional Information on applications
the advantages" of single crystal operation, and designs for phase locked-Ioops and digital
simple channei selection, and elimnaton of frequency synthesizers. see Moiorola Applica-
special circuitry to preven: harmonic lockup, tion Notes A N - 5 3 2 A , AN-535, AN-553, AN-
Addtonal features nclude de digital switching 564 or AN594.
4-8
MC1648/MC1648M
N No * P A
Figure 1 O shows tha MC1648 n the variable frequency Figure 12 shows he MC1648 operating from +5.0 Vdc
mode op^rating from a +5.0 Vdc supply. To obtain a sine and +9.0 Vdc pcuver supplies. This permhs a higher voltage
wave at the output, a resistor is added from the AGC swing and hightr output power than is possible from the
circuit [pin 5) to V. MECL outpm (pin 31. Plots o output power versus total
Figure 11 shows the MCI 648 n the variable frequency collector load resisiance at pin 1 are giv*;n m Figures 13
mode operating from a +5.0 Vdc supply. To extend the and 14 for 100 MHz and 10 MHz opdration. The total
usaful range of he devce (maintain a square wave output collector load includes R in parallel with Rp of Ll and
above 175 MHz), a resistor is added to the AGC circu: ai Cl at resonance. The optimum valu or R at 100 MHz is
pin 5 (1 k-ohm mnimum). approximately 850 ohms.
4-9
POWER OUTPUT (inW RMS)
-* M U t O 01 J n
o n o w
M O U *
T O T A L C OLLECTOR L O A Q { o n m i |
o r 3; 3 r r - en
U KJ -o 31 n u
10.0OO 1000 100 10
k < 5 o ' 3 b " co
6 - ~ tn o , G.
' 0 ? - < I 0
.ES " MM3 U
ui Sc
^ 3 5- a , * * Dr o
s\ X
Q
Q ^ -n _
TI
CT)
00
\
\
X
s
\
X 82
:>f=
Q AWG 3/16" ID
-J
r
1 " 11 klta l O O M H i ReQ nance
k
Cl 1.0 - 7.0 eF
> D
H TI
(*'
RF Transistor*
flFTrans/Vfors
2N3866 (continued)
2N3866 (SILICON)
t c = 0.4 A
V
C 3 g 11
5t -b..
1 _ b..
c w w
i,
CURRt
j i
-;
r-c=-.
-^ "
n . ._ -L, I-.
FIGURE 10-DC CURRENT GAIN (0 W 10
FIGURE 9 - iv Ce versus COLLECTOR CURRENT versus COLLECTOR CURRENT 1C.CCWC1M CUSRW! Miel
loCOHfClOflCUffiNIl^W]
DESIGN NOTE
Figures U Ihrough 18 show small-slgnal admittance-parameer data. This dala can be used f
Class A arnplifier deslgns.
B w For Class C power-ampl(er desiens, the small-signal parameters are not applicablu. Figures A a
5 EVC parallel output capacitance and the parallel nput resistance and capacitance for Class C pow
amplifier operation.
The parallel resistive portion o the collector load Impedance or a power amplifer, R t ', may b
10 C
computed by assuming a peak voltage swng equal to Vcc, and using Ihe expression
RF Transislors
RF Transsfors
2N3866(contnued)
2N3924thru2N3927 V CB = 36 V
l c = 0.5-3.0 A
P 0 = 7.0-23.2
y PARAMETER VARIATIONS -i
(VcE=15 Vdc, le =80 mAdc, TA = 25'C) NPN silcon annular RF power traiisistors, opti
mized for large-signi power-amplLfier aiid drive
FIGURE 15 - SMALL-SIGNAL INPUT ADMITTAHCE FIGURE 17 - SMALL-S1GNAL FORWARD TRANSFER applications, fealure a wide cholee of power levi
versus FREQ.UENCY ADMITTANCE versus FREQUENCY
'Colleclor connecled )o ca
ilud hoUled rom c*ie
\d 70 1M
"Emitter connoctod lo c i t e
ilud iiolitod from c i t e
'CASE 79 'CASE 24 * * C A S E 30
(TO-39) (TO-102) (TO-60)
2N3924 2N3925 2N392
2 N 39 27
C,
(.fRfOUtNCYWKi)
" +Vcc-
IJ.Vie
MV2115 (SILICON)
vvc-WI-
VOLTAGE-VARIABLE
CAPACITANCE DIODES
6.B-100pF
30 VOLTS
SILICON EPICAP DIODES
MXIMUM RATINGS
Raling Symbol ValuB Unil
/..J. ,.
3-991
MV2101 thru MV2115 (continuad)
PARAMETER TESTMSTHODS
'3-992
MV2101 thru MV2115 (continued)
1.0 *.Q
VR, REVERSE VOLTAGE IVOLTS]
w
. 5.0
2.0 TA ;sc -
1.0
D.50
: Q.20
D.10
0.05
0.02
0.01
-25 O 25 50 75 1QD 125
FIGURE 4 - FIGURE OF MERIT veraui REVERSE VOUTAGE FIGURE 5 - FIGURE OF MERIT varaui FREQUENCY
:.0 5.0 10 20 30
Vfl. REVERSE VOLTACE (VOLTS! I.FHEQUeNCY(MHr)
3-993
NETWORK B
The followlng ls a computer solution or the P nefwork when RLequals 50 otuns.
XL
. ,. ^~v-^ . n n rn nrsir.N A NETWORK TTSTKT. THF T A R I rs
L5 i i-reo
R c ut " X C!
(SeSte P 2)
I1
-pXC2
~ T
KL
50 1-
> 1.
2.
Define Q, in column one, as H./X
l
C. actual ts equal to C. - parallel C
C1
.
of device to
be1 matched. * out
Q XC1 XC2 XL Rl
Q XC1 X C2 XL Rl
Q X C1 XC2 XL Rl
20-39
Q Q Q X C1 X C2 XL Rl
XC1 X C2 XL Rl XC1 X C2 XL Hl
7 21.43 12.63 32.87 150 10 0.1 0.7 0.8 1 16 18.75 7.73 26.23 300
7 25 13.72 37.26 175 10 5 5 9.9 50 16 25 8.96 33.59 400
7 28.57 14.74 41.56 200 10 10 7.11 16.87 100 16 31.25 10.06 40.8 500
7 32.14 15,72 45.81 225 10 15 8.75 23.34 150 16 37.5 11.07 47.9 600
7 35.71 16.67 50 250 10 20 10.15 29.55 200 16 43.75 12 54.93 700
7 42.86 18.46 58.25 300 10 25 11.41 35.6 250 16 50 12.68 61.89 800
7 57.14 21.82 74.33 400 10 30 12.57 41.52 300 16 56.25 13.72 68.79 900
7 71.43 25 90 sod 10 40 14.66 53.11 400 16 62.5 14.52 75.65 1000
7 85.71 28.1 105.35 600 10 50 16.57 64.44 500 16 75 16.05 89.26 1200
7 100 31.18 120.45 700 10 60 18.36 75.58 600 16 87. S 17.48 102.74 1400
7 114.29 34.3 135.32 800 10 70 20.06 86.58 700 16 100 18.86 116.12 1600
7 128.57 37.5 150 900 10 30 21.69 97.46 800 16 112.5 20.18 129.42 1800
7 142.86 40.82 164.49 1000 10 90 23.28 108.24 900 16 125 21.47 142.64 2000
7 171.43 48.04 192.98 1200 10 100 24.85 118.94 1000 16 137.5 22.73 155.8 2200
7 200 56.41 220.82 1400 10 120 27.91 140.09 1200 16 150 23.96 168.9 2400
7 228.57 66.67 248 1600 10 140 30.97 161 1400 16 162.5 25.18 181.95 2600
7 57.14 80.18 274.45 1800 10 160 34.05 181.68 1600 16 175 26.39 194.96 "2800
7 85.71 100 300 2000 10 180 37.21 202.17 1300 16 187.5 27.59 207.92 3000
7 314.29 135.4 324.25 2200 10 200 40.49 222.47 2000 16 218.75 30.59 240. 16 35O
7 342.86 244.95 345.8 2400 10 220 43.93 242.61 2200 16- 250 33.61 272. 18 4000
10 240 47.58 262.59 2400 16 231.25 36.71 304.01 4500
16 312.5 39.9 335.66 5000
8 0.13 0.88 1 1 16 343.75 43.25 367.15 5500
3 3.13 4.4 7.45 25 12 25 10.39 34.79 300 16 375 46.8 398.49 6000
D 6.13 6 .* 3
) 12 31 50 12 33.33 12.08 44.52 400 18 16.67
8 9.38 7.68 16.74 75 6.86 23.35 300
12 41.67 13.61 54.05 500 18 22. 22 7.94
8 12.5 8.91 20.94 100 29.9 400
12 50 15.02 63.43 600 18 27.78 8.91
8 15.63 10 25 125 12 58.33 16.35 72.7 36.33 500
700 18 33.33 9.79 42.66 600
8 18.75 11 28.95 150 12 66.67 17.61 81.87 800
8 21.88 11.93 32.82 175 18 38.39 10.61 48.92 700
12 75 18.82 90.97 900 18 55. 13
8 2S 12.8 36.63 200 12 83.33 20 100 44.44 11.38 300
1000 18 50 12. 11 61.28
8 28.13 13.64 40.38 225 12 100 900
22.27 117.89 1200 18 55. 56 12.8
8 31.25 14.43 44.09 250 67.4 1000
12 116.67 24.46 135.6 1400 18 66.67
8 37.5 15.94 51.4 300 12 133.33 26.61 153.15 1600 14. 12 79.54 1200
8 50 18.73 65.66 400 18 77.78 15.35 91.57 1400
'12 150 23.73 170.57 1800 18 88.89
8 62.5 21.32 79.58 500 16.52 103.51 1600
12 166.67 30.86 187.86 2000 18 100 17.65
8 75 23.79 93.25 600 12 183.33 33 205.06 2200 115.38 1800
8 87.5 26.2 106.71 700 18 111.11 18.73 127.2 2000
12 200 35.17 222. 15 2400 18 122.22
8 100 28.57 120 800 19.79 138.95 2200
12 216.67 37.39 239.16 2600 18 133.33 20.81 150.66
8 112.5 30.94 133.14 900 12 233.33 39.66 2400
256.07 2800 18 144.44 21.82 162.33 2600
8 125 33.33 146. 15 1000 12 250 42.01 272.9 3000
8 150 38.25 171.82 1200 18 155.56 22.81 173.96 2800
12 291.67 48. 3 314.64 3500 18 166.67 23.79 185.55
3 175 43.5 197.07 1400 12 333.33 355.9 3000
55.47 4000
a 200 49.24 221.92 1600 12 375 63.96 396.67 4500
18 194.44 26.2 214.4 3500
8 225 55.71 246.39 1800 18 222.22 28.57 243.08 4000
12 416.67 74.54 436.92 5000
8 250 63.25 270.48 2000 12 453.33 88.64 476.57 5500
ia 250 30.94 271.6 4500
8 275 72.37 294.15 2200 18 277.78 33.33 300 5000
12 500 109.54 515.44 6000 18
8 300 84.02 317.36 2400 305.56 35.76 323.27 5500
18 333.33 38.25 356.44 6000
14 21.43 8.86 29.91 300 20 15 6. 16 21.03 300
9 8.33 6.83 14.93 75 14 28.57 10.29 38.3 400 20 20 7.13 26.94 400
9 11.11 7.91 18.69 100 14 35.71 11.56 46.51 500 20 25 8 32.73 500
9 13.89 8.87 22.32 125 14 42.86 12.73 54.6 600 20 30 8.78 38.44 600
9 16.67 9.74 25.85 150 14 50 13.83 62.59 700 20 35 9.51 44.09 700
9 19.44 10.56 29.31 175 14 57.14 14.87 70.51 800 20 40 10.19 49.69 800
9 22.22 11.32 32.72 200 14 64.29 15.86 78.37 900 20 45 10.84 55.24 900
9 25 12.05 36,08 225 14 71.43 16.81 86.17 1000 20 50 11.46 60.76 1000
9 27.78 12.74 39.4 250 14 85.71 18.62 101.63 1200 20 50 12.62 71.71 1200
9 33.33 14.05 45.95 300 14 100 20.35 116.95 1400 20 70 13.7 82.57 1400
9 44.44 16.44 58.74 400 14 114.29 22.02 132.15 1600 20 80 14.72 93.35 1600
9 55.56 18.63 71.24 500 14 128.57 23.64 147.24 1800 20 90 15.7 104.07 1800
9 66.67 20.7 83.53 600 14 142.86 25.24 162.25 2000 20 100 16.64 114.73 2000
9 77.78 22.69 95.64 700 14 157. 14 26.81 177. 17 2200 20 110 17.55 125.35 2200
9 88.89 24.62 107.62 800 14 171.43 28.38 192.02 2400 20 120 18.44 135.93 2400
9* 100 26.52 119.48 900 14 185.71 29.94 206.81 2600 20 130 19.3 146.47 2600
9 111.11 28.4 131.23 1000 14 200 31.51 221.54 2800 20 140 20.14 156.98 2800
9 133.33 32.16 154.46 1200 14 214.29 33.09 236.21 3000 20 150 20.97 167.46 3000
9 155.56 36 177.37 1400 14 250 37.12 272.66 3500 20 175 22.99 193.54 3500
9 177.78 40 200 1600 14 285.71 41.34 308.82 4000 20 200 24.96 219.48 4000
9 200 44.23 222.37 1800 14 321.43 45.86 344.7 4500 20 225 26.9 245.3 4500
9 222.22 48.8 244.5 2000 14 357.14 50.77 380.33 5000 20 250 28.82 271.01 5000
9 244.44 53.8 268.4 2200 14 392.86 56.22 415.69 5500 20 275 30.74 296.62 5500
9 266.67 59.41 288.05 2400 14 428.57 62.42 450.79 6000 20 300 32.67 322. 15 6000
20-40
National Semiconductor i
LM381A Dual Preamplifier Application Note 70 -N
for Ultra-Low Joe E. Byerly O
Noise Applications Dennis Bonn
August 1972
OJ
co
INTRODUCTION
The LM381A is a dual preamplifier expressiy de- Figures 2A and 26 show the wide-band [10 H"z o
sgned to mee: the requrements of amplifyng low 10 kHz) input noise voltage and input noise cur- c
level signis in noise critical applications. Such rent versus collector current for the single ended QJ
applications include hydrophones, scientfic and
instrumentation recorders, low level wideband gain
blocks, tape recorders, studio sound equipment, O)'
etc. CU
The LM3S1A can be externaliy based for optimum 3
_ noise performance n ultra-low noise applications.
VVhen thsisdone che LM381A provides a wideband,
high gain amplifer with noise performance that
exceeds that of todays best transistors. cu
i
The amplfier can be operated n either the dffer- t
ential or single ended nput confguration. How- o
-1
ever, for optimum noise performance, the nput
must be operated single ended, since both transis-
tors contribute noise in a differential stage, de-
FIGURE2A. Widfaand EquivJ*nt Inpot fJoi
vi Callecior Curtnt
c
It-
gradng input noise by the factor A/2. A second -1
consideraron s the design of the input bias cir- 01
I
cuitry. Both the load and bssng elements mus: r*
be resistive, snce active components would each o
contnbute additional noise equal to that of the
input device. Thirdly, ihe current densty of the
input device should be optimized for the source
resistance of the input transducer.
FIGURE 1. LM3S1ASchm4ticDsrain
AN70-1
inpu: configuraron of the LM381A. Total input
nose of the amplifer is found by:
ET = B.W. (1)
Where:
Rs = source resistance fi
10
(3)
Where:
P.S.R. = Supply rejection in referred to
E.IQtQ 1U; l V L Mil
input
!!! l SV 10* Di i IDi fs = Frequency of supply ripple
flllil-
AT = Voltage gain of first stage
FIGURE 3. Col laclar Curren! vi Sourca Rasiswnca As R! becomes smaller capacitor C-, ncreases for
for Opiimum Noiw performanca
a given power supply re|ection rario. Conversely,
as R 2 becomes smaller the gain of the nput stage
decreases, adversely affecting noise performance.
Figure 4 shows the input stage of the LM381A with For the range of collector currents over which the
the external components added to ncrease the LM3S1A is operating, a reasonable compromise is
current density of transistor Q,, Resistors f\- and obtained with:
fl2 supply the additonal current (I2) to the exist-
ng collector current (I,) which is approxmately R2 = 3 14J
The sum of resistors R T d R 2 is given by: The gain of the input stage s:
R Vs-2.1 ( 2 x 10 5 ]R-,
(2)
Ic-ISxlQ-6 105
A, = (5)
1 " .026 1
For DC consideradora, only the sum (Rj + R 2 ) s
importan!. When considering the AC effects, how- le 1 . 1 . 1
ever, the vales of R 1 and R2 become significan!.
AN70-2
Resistor dvider R|/R3 provides negative DC feed-
C-, = -4 x 10'12 (11)
back around the amplifier establishing the quies-
i .026 \
cent operaling point. Rf is found by; 102D
1 f V s R 3 x 104 Where:
2 x 104) + lc (R: x l O 4 )
l.55{R 3 + j f-) = high frequency 3 dB crner
Ic = Q! collectar current
R a x 10*
(6) A = mid band gain dB
R 3 r 1 x lO4
Example: Design an ultra-low noise preamplfier
For DC stability let: with a gain of 1,000 ooarating from a 24 volt
supply and a OQH source impedance. Bandwidth
R 3 = 1 kCl Mximum (7) of interest is 20 Hz to 10 kHz.
R can then be found from: 1. From Figure 3 the optimum collector cur-
rent for 6GOn source resistance is 170 A.
2. From equation (2),
-910 (8)
2 6.05 X 103+ I C X 107
V s -2.1
! + R2 =
Sx 10"6
Where:
V s = Supply Voltage 24 - 2.1
The AC closed loop gain is set by the ratio: R! +fl a = 1.44 x 105.
V3 x 107
-910
6.05 x 103r l c x 107
1 24 x 107
R f = r- -910
* [ 6.05 x 1Q 3 T 1.7 x 10'
R f = 2.67 x lO J ^27k.Q.
27 x 103
HA = = ^7
103
AN70-3
8. From equation (51 the gain of the input
stage s:
( 2 x 10r\Si
S) R 2
R, + 2 x 105
AI =
.026 s~T^ U.F
1 . 1
2 x 1Q5 x 10S
1Q5-r2x1Q5
A, =
1 .026 1
1.7xlO-4
_
104 103
_
27
FIGURE 6. Typical Appllcation wth Incrsis*d Current
9. For 100 dB supply rejecton at 120 Hz.
Danuty of lnp<Jl Su^a
Equation (3),
The noise performance of the circuir of Figure 6 Other outstandng features include, hgh gain
can be found with the aid of Figures 2A and 2B (112 dB) large output vokage swing {V s - 2V)
peak to peak, wde supply operating range {9 -
and equation (i!. From Figures 2A and 28 the
noise voltage (en) and noise current (in) at 170 pA 40V], wide power bandwidth (75 kHz, 20 V OSJ ),
l c are: en = 3.0 nVA/RT, n = .72 pAA/Hz". From internal frequency compensation, and short-crcuit
equation (1) protection
REFERENCE
ET
J.E. Byeriy and E.L. Long - "LM381 Low Noise
Dua! Preamplfier" National Semiconductor Cor-
\/l!3.0x 10- 9 ) a + [7.2 x 10* 13 x 600)* + 9.94 K 10'18| 10* poration AN-64, May 1972.
AN70-4
o
a Precisin i Waveform1'-;-
Generator/Voltage ;:;
Contrblled Oscilaor;
GENERAL DESCRiPTION ' ; ' [ : : . . - _ FEATURES-- . . "- , : -.
The 1CLB036 Waveform Generapr is monolithic inte- Low Frequency Drift V/lth Temperatura" .
gratecJ crcuit capable of producing high accuracy sina, . 250ppm/ C . . : .- . .
square, triangular, sawooth and pulse waveforms with a Smultaneous Sine, Square, and Trlangle \Vave
mnimum of exernal componens. The (requency (or repet-. Outputs
lion rale) can be selected exernay from .OOiHz to more Low Distorlon 1% (Slne Wave Outpt)
than SOOkHz using eilbgr resistors ~or capacitors, and High Llneafity 0.1% (Trangle. Wave Outpt)
frequericy modulation and jweeoinQ-can be ^ccompjisiiejj Wide Operaling Frequency Range O.OOlHz to
wilh an externa! vllaga. The ICLB038 is fabricaied with .-300kHz
advanced monoiithic technology, usng Schottky-barrier Variable Duty Cycle 2% to 98%
dodes and thin film resistors, and the oulput is stabte over a High Leve! Outputs TTL to.28V
wde range of temperaure and suppiy variations. These Easy to Use Jus A Handful o Extemal
devices may be interfaced with phase Jodied loop circuiry Components Required .
to reduce temperatuie dri/l to less than 25Gppm/C.. .
ORDER1NG INFORMATION
PAHT NUMQER STAB1LITY TEMP. RANGE PACKAGE
icuao33CCXJD 250[)pin/"C !yp - O'C lo +70'C CE.RDIP
ICLS036HCJD 1SOppm/'C typ o"C 10 T?crc CERDIP
ICL6038.ACJO 110ppni/'C ryp rf 0"C le +70*C CERDIP
ICLE033BMJO* 3Oppm/*C max- * . -55'C lo -t-125'C CERDIP
ICLB31AMJD' 2!)0ppm/ *C max -55"C lo t- i25*C CERDIP
ICLSC^S/D ~ - DICE"
CUHflEHT /V
souncE ka
BUFFEH sme
CONVERTER
1
JLTL.
5-72 302600-OC
Nolc: All lypical vales have been guaranlad hy charactorization and ara no! c-sled.
ICL8033 :: .' ; . .' -.
ABSOLUTE MAXIMU/ RATiNGS-- "
Supply Voltage (V" to'v+);';;!;;...:...7."7,~'~.7."...'.'36V"":' ' Storage-'Temperatura Rahge".7^~"."f:650C lo'VT50"C'-
Power Dissipation'V.....,.-...-'.'.'.'.,.,.'..,'.,.-'.:;....,.750mVV...'.. ...Operaing Temperatura Rangei-lii^l'jJL1'" "...'. '.'
Input Voltngo (any pin). ;....: ....,.;.....V~ to y T 8038AM, 8038SM.. ....'...:.-55'C lo -i-125C'
Input Currenl (Pns 4 and 5) ; ......' ...... 25rnA . " 8038AC, 803S8C/8038CC ..'."..7,...0C to +70C
Output Snk Currenl {Pns 3 and 9}-; ',. ;.,.25mA-. ' _ Lead Temperatura {Soldering, 10see)-,-.;.;.'. ...300C'
Stresses abova ttiose lislud undef Absolle Mximum Flatings tnay cause permanenl damage to ttie devca. These are stress ratngs only, anc functional
cperaibn o ".ne da-.ice al [nese'ar any clnar conditions abova those ndicaled in Ihe op^ralional sactiotw o lile s?cificationa _fa nol implicd. Exposuie lo
absoluta mximum rating condilions (or extended pariods m&y effect avce [eliabily. . .... .. . _ ___ . ... . .'"' '
NOTE 1: Oerale ce/ain:c package at' 1^.5mV//*C df ambient .lempotaluras atwvfl 100'C '_ _._ . , . ' " .:_.
' ir Risa Time (R[. - 4.7Knj : . ' ' 180 160 180 nn
ii Fall Timo (RL - 4.7K) ' 40 JO . 10 ns
AD TypCJ! Duly Cycio Adjus! (Nole 6} ^ ! !)3 2 98 2 aa %
Trianqle/Sawtooth/namp : 1
VTRIANGLE Afnp!:lud9 (RtHI - lOOkfi) 0.30 0.33 0.30 0.33 0.30 0,33 VSUWLV
j Lineanly 0.1 0.05 - 0.05 %
Noto: AH ' vales have buen gua/anl*^ by charadefiinl-on and are nol losled.
co
co
o
TST CONDITIONS'
1 ! PARAMETER .'' ' r. . , RA ...i; RB ' RU-- 'O \"SVJi '. MEASURE \' -.
Suppiy Cwrnt ;"' . lOk .; i lOk tokl 3.3nF Glosad Cunon; into Pin 6 - -.
Swep FM BangeO) .- ' '! :",_ Mokn r ', 10K IGKfl 3.3nF Gpn 'Fiequenc/ a\n 9 '.' '
Fiequancy Drill witn Temperatura iokn I iokn mil 3.3nF Clos&d- Fifccjuancy al Pin 3
Fequency Dff with Supply Voltage^' "- 10kU ' r - lOftn icki 3.3riF Closed Ftequncy at Pin 8 '
Qutpul Amplilude: Sina ' ' 10W '.. IQXi ' lOkl . 2.3nF Closed Pk-Pk outpul al Pin 2
(Note 4}; Triangfa 10 M . lOkQ 10K . 3.3nF Closed Pk-Pk oulpul a! Pin 3 .- \ Closed
Saluration Voltage (on}{3' 10KH - 10kf 3.3nF Clased . Output (lo-iv) at Pin 9
nise and Fall Times (ola 5) 10kP. . iok 4.?kn 3.3nF Clased Waveorm al Pin 9
Duly Cycls Adjust: MAX 5okn -i.6kl . . lOk 3.3nF . Closfld Wavolorm at Pin 9
(Cile 5) WIN . ~25^n 50V.O lV-fl 3.3nF Glosan . Wauefotm al Pin 9.
Triangle Waveorm Linearity - ioka iokn 10K1 3.3 r,F Glosad Waveform al Pin 3
Tola! Harmonio Distortion . lOkl 10K 10kf! | 3.3nF j Clo&ed Wavaform al Pin 2
pin 8 lo pm 6 (f]0). Olhanvise
appl/ Swocp Vbllaga at pin 6 (2/3 VsuPPLY "*"2V) - '-'SVVEHP - VsuPPLY whafe VsuPPLY '5 llfl 1 lal suppty yoltagg. [n Figure 7b.
pin 6 should vsr/ bsiwaen 5.3V and 1CV _wih. rsped lo ground.
2. i o v < v * <3ov, of sv<VSUPPLY--15V.
3. Oscillaon can be halled oy lorcing pin 10 to 4 5 volts or -5 volls,
4. Oulpul Ampliluda is tested undar slalic condilions by forcing p!ti 10 lo S.OV tnen to -5.0V.
5. Hoi Issted; (or design purposes on!y. ' . . . , _ ' . ' .
5-7-1
Mole: All typica! valuos hava beon guaranleod by characlarizaton arxi ara not leslod.
J..-.TYPICAL PERFORMANCE ; CHARACTERSTICS U
.O
TyjTTTfpJ
s 10 is K a 10 ;o j i
. > ttJPPtr VOLTJGE . . - -' TEVPRJLIURE'C '
Q<*XIX:
ir
I 1 _, .
jTi..uj"
121 . . . ,
i -i I
rn 1
-.,.1...,_._.
Ii M'
UHAJUSTEDI I
Note: Ail typica valas riaye btn guaranteed by criaracierizalkMi" and ara not tesied. ' ,
i' i;
-'f (V
>
"-J:
' rt !
- o 1
cp l
O
DETAILED DESCRIPTION ' . ' controis Ihe rising porticn o the triangle and sine-wavo and
(See Figure 1) . . Ihe 1 state o Ihe square-wave.
The magnitude of the triangle-waveform is 301 ai 1/3
An external capacitor C is charged and discharged by two
VSUPPLY: thereore the rising portion of Ihe triangle s,
current sources. Cutront sourco # 2 is s\vtched on and of
by a Ilip-lop, while currenl source #1 is on conlinuously. Cxv c x lo x VSUPPLY x RA 5
Assuniing tha tho Ilip-fop is in a state such that current ti = = -= - F./, >: C
source i? 2 is o, snd the capacitor is charged with a curren
! Va x VSUPPLY 3
1. hs voltage across the capacitor rises linariiy v.-lh time.1. The falling portion of Ihe triangle and sine-wavj and he O
When this volago reaches the leve! o comparatcr # 1 (sst state of the square-wave is:
at 2/3 of the supply vollage), Ihe flip-llop is trigoered,
changos stales, and rolease.1; current source #2. This CxV C x i / 3 vSUppLY
current source normally carries a current 21. thus the
capacitor is discharged with a not-current I and the voltago VSUPFLV VSUPPLY
across i: drops linearly with time. When i has reached tho
lovol o coniparalor # 2 (sol ai 1/3 of tha suppiy volagu),
the the lip-flop is triggerod into its original sato and tho
cyclo slarts again. Thus a 50% duty cycle is achieved whan F '* RB. .
'Four waveforms aro ready obtainable [rom this basic 11 t!o duty-cycd is to be varied ovar a small r moo about
goneralor circuit. With Ihe curran sources sol at I and 21 50% oniy, tho connc-jtion shown in Figuio 5t. is slighlly
rospeclivoly,- tho charge and discharge timos are equal. moro con'.'Giiien. l no adjustment o Iha duty cyclo is
Thus a triangle v/aveform is created across the capacitor cosired, terminis 4 and 5 can be shorted U'tjelher. as
and tho flip-flop produces a square-wavo. Bolh waveforrns snown in Figure 5c. This connection. hov/over, c:ausos an
are cd to bufr slagos and aro availablo al pins 3 and 9. inheronlly Irujoi variation of Iho duiy-cyc-It, fraujuncy, etc.
Wih tv/o seprale timing rosislors, tho liqic:n:y i; ci
Tho levis o! Ihe curren! sources can, however, bo by
selected ovor a wido range v/ilh two oxternal resislors.
Thoroore, wih Iho two crrente set al vales dferonl (rom
I and 21, an asymmeirical sav.looth appears al terminal 3
and pulsos wih a duty cycle from losy than 1% to greator
han 99% are availabe at termina! 9. . 1 *
Tho sne-wave is crealed by eeding the Uianglo-v/ave
into a non-linoar network (sine-convorter). This nelwork
provides a decrcasing shunt-impedanco as thc potonial o! or. i nA
Ihe Iriangle moves toward Ihe v/o extremes.
0.3
f " (or Figure 5a)
WAVEFORM TIMNG RC . -
The symme(/y of all wavoforms can be adjusted with Ihe If a single timing resistor is used (Figuro 5 ^ only), tho
externa/ ming resistors. Two possible ways to accomplish requoncy is
this are shown in Figure 5. Bast results are obtaincd by 0.15
koeping Ihe timing resistors RA and RB seprale (a). R A i _
RC
5-76
5-77
NQG:- AK typical valas rtave baon guaianleed by characleniollon and c/c no! tesiad.
O
co
u
:--.... (b):
' fU - > Ra
^JLTL . .flTL;
10 n = Vl; 10 n 'VA, -
t r J \~olGHD
Lcntiso
Figure 7: Connections for Frequency Modulation (a) and Sweep (b)
'T
Figure 8: Sne Wave Ouput Buffer Ampllfers
5-78
Note: All typicnl vales hava Qeen guaranleod by characleriralton and afe nol
'
CL8038;i?;;.
* I'. . vi.r-'t-r*.- -' - ~:,~,V^:.-.V-;v..* : - .f/..-, ,L> -:. -,'...rf:-,,- .^-,,
-. ",. ^
-. '
.
. .^V. ,,-.-,f
t ,.'
.j a, : .:L":--;.
1
: - , . ' ' . - ,
[ 7
s - t * l" ' CYCXI '
4 ' iWvi
ICLB034
u' I * I , I a
A j nn_
i1 " ' 10 2
1H9H -
';=P^l
i^Ta TROBE 10
X . _-, . >
^ -. "\A/
&FF
j p-isv(-Hav)
_^iv LJ LJ
OH
-ISV(-IOV)
( '
10 11 13 J
con ' ..,._. . i
. F gure 9: Strobe-Tone Burst Cienerator : -JW X^.- ZZJXVW S^D^TOBTIOfi
' ..-'.*. -' /> 100. _^.
The Lneariry o npul sweep voltage vcrsus oulput fro- voltage will. nol oxceed Ihe capabilic-j of tho...pha
cuoncy can be siQni'icanlly mproyed by using an op amp as delector. II a smaer VCO signol is roquired, a sim
iliown n FKjure 11. rsistive volo|]o divider s connecied bolvon pin 9 o
waveform gc-norator and Ihe VCO nput of the pha
USE IN PHASE-LOCKED LOOPS . detector. *
. Its high roquency stabilily maks the ICL8038 an ideal Second, th DC otpul leve] of the anplfior mus
buildmg block or a phase-locked loop as shown in Figure made cornpalible lo the DC leve! roquired .l tho FM inpu
12. In this application [ho remar.ing unclional blocks, ho
Ihe waveorm gcneralor (pin 8. O.SV*"). Tho simp
phas-3-dC'iector and tha amplilier, can be (ormed "oy a
soluon hero a 10 prvida a voltago dividi.-r to V* (R 1p
numhor of avalablo |C*- (e.g. MC4344. NE562. HA2800,
HA2H20) as shown} il Ihe amplifier has a lower oulput lovcl, or
ground I its Ic^oi s higher. The divider car be niado par
In order to match hcse bulding blocks lo each other, Iwo Ine low-pasb lilier.
slops mjst be laKen. First, two diflerem supply vollages are
used snd tho squara v/ave output is relurnod to (ho supply ' This'applicition nol only provides lo.- a free-runn
of ho phasfl detoclor. This assures Ihat the VCO input Irequoncy wilh very low temperaturo drilt, bul aiso has
5-79
Note- All lypical voluo hav oeen guaranlcfri b/ cha/seleri;alian and tuo nol le&tod.
co . ' '' " - V--
p>
o - : ' | [
05
unicua (esure o producing a large reconstitutad smewave For further informaon; 'see "Intersil Application Note
signal with a frcqusncy dentical lo that at the input. , .A013, "Everytbing You Aiways Warited to Know About Th
ICL8038." ..; ' . . ;-, '
Nolo: Al tyfxcal vales have bson guaranleed by ctiaracterzat'on and are nol tasted
National Audio/Radio Circuits
Semiconductor O
CD
CT)
l Cin PiCkig,
Scherrutic and Connection Diagrams
[w .i-
f LW1496N
9* N14A
d CjfT*r
10-107
5 tO
Ii s Absolute Mximum Ratings
V (
!i i
i Iniecnal Pawer Oiin'pation [Note 1)
ADpliod Voltage INale 2)
500 mW
30V
Oifferential Inpot Signa! [V7 - Vgl sfi.OV
1 " to DIHcr.entitllnputSigruI [V* - V,J :[5*ISR.|V >
O) Inoot SlyaJ (V - V,, V 3 - V 4 | 5.0V
j LO BiiiCtmn[ US) 12 mA
Oparaiinj Tt<np*ritur* flange LM1596 -55*CtorI2SC
UM1496
-65C lo t
Uad Tmp*mure (Soldering. 10 s 300*C
LM1596 LM149
PAHAMETER CONDITIONS UNITS
MIN TVP MAX MIN TYP MX
Cimtf FJlniougn V c - 60 mVrm lint v,e 40 40 iWmi
'c " 1.0 lHi. olf[ idjuited
V c - 60 mVrmi wm wjv 140 140 /Vrms
C - 10 MHf, oAwn jjuiied
Vc - 300 mVpo tcw"e we 0,04 0.2 0.04 n mVrm
C * 1.0 *Hz, of[ adjuilid
' Vc - 300 mVp,, touar. w*- 20 100 20 15 -nVrrra
fe ' l.OiHi, olfielnot idjusted
Carril* Supfxraion s - 10kH/, aOOmVrm 50 65 50 65 03
Ic 5OO kHr, 60 mVrm in we '.
oHwi idjuslrf
s - IQkH, 30QmVrmi 50 50 dB
f g - 10 MHi. 60 mVmii n wj.
PQSJI! SiJDpJy Curienl " (U -Mu ' 2.0 3.0 2.0 3.0 mA
Ntoitv* Suppiy Currmt lijo) 3.0 4.0 3.0 *.o mA
Pow, DiaJMtan 33 33 mW
Not 1; LM1596 raling apoliei to case temperatucej to ^-125C; derale nearly at 6.5 mW/^C Jar
ambiem temperature above 75C. LM1496 nting appJies to case temperatures to ^70C. ' ' ,
Nott 2: Voltafle appid betWMti pini 6-7, 8-1, 9-7, 9-6, 7-4, 7-1, S-4, 6-6, 2-5, 3-5.
N
10-108
Typical Performance Characteristics
596
Car rier Supprtulon vi Crr'wr SuppfaiIJon vi Carrir Fendthrough vi
Carrir Inpui Lv FrsqOocy
496
IM IDO 300 Wfl SOO 0.05 0.1 0.5 1.0 LO 10 LOS a,| a.s i.n i. u IB 5o
CARBIER INFUT UVEL [V|iw) C A R R I E f l F R f d U E N C Y (UHj} CARHIEfl FflEQUENCr IMHi
Applications (Cominued)
Bisanuo\
iNfUT ^ J ^ 4 _>JCv 1 O """OULArE
~-w^^ j ^u Af g u r r u T
LM I
-4 Vli
adjuitment i not requred. ThJ circuit may aJfO be ussd as in AM detector by appying compoiite and carrer sgnali
!n ths iatri manner ai datcribed for product detictor opuraton.
10-109
co
t^
T_ Typical Applications (Continuad)
2
en
-i Vic
Tha frequency doubler crcuit shown will double low-Jeval signis with. low distorton. The valu of C should be chosen
of low reactance at the operating frequency.
Signal level at the carrier input rnuit b lesi trian 25 mV peak to maintan op^ration n the linear regin of tha switching
diKerential amplifer. Levis to 50 mV peale may be usad with some dscortion of the output waveform. f a larger input
signal is available a resistiva divider may be used at the carrier input, with ful! signaJ applled to tha signal npui.
10-110
en
CO National
Q
Tf
Q
Semiconductor
O
CD4018BM/CD4018BC Presettable Divide-by-N Counter
en
CO
Logic Diagram
Connection Diagram
Dual-In-Lne and Fat Package
V OD atii cinc os i
i( is K In U
5-58
O
Typical Performance Characteristcs o
Typical Transition Tm vs _ Typical Propagaron Delay vi. C[__
CD
JDD CD
O
o
co
ca
O
2Q 40 G 30 1QQ 2D 10 SO SD 100
CL - L O A O CAPACITAfJCE |F) CL - LOAG CAPACirANCE \vI
Divida B y S l
o ro-a*iA-iMui
Divide By 3 CONSECHD r a - O
5-61
O
QG
CN(
LO
National
O
TT Semiconductor
Q
U
CU
CD4Q51BM/CD4Q51BC Single 8-Channel Analog
CM
LO
Muitplexer/Demultiplexer
O
Tj- CD4052BM/CD4Q52BC Dual 4-Channe! Analog
Q
O
Multiplexer/Demultipiexer
CD4Q53BM/CD4Q53BC Triple 2-Channel Analog
m CQ
T- CO
Multiplexer/Demultipiexer
LO LO
O O
r- TT
QQ General Description Features
OO
These analog multiplexers/demultiplexers are digitally Wide range of digital and analog signal levis: d
i conrolled analog switches having low "ON" impedance 3-15 V, analog to l5Vp.p
CQ CU and very low "OFF" leakage currents. Control of analog
T- CO signis up to 15Vp.p can be achieved by digital signal Low "ON" resistance: 80 {typ.) over entire
LO LO signal-input range lor VDO Vgc = l5V
O O amplitudes o 3-15V. For example, if VDD = 5V, VSS=OV
^ T and Vcg = -5V, analog signis from -5V to +5V can be High "OFF1 resistance: channel leakage of =
QQ conrolled by digital inputs of 0-5 V. The multiplexer cir- (typ.) at Voo-VES = 10 V
OO cuits dissipale extremely low quiescent power over the
full VDD - Vss and Voo - VEE supply voltage ranges, inde- Logic level conversin for digital addressing si
penden! of the logic sate of the control signis. When a of 3-15V (V DO -V SS = 3-15V) to swtch analog sig
logical "l" Is present at the inhbit input terminal all tolSV p . p (V D D -V E E =15V)
channels are "OFF". Mached switch characterisics: (typ
CD4051BM/CD4051BC is a single 8-channel multiplexer
having three binary control inputs. A, B, and G, and an in-
Very low quiescent power dissipation under all di
hbit input.The tnree binary signis select 1 of 8 channels
control input and supply ccnditons: ipW (typ
to be turned "ON" and connect the nput to the output.
VDO -Vss = VnD-VgE = iOV
CD4052BM/C04052BC is a differential 4-channel multi-
Binary address decoding on chp
plexer having two binary control inputs, A and S, and an
nhibit input. The lwo binary input signis select 1 or 4
pairs of channels to be turned on and connect the dif-
ferential analog inputs to the differential outputs.
CD4053BM/CD4053BC Is a triple 2-channeh multiplexer
having three seprate digital control inputs, A, B, and G,
and an inhibit input. Each control input selecs one of a
palr of-channels whlch are connected n a single-pole
double-throw configuration.
Connection Dagrams
k 15 14 13 13 11 in 1; 1G IS U 13 II 11 10 1 13 ti ll lO
p J J
I-
1 2 3
*
5 E 7 i I 1 3 1
5 G J
!'
1N/DUT ' O U T / I H INOUI
5-152
53 MSI DM54/DM7490A, L90, LS90, 92A, LS92 , 93A, L93, LS93
Connection Dagrams
NPUT INPUT
A NC QA QD GNO 3g QC A NC OA QB GND Qc 0D
14 13 12 11 10 9 8 14 13 12 11 10 9 B
I o >
r ' r> i
1 2 3 4 5 6 7 1 2 3 4 5 6 7
u> u>
<c1
c> r^~ ~
1
i 2 3
5
6
' 1 2 3 4 5 6 7
INPUT RO(D R0(2) NC Vr NC NC '
B HO(D H0{2) NC VCC NC NC NC ;
6-36
MSI DM54/DM7490A, L90, LS90, 92A, LS92, 93A, L93, LS93
Logic Diagrams
90A, L90, LS90
H9[l] -
H9|21
j a
CLOCi
J Q
CUOCi
K O
BOflI 1 \-_
ROI-Jr
92A,LS92 93A, L93, LS93
| (he J ana K mans snowa *unout conneclian aie lor relerence only ana are lunclionally al a Hign level
22 MS| DM54/DM74147, 1
Priority Encode
General Descripion Feaures
DM54147, DM7414-7
These TTL encoders feaiure priority decading o the nput
data to ensure ihat only the highest-order data Une s en- Encodes lO-line decimal lo 4-lme BCD
coded. The DM54147 and DM74147 encode nine data Unes Applications include:
to four-Iine ( 8-4-2-1) BCD. The implied decimal zero condi- Keyboard encoding
lion requires no inpu condition as zero is encoded when all Range selection
nine data lines are at a high logic level. All inputs are Typ cal data delay lO
buffered to represen! one normalzed Series 5 4 / 7 4 load.
Typical power dissipation 225
The DM54148 and DM74148 encode eight data Unes to
Ihree-Hne (4-2-1) bnary (octal). Cascading circuitry (en- DM54148, DM74148
able input El and enable oufput EO) has been provided to i Encodes 8 data lines to 3-line binary (octal)
allow octal expansin without the need lor externa! circuit- Applications nclude:
ry. For all types. data inputs and outpus are active ai the N-bit encoding
ow logic level. Code conveners and generators
Typical data delay 10
Typical power dissipation 190
Connection Diagrams
n O O O O O l
(
jC
J iC D-l
o o y o o o 0 C 0 0 0 (J
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
4 5 6 7 8 C B GND I
j , ,_ , 4 5 6 7 l A2 A1 GND
INPUTS OUTPUTS -*
INPUTS OUTPUT s
Truth Tables .
54147/74147 54148/741-18
1 2 3 4 5 6 7 B 9 D C B A E 0 1 2 3 4 5 6 7 A 2 A 1 AO GS
H H H H H H H H H H H H H H X X X X X X X X H H H H
X X X X X X X X L L H H L L H H H H H H H H H H H H
X X X X X X X L H L H H H L X X X X X X X L L L L L
X X X X X X L H H H L L L L X X X X X X L H L L H L
X X X X X L H H H H L L H L X X X X X L H H L H L L
X X X X L H H H H H L H L L X X X X L H H H L H H L
X X X L H H H H H H L H H L X X X L H H H H H L L L
X X L H H H H H H H H L L L X X L H H H H H H L H L
X L H H H H H H H H H L H L X L H H H H H H H H L L
L H H H H H H H H H H H L L L H H H H H H H H H H L
6 58
MSI DM54/DM74176, 177, 196, LS196, S196, 197, LS197, S19
Connection Diagram
DATA JNPUTS
Not: Low rnpul lo Cleaf sais
DM54/DM74192, L192, LS192, 193, L193, LS193
Connection Diagram
IHPUTS
16 15 14 13 12 n 10 9
r\ S c\
-*
i\ \
1 2 3 4 7 8
OUTPUTS INPUTS
6-161
22 MSI DM54/DM74194, LS194A, S194
General Description
These bidirectional shift registers are designed to incorp- Clocking of the flip-flop is inhibiled when both mode control
rale virtually all o (he features a system designermay want inputs are low. The mode controls of the of .the DM54 194/
in shift register; they feature parallel inputs . parallel DM74194 should be changed only while the clock inpul is
oulputs. righ-shift and left-shift serial nputs, operating- high.
mode-control inpuis. and a direct overrding clear line. The
register has four disinct modes of operaton, namely:
V1
1 7 3 4 5 6 7 a
CLEAH SHi^r A B C 0 ShiFT C
RIGHT ' ' LEFT
Truth Table
lnDO|. OulpuU
Moda Serial Parallel
Claaf si so
Cloc
k Ult filfjril A B C D OA a oc QD
L X X X X X X X X X L t L L
H X X U X X X X X X AO SO CO DO
H H H 1 X X a b c d a o c d
H L H ! X H X X X X H O An QB(1 QCn
H L H i X L X X X X L CAf OBn OCn
H H L, ' 1 H X X X X X Ogn QCn QDll H
H H L / 1 L X X X X X OBn Cn Dn L
H L L X X X X X X X OAQ c so co DO
H = Hih Level fsteatJy siala). L = Lo- Level (sleady stale). X = Don'l Cafa (any nput, -icludmg tiadiiions)
j = Tfaitanion Irom tow to fvgn tevl
a. b. c, a = Th Itfvel o al aacy stale mpul a| inpul A, B, C. Of D. respeciively
GAO- ao- co- oo * Tne * vel o Q^. Gg, Q^, or DQ, resQiC! ely, eiofa ne ndicaied sleady siale inpul cono
Uons were esiaoliisned.
oAn.oen.Qcn.a0n^^e level olO A .Q 3 .Q c .:e 3 jeet vly. balofe me mos l.fCent(KJMilionoimeciock
6 169
MSI DM54/DM7419S, LS195A, S1
puls afier the positive iransilion o the cock input. During i J and K inpuls to [irsl stage
loading. serial dala low is inhibited. Complementary outpuls rom las! stage
Shilting is accomplished synchronously when the shift; For use in high-performance:
load conlrol inpu is high. Serial data or this mode s en- accumulators/processors
tered at Ihe J-K inpuls. These inpuls permit the irst stage serial-to-parailel, parallel-to-seriai converters
lo perform as a J-K, D. or T-type flip-flop as shown in the
Typical Clock Typical
trulh labia. Type Frequency Power Dissipati
The high-perormance 3195, with a 105 MHr typical shilt 195 39 MHz 195 mVV
/rc-quoncy, is particularly attractive for very high-speed LS195A 39 MHz 70 mW
dala processng systems. n most cases exising systems S195 105 MHz 350 mW
Connection Diagram
Truth Table
Inpuls Qutput
Shtft Salal Parallel
CI03 P,n,>
Load J K A B C D
L X X X X X X X X U L L L H
H L 1 X X a D c d a C c 3 ti
H H U X X X X X X AO Qso co oo QDO
H H ! L H X X X X 0*0 GAO QQn OCn OCn
H H ! L L X X X X L Q An QBn OCn QCn
H H ! H H X X X X H OAn QBn Ocn CCfi
H H 1 H L X X X X An 0 An QBn OCn QCn
H - Hign Lfcvtl (sieady alai u). L = Lo* LevtI [Mead/ sldle), X = Oon'l Care {any mpui. mcludmg iiansiliona)
- ansiluii Iforn low ID ti.gn leve)
a.b.c.a Ttie level o sieaay. siale inpm al A, B. C. o D. respeciivBly.
AD- eo- GO- DO = Thejevel O Q A . Q B , QC- f OD- fespeclively. belore ine Jndicaleo sieady slale inpul
condilions v-uie esIaDNsneo.
Q An . Gg(|. QC,, -= Tne levsl O Q^. O0- OQ, f especvely. oelo'e ne mos! ecenl Iransidon o Itie Clack
6-174
CIRCUITOS IMPRESOS DE LAS TARJETAS CONSTRUIDAS
ETAPA DE AUDIO
MODULADOR FM UTILIZANDO EL MTODO DIRECTO
ETAPA DE LA ONDA P ORTAD ORA
MODULADOR FM UTILIZANDO EL MTODO DIRECTO
ETAPA BE POTENCIA
MODULADOR FM UTILIZJNDO EL MTODO INDIRECTO
SEAL FM DE BANDA ESTRECHA
MODULADOR FM UTILIZANDO EL MTODO INDIRECTO
SEAL FM A 31.25 MHz