Dell Inspiron 143421 Dne40cr 122041 A00 Schematics

5 4 3 2 1
D D
Essentials Oak 14 Schematic

Chief River
w
w
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fix
2012-09-05
.c
om
C C
REV : A00
B B
A
DY : None Installed M14 DIS A
Wistron Corporation
UMA: UMA only installed 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
OPS: DISCRTE OPTIMUS installed Title
Cover Page
Size Document Number Rev
A3
OAK14 Chief River DIS A00
5 4 http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
Date: W ednesday, September 05, 2012 Sheet
1
1 of 105
5 4 3 2 1
CHARGER
BQ24727 40
Project code: 91.4WT01.001 INPUTS OUTPUTS
91.4XP01.001
PCB P/N : 12204
Oak14 Block Diagram AD+
BT+
DCBATOUT
SYSTEM DC/DC
Revision: A00 TPS51225 41
INPUTS OUTPUTS
3D3V_AUX_S5
D 5V_AUX_S5 D
DCBATOUT 5V_S5
3D3V_S5
DDR3
CPU Core/NB Power
Intel CPU DDR3 1333/1600MHz Channel A
1333/1600
ISL95833 42~44
33
SODIMM A INPUTS OUTPUTS
Nvidia Ivy Bridge 14
VRAM(DDR3) *8 VCC_CORE
128Mx16bx4(1GB) N13P - GS - OP PCIe x 8 17W (DC)
DCBATOUT
VCC_GFXCORE
26
256Mx16bx4(2GB) DDR3
DDR3
N13M- GSR 1333/1600
128Mx16bx8(2GB)
25W DDR3 1333/1600MHz Channel B DDR3 SUS
BGA1023
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88,89,90,91 TPS51216 46
83,84,85,86,87
SODIMM B
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INPUTS OUTPUTS
15
4,5,6,7,8,9,10
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Switchable Graphic only DCBATOUT 1D5V_S3
DDR3 VTT
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TPS51216 46
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FDIx4x2 DMIx4 INPUTS OUTPUTS
DCBATOUT 0D75V_S0
fix
CPU VCCP_CPU
.c
10/100 NIC TPS51219 45
HDMI V1.4a HDMI
om
C
RJ45 INPUTS OUTPUTS C
51 PCIE x 1 Realtek
DCBATOUT 1D05V_S0
RTL8105E-VD Conn.
Intel PCH 31
59 Intel PCH 1D8V_S0
14.0" LCD SYW231 47
LVDS (2channel)
Panther Point INPUTS OUTPUTS
(16:9) 49
PCIE x 1
BGA989 Mini-Card 3D3V_S5 1D8V_S0
802.11 b/g/n Intel CPU_VCCSA

TPS51463 48
Camera HM76 USB2.0 x 1 BT V4.0 combo
USB2.0 x 1 65 INPUTS OUTPUTS
49 12 USB 2.0/1.1 ports
Digital MIC 5V_S5 0D85V_S0
4 USB 3.0 ports Left side Nvidia VGA_CORE
High Definition Audio USB3.0 x 2 ADP3211MNR2G 92
6 SATA ports USB3.0 Port x 2 INPUTS OUTPUTS
8 PCIE ports DCBATOUT VGA_CORE
USB2.0 x 2
HDA LPC I/F 61,62,63
MIC_IN/GND Switches 36 93
CODEC ACPI 4.0a
USB Board
HDA INPUTS OUTPUTS
HP_R/L Realtek Right side
58 1D5V_S3 1D5V_S0
B Combo Jack ALC3221 29 B
5V_S5 5V_S0
USB2.0 x 1 USB2.0 Port x 1 3D3V_S5 3D3V_S0
2CH SPEAKER
(2CH 2W/4ohm) VCCP_CPU 1D05V_VGA_S0
3D3V_S0 3D3V_VGA_S0
1D5V_S3 1D5V_VGA_S0
58
LPC debug port LPC BUS CardReader SD/SDHC/MS/MS Pro
USB2.0 x 1 Realtek
71
RTS5170
Slot
74
PCB LAYER
32
L1:Top L4:Signal
Thermal 17,18,19,20,21,22,23,24,25
L2:VCC L5:GND
NUVOTON SMBUS
L3:Signal L6:Bottom
NCT7718W 28 KBC
NUVOTON SPI SATA(Gen3) x 1 HDD
Fan Control NPCE885P 56
NUVOTON 27
NCT3940S-A 28
PS2 Flash ROM

Int. 8MB SATA(Gen1) x 1 ODD
60
FAN 28
A
KB 69 56 A
Touch PAD SMBUS

Profile/Image sensor M14 DIS
69
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Block Diagram
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C OAK14 Chief River DIS A00
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03-05-151:22:21 PM 3 2
Date: Wednesday, September 05, 2012
1
Sheet 2 of 105
A B C D E
PCH Strapping Chief River Schematic Checklist Revision 1.5
Name Schematics Notes Power Plane

Processor Strapping Chief River Schematic Checklist Revision 1.5
The signal has a weak internal pull-down. Configuration (Default value for each bit is Default Voltage Rails
Pin Name Strap Description POWER PLANE VOLTAGE DESCRIPTION
Note: the internal pull-down is disabled after PLTRST# deasserts. 1 unless specified otherwise) Value ACTIVE IN
SPKR
If the signal is sampled high, this indicates that the system is strapped to the 5V_S0 5V
No Reboot mode (Panther Point will disable the TCO Timer system reboot 3D3V_S0 3.3V
CFG[0] Connect a series 1 kOhms resistor on the critical CFG[0] 1D8V_S0 1.8V
feature). 1D5V_S0 1.5V
trace in a manner which does not introduce any stubs to 1D05V_VTT 1.05V
This signal has a weak internal pull-up.
INIT3_3V# CFG[0] trace. Route as needed from the opposite side of 0D85V_S0 0.95 - 0.85V
Note: The internal pull-up is disabled after PLTRST# deasserts. 0D75V_S0 0.75V
this series isolation resistor to the debug port. ITP
NOTE: This signal should not be pulled low. Leave as "No Connect".
4 INTVRMEN Integrated 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when high
will drive the net to GND.
VCC_CORE
VCC_GFXCORE
1D8V_VGA_S0
0.35V to 1.5V
0.4 to 1.25V
1.8V
S0
CPU Core Rail

4
CFG[2] PCIe Static x16 Lane 1: Normal Operation; Lane # definition 3D3V_VGA_S0 3.3V Graphics Core Rail
NOTE: This signal should always be pulled high 1V_VGA_S0 1V
Numbering Reversal. matches socket pin map definition 1
External 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when Low.
NOTE: This signal should be pulled down to GND through 330 kOhms resistor 0:Lane Reversed
5V_USBX_S3 5V
1:Disabled - No Physical Display Port attached to 1D5V_S3 1.5V S3
CFG[4] Display Port Presence DDR_VREF_S3 0.75V
Embedded DisplayPort No connect for disable
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. strap 0:Enabled - An external Display Port device is connected 1
GNT2#/GPIO53 Used as GPIO only. Pull-up resistors are not required on these signals. If pull-ups are used, they BT+ 6V-14.1V AC Brick Mode only
to the Embedded Display Port Pull-down to GND through a
GNT1#/GPIO51 should be tied to the Vcc3_3 power rail. DCBATOUT 6V-14.1V
1K 5% resistor to enable port 5V_S5 5V All S states
5V_AUX_S5 5V
This signal is a strap for selecting DMI and FDI termination voltage. 3D3V_S5 3.3V
PCIE Port Bifurcation 00 = 1 x 8, 2 x 4 PCI Express 3D3V_AUX_S5 3.3V
For Ivy Bridge processor only implementation:
CFG[6:5] Straps 01 = reserved
DF_TVS DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms 5% resistor. 3D3V_LAN_S5 3.3V WOL_EN Legacy WOL
For future processor compatibility: 10 = 2 x 8 PCI Express 1
It needs to be connected to PROC_SELECT through a 11 = 1 x 16 PCI Express
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1.0 kOhms 5% series resistor. The PROC_SELECT signal would need a 2.2 kOhms 5% pull-up resistor 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states
to
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PCH VccDFTERM. Reserved configuration
CFG[17:7] lands. A test point may
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Bit11 Bit 10 Boot BIOS Destination Powered by Li Coin Cell in G3
be placed on the board 3D3V_AUX_S5 3.3V G3, Sx and +V3ALW in Sx
0 1 Reserved
.ro
1 0 PCI for these lands.
SATA1GP/ 1 1 SPI
GPIO19 0 0 LPC
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NOTE: If option 00 LPC is selected BIOS may still be placed on LPC, but all platforms with Panther
Point require SPI flash connected directly to the Panther Point's SPI bus with a valid descriptor
fix
in order to boot.
NOTE: Booting to PCI is intended for debut/testing only. Boot BIOS
Destination Select to LPC/PCI by functional strap or via Boot BIOS
.c
Destination Bit will not affect SPI accesses initiated by Management
3 Engine or Integrated GbE LAN.
3
om
NOTE: PCI Boot BIOS destination is not supported on mobile.
Reserved.
SATA2GP/
GPIO36
This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after PLTRST# deasserts.
Sandy Bridge + Ivy Bridge Compatibility Requirements
Chief River Schematic Checklist Revision 1.5
PCIE Routing USB Table
NOTE: This signal should not be pulled high when strap is sampled.
Pair Device
Reserved Pin Name Configuration Schematic Notes LANE1 X
SATA3GP/ This signal has a weak internal pull-down. 0 USB3.0 port1
GPIO37 NOTE: The internal pull-down is disabled after PLTRST# deasserts. DDR3 VREF M1 and M3 Guidelines are required. LANE2 X 1 USB3.0 port2, with Debug Port
NOTE: This signal should not be pulled high when strap is sampled. DDR3 VREF Note: The M3 traces are routed to the Sandy Bridge Processor
Sandy Bridge + Ivy Bridge 2 USB2.0 port3
HDA_DOCK_EN# High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking reserved pins.
/GPIO33 isolation logic. This is an active-low-signal. When deasserted the external docking switch is in
LANE3 Mini Card1(WLAN) 3 X
isolate mode. When asserted the external docking switch electrically connects the IntelR HD Audio Ivy Bridge No change. 4 X
dock signals to the corresponding Panther Point signals. This signal can instead be used as GPIO33. LANE4 x
5 Touch Panel
Signal has a weak internal pull-down. LANE5 X
If strap is sampled low, the security measures defined in the Flash Descriptor will be in effect Connect DF_TVS signal of the PCH to PROC_SELECT# of the 6 HM76 NC
HDA_SDO Sandy Bridge + Ivy Bridge processor through a 1K5% series resistor. PROC_SELECT#
(default).If sampled high, the Flash Descriptor Security will be overridden. PROC_SELECT#
also needs a 2.2K5% pull up resistor to PCH VccDFTERM LANE6 Onboard LAN 7 HM76 NC
This strap should only be asserted high via external pull-up in manufacturing/debug environments &
ONLY. rail. 8 X
DF_TVS
Note: The weak internal pull-down is disabled after PLTRST# deasserts. Ivy Bridge No change. LANE7 X 9 X
Asserting the HDA_SDO high on the rising edge of PWROK will also halt Intel Management Engine
after chipset bring up and disable runtime Intel Management Engine features. This is a debug mode LANE8 X 10 CARD READER
and must not be asserted after manufacturing/ debug.This signal has a 20k internal pull down The POR for Ivy Bridge mobile parts is now 1.05 V. There is no 11 Mini Card (WLAN)
resistor. Sandy Bridge + Ivy Bridge longer a requirement for a separate VCCIO VR for Sandy Bridge
This signal has a weak internal pull-down. VCCIO VR 12 X
+ Ivy Bridge compatibility.
On Die PLL VR is supplied by 1.5 V from VCCVRM when sampled high, 1.8 V from VCCVRM when sampled Implementation
HDA_SYNC 13 CAMERA
low.
Needs to be pulled High for Chief River platform. Ivy Bridge No change.
Note: HDA_SYNC signal also serves as a strap for selecting VRM voltage to the PCH. The strap is
2 sampled on the rising edge of RSMRST# signal. Due to potential leakage on the codec (path to GND),
the strap may not be able to achieve the Vihmin at PCH input.Therefore, platform may need to Sandy Bridge + Ivy Bridge VCCSA_SELECT[0:1] which should be connected to SATA Table 2
isolate this signal from the codec during the strap phase. Refer to the example circuits provided in VCCSA_SEL VID[1:0] of the System Agent (SA) VR controller.
the latest Chief River platform design guide. connection to
VCCSA_VID[1:0] SATA
TLS Confidentiality
GPIO15 Low (0) Intel ME Crypto Transport Layer Security (TLS) cipher suite with no lines Ivy Bridge No change. Pair Device
confidentiality
High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality 0 HDD1
NOTE:The weak internal pull-down is disabled after RSMRST# deasserts. 1 X
Sandy Bridge + Ivy Bridge The total motherboard length for a pair of consecutive PCI
NOTE: A strong pull-up may be needed for GPIO functionality Layout Requirement Express Tx lanes be length matched within 100 mils (2.54 mm) 2 X
on PCI Express
LVDS Detected. 3 X
Gen3 Ivy Bridge No change.
When '1'- LVDS is detected; When '0'- LVDS is not detected.
L_DDC_DATA 4 ODD1
NOTE:The internal pull-down is disabled after PLTRST# deasserts. 5 X
GT Core VR Sandy Bridge + Ivy Bridge Depending on the PDDG specifications, some IVB GT2 SKUs may
Implementation require a new VR controller and 2 phase VCC GT core VR.
Port B Detected
When '1'- Port B is detected; When '0'- Port B is not detected
SDVO_CTRLDATA Ivy Bridge No change.
NOTE:The internal pull-down is disabled after PLTRST# deasserts.
Processor PCI Sandy Bridge + Ivy Bridge To support Gen 3 PCI Express Graphic, the value of the AC
Port C Detected. Express (PCIe Gen3): coupling capacitor should be 180 - 265 nF.
When '1'- Port C is detected; When '0'- Port C is not detected Graphics
DDPC_CTRLDATA
This signal has a weak internal pull-down. Guidelines Ivy Bridge No change.
Port D Detected.
When '1'- Port D is detected; When '0'- Port D is not detected
DDPD_CTRLDATA
The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL
1 GPIO28 Voltage Regulator is disabled.If not used, 8.2-k to 10-k pull-up to +V3.3A power-rail.
GPIO28 signal also needs to be pulled up to 3.3V_SUS with 4.7K resistor to ensure proper strap
1
setting when use as the chipset test interface.Refer to the latest platform debug design guide and
platform design guide for more details.
NOTE:This signal has a weak internal pull-up. The internal pull-up is disabled after RSMRST# M14 DIS
deasserts.
Wistron Corporation
GPIO29 is multiplexed with SLP_LAN#. If Intel LAN is implemented on the platform, 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SLP_LAN# must be used to control the power to the PHY LAN (no other implementation is supported). Taipei Hsien 221, Taiwan, R.O.C.
GPIO29/
If integrated Intel LAN is not supported on the platform, GPIO29 can be used as a normal GPIO. Title
SLP_LAN#
A soft strap determines the functionality of GPIO29, either as SLP_LAN# or GPIO. By default,
the soft strap enables SLP_LAN# functionality on the pin. If the soft trap is changed to enable Table of Content
GPIO functionality, then SLP_LAN# functionality is no longer available, and the signal can
http://vinafix.vn
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be used as a normal GPIO (default to GPI).
Wednesday, September 05, 2012
03-05-151:22:21 PM
Date: Sheet 3 of 105
A B C D E
5 4 3 2 1
SSID = CPU
Layout Note:
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
D D
VCCP_CPU
CPU1A 1 OF 9
G3 PEG_IRCOMP_R R401 1 2 24D9R2F-L-GP
PEG_ICOMPI
19 DMI_CPU_RXN_PCH_TXN[3:0] PEG_ICOMPO G1
DMI_CPU_RXN_PCH_TXN0 M2 G4
DMI_CPU_RXN_PCH_TXN1 DMI_RX#0 PEG_RCOMPO
P6 DMI_RX#1
DMI_CPU_RXN_PCH_TXN2 P1
DMI_CPU_RXN_PCH_TXN3 DMI_RX#2
P10 DMI_RX#3 PEG_RX#0 H22
Layout Note: 19 DMI_CPU_RXP_PCH_TXP[3:0]
DMI_CPU_RXP_PCH_TXP0 N3
PEG_RX#1 J21
B22
DMI_RX0 PEG_RX#2
DMI trace length 2000~8000mil DMI_CPU_RXP_PCH_TXP1 P7 DMI_RX1 PEG_RX#3 D21
DMI
DMI_CPU_RXP_PCH_TXP2 P3 A19
DMI_CPU_RXP_PCH_TXP3 DMI_RX2 PEG_RX#4
P11 DMI_RX3 PEG_RX#5 D17
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19 DMI_CPU_TXN_PCH_RXN[3:0] PEG_RX#6 B14
DMI_CPU_TXN_PCH_RXN0 K1 D13
DMI_TX#0 PEG_RX#7
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DMI_CPU_TXN_PCH_RXN1 M8 A11 CPU_RXN_C_dGPU_TXN7
DMI_CPU_TXN_PCH_RXN2 DMI_TX#1 PEG_RX#8 CPU_RXN_C_dGPU_TXN6
N4 B10
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DMI_CPU_TXN_PCH_RXN3 DMI_TX#2 PEG_RX#9 CPU_RXN_C_dGPU_TXN5
R2 DMI_TX#3 PEG_RX#10 G8
.ro
A8 CPU_RXN_C_dGPU_TXN4
19 DMI_CPU_TXP_PCH_RXP[3:0] DMI_CPU_TXP_PCH_RXP0 PEG_RX#11 CPU_RXN_C_dGPU_TXN3
K3 DMI_TX0 PEG_RX#12 B6
DMI_CPU_TXP_PCH_RXP1 M7 H8 CPU_RXN_C_dGPU_TXN2
se
DMI_CPU_TXP_PCH_RXP2 DMI_TX1 PEG_RX#13 CPU_RXN_C_dGPU_TXN1
P4 DMI_TX2 PEG_RX#14 E5 CPU_RXN_C_dGPU_TXN[7..0] 83
DMI_CPU_TXP_PCH_RXP3 T3 K7 CPU_RXN_C_dGPU_TXN0
DMI_TX3 PEG_RX#15
fix
PEG_RX0 K22
.c
PEG_RX1 K19 CPU_RXP_C_dGPU_TXP[7..0] 83
19 FDI_CPU_TXN_PCH_RXN[7:0] PEG_RX2 C21
om
C FDI_CPU_TXN_PCH_RXN0
FDI_CPU_TXN_PCH_RXN1
U7
W11
FDI0_TX#0 PEG_RX3 D19
C19
C
FDI_CPU_TXN_PCH_RXN2 FDI0_TX#1 PEG_RX4
W1 FDI0_TX#2 PEG_RX5 D16
FDI_CPU_TXN_PCH_RXN3 AA6 C13
FDI_CPU_TXN_PCH_RXN4 FDI0_TX#3 PEG_RX6
Layout Note: FDI_CPU_TXN_PCH_RXN5
W6
V4
FDI1_TX#0 PEG_RX7 D12
C11 CPU_RXP_C_dGPU_TXP7 dGPU_RXN_C_CPU_TXN[8..15] 83
FDI1_TX#1 PEG_RX8
FDI trace length 2000~6500mil FDI_CPU_TXN_PCH_RXN6 CPU_RXP_C_dGPU_TXP6
PCI EXPRESS -- GRAPHICS

Y2 FDI1_TX#2 PEG_RX9 C9
FDI_CPU_TXN_PCH_RXN7 AC9 F8 CPU_RXP_C_dGPU_TXP5
FDI1_TX#3 PEG_RX10
Intel(R) FDI
C8 CPU_RXP_C_dGPU_TXP4
PEG_RX11 CPU_RXP_C_dGPU_TXP3 dGPU_RXP_C_CPU_TXP[8..15] 83
19 FDI_CPU_TXP_PCH_RXP[7:0] PEG_RX12 C5
FDI_CPU_TXP_PCH_RXP0 U6 H6 CPU_RXP_C_dGPU_TXP2
FDI_CPU_TXP_PCH_RXP1 FDI0_TX0 PEG_RX13 CPU_RXP_C_dGPU_TXP1
W10 FDI0_TX1 PEG_RX14 F6
FDI_CPU_TXP_PCH_RXP2 W3 K6 CPU_RXP_C_dGPU_TXP0
FDI_CPU_TXP_PCH_RXP3 FDI0_TX2 PEG_RX15
AA7 FDI0_TX3
FDI_CPU_TXP_PCH_RXP4 W7 G22
FDI_CPU_TXP_PCH_RXP5 FDI1_TX0 PEG_TX#0
T4 FDI1_TX1 PEG_TX#1 C23
FDI_CPU_TXP_PCH_RXP6 AA3 D23
FDI_CPU_TXP_PCH_RXP7 FDI1_TX2 PEG_TX#2
AC8 FDI1_TX3 PEG_TX#3 F21
PEG_TX#4 H19
FDI_FSYNC0 AA11 C17
19 FDI_FSYNC0 FDI0_FSYNC PEG_TX#5
FDI_FSYNC1 AC12 K15
19 FDI_FSYNC1 FDI1_FSYNC PEG_TX#6
PEG_TX#7 F17
19 FDI_INT
FDI_INT U11 FDI_INT PEG_TX#8 F14 CPU_TXN_dGPU_RXN7 1OPS 2 C401 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN8
PEG_TX#9 A15 CPU_TXN_dGPU_RXN6 1OPS 2 C402 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN9
19 FDI_LSYNC0
FDI_LSYNC0 AA10
FDI0_LSYNC PEG_TX#10 J14 CPU_TXN_dGPU_RXN5 1OPS 2 C403 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN10
19 FDI_LSYNC1
FDI_LSYNC1 AG8
FDI1_LSYNC PEG_TX#11 H13 CPU_TXN_dGPU_RXN4 1OPS 2 C404 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN11
PEG_TX#12 M10 CPU_TXN_dGPU_RXN3 1OPS 2 C405 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN12
PEG_TX#13 F10 CPU_TXN_dGPU_RXN2 1OPS 2 C406 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN13
PEG_TX#14 D9 CPU_TXN_dGPU_RXN1 1OPS 2 C407 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN14
J4 CPU_TXN_dGPU_RXN0 1OPS 2 C408 SCD22U10V2KX-1GP dGPU_RXN_C_CPU_TXN15
B VCCP_CPU R402 1 2 24D9R2F-L-GP DP_COMP AF3 EDP_COMPIO
PEG_TX#15 B
AD2 EDP_ICOMPO PEG_TX0 F22
AG11 EDP_HPD# PEG_TX1 A23
PEG_TX2 D24
PEG_TX3 E21
Layout Note: AG4
AF4
EDP_AUX# PEG_TX4 G19
B18
EDP_AUX PEG_TX5
Signal Routing Guideline: PEG_TX6 K17
eDP
EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_TX7 G17
AC3 E14 CPU_TXP_dGPU_RXP7 1OPS 2 C409 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP8
EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils. AC4
EDP_TX#0 PEG_TX8
C15 CPU_TXP_dGPU_RXP6 1OPS 2 C410 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP9
EDP_TX#1 PEG_TX9
AE11 EDP_TX#2 PEG_TX10 K13 CPU_TXP_dGPU_RXP5 1OPS 2 C411 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP10
AE7 EDP_TX#3 PEG_TX11 G13 CPU_TXP_dGPU_RXP4 1OPS 2 C412 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP11
PEG_TX12 K10 CPU_TXP_dGPU_RXP3 1OPS 2 C413 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP12
AC1 EDP_TX0 PEG_TX13 G10 CPU_TXP_dGPU_RXP2 1OPS 2 C414 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP13
AA4 EDP_TX1 PEG_TX14 D8 CPU_TXP_dGPU_RXP1 1OPS 2 C415 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP14
AE10 EDP_TX2 PEG_TX15 K4 CPU_TXP_dGPU_RXP0 1OPS 2 C416 SCD22U10V2KX-1GP dGPU_RXP_C_CPU_TXP15
AE6 EDP_TX3
Note:
IVY-BRIDGE-GP-NF PEG with reversal type.
71.00IVY.A0U
A M14 DIS
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
CPU(PCIE/DMI/FDI)
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03-05-1512:40:57 PM
A3 A00
OAK14 Chief River DIS
03-05-151:22:21 PM Date: W ednesday, September 05, 2012 Sheet 4 of 105
5 4 3 2 1
SSID = CPU
D CPU1B 2 OF 9
D
J3 CLK_EXP_P CLK_EXP_P 20
BCLK CLK_EXP_N
BCLK# H2 CLK_EXP_N 20
MISC
CLOCKS
22 H_SNB_IVB# H_SNB_IVB# F49 RN503
PROC_SELECT# CLK_DP_P_R1
DPLL_REF_CLK AG3 4
CLK_DP_N_R2
TPAD14-OP-GP TP501 1 SKTOCC#_R C57
DPLL_REF_CLK# AG1 3 VCCP_CPU Layout Note:
PROC_DETECT# SRN1KJ-7-GP Checking the connector pin's LAYOUT
VCCP_CPU
TPAD14-OP-GP TP502 1 H_CATERR# C49 R507
R501 CATERR# 4K99R2F-L-GP
THERMAL
w
1 2 H_PROCHOT# 1 2
w
62R2J-GP H_PECI A48 AT30 SM_DRAMRST# SM_DRAMRST# 37
22,27 H_PECI PECI SM_DRAMRST#
w
.ro
R513 BF44 SM_RCOMP_0 R506 1 2 140R2F-GP
SM_RCOMP0
DDR3
MISC
1 2 H_PROCHOT#_R C45 BE43 SM_RCOMP_1 R508 1 2 25D5R2F-GP
27,38,40,42 H_PROCHOT# PROCHOT# SM_RCOMP1
BG43 SM_RCOMP_2 R511 1 2 200R2F-L-GP
se
56R2J-4-GP SM_RCOMP2
fix
H_THERMTRIP#
22 H_THERMTRIP# D45 THERMTRIP# Layout Note:
Signal Routing Guideline:
.c
Layout Note: N53 XDP_PRDY# XDP_PRDY# 71 SM_RCOMP keep routing length less than 500 mils.
PRDY#
om
C R501, R513 place near to CPU PREQ# N55 XDP_PREQ# XDP_PREQ# 71 Trace width = 15mil C
L56 XDP_TCLK
TCK XDP_TMS VCCP_CPU
TMS L55
PWR MANAGEMENT
J58 XDP_TRST#
TRST#
JTAG & BPM

19 H_PM_SYNC H_PM_SYNC C48 M60 XDP_TDI
PM_SYNC TDI XDP_TDO RN501
TDO L59
R504 XDP_TDI 1 8
0R0402-PAD XDP_TMS 2 7
1 2 H_CPUPW RGD_R B46 XDP_TDO 3 6
22 H_CPUPW RGD UNCOREPWRGOOD
K58 XDP_DBRESET# XDP_DBRESET# 19 4
XDP 5
DBR#
1 R503 2
10KR2J-3-GP SRN51J-1-GP
37 VDDPW RGOOD VDDPW RGOOD BE45 G58 XDP_BPM0 XDP_BPM0 71
SM_DRAMPWROK BPM#0 XDP_BPM1 RN502
BPM#1 E55 XDP_BPM1 71
E59 XDP_BPM2 XDP_BPM2 71 XDP_TRST# 1 4
BPM#2 XDP_BPM3 XDP_TCLK
G55 2 3
BPM#3
G59 XDP_BPM4
XDP_BPM3
XDP_BPM4
71
71
XDP
BUF_CPU_RST# BPM#4 XDP_BPM5 SRN51J-GP
18,27,31,65,71,83 PLT_RST# 1 2 D44 RESET# BPM#5 H60 XDP_BPM5 71
J59 XDP_BPM6 XDP_BPM6 71
BPM#6
1
R510 J61 XDP_BPM7 XDP_BPM7 71

BPM#7
1
1K5R2F-2-GP
R509 C501
698R2F-GP DY SC220P50V2KX-3GP
2
2
IVY-BRIDGE-GP-NF
71.00IVY.A0U
B Layout Note:
B
C501 place near to CPU
H_CPUPW RGD PLT_RST# XDP_DBRESET#

1
EC501 EC502 EC503

SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
DY DY DY
2
reserve for EMI Request
A M14 DIS
A
Wistron Corporation
Title
CPU(THERMAL/CLOCK/PM)
http://vinafix.vn
03-05-1512:40:57 PM
A3 A00
5 4 3 2 1
SSID = CPU
CPU1D 4 OF 9
CPU1C 3 OF 9
M_B_DQ[63:0]
M_A_DQ[63:0] 15 M_B_DQ[63:0]
M_B_DQ0 AL4
14 M_A_DQ[63:0] SB_DQ0
D M_A_DQ0 AG6 M_B_DQ1 AL1 BA34 D
M_A_DQ1 SA_DQ0 M_B_DQ2 SB_DQ1 SB_CK0 M_B_DIMB_CLK_DDR0 15
AJ6 SA_DQ1 SA_CK0 AU36 M_A_DIMA_CLK_DDR0 14 AN3 SB_DQ2 SB_CK#0 AY34 M_B_DIMB_CLK_DDR#0 15
M_A_DQ2 AP11 AV36 M_B_DQ3 AR4 AR22
M_A_DQ3 SA_DQ2 SA_CK#0 M_A_DIMA_CLK_DDR#0 14 M_B_DQ4 SB_DQ3 SB_CKE0 M_B_DIMB_CKE0 15
AL6 SA_DQ3 SA_CKE0 AY26 M_A_DIMA_CKE0 14 AK4 SB_DQ4
M_A_DQ4 AJ10 M_B_DQ5 AK3
M_A_DQ5 SA_DQ4 M_B_DQ6 SB_DQ5
AJ8 SA_DQ5 AN4 SB_DQ6
M_A_DQ6 AL8 M_B_DQ7 AR1
AL7 SA_DQ7 AU4 SB_DQ8
M_A_DQ8 AR11 M_B_DQ9 AT2 BA36
M_A_DQ9 SA_DQ8 M_B_DQ10 SB_DQ9 SB_CK1 M_B_DIMB_CLK_DDR1 15
AP6 SA_DQ9 SA_CK1 AT40 M_A_DIMA_CLK_DDR1 14 AV4 SB_DQ10 SB_CK#1 BB36 M_B_DIMB_CLK_DDR#1 15
M_A_DQ10 AU6 AU40 M_B_DQ11 BA4 BF27
M_A_DQ11 SA_DQ10 SA_CK#1 M_A_DIMA_CLK_DDR#1 14 M_B_DQ12 SB_DQ11 SB_CKE1 M_B_DIMB_CKE1 15
AV9 SA_DQ11 SA_CKE1 BB26 M_A_DIMA_CKE1 14 AU3 SB_DQ12
M_A_DQ12 AR6 M_B_DQ13 AR3
AP8 SA_DQ13 AY2 SB_DQ14
M_A_DQ14 AT13 M_B_DQ15 BA3
SA_DQ14 SB_DQ15
w
M_A_DQ15 AU13 M_B_DQ16 BE9
BC7 SA_DQ16 BD9 SB_DQ17 SB_CS#0 BE41
w
M_A_DQ17 M_B_DQ18 M_B_DIMB_CS#0 15
BB7 SA_DQ17 SA_CS#0 BB40 M_A_DIMA_CS#0 14 BD13 SB_DQ18 SB_CS#1 BE47 M_B_DIMB_CS#1 15
M_A_DQ18 BA13 BC41 M_B_DQ19 BF12
w
M_A_DQ19 SA_DQ18 SA_CS#1 M_A_DIMA_CS#1 14 M_B_DQ20 SB_DQ19
BB11 SA_DQ19 BF8 SB_DQ20
.ro
M_A_DQ20 BA7 M_B_DQ21 BD10
BA9 SA_DQ21 BD14 SB_DQ22
M_A_DQ22 BB9 M_B_DQ23 BE13
se
AY13 SA_DQ23 BF16 SB_DQ24 SB_ODT0 AT43 M_B_DIMB_ODT0 15
M_A_DQ24 AV14 AY40 M_B_DQ25 BE17 BG47
SA_DQ24 SA_ODT0 M_A_DIMA_ODT0 14 SB_DQ25 SB_ODT1 M_B_DIMB_ODT1 15
fix
M_A_DQ25 AR14 BA41 M_B_DQ26 BE18
M_A_DQ26 SA_DQ25 SA_ODT1 M_A_DIMA_ODT1 14 M_B_DQ27 SB_DQ26
AY17 SA_DQ26 BE21 SB_DQ27
M_A_DQ27 M_B_DQ28
.c
AR19 SA_DQ27 BE14 SB_DQ28
M_A_DQ28 BA14 M_B_DQ29 BG14
SA_DQ28 SB_DQ29
om
C M_A_DQ29 AU14 M_B_DQ30 BG18 M_B_DQS#[7:0] 15
C
M_A_DQ30 SA_DQ29 M_B_DQ31 SB_DQ30 M_B_DQS#0
BB14 SA_DQ30 M_A_DQS#[7:0] 14 BF19 SB_DQ31 SB_DQS#0 AL3
M_A_DQ31 BB17 AL11 M_A_DQS#0 M_B_DQ32 BD50 AV3 M_B_DQS#1
M_A_DQ32 SA_DQ31 SA_DQS#0 M_A_DQS#1 M_B_DQ33 SB_DQ32 SB_DQS#1 M_B_DQS#2
BA45 SA_DQ32 SA_DQS#1 AR8 BF48 SB_DQ33 SB_DQS#2 BG11
M_A_DQ33 AR43 AV11 M_A_DQS#2 M_B_DQ34 BD53 BD17 M_B_DQS#3
AW48 SA_DQ34 SA_DQS#3 AT17 BF52 SB_DQ35 SB_DQS#4 BG51
M_A_DQ35 BC48 AV45 M_A_DQS#4 M_B_DQ36 BD49 BA59 M_B_DQS#5
BC45 SA_DQ36 SA_DQS#5 AY51 BE49 SB_DQ37 SB_DQS#6 AT60
DDR SYSTEM MEMORY B

M_A_DQ37 AR45 AT55 M_A_DQS#6 M_B_DQ38 BD54 AK59 M_B_DQS#7
SA_DQ37 SA_DQS#6 SB_DQ38 SB_DQS#7
DDR SYSTEM MEMORY A
M_A_DQ38 AT48 AK55 M_A_DQS#7 M_B_DQ39 BE53

M_A_DQ39 SA_DQ38 SA_DQS#7 M_B_DQ40 SB_DQ39
AY48 SA_DQ39 BF56 SB_DQ40
M_A_DQ40 BA49 M_B_DQ41 BE57
AV49 SA_DQ41 BC59 SB_DQ42
M_A_DQ42 BB51 M_B_DQ43 AY60
AY53 SA_DQ43 BE54 SB_DQ44
M_A_DQ44 BB49 M_A_DQS[7:0] 14 M_B_DQ45 BG54 M_B_DQS[7:0] 15
M_A_DQ45 SA_DQ44 M_A_DQS0 M_B_DQ46 SB_DQ45 M_B_DQS0
AU49 SA_DQ45 SA_DQS0 AJ11 BA58 SB_DQ46 SB_DQS0 AM2
M_A_DQ46 BA53 AR10 M_A_DQS1 M_B_DQ47 AW59 AV1 M_B_DQS1
M_A_DQ47 SA_DQ46 SA_DQS1 M_A_DQS2 M_B_DQ48 SB_DQ47 SB_DQS1 M_B_DQS2
BB55 SA_DQ47 SA_DQS2 AY11 AW58 SB_DQ48 SB_DQS2 BE11
M_A_DQ48 BA55 AU17 M_A_DQS3 M_B_DQ49 AU58 BD18 M_B_DQS3
AV56 SA_DQ49 SA_DQS4 AW45 AN61 SB_DQ50 SB_DQS4 BE51
M_A_DQ50 AP50 AV51 M_A_DQS5 M_B_DQ51 AN59 BA61 M_B_DQS5
AP53 SA_DQ51 SA_DQS6 AT56 AU59 SB_DQ52 SB_DQS6 AR59
M_A_DQ52 AV54 AK54 M_A_DQS7 M_B_DQ53 AU61 AK61 M_B_DQS7
M_A_DQ53 SA_DQ52 SA_DQS7 M_B_DQ54 SB_DQ53 SB_DQS7
AT54 SA_DQ53 AN58 SB_DQ54
M_A_DQ54 AP56 M_B_DQ55 AR58
AP52 SA_DQ55 AK58 SB_DQ56
M_A_DQ56 AN57 M_B_DQ57 AL58
AN53 SA_DQ57 AG58 SB_DQ58
B M_A_DQ58 M_B_DQ59 B
AG56 SA_DQ58 AG59 SB_DQ59
M_A_DQ59 AG53 M_B_DQ60 AM60
M_A_DQ60 SA_DQ59 M_B_DQ61 SB_DQ60 M_B_A0 M_B_A[15:0] 15
AN55 SA_DQ60 M_A_A[15:0] 14 AL59 SB_DQ61 SB_MA0 BF32
M_A_DQ61 AN52 BG35 M_A_A0 M_B_DQ62 AF61 BE33 M_B_A1
M_A_DQ62 SA_DQ61 SA_MA0 M_A_A1 M_B_DQ63 SB_DQ62 SB_MA1 M_B_A2
AG55 SA_DQ62 SA_MA1 BB34 AH60 SB_DQ63 SB_MA2 BD33
M_A_DQ63 AK56 BE35 M_A_A2 AU30 M_B_A3
SA_DQ63 SA_MA2 M_A_A3 SB_MA3 M_B_A4
SA_MA3 BD35 SB_MA4 BD30
AT34 M_A_A4 AV30 M_B_A5
SA_MA4 M_A_A5 SB_MA5 M_B_A6
SA_MA5 AU34 SB_MA6 BG30
BB32 M_A_A6 15 M_B_BS0 BG39 BD29 M_B_A7
SA_MA6 M_A_A7 SB_BS0 SB_MA7 M_B_A8
14 M_A_BS0 BD37 SA_BS0 SA_MA7 AT32 15 M_B_BS1 BD42 SB_BS1 SB_MA8 BE30
14 M_A_BS1 BF36 AY32 M_A_A8 15 M_B_BS2 AT22 BE28 M_B_A9
SA_BS1 SA_MA8 M_A_A9 SB_BS2 SB_MA9 M_B_A10
14 M_A_BS2 BA28 SA_BS2 SA_MA9 AV32 SB_MA10 BD43
BE37 M_A_A10 AT28 M_B_A11
SA_MA10 M_A_A11 SB_MA11 M_B_A12
SA_MA11 BA30 SB_MA12 AV28
BC30 M_A_A12 15 M_B_CAS# AV43 BD46 M_B_A13
SA_MA12 M_A_A13 SB_CAS# SB_MA13 M_B_A14
14 M_A_CAS# BE39 SA_CAS# SA_MA13 AW41 15 M_B_RAS# BF40 SB_RAS# SB_MA14 AT26
14 M_A_RAS# BD39 AY28 M_A_A14 15 M_B_W E# BD45 AU22 M_B_A15
SA_RAS# SA_MA14 M_A_A15 SB_WE# SB_MA15
14 M_A_W E# AT41 SA_WE# SA_MA15 AU26
IVY-BRIDGE-GP-NF
IVY-BRIDGE-GP-NF 71.00IVY.A0U
71.00IVY.A0U
A M14 DIS A
Wistron Corporation
Title
CPU (DDR)
A3 A00
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
6 of 105
5 4 3 2 1
SSID = CPU
CFG2
CPU1E 5 OF 9
D D
1
PEG Static Lane Reversal
R702
1KR2J-1-GP 1: Normal Operation; Lane #
71 CFG0 CFG0 B50 N59 BCLK_ITP 1 TP721 OPS CFG[2] definition matches socket pin map definition
TP701 CFG1 CFG0 BCLK_ITP BCLK_ITP# TP722
1 C51 N58 1
2
CFG1 BCLK_ITP#
CFG2 B54 0:Lane Reversed
TP702 CFG3 CFG2
1 D53 CFG3
TP703 1 CFG4 A51 N42
CFG5 CFG4 RSVD30
C53 CFG5 RSVD31 L42
CFG6 C55 L45
CFG6 RSVD32
H49 CFG7 RSVD33 L47
A55 CFG8
H51 CFG9
K49 CFG10 RSVD34 M13
w
K53 CFG11 RSVD35 M14 Display Port Presence Strap
F53 CFG12 RSVD36 U14
w
G53 W14 1: Disabled; No Physical Display Port
CFG13 RSVD37
L51 P13 CFG[4] attached to Embedded Display Port
w
CFG14 RSVD38
F51 CFG15
.ro
D52 0: Enabled; An external Display Port device is
CFG16
L53 CFG17 RSVD39 AT49 connected to the Embedded Display Port
K24
se
RSVD40
H43
RESERVED
VCC_VAL_SENSE
fix
K43 VSS_VAL_SENSE RSVD41 AH2
RSVD42 AG13
.c
RSVD43 AM14
H45 VAXG_VAL_SENSE RSVD44 AM15
om
C K45 CFG5 C
VSSAXG_VAL_SENSE
RSVD45 N50 CFG6 PCIE Port Bifurcation Straps

TP719 1VCC_DIE_SENSE F48 VCC_DIE_SENSE
1
G48 RSVD47 R701 R704 CFG[6:5] 11: 1x16 PCI Express
H48
K48
RSVD6 DY 1KR2J-1-GP OPS 1KR2J-1-GP 10: 2 x8 - PCI Express
RSVD7
A4
2
DC_TEST_A4
DC_TEST_C4 C4 01: Reserved
BA19 D3 DC_TEST_C4_D3
RSVD8 DC_TEST_D3
AV19 RSVD9 DC_TEST_D1 D1 00: 1x8, 2x4 PCI Express
AT21 RSVD10 DC_TEST_A58 A58
BB21 RSVD11 DC_TEST_A59 A59
BB19 C59 TP_DC_TEST_A59_C59
RSVD12 DC_TEST_C59
AY21 RSVD13 DC_TEST_A61 A61
BA22 C61 TP_DC_TEST_A61_C61
RSVD14 DC_TEST_C61
AY22 RSVD15 DC_TEST_D61 D61
AU19 RSVD16 DC_TEST_BD61 BD61
AU21 RSVD17 DC_TEST_BE61 BE61
BD21 RSVD18 DC_TEST_BE59 BE59 TP_DC_TEST_BE59_BE61
BD22 RSVD19 DC_TEST_BG61 BG61
BD25 RSVD20 DC_TEST_BG59 BG59 DC_TEST_BG59_BG61
BD26 RSVD21 DC_TEST_BG58 BG58
BG22 RSVD22 DC_TEST_BG4 BG4
BE22 RSVD23 DC_TEST_BG3 BG3
BG26 BE3 DC_TEST_BE3_BG3
RSVD24 DC_TEST_BE3
BE26 RSVD25 DC_TEST_BG1 BG1
BF23 BE1 DC_TEST_BE1_BG1
B RSVD26 DC_TEST_BE1 B
BE24 RSVD27 DC_TEST_BD1 BD1
IVY-BRIDGE-GP-NF
71.00IVY.A0U
M14 DIS
A A
Wistron Corporation
Title
CPU (RESERVED)
A3 A00
http://vinafix.vn
03-05-1512:40:57 PM
Date: W ednesday, September 05, 2012 Sheet 7 of 105
5 4 03-05-151:22:21 PM 3 2 1
5 4 3 2 1
SSID = CPU
VCC_CORE
CPU1F POWER 6 OF 9
VCCP_CPU
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1
VCC_CORE
VCCIO1
AF46 8.5A
1
C801
C803
C804
C805
C806
C807
C808
C809
C810
C811
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
AG48
ULV 33A VCCIO3
VCCIO4
AG50
A26 AG51
2
2
VCC1 VCCIO5
1
C830
C831
C832
C833
C835
C834
C836
C838
A29 AJ17
VCC2 VCCIO6
A31 AJ21
VCC3 VCCIO7
A34 AJ25 DY
2
VCC4 VCCIO8
A35 AJ43
VCC5 VCCIO9
D A38 AJ47 D
VCC6 VCCIO10
A39 AK50
VCC7 VCCIO11
A42 AK51
VCC8 VCCIO12
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C26 AL14
VCC9 VCCIO13
C27 AL15
1
VCC10 VCCIO14
C812
C813
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C32 AL16
VCC11 VCCIO15
C34 AL20
VCC12 VCCIO16
C37 AL22
2
VCC13 VCCIO17
1
C843
C845
C844
C837
C840
C839
C841
C842
C39 AL26
VCC14 VCCIO18
C42 AL45
VCC15 VCCIO19
D27 AL48 DY DY DY DY
2
VCC16 VCCIO20
D32 AM16
VCC17 VCCIO21
D34 AM17
VCC18 VCCIO22
D37 AM21
VCC19 VCCIO23
D39 AM43
PEG IO AND DDR IO

VCC20 VCCIO24
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
SC4D7U6D3V3KX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP
D42 AM47
VCC21 VCCIO25
E26 AN20
VCC22 VCCIO26
E28 AN42
VCC23 VCCIO27
1
1
C814
C815
C816
C817
C819
C818
C820
C821
C822
C823
C894
C896
C892
C888
C884
E32 AN45
VCC24 VCCIO28
E34 AN48
VCC25 VCCIO29
DY DY E37 DY
2
2
VCC26
E38
VCC27
w CORE SUPPLY
F25
VCC28
F26
VCC29 VCCP_CPU
F28
w
VCC30
F32
VCC31
F34
w
VCC32
F37 AA14
VCC33 VCCIO30
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
F38 AA15
VCC34 VCCIO31
.ro
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
SC2D2U6D3V2MX-GP
F42 AB17
VCC35 VCCIO32
G42 AB20
VCC36 VCCIO33
1
C887
C891
C890
C846
C848
C847
C881
C882
C883
C886
H25 AC13
1
VCC37 VCCIO34
C824
C825
C826
C827
C828
C829
H26 AD16
se
VCC38 VCCIO35
H28 AD18 DY DY DY DY
2
VCC39 VCCIO36
DY DY DY H29 AD21
2
VCC40 VCCIO37
H32 AE14
VCC41 VCCIO38
fix
H34 AE15
VCC42 VCCIO39
H35 AF16
VCC43 VCCIO40
H37 AF18
VCC44 VCCIO41
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
H38 AF20
.c
VCC45 VCCIO42
H40 AG15
VCC46 VCCIO43
C J25 AG16 C
1
VCC47 VCCIO44
om
C895
C897
C893
C889
C885
J26 AG17
VCC48 VCCIO45
J28 AG20
VCC49 VCCIO46
J29 AG21 DY DY DY
2
VCC50 VCCIO47
J32 AJ14
VCC51 VCCIO48
J34 AJ15
VCC52 VCCIO49
J35
VCC53
J37
VCC54
J38
VCC55
J40
VCC56
J42
VCC57
K26 W16
VCC58 VCCIO50
K27 W17
VCC59 VCCIO51
K29
VCC60
K32
VCC61
K34
VCC62
K35
VCC63
K37
VCC64
K39
VCC66 H_SNB_IVB#_PWRCTRL TP801
K42
VCC67 VCCIO_SEL
BC22 1 VCCPQ Output Decoupling CAP Recommendation:
L25
VCC68
L28
VCC69
1 x 1 uF (0402)
L33
VCC70
L36
VCC71 +V1.05S_VCCPQE_R R812 VCCP_CPU VCCP_CPU
L40
VCC72 0R0402-PAD
N26
VCC73
QUIET
RAILS
N30 AM25 2 1
VCC74 VCCPQE1
N34 AN22
Layout Note:
1
VCC75 VCCPQE2
N38
1
VCC76 C802 R803, R804, R805 need close to CPU
SC1U6D3V2KX-GP R805 R804
Alert# signal must be routed between the Clock and Data
2
75R2F-2-GP 130R2F-1-GP
lines to reduce the cross talk between them
R803
2
43R2J-GP
A44 H_CPU_SVIDALRT# 1 2
VIDALERT# VR_SVID_ALERT# 42
H_CPU_SVIDCLK
VIDSCLK
B43 H_CPU_SVIDCLK 42 Need place Pull Hi
SVID
C44 H_CPU_SVIDDAT
VIDSOUT H_CPU_SVIDDAT 42
at IMVP page
VCC_CORE
B B
Layout Note:
1
R801 1. PH/PL resisors place close CPU
100R2F-L1-GP-U 2. SENSE signal recommend differential routing
2
F43 VCCSENSE VCCSENSE 43
SENSE LINES
VCC_SENSE VSSSENSE
G43 VSSSENSE 43
VSS_SENSE
1
VCCP_CPU
R802
100R2F-L1-GP-U
1
AN16
VCCIO_SENSE R807
AN17
2
VSS_SENSE_VCCIO
10R2F-L-GP
VCCIO_SENSE 45
2
VSSIO_SENSE 45
1
IVY-BRIDGE-GP-NF
71.00IVY.A0U R806
10R2F-L-GP
Layout Note:
2
1. PH/PL resisors place close CPU
2. SENSE signal recommend differential routing
Voltage Rail Voltage(V) Iccmax(A)
VCC_CORE 0.3~1.52 33
VAXG 0~1.52 29 (GT2)
VCCIO 1.05 8.5
VDDQ 1.5 5
VCCSA 0.675~0.9 4
VCCPLL 1.8 1.2
A A
Refer to CPU EDS V.1.7.5

M14 DIS
Wistron Corporation
Title
CPU (VCC_CORE)
A2 A00
http://vinafix.vn
03-05-1512:40:57 PM
Date: Wednesday, September 05, 2012 Sheet 8 of 105
03-05-151:22:21 PM
5 4 3 2 1
5 4 3 2 1
SSID = CPU
Voltage Rail Voltage(V) Iccmax(A)
VCC_CORE 0.3~1.52 33
Layout Note: VAXG 0~1.52 29 (GT2)
CPU1G POWER 7 OF 9
+V_SM_VREF_CNT should have 10 mil trace width
VCCIO 1.05 8.5
+V_SM_VREF_CNT VDDQ 1.5 5
VCC_GFXCORE ULV GT2 33A
SM_VREF
AY43 VCCSA 0.675~0.9 3
AA46
VREF
VAXG1 RN902
AB47
VAXG2
VCCPLL 1.8 1.2
D AB50 BE7 DDR_WR_VREFA 3 2 D
VAXG3 SA_DIMM_VREFDQ
1
SC22U6D3V5MX-2GP
C901
C902
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
C903
C904
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
C905
SC22U6D3V5MX-2GP
C906
AB51 BG7 DDR_WR_VREFB 4 1
AB52
VAXG4 SB_DIMM_VREFDQ DY
AB53
VAXG5
Refer to CPU EDS V2.0
2
VAXG6 SRN1KJ-7-GP
AB55
VAXG7
AB56
VAXG8
AB58
VAXG9
AB59
VAXG10
AC61
VAXG11 1D5V_S0
AD47
VAXG12
AD48
VAXG13 5A
C938
SC10U6D3V3MX-GP
C939
SC10U6D3V3MX-GP
C940
SC10U6D3V3MX-GP
C941
SC10U6D3V3MX-GP
C942
SC10U6D3V3MX-GP
C943
SC10U6D3V3MX-GP
AD50
1
VAXG14
AD51 AJ28
- 1.5V RAILS
VAXG15 VDDQ1
AD52 AJ33
VAXG16 VDDQ2
AD53 AJ36
DY
2
VAXG17 VDDQ3
AD55 AJ40
VAXG18 VDDQ4
1
C927
SC1U6D3V2KX-GP
C928
SC1U6D3V2KX-GP
C929
SC1U6D3V2KX-GP
C930
SC1U6D3V2KX-GP
C931
SC1U6D3V2KX-GP
C932
SC1U6D3V2KX-GP
C933
SC1U6D3V2KX-GP
C934
SC1U6D3V2KX-GP
C935
SC1U6D3V2KX-GP
C936
SC1U6D3V2KX-GP
AD56 AL30
VAXG19 VDDQ5
AD58 AL34
VAXG20 VDDQ6
AD59 AL38 DY DY
2
VAXG21 VDDQ7
AE46 AL42
VAXG22 VDDQ8
N45 AM33
VAXG23 VDDQ9
P47 AM36
VAXG24 VDDQ10
w
P48 AM40
VAXG25 VDDQ11
P50 AN30
VAXG26 VDDQ12
C944
SC1U6D3V2KX-GP
C945
SC1U6D3V2KX-GP
C946
SC1U6D3V2KX-GP
C947
SC1U6D3V2KX-GP
C948
SC1U6D3V2KX-GP
C949
SC1U6D3V2KX-GP
P51 AN34
w
1
1
VAXG27 VDDQ13
P52 AN38
VAXG28 VDDQ14
P53 AR26
DDR3
w
VAXG29 VDDQ15
DY DY P55 AR28
GRAPHICS
2
2
VAXG30 VDDQ16
1
C919
SC10U6D3V3MX-GP
C920
SC10U6D3V3MX-GP
C921
SC10U6D3V3MX-GP
C922
SC10U6D3V3MX-GP
C923
SC10U6D3V3MX-GP
C924
SC10U6D3V3MX-GP
C925
SC4D7U6D3V3KX-GP
C926
SC10U6D3V3MX-GP
P56 AR30
VAXG31 VDDQ17
.ro
P61 AR32
VAXG32 VDDQ18
T48 AR34
2
VAXG33 VDDQ19 DY
T58 AR36
VAXG34 VDDQ20
T59 AR40
se
VAXG35 VDDQ21
T61 AV41
VAXG36 VDDQ22
U46 AW26
C953 VAXG37 VDDQ23
SC1U6D3V2KX-GP
C951
SC1U6D3V2KX-GP
C952
SC1U6D3V2KX-GP
C954
SC1U6D3V2KX-GP
C950
SC1U6D3V2KX-GP
V47 BA40
VAXG38 VDDQ24
1
fix
V48 BB28
VAXG39 VDDQ25
V50 BG33
VAXG40 VDDQ26
DY DY V51
2
2
VAXG41
V52
.c
VAXG42
V53
VAXG43
C V55 C
VAXG44
om
V56
VAXG45
V58
VAXG46
V59
VAXG47
W50
VAXG48
W51
VAXG49
W52
VAXG50
W53
VAXG51
W55
VAXG52
W56
VCC_GFXCORE VAXG53
W61
VAXG54
Y48
VAXG55
Y61
VAXG56
Layout Note:
1
1. PH/PL resisors place close CPU R901 +V1.5S_VCCD_Q 1D5V_S0
100R2F-L1-GP-U
2. SENSE signal recommend differential routing R903
0R0402-PAD
QUIET RAILS
AM28 2 1
SENSE
LINES
2
VCC_AXG_SENSE VCCDQ1
44 VCC_AXG_SENSE F45 AN26
VSS_AXG_SENSE VAXG_SENSE VCCDQ2
44 VSS_AXG_SENSE G45
1
VSSAXG_SENSE
C937
SC1U6D3V2KX-GP
1
R902
2
100R2F-L1-GP-U
1.8V RAIL
2
BB3
VCCPLL1
BC1
1D8V_S0 VCCPLL2
BC4
1.2A VCCPLL3
C907
SC1U6D3V2KX-GP
C908
SC1U6D3V2KX-GP
C955
SC10U6D3V5KX-1GP
BC43 TP_VDDQ_SENSE 1 TP901 TPAD14-OP-GP
1
1
VDDQ_SENSE TP_VDDQ_VSS TP902 TPAD14-OP-GP
BA43 1
VSS_SENSE_VDDQ
SENSE LINES
L17
DY
2
VCCSA1
L21
VCCSA2
N16
VCCSA3
N20
0D85V_S0 VCCSA4
N22
ULV 4A
SA RAIL
B VCCSA5 B
P17
VCCSA6 VCCSA_SENSE
P20 U10
VCCSA7 VCCSA_SENSE VCCSA_SENSE 48
R16
1
VCCSA8
C913
SC10U6D3V3MX-GP
C912
SC10U6D3V3MX-GP
C911
SC10U6D3V3MX-GP
C910
SC10U6D3V3MX-GP
C909
SC10U6D3V3MX-GP
R18
VCCSA9
VCCSA Power Select
R21
VCCSA10
U15
VCCSA VID
2
VCCSA11
DY DY V16 Voltage(ULV) VID[0] VID[1]
VCCSA12 VCCSA_SEL0
V17 D48
VCCSA13 VCCSA_VID0 VCCSA_SEL0 48
lines
V18 D49 VCCSA_SEL1
VCCSA14 VCCSA_VID1 VCCSA_SEL1 48
V21 0.9 0 0
2
1
VCCSA15
W20
VCCSA16 RN901
1
1
C918
SC1U6D3V2KX-GP
C917
SC1U6D3V2KX-GP
C916
SC1U6D3V2KX-GP
C915
SC1U6D3V2KX-GP
C914
SC1U6D3V2KX-GP
SRN1KJ-7-GP 0.85 0 1
DY DY
2
IVY-BRIDGE-GP-NF 0.775 1 0
3
4
71.00IVY.A0U
0.75 1 1
A A
M14 DIS
Wistron Corporation
Title
CPU (VCC_GFXCORE)
A2 A00
http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1H 8 OF 9
CPU1I 9 OF 9
A13 VSS1 VSS91 AM38 BG17 VSS181 VSS250 M4

A25 VSS4 VSS94 AM45 BG28 VSS184 VSS253 N1
D A28 VSS5 VSS95 AM48 BG37 VSS185 VSS254 N17 D
A33 VSS6 VSS96 AM58 BG41 VSS186 VSS255 N21
A37 VSS7 VSS97 AN1 BG45 VSS187 VSS256 N25
A53 VSS11 VSS101 AN33 C29 VSS191 VSS260 N40
A9 VSS12 VSS102 AN36 C35 VSS192 VSS261 N43
AA1 VSS13 VSS103 AN40 C40 VSS193 VSS262 N47
AA13 VSS14 VSS104 AN43 D10 VSS194 VSS263 N48
AA53 VSS18 VSS108 AP10 D26 VSS198 VSS267 N61
AA55 VSS19 VSS109 AP51 D29 VSS199 VSS268 P14
w
w
AB16 VSS22 VSS112 AR13 D40 VSS202 VSS271 P21
AB18 AR17 D43 P58
w
AB21
VSS23
VSS24
VSS113
VSS114 AR21 D46
VSS203
VSS204 VSS VSS272
VSS273 P59
.ro
AB48 VSS25 VSS115 AR41 D50 VSS205 VSS274 P9
AB61 VSS26 VSS116 AR48 D54 VSS206 VSS275 R17
AC10 AR61 D58 R20
se
VSS27 VSS117 VSS207 VSS276
AC14 VSS28 VSS118 AR7 D6 VSS208 VSS277 R4
AC46 VSS29 VSS119 AT14 E25 VSS209 VSS278 R46
fix
AC6 VSS30 VSS120 AT19 E29 VSS210 VSS279 T1
AD17 VSS31 VSS121 AT36 E3 VSS211 VSS280 T47
.c
AD20 VSS32 VSS122 AT4 E35 VSS212 VSS281 T50
AD4 AT45 E40 T51
VSS33
VSS VSS123 VSS213 VSS282
om
C AD61 AT52 F13 T52 C
AE13 VSS35 VSS125 AT58 F15 VSS215 VSS284 T53
AE8 VSS36 VSS126 AU1 F19 VSS216 VSS285 T55
AF1 VSS37 VSS127 AU11 F29 VSS217 VSS286 T56
AF17 VSS38 VSS128 AU28 F35 VSS218 VSS287 U13
AF21 VSS39 VSS129 AU32 F40 VSS219 VSS288 U8
AF47 VSS40 VSS130 AU51 F55 VSS220 VSS289 V20
AF48 VSS41 VSS131 AU7 G51 VSS221 VSS290 V61
AF50 VSS42 VSS132 AV17 G6 VSS222 VSS291 W13
AF51 VSS43 VSS133 AV21 G61 VSS223 VSS292 W15
AF52 VSS44 VSS134 AV22 H10 VSS224 VSS293 W18
AF58 VSS48 VSS138 AV55 H4 VSS228 VSS297 Y4
AF59 VSS49 VSS139 AW13 H53 VSS229 VSS298 Y47
AG10 VSS50 VSS140 AW43 H58 VSS230 VSS299 Y58
AG14 VSS51 VSS141 AW61 J1 VSS231 VSS300 Y59
AG18 VSS52 VSS142 AW7 J49 VSS232
AG47 VSS53 VSS143 AY14 J55 VSS233
AG52 VSS54 VSS144 AY19 K11 VSS234
AG61 AY30 K21

VSS55 VSS145 VSS235
AG7 VSS56 VSS146 AY36 K51 VSS236
A5,A57,BC61,BG5
AH4 AY4 K8 A5
BG57,C3,E1,E61
VSS57 VSS147 VSS237 VSS_NCTF_1#A5
NCTF TEST PIN

AH58 VSS58 VSS148 AY41 L16 VSS238 VSS_NCTF_2#A57 A57
AJ13 VSS59 VSS149 AY45 L20 VSS239 VSS_NCTF_3#BC61 BC61
AJ16 VSS60 VSS150 AY49 L22 VSS240 VSS_NCTF_8#BG5 BG5
AJ20 VSS61 VSS151 AY55 L26 VSS241 VSS_NCTF_9#BG57 BG57
AJ22 VSS62 VSS152 AY58 L30 VSS242 VSS_NCTF_10#C3 C3
B B
AJ26 VSS63 VSS153 AY9 L34 VSS243 VSS_NCTF_13#E1 E1
AJ30 VSS64 VSS154 BA1 L38 VSS244 VSS_NCTF_14#E61 E61
NCTF
AJ34 VSS65 VSS155 BA11 L43 VSS245
AJ38 VSS66 VSS156 BA17 L48 VSS246
AJ42 VSS67 VSS157 BA21 L61 VSS247 VSS_NCTF_4 BD3
AJ45 VSS68 VSS158 BA26 M11 VSS248 VSS_NCTF_5 BD59
AJ48 VSS69 VSS159 BA32 M15 VSS249 VSS_NCTF_6 BE4
AJ7 VSS70 VSS160 BA48 VSS_NCTF_7 BE58
AK1 VSS71 VSS161 BA51 VSS_NCTF_11 C58
AK52 VSS72 VSS162 BB53 VSS_NCTF_12 D59
AL10 VSS73 VSS163 BC13
AL21 BD12 IVY-BRIDGE-GP-NF
VSS76 VSS166
AL25 VSS77 VSS167 BD16 71.00IVY.A0U
AL28 VSS78 VSS168 BD19
AM13 VSS85 VSS175 BD48
AM30 VSS89 VSS179 BE5
AM34 VSS90 VSS180 BG13
A M14 DIS A
Wistron Corporation
IVY-BRIDGE-GP-NF 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
71.00IVY.A0U Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU (VSS)
A3 A00
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
10 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
XDP
A3 A00
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
11 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
12 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
(Reserved)
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
13 of 105
5 4 3 2 1
SSID = MEMORY
DM1
6 M_A_A[15:0]
M_A_A0 98 NP1
M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2
96
M_A_A3 A2
95 110 M_A_RAS# 6
M_A_A4 A3 RAS# SA0_DIMA
M_A_A5
92
A4 WE#
113 M_A_WE# 6
SA1_DIMA
Note:
91 115 M_A_CAS# 6
M_A_A6 A5 CAS# SA0 DIM0 = 0, SA1_DIM0 = 0
90
A6
1
M_A_A7 86 114 M_A_DIMA_CS#0 6 SO-DIMMA SPD Address is 0xA0
1
M_A_A8 A7 CS0# R1402
89 121 M_A_DIMA_CS#1 6
A8 CS1#
M_A_A9 85
A9
R1401 0R0402-PAD SO-DIMMA TS Address is 0x30
M_A_A10 107 73 0R0402-PAD
A10/AP CKE0 M_A_DIMA_CKE0 6
M_A_A11 84 74 M_A_DIMA_CKE1 6
2
M_A_A12 A11 CKE1
83
2
M_A_A13 A12
119 101 M_A_DIMA_CLK_DDR0 6
M_A_A14 A13 CK0
D 80 103 M_A_DIMA_CLK_DDR#0 6 D
M_A_A15 A14 CK0#
78
A15
79 102 M_A_DIMA_CLK_DDR1 6
6 M_A_BS2 A16/BA2 CK1
104 M_A_DIMA_CLK_DDR#1 6
CK1#
109
6 M_A_BS0 BA0
108 11
DDR_VREF_S3 6 M_A_BS1 BA1 DM0
6 M_A_DQ[63:0] 28
M_A_DQ0 DM1
5 46
Layout Note: M_A_DQ1 7
DQ0 DM2
63
1
M_A_DQ2 DQ1 DM3

Place these caps 15
DQ2 DM4
136
R1405 M_A_DQ3 17 153
0R0402-PAD
close to VREF_CA M_A_DQ4 DQ3 DM5
4 170
M_A_DQ5 DQ4 DM6
6 187
M_VREF_CA_DIMMA M_A_DQ6 DQ5 DM7
16
2
M_A_DQ7 DQ6
18 200 PCH_SMBDATA 15,20,69
M_A_DQ8 DQ7 SDA
21 202 PCH_SMBCLK 15,20,69
M_A_DQ9 DQ8 SCL
23
M_A_DQ10 DQ9 3D3V_S0
33 198
DQ10 EVENT#
1
M_A_DQ11 35
M_A_DQ12 DQ11
C1427
C1428
C1426
22 199
DY
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
M_A_DQ13 DQ12 VDDSPD

24
2
M_A_DQ14 DQ13 SA0_DIMA

34 197
1
DQ14 SA0
w
M_A_DQ15 36 201 SA1_DIMA C1401
M_A_DQ16 DQ15 SA1 SCD1U10V2KX-5GP
39
M_A_DQ17 DQ16
41 77
w
2
M_A_DQ18 DQ17 NC#1
51 122
M_A_DQ19 DQ18 NC#2 1D5V_S3
53 125
w
M_A_DQ20 DQ19 NC#/TEST
40
DQ20 Close to DIMM1.199
M_A_DQ21 42 75
DQ21 VDD1
.ro
M_A_DQ22 50 76
DDR_VREF_S3 M_A_DQ23 DQ22 VDD2
52 81
Layout Note: M_A_DQ24 57
DQ23 VDD3
82
M_A_DQ25 DQ24 VDD4
Place these caps 59 87
se
DQ25 VDD5
1
M_A_DQ26 67 88
R1404
close to VREF_DQ M_A_DQ27 DQ26 VDD6
69 93
0R0402-PAD M_A_DQ28 DQ27 VDD7
56 94
DQ28 VDD8 1D5V_S3
fix
M_A_DQ29 58 99
M_VREF_DQ_DIMMA M_A_DQ30 DQ29 VDD9
68 100
2
M_A_DQ31 DQ30 VDD10

70 105
M_A_DQ32 DQ31 VDD11
129 106
.c
ST330U2VDM-4-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
M_A_DQ33 DQ32 VDD12
TC1401
C1403
C1404
C1405
C1406
C1407
C1408
131 111
DQ33 VDD13
1
C M_A_DQ34 141 112 C
1
DQ34 VDD14
om
M_A_DQ35 143 117
M_A_DQ36 DQ35 VDD15 DY DY DY DY DY
C1411
C1423
C1429
130 118
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
2
M_A_DQ37 DQ36 VDD16
132 123
2
M_A_DQ38 DQ37 VDD17

140 124
M_A_DQ39 DQ38 VDD18
142
M_A_DQ40 DQ39
147 2
M_A_DQ41 DQ40 VSS
149 3
M_A_DQ42 DQ41 VSS
157 8
M_A_DQ43 DQ42 VSS
159 9
M_A_DQ44 DQ43 VSS
146 13
M_A_DQ45 DQ44 VSS
148 14
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_A_DQ46 DQ45 VSS
C1414
C1415
C1416
C1417
158 19
1
M_A_DQ47 DQ46 VSS
160 20
M_A_DQ48 DQ47 VSS
163 25
M_A_DQ49 DQ48 VSS
Layout Note: 165 26
2
M_A_DQ50 DQ49 VSS
175 31
M_A_DQ51 DQ50 VSS
Place these caps 177
DQ51 VSS
32
M_A_DQ52 164 37
0D75V_S0 close to VTT1 and M_A_DQ53 DQ52 VSS
166 38
VTT2. M_A_DQ54 DQ53 VSS
174 43
M_A_DQ55 DQ54 VSS
176 44
M_A_DQ56 DQ55 VSS
181 48
M_A_DQ57 DQ56 VSS
183 49
M_A_DQ58 DQ57 VSS
191 54
Layout Note:
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
M_A_DQ59 DQ58 VSS

C1419
C1420
C1418
193 55
1
M_A_DQ60 DQ59 VSS

180
DQ60 VSS
60 Place these Caps near SO-DIMMA.
M_A_DQ61 182 61
DY M_A_DQ62 192
DQ61 VSS
65
2
M_A_DQ63 DQ62 VSS

194 66
DQ63 VSS
6 M_A_DQS#[7:0] 71
M_A_DQS#0 VSS 1D5V_S0 1D5V_S3
10 72
M_A_DQS#1 DQS0# VSS
27 127
M_A_DQS#2 DQS1# VSS
45 128
M_A_DQS#3 DQS2# VSS
62 133 1 2
M_A_DQS#4 DQS3# VSS
135 134
M_A_DQS#5 152
DQS4# VSS
138
DY
M_A_DQS#6 DQS5# VSS C1421
169 139
M_A_DQS#7 DQS6# VSS SCD1U10V2KX-5GP
186 144
DQS7# VSS
6 M_A_DQS[7:0] 145
M_A_DQS0 VSS
12 150 1 2
B M_A_DQS1 DQS0 VSS B
29 151
M_A_DQS2 47
DQS1 VSS
155 DY
M_A_DQS3 DQS2 VSS C1424
64 156
M_A_DQS4 DQS3 VSS SCD1U10V2KX-5GP
137 161
M_A_DQS5 DQS4 VSS
154 162
M_A_DQS6 DQS5 VSS
171 167
M_A_DQS7 DQS6 VSS
188
DQS7 VSS
168
172
Layout Note:
VSS
6 M_A_DIMA_ODT0
116
ODT0 VSS
173 For S3 reduction circuit's 1D5V return pass.
120 178
6 M_A_DIMA_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMMA 126 184
VREF_CA VSS
1 185
Layout Note: M_VREF_DQ_DIMMA VREF_DQ VSS
189
VSS
All VREF traces should 15,37 DDR3_DRAMRST#
30
RESET# VSS
190
EC1401 1 2 195
have width=20mil; SCD1U10V2KX-5GP VSS
196
spacing=20 mil
0D75V_S0
DY 203
VSS
205
VTT1 VSS
204 206
VTT2 VSS
DDR3-204P-119-GP-U
62.10017.Z81
A A
M14 DIS
Wistron Corporation
Title
DDR3-SODIMM1
A2 A00
DNE40 14 CR DIS
http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
5 4 3 2 1
5 4 3 2 1
SSID = MEMORY DM2

6 M_B_A[15:0]
M_B_A0 98 NP1
M_B_A1 A0 NP1
97 NP2
M_B_A2 A1 NP2
96
M_B_A3 A2
95 110 M_B_RAS# 6
M_B_A4 A3 RAS#
92 113 M_B_WE# 6
M_B_A5 A4 WE#
M_B_A6
91
A5 CAS#
115 M_B_CAS# 6 Note:
90
M_B_A7 A6 SO-DIMMB SPD Address is 0xA4
86 114 M_B_DIMB_CS#0 6
M_B_A8 A7 CS0#
89 121 M_B_DIMB_CS#1 6 SO-DIMMB TS Address is 0x34
M_B_A9 A8 CS1#
85
M_B_A10 A9
107 73 M_B_DIMB_CKE0 6
M_B_A11 A10/AP CKE0
84 74 M_B_DIMB_CKE1 6
M_B_A12 A11 CKE1
83
M_B_A13 A12
119 101 M_B_DIMB_CLK_DDR0 6
M_B_A14 A13 CK0
80 103 M_B_DIMB_CLK_DDR#0 6
DDR_VREF_S3 M_B_A15 A14 CK0#
D 78 D
A15
79 102 M_B_DIMB_CLK_DDR1 6
6 M_B_BS2 A16/BA2 CK1
104 M_B_DIMB_CLK_DDR#1 6
CK1#
109
1
6 M_B_BS0 BA0
108 11
R1505 6 M_B_BS1 BA1 DM0
6 M_B_DQ[63:0] 28
0R0402-PAD M_B_DQ0 DM1
5 46
M_B_DQ1 DQ0 DM2
7 63
M_VREF_CA_DIMMB M_B_DQ2 DQ1 DM3
15 136
2
M_B_DQ3 DQ2 DM4

17 153
M_B_DQ4 DQ3 DM5
4 170
Layout Note: M_B_DQ5 6
DQ4 DM6
187
M_B_DQ6 DQ5 DM7
Place these caps 16
DQ6
1
M_B_DQ7 18 200
close to VREF_CA M_B_DQ8 DQ7 SDA PCH_SMBDATA 14,20,69
C1523
C1524
C1522
21 202
DY
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
M_B_DQ9 DQ8 SCL PCH_SMBCLK 14,20,69

23
2
M_B_DQ10 DQ9 3D3V_S0

33 198
M_B_DQ11 DQ10 EVENT# 3D3V_S0
35
M_B_DQ12 DQ11
22 199
M_B_DQ13 DQ12 VDDSPD R1507
24
1
M_B_DQ14 DQ13 SA0_DIMB SA1_DIMB
34 197 1 2
M_B_DQ15 DQ14 SA0 SA1_DIMB C1501
36 201
DQ15 SA1
w
M_B_DQ16 39 SCD1U10V2KX-5GP 10KR2J-3-GP
2
M_B_DQ17 DQ16
41 77
M_B_DQ18 DQ17 NC#1 R1506
51 122
w
M_B_DQ19 DQ18 NC#2 1D5V_S3 SA0_DIMB
53 125 1 2
DDR_VREF_S3 M_B_DQ20 DQ19 NC#/TEST
40
w
M_B_DQ21 DQ20
42
DQ21 VDD1
75 Close to DIMM1.199 0R0402-PAD
M_B_DQ22 50 76
DQ22 VDD2
.ro
M_B_DQ23 52 81
1
M_B_DQ24 DQ23 VDD3

57 82
R1503 M_B_DQ25 DQ24 VDD4
59 87
0R0402-PAD M_B_DQ26 DQ25 VDD5
67 88
Layout Note:
se
M_B_DQ27 DQ26 VDD6
69 93
M_VREF_DQ_DIMMB M_B_DQ28 DQ27 VDD7
Place these caps 56 94
2
M_B_DQ29 DQ28 VDD8

close to VREF_DQ 58 99
DQ29 VDD9
fix
M_B_DQ30 68 100
M_B_DQ31 DQ30 VDD10 1D5V_S3
70 105
M_B_DQ32 DQ31 VDD11
129 106
1
M_B_DQ33 DQ32 VDD12

131 111
.c
M_B_DQ34 DQ33 VDD13
C1515
C1516
C1517
141 112
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
M_B_DQ35 DQ34 VDD14

C 143 117 C
2
DQ35 VDD15
om
M_B_DQ36 130 118
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
M_B_DQ37 DQ36 VDD16
C1503
C1504
C1507
C1509
C1510
132 123
SC10U6D3V5KX-1GP
1
1
M_B_DQ38 DQ37 VDD17
140 124
M_B_DQ39 DQ38 VDD18
C1508
142
M_B_DQ40 147
DQ39
2
DY DY DY DY
2
M_B_DQ41 DQ40 VSS
149 3
M_B_DQ42 DQ41 VSS
157 8
M_B_DQ43 DQ42 VSS
159 9
M_B_DQ44 DQ43 VSS
146 13
M_B_DQ45 DQ44 VSS
148 14
M_B_DQ46 DQ45 VSS
158 19
0D75V_S0 M_B_DQ47 DQ46 VSS
160 20
M_B_DQ48 DQ47 VSS
163 25
Layout Note:
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_B_DQ49 DQ48 VSS
C1511
C1512
C1513
C1514
165 26
DQ49 VSS
1
Place these caps M_B_DQ50 175 31
M_B_DQ51 DQ50 VSS
177 32
close to VTT1 and M_B_DQ52 DQ51 VSS DY
C1518
C1519
C1521
164 37
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
2
1
VTT2. M_B_DQ53 DQ52 VSS

166 38
M_B_DQ54 DQ53 VSS
174 43
DY M_B_DQ55 176
DQ54 VSS
44
2
M_B_DQ56 DQ55 VSS

181 48
M_B_DQ57 DQ56 VSS
183 49
M_B_DQ58 DQ57 VSS
191 54
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ60 DQ59 VSS
180 60
M_B_DQ61 DQ60 VSS
182 61
M_B_DQ62 192
DQ61 VSS
65
Layout Note:
M_B_DQ63 DQ62 VSS
194
DQ63 VSS
66 Place these Caps near SO-DIMMA.
6 M_B_DQS#[7:0] 71
M_B_DQS#0 VSS
10 72
M_B_DQS#1 DQS0# VSS
27 127
M_B_DQS#2 DQS1# VSS
45 128
M_B_DQS#3 DQS2# VSS
62 133
M_B_DQS#4 DQS3# VSS
135 134
M_B_DQS#5 DQS4# VSS
152 138
M_B_DQS#6 DQS5# VSS
169 139
M_B_DQS#7 DQS6# VSS
186 144
DQS7# VSS
6 M_B_DQS[7:0] 145
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
29 151
B M_B_DQS2 DQS1 VSS B
47 155
M_B_DQS3 DQS2 VSS
64 156
M_B_DQS4 DQS3 VSS
137 161
M_B_DQS5 DQS4 VSS
154 162
M_B_DQS6 DQS5 VSS
171 167
M_B_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
116 173
6 M_B_DIMB_ODT0 ODT0 VSS
120 178
6 M_B_DIMB_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMMB 126 184
VREF_CA VSS
M_VREF_DQ_DIMMB 1 185
VREF_DQ VSS
189
Layout Note: 30
VSS
190
14,37 DDR3_DRAMRST# RESET# VSS
All VREF traces should EC1501 1 2
VSS
195
have width=20mil;
0D75V_S0
DY SCD1U10V2KX-5GP
203
VSS
196
205
spacing=20 mil VTT1 VSS
204 206
VTT2 VSS
DDR3-204P-90-GP
62.10017.U81
A A
M14 DIS
Wistron Corporation
Title
DDR3-SODIMM2
A2 A00
http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
5 4 3 2 1
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
16 of 105
5 4 3 2 1
SSID = PCH
D D
3D3V_S0
RN1701 4 OF 10 3D3V_S0
PCH1D
1 4 L_CTRL_DATA 27 L_BKLT_EN J47 AP43
L_CTRL_CLK L_BKLTEN SDVO_TVCLKINN
2 3 49 LVDS_VDD_EN M45 L_VDD_EN SDVO_TVCLKINP AP45
SRN2K2J-1-GP 49 L_BKLT_CTRL P45 L_BKLTCTL SDVO_STALLN AM42
3
4
SDVO_STALLP AM40
LVDS_DDC_CLK_R RN1706
49 LVDS_DDC_CLK_R
49 LVDS_DDC_DATA_R
T40
LVDS_DDC_DATA_R K47 L_DDC_CLK
AP39 SRN2K2J-1-GP
Layout Note:
L_DDC_DATA SDVO_INTN
SDVO_INTP AP40 Close HDMI port
w
RN1702 L_CTRL_CLK T45
L_BKLT_EN L_CTRL_DATA L_CTRL_CLK
2 3 P39
2
1
L_CTRL_DATA
w
1 4 LVDS_VDD_EN
LVDS_IBG AF37 P38
w
LVD_IBG SDVO_CTRLCLK PCH_HDMI_CLK 51
SRN100KJ-6-GP TP1701 1 LVDS_VBG AF36 M39
LVD_VBG SDVO_CTRLDATA PCH_HDMI_DATA 51
.ro
1
AE48 LVD_VREFH
R1701
Layout Note: AE47 AT49
se
2K37R2F-GP LVD_VREFL DDPB_AUXN
DDPB_AUXP AT47
Place near PCH; DDPB_HPD AT40 HDMI_PCH_DET 51
fix
trace to trace spacing=20mil 49 LVDSA_CLK# AK39
2
LVDSA_CLK#
LVDS
49 LVDSA_CLK AK40 LVDSA_CLK DDPB_0N AV42 HDMI_DATA2_R# 51
.c
DDPB_0P AV40 HDMI_DATA2_R 51
49 LVDSA_DATA0# AN48 LVDSA_DATA#0 DDPB_1N AV45 HDMI_DATA1_R# 51
om
C AM47 AV46 C
49 LVDSA_DATA1# LVDSA_DATA#1 DDPB_1P HDMI_DATA1_R 51
Digital Display Interface

49 LVDSA_DATA2# AK47 LVDSA_DATA#2 DDPB_2N AU48 HDMI_DATA0_R# 51
AJ48 LVDSA_DATA#3 DDPB_2P AU47 HDMI_DATA0_R 51
DDPB_3N AV47 HDMI_CLK_R# 51
49 LVDSA_DATA0 AN47 LVDSA_DATA0 DDPB_3P AV49 HDMI_CLK_R 51
49 LVDSA_DATA1 AM49 LVDSA_DATA1
49 LVDSA_DATA2 AK49 LVDSA_DATA2
Layout Note: AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
P42
Layout Note:
DDPC_CTRLDATA
LVDS signal trace HDMI trace length to DC CAP. max 10000mil
length max 4000mil 49 LVDSB_CLK# AF40 LVDSB_CLK#
49 LVDSB_CLK AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
49 LVDSB_DATA0# AH45 LVDSB_DATA#0 DDPC_HPD AT38
49 LVDSB_DATA1# AH47 LVDSB_DATA#1
49 LVDSB_DATA2# AF49 LVDSB_DATA#2 DDPC_0N AY47
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
3D3V_S0 AH43 AY45
49 LVDSB_DATA0 LVDSB_DATA0 DDPC_1P
49 LVDSB_DATA1 AH49 LVDSB_DATA1 DDPC_2N BA47
49 LVDSB_DATA2 AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49
3
4
RN1707
SRN2K2J-1-GP N48 CRT_BLUE DDPD_CTRLCLK M43
P49 CRT_GREEN DDPD_CTRLDATA M36
T49 CRT_RED
2
1
B B
DDPD_AUXN AT45
CRT
CRT_DDCCLK T39 AT43
CRT_DDCDATA CRT_DDC_CLK DDPD_AUXP
M40 CRT_DDC_DATA DDPD_HPD BH41
DDPD_0N BB43
M47 CRT_HSYNC DDPD_0P BB45
M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
DDPD_2N BF42
DAC_IREF_R T43 BE42
DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
1
Layout Note: R1702 DDPD_3P BG42
Place near PCH; 1KR2J-1-GP PANTHER-GP-NF

trace to trace spacing=30mil 71.0HM76.A0U
2
A M14 DIS A
Wistron Corporation
Title
PCH (LVDS/CRT/DDI)
A3 A00
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
17 of 105
5 4 3 2 1
SSID = PCH
PCH1E 5 OF 10
3D3V_S0 AY7
RN1803 RSVD1
RSVD2 AV7
SRN10KJ-6-GP BG26 AU3
PCH_GPIO50 TP1 RSVD3
8 1 BJ26 TP2 RSVD4 BG4
7 2 PCH_GPIO54 BH25
PCH_GPIO02 TP3
6 3 BJ16 TP4 RSVD5 AT10
D 5 4 BOARD_ID1 BOARD_ID1 20 BG16 BC8 D
TP5 RSVD6
AH38 TP6
AH37 TP7 RSVD7 AU2
3D3V_S0 AK43 AT4
RN1804 TP8 RSVD8
AK45 TP9 RSVD9 AT3
SRN10KJ-6-GP C18 AT1
INT_PIRQD# TP10 RSVD10
8 1 N30 TP11 RSVD11 AY3
7 2 KB_LED_BL_DET H3 AT5
INT_PIRQC# TP12 RSVD12
6 3 AH12 TP13 RSVD13 AV3
5 4 PCH_GPIO04 AM4 AV1
TP14 RSVD14
AM5 TP15 RSVD15 BB1
Y13 TP16 RSVD16 BA3
3D3V_S0 K24 BB5
RN1805 TP17 RSVD17
L24 TP18 RSVD18 BB3
SRN10KJ-6-GP AB46 BB7
TP19 RSVD19
w
8 1 PCH_GPIO52 AB45 BE8
TP20 RSVD20
RSVD
7 2 INT_PIRQB# BD4
RSVD21
w
6 3 SATA_ODD_DA# BF6
INT_PIRQA# RSVD22
5 4
Layout Note:
w
B21 AV5
TP21 RSVD23 USB Table
.ro
Trace Length : M20 TP22 RSVD24 AV10
PCH ~~9000mil~~Cap~~1000mil~~CONN AY16 TP23
BG46 AT8 Pair Device
se
TP24 RSVD25
RSVD26 AY5 0 USB3.0 port2
fix
RSVD27 BA2
USB3_RX1_N BE28 1 USB3.0 port1, with Debug Port
USB3.0/2.0 Mapping Table 62 USB3_RX1_N USB3_RX2_N USB3RN1
.c
62 USB3_RX2_N BC30 USB3RN2 RSVD28 AT12
BE32 USB3RN3 RSVD29 BF3 2 USB2.0 port3
om
C USB 3.0 Port USB 2.0 port BJ32 USB3RN4
C
62 USB3_RX1_P
USB3_RX1_P BC28 USB3RP1 3 NC
Port 1 Port 0 USB3_RX2_P BE30
62 USB3_RX2_P
BF32
USB3RP2
USB3RP3
USB2.0 Signal Group 4 NC
Port 2 Port 1 BG32 USB3RP4 USBP0N C24 USB_PN0 62
62 USB3_TX1_N USB3_TX1_N AV26 USB3TN1 USBP0P A24 USB_PP0 62 5 Touch Panel
Port 3 Port 2 62 USB3_TX2_N USB3_TX2_N BB26 USB3TN2 USBP1N C25 USB_PN1 62
AU28 USB3TN3 USBP1P B25 USB_PP1 62 6 HM76 NC
Port 4 Port 3 AY30 USB3TN4 USBP2N C26 USB_PN2 82
62 USB3_TX1_P USB3_TX1_P AU26 USB3TP1 USBP2P A26 USB_PP2 82 7 HM76 NC
62 USB3_TX2_P USB3_TX2_P AY26 K28
USB3TP2 USBP3N
AV28 USB3TP3 USBP3P H28 8 NC
AW30 E28 USB_PN4 1 TP1803
USB3TP4 USBP4N
USBP4P D28 USB_PP4 1 TP1804 9 NC
USBP5N C28 USB_PN5 49
USBP5P A28 USB_PP5 49 10 Card reader
USBP6N C29
USBP6P B29 11 WLAN
INT_PIRQA# K40 N28
PIRQA# USBP7N
INT_PIRQB# K38 PIRQB# USBP7P M28 12 NC
PCI
INT_PIRQC# H38 L30
Boot Bios Strap PIRQC# USBP8N
INT_PIRQD# G38 PIRQD# USBP8P K30 13 CAMERA
USBP9N G30
PCH_GPIO50 C46 E30
REQ1#/GPIO50 USBP9P
USB
GNT1#/GPIO51 SATA1GP/GPIO19 Boot BIOS Location PCH_GPIO52 C44 REQ2#/GPIO52 USBP10N C30 USB_PN10 32 1. USB Ext. port 9 (HS) External debug port
3D3V_S0 PCH_GPIO54 E40 A30
REQ3#/GPIO54 USBP10P USB_PP10 32 use on Chief River platform.
USBP11N L32 USB_PN11 65
0 0 LPC R1808 1 2 10KR2J-3-GP BBS_BIT1 D47 K32 USB_PP11 65
2. 2011 July; Microsoft will support USB3.0
GNT1#/GPIO51 USBP11P
B
TP1801 1 PCH_GPIO53 E42 GNT2#/GPIO53 USBP12N G32 debug--> Port1 useable. B
PCI_GNT3# F46 E32
0 1 Reserved DY GNT3#/GPIO55 USBP12P
USBP13N C32 USB_PN13 49
USBP13P A32 USB_PP13 49
PCH_GPIO02 G42
1 0 PIRQE#/GPIO2
Reserved 56 SATA_ODD_DA# G40 PIRQF#/GPIO3
PCH_GPIO04 C33 USB_RBIAS
C42
KB_LED_BL_DET D44 PIRQG#/GPIO4 USBRBIAS# 1
R1811
2
Layout Note:
PIRQH#/GPIO5
1 1 SPI(Default) 22D6R2F-L1-GP 1. USBRBIAS/# use 50ohm single-ended impedance
USBRBIAS B33 spacing to other signal=15mil
TP1802 1 PCI_PME# K10 PME# 2. Length < 500mil
PCI_PLTRST# C6 A14 USB_OC#0_1 USB_OC#0_1 61
PLTRST# OC0#/GPIO59
OC1#/GPIO40 K20
2 1 PCI_GNT3# B17 USB_OC#4_5
DY 71 CLK_PCI_LPC R1807 1 LPC 2 22R2J-2-GP CLK_PCI_LPC_R H49
OC2#/GPIO41
C16
USB_OC#4_5 61
R1801 R1805 CLKOUT_PCI0 OC3#/GPIO42
20 CLK_PCI_FB 1 2 22R2J-2-GP CLK_PCI_FB_R H43 CLKOUT_PCI1 OC4#/GPIO43 L16
4K7R2J-2-GP 27 CLK_PCI_KBC R1806 1 2 22R2J-2-GP CLK_PCI_KBC_R J48 A16 R1812
CLKOUT_PCI2 OC5#/GPIO9 8K2R2J-3-GP
K42 CLKOUT_PCI3 OC6#/GPIO10 D14
H40 C14 OC# 1 2 3D3V_S5
CLKOUT_PCI4 OC7#/GPIO14
2
A16 Swap Override jumper EC1802

DY DY EC1804DY EC1805 PANTHER-GP-NF RN1802
SC4D7P50V2CN-1GP
1
SC4D7P50V2CN-1GP
71.PANTH.00U USB_OC#0_1 1 4
SC10P50V2JN-4GP
3D3V_S5
PCI_GNT#3 Low = A16 swap override/Top-Block USB_OC#4_5 2 3
Swap Override enabled
High = Default SRN10KJ-5-GP
A M14 DIS A
R1823
5,27,31,65,71,83 PLT_RST# 1 2 PCI_PLTRST# Wistron Corporation
0R0402-PAD 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1

1
R1816 C1801
100KR2J-1-GP SC220P50V2KX-3GP Title
DY DY
PCH (PCI/USB/NVRAM)
2
2

A3 A00
DNE40 14 CR DIS
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
18 of 105
5 4 3 2 1
SSID = PCH
PCH1C 3 OF 10
4 DMI_CPU_TXN_PCH_RXN[3:0] FDI_CPU_TXN_PCH_RXN[7:0] 4
DMI_CPU_TXN_PCH_RXN0 BC24 BJ14 FDI_CPU_TXN_PCH_RXN0
DMI_CPU_TXN_PCH_RXN1 DMI0RXN FDI_RXN0 FDI_CPU_TXN_PCH_RXN1
BE20 DMI1RXN FDI_RXN1 AY14
DMI_CPU_TXN_PCH_RXN2 BG18 BE14 FDI_CPU_TXN_PCH_RXN2
DMI_CPU_TXN_PCH_RXN3 DMI2RXN FDI_RXN2 FDI_CPU_TXN_PCH_RXN3
BG20 DMI3RXN FDI_RXN3 BH13
D BC12 FDI_CPU_TXN_PCH_RXN4 D
4 DMI_CPU_TXP_PCH_RXP[3:0] FDI_RXN4
DMI_CPU_TXP_PCH_RXP0 BE24 BJ12 FDI_CPU_TXN_PCH_RXN5
DMI_CPU_TXP_PCH_RXP1 DMI0RXP FDI_RXN5 FDI_CPU_TXN_PCH_RXN6
BC20 DMI1RXP FDI_RXN6 BG10
DMI_CPU_TXP_PCH_RXP2 BJ18 BG9 FDI_CPU_TXN_PCH_RXN7
DMI_CPU_TXP_PCH_RXP3 DMI2RXP FDI_RXN7
BJ20 DMI3RXP FDI_CPU_TXP_PCH_RXP[7:0] 4
BG14 FDI_CPU_TXP_PCH_RXP0
4 DMI_CPU_RXN_PCH_TXN[3:0] DMI_CPU_RXN_PCH_TXN0 FDI_RXP0 FDI_CPU_TXP_PCH_RXP1
AW24 DMI0TXN FDI_RXP1 BB14
DMI_CPU_RXN_PCH_TXN1 AW20 BF14 FDI_CPU_TXP_PCH_RXP2
DMI_CPU_RXN_PCH_TXN2 DMI1TXN FDI_RXP2 FDI_CPU_TXP_PCH_RXP3
BB18 DMI2TXN FDI_RXP3 BG13
DMI_CPU_RXN_PCH_TXN3 AV18 BE12 FDI_CPU_TXP_PCH_RXP4
DMI3TXN FDI_RXP4
DMI
FDI
BG12 FDI_CPU_TXP_PCH_RXP5
4 DMI_CPU_RXP_PCH_TXP[3:0] DMI_CPU_RXP_PCH_TXP0 FDI_RXP5 FDI_CPU_TXP_PCH_RXP6
AY24 DMI0TXP FDI_RXP6 BJ10
DMI_CPU_RXP_PCH_TXP1 AY20 BH9 FDI_CPU_TXP_PCH_RXP7
DMI_CPU_RXP_PCH_TXP2 DMI1TXP FDI_RXP7
Layout Note: DMI_CPU_RXP_PCH_TXP3
AY18
AU18
DMI2TXP
DMI3TXP
w
DMI_ZCOMP keep W=4 mils and FDI_INT AW16 FDI_INT FDI_INT 4
routing length less than 500 1D05V_PCH DSWODVREN - On Die DSW VR Enable
w
BJ24 AV12 FDI_FSYNC0 FDI_FSYNC0 4
mils. DMI_ZCOMP FDI_FSYNC0
w
DMI_IRCOMP keep W=4 mils and HIGH Enabled (DEFAULT)
R1901 1 2 49D9R2F-GP DMI_COMP_R BG25 BC10 FDI_FSYNC1 FDI_FSYNC1 4
DMI_IRCOMP FDI_FSYNC1
.ro
routing length less than 500 LOW Disabled
mils. R1902 1 2 750R2F-GP RBIAS_CPY BH21 AV14 FDI_LSYNC0 FDI_LSYNC0 4
DMI2RBIAS FDI_LSYNC0
se
BB10 FDI_LSYNC1 FDI_LSYNC1 4
FDI_LSYNC1
fix
RTC_AUX_S5
DSW ODVREN RTC_AUX_S5
.c
DSWVRMEN A18
DSW ODVREN R1917 1 2 330KR2J-L1-GP
om
C R1911 1 2 10KR2J-3-GP C
DY
System Power Management

3D3V_S0 TP1907 1 SUSACK# C12 E22 PCH_DPW ROK R1927 1 2 PM_RSMRST#
SUSACK# DPWROK 0R0402-PAD
R1905 1 2 10KR2J-3-GP
5 XDP_DBRESET# K3 B9 PCH_W AKE#
SYS_RESET# WAKE# 3D3V_S0
36 SYS_PW ROK P12 N3 PM_CLKRUN# 1 R1929 2 PM_CLKRUN#_EC 27

SYS_PWROK CLKRUN#/GPIO32 0R0402-PAD PM_CLKRUN# R1919 1 2 8K2R2J-3-GP
27,36 S0_PW R_GOOD 1 R1921 2 PW ROK L22 PWROK SUS_STAT#/GPIO61 G8 PM_SUS_STAT# 1 TP1901 TPAD14-OP-GP
0R0402-PAD 1 R1916 2
0R0402-PAD
1 2 MEPW ROK L10 N14 SUS_CLK 1 R1925 2
45,46,47,93 RUNPW ROK
R1907 DY 0R2J-2-GP APWROK SUSCLK/GPIO62 0R0402-PAD
PCH_SUSCLK_KBC 27
PCH_SUSCLK_KBC
37 PM_DRAM_PW RGD B13 D10 PM_SLP_S5# 1 TP1902 TPAD14-OP-GP

DRAMPWROK SLP_S5#/GPIO63
2
R1924 EC1901
27 RSMRST#_KBC 1 2 PM_RSMRST# C21 H4 PM_SLP_S4# PM_SLP_S4# 27,46 SC4D7P50V2CN-1GP DY
1
0R0402-PAD RSMRST# SLP_S4#
SUS_PW R_ACK K16 F4 PM_SLP_S3# PM_SLP_S3# 27,36,37,47

SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3#
27 PM_PW RBTN# PM_PW RBTN# E20 G10 PM_SLP_A# 1 TP1903

PWRBTN# SLP_A#
27,86 AC_PRESENT AC_PRESENT H20 G16 PM_SLP_SUS# 1 TP1904

B ACPRESENT/GPIO31 SLP_SUS# B
27 BATLOW # BATLOW # E10 AP14 H_PM_SYNC H_PM_SYNC 5

BATLOW#/GPIO72 PMSYNCH
PM_RI# A10 K14 PM_SLP_LAN# 1 TP1905

RI# SLP_LAN#/GPIO29
PANTHER-GP-NF
Sequence: 71.PANTH.00U
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
3D3V_S5
SYS_PW ROK S0_PW R_GOOD RUNPW ROK
RN1901
8 1 BATLOW #
1
7 2 PM_RI# EC1907 EC1902 EC1903

6 3 SUS_PW R_ACK SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
5 4 PCH_W AKE#
DY DY DY
2
SRN10KJ-6-GP
R1909 1 2 100KR2J-1-GP AC_PRESENT

R1920 2 1 10KR2J-3-GP PM_SLP_LAN# PM_DRAM_PW RGD RSMRST#_KBC AC_PRESENT
DY
A M14 DIS A
1
EC1904 EC1905 EC1906

SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
DY DY DY Wistron Corporation
2
R1908 2 1 10KR2J-3-GP PM_RSMRST#

R1926 1 2 100KR2J-1-GP SYS_PW ROK
R1904 1
DY 2 100KR2J-1-GP PW ROK Title
reserve for EMI Request PCH (DM I/FDI/PM)

A3 A00
DNE40 14 CR DIS
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
19 of 105
5 4 3 2 1
SSID = PCH S5 power rail CLKREQ#: 3D3V_S5
PCIECLKRQ[0]# SMB_CLK 4 1 RN2003

SMB_DATA 3 2 SRN2K2J-1-GP
3D3V_S5 PCIECLKRQ[7:3]#
RN2001
1 8 PCIE_CLK_REQ6# PCIE_CLK_RQ6# SML0_DATA 1 8 RN2004
2 7 PCIE_CLK_REQ3# PCIE_CLK_RQ3# PCH1B 2 OF 10 SML0_CLK 2 7 SRN2K2J-2-GP
3 6 PCIE_CLK_REQ0# PCIE_CLK_RQ0# SML1_CLK 3 6
4 5 PCIE_CLK_REQ4# PCIE_CLK_RQ4# BG34 SML1_DATA 4 5
PERN1 EC_SW I#
BJ34 PERP1 SMBALERT#/GPIO11 E12 EC_SW I# 27
SRN10KJ-6-GP
RN2002
AV32
AU32
PETN1 NC H14 SMB_CLK
EC_SW I# PETP1 SMBCLK PCH_GPIO74 R2011 1 10KR2J-3-GP
D 1 8 2 D
2 7 PCIE_CLK_LAN_REQ# PCIE_CLK_RQ5# BE34 C9 SMB_DATA
CLK_PCIE_REQ7# PERN2 SMBDATA DRAMRST_CNTRL_PCH 1
3 6 PCIE_CLK_RQ7# BF34 PERP2 2
CLK_PEG_B_REQ# R2009 1KR2J-1-GP
4 5 BB32
AY32
PETN2 NC
PETP2
SMBUS
SRN10KJ-6-GP A12 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH 37
SML0ALERT#/GPIO60 3D3V_S0
65 PCIE_RXN3 BG36 PERN3
65 PCIE_RXP3 BJ36 C8 SML0_CLK RN2007
C2005 1 PERP3 SML0CLK
65 PCIE_TXN3 2 SCD1U10V2KX-5GP PCIE_TXN3_C AV34 PETN3 NC 2 3
C2006 1 2 SCD1U10V2KX-5GP PCIE_TXP3_C SML0_DATA
65 PCIE_TXP3 AU34 PETP3 SML0DATA G12
Layout Note: 1 4
BF36 PERN4
Can Place Far away PCH SRN2K2J-1-GP
BE36 PERP4 PCH_GPIO74
AY34
BB34
PETN4 WLAN SML1ALERT#/PCHHOT#/GPIO74 C13
PETP4
w
E14 SML1_CLK
SML1CLK/GPIO58 SML1_CLK 27,28,86
PCI-E*
BG37 PERN5
w
BH37 M16 SML1_DATA SMB_DATA 6 1
PERP5 SML1DATA/GPIO75 SML1_DATA 27,28,86 PCH_SMBDATA 14,15,69
AY36 NC
w
PETN5
BB36 PETP5 5 2
.ro
84.2N702.A3F
31 PCH_RXN_C_LAN_TXN6 BJ38 PERN6 4 3 2nd = 84.DM601.03F
31 PCH_RXP_C_LAN_TXP6 BG38 3rd = 84.2N702.E3F
se
C2001 1 PERP6
2 SCD1U10V2KX-5GP PCH_TXN_LAN_RXN6 LAN
Controller
31 LAN_RXN_C_PCH_TXN6 AU36 PETN6 CL_CLK1 M7 Q2001 4th = 84.2N702.F3F
31 LAN_RXP_C_PCH_TXP6 C2002 1 2 SCD1U10V2KX-5GP PCH_TXP_LAN_RXP6 AV36 2N7002KDW -GP
PETP6
fix
PCH_SMBCLK 14,15,69
Link
BG40 PERN7 CL_DATA1 T11
SMB_CLK
.c
BJ40 PERP7 NC
Layout Note: AY40 PETN7
om
C BB40 P10 C
PETP7 CL_RST1#
Layout trace < 14000mil XTAL25_IN 1 2
X2001
BE38 PERN8 Layout Note: C2008
BC38
AW38
PERP8 NC CLKOUT termination 1 4 SC15P50V2JN-2-GP
PETN8
2
S0 power rail CLKREQ#: AY38 PETP8 place close to PCH <500mil
R2006
PCIECLKRQ[2:1]# M10 PEG_CLKREQ# 83 1M1R2J-GP
3D3V_S0 PEG_A_CLKRQ#/GPIO47 C2007
Y40 CLKOUT_PCIE0N 2 3
RN2018 RN2016 SC15P50V2JN-2-GP
Y39 NC
1
CLK_PCIE_W LAN_REQ# CLKOUT_PCIE0P CLKOUT_PEG_A_N
1 4 PCIE_CLK_RQ2# CLKOUT_PEG_A_N AB37 1 4 CLK_PCIE_VGA# 83
CLK_PCIE_REQ1# PCIE_CLK_RQ1# PCIE_CLK_REQ0# CLKOUT_PEG_A_P XTAL25_OUT XTAL-25MHZ-155-GP1
CLOCKS
2 3 J2 AB38 2 3 2
PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P OPS CLK_PCIE_VGA 83
SRN10KJ-5-GP SRN0J-6-GP
AB49 AV22 CLKOUT_DMI_N R1930 1 2 CLK_EXP_N 5 82.30020.D41
CLKOUT_PCIE1N CLKOUT_DMI_N CLKOUT_DMI_P R1931 10R0402-PAD
AB47 CLKOUT_PCIE1P NC CLKOUT_DMI_P AU22 2
0R0402-PAD
CLK_EXP_P 5 2nd = 82.30020.G61
CLK_PCIE_REQ1# M1 PCIECLKRQ1#/GPIO18
CLKOUT_DP_N AM12
AM13 3D3V_S0
R1918 1 CLK_PCH_SRC2_N CLKOUT_DP_P
65 CLK_PCIE_W LAN# 2 AA48 CLKOUT_PCIE2N
R1922 10R0402-PAD CLK_PCH_SRC2_P
65 CLK_PCIE_W LAN 2 AA47 CLKOUT_PCIE2P WLAN CLK
1
0R0402-PAD BF18 CLK_BUF_EXP_N 2 3 3D3V_S5
CLKIN_DMI_N CLK_BUF_EXP_P RN2019 1 R2014
65 CLK_PCIE_W LAN_REQ# V10 PCIECLKRQ2#/GPIO20 CLKIN_DMI_P BE18 4
1
SRN10KJ-5-GP 10KR2J-3-GP
OPS
R2004
Y37 BJ30 CLK_BUF_CPYCLK_N 2 3 10KR2J-3-GP
2
CLKOUT_PCIE3N CLKIN_GND1_N CLK_BUF_CPYCLK_P RN2008 1
Y36 CLKOUT_PCIE3P NC CLKIN_GND1_P BG30
SRN10KJ-5-GP
4
Layout Note:
2
B PCIE_CLK_REQ3# PEG_CLKREQ# B
A8 PCIECLKRQ3#/GPIO25 22 BOARD_ID2
G24 CLK_BUF_DOT96_N 2 3
CLKIN_DOT_96N
1
CLKOUT termination CLKIN_DOT_96P E24 CLK_BUF_DOT96_P RN2020 1 4
place close to PCH <500mil Y43 SRN10KJ-5-GP R2010
CLKOUT_PCIE4N
Y45 CLKOUT_PCIE4P NC CLK_BUF_CKSSCD_N
UMA 10KR2J-3-GP
CLKIN_SATA_N AK7 2 3
PCIE_CLK_REQ4# L12 AK5 CLK_BUF_CKSSCD_P RN2021 1 4
2
PCIECLKRQ4#/GPIO26 CLKIN_SATA_P SRN10KJ-5-GP
31 CLK_PCIE_LAN# R1923 1 2 CLK_PCH_SRC5_N V45 K45 CLK_BUF_REF14 R2008 1 2

R1928 10R0402-PAD CLK_PCH_SRC5_P CLKOUT_PCIE5N REFCLK14IN 10KR2J-3-GP
31 CLK_PCIE_LAN 2
0R0402-PAD
V46 CLKOUT_PCIE5P LAN CLK
31 PCIE_CLK_LAN_REQ# L14 H45 CLK_PCI_FB CLK_PCI_FB 18
Layout Note: BIOS UMA/DIS Strap pin
PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK
1500mil < Layout trace < 10000mil
AB42 CLKOUT_PEG_B_N XTAL25_IN V47 XTAL25_IN BOARD_ID1 BOARD_ID2
XTAL25_OUT
AB40 CLKOUT_PEG_B_P NC XTAL25_OUT V49
CLK_PEG_B_REQ# PX(AMD) 0 0
Layout Note: E6 PEG_B_CLKRQ#/GPIO56 R2007
Layout trace < 14000mil XCLK_RCOMP Y47 XCLK_RCOMP 1 2 +VCCDIFFCLKN
V40 CLKOUT_PCIE6N
DIS 0 1
90D9R2F-1-GP
V42 CLKOUT_PCIE6P NC
PCIE_CLK_REQ6# T13 PCIECLKRQ6#/GPIO45
UMA 1 0
V38 K43 JTAG_TCK 1 TP2004
FLEX CLOCKS
CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64
V37 CLKOUT_PCIE7P NC Optimus(NV) 1 1
A F47 CARD_READER_48M 1 TP2005 M14 DIS A
CLK_PCIE_REQ7# CLKOUTFLEX1/GPIO65
K12 PCIECLKRQ7#/GPIO46
CLKOUTFLEX2/GPIO66 H47 CLK_27M_VGA_R 1 TP2006
AK14
AK13
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 K49 BOARD_ID1 BOARD_ID1 18
Wistron Corporation
PANTHER-GP-NF
Title
71.PANTH.00U
PCH (PCI-E/SMBUS/CLOCK/CL)
A3 A00
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
20 of 105
5 4 3 2 1
SSID = PCH
RTC_AUX_S5
R2127 1 220KR2F-L-GP
R2128 1 220KR2F-L-GP Integrated SUS 1V VRM Enable
1
C2104 Low = External VRs
INTVRMEN Layout Note:
SC1U6D3V2KX-GP
High = Internal VRs*
Place near PCH
2
D D
PCH1A 1 OF 10 LPC_AD[3..0]
LPC_AD[3..0] 27,71
RN2101 SRN0J-7-GP
RTC_X1 A20 C38 LPC_LAD0_PCH 1 8 LPC_AD0
RTCX1 FWH0/LAD0 LPC_LAD1_PCH LPC_AD1
FWH1/LAD1 A38 2 7
LPC
RTC_X2 C20 B37 LPC_LAD2_PCH 3 6 LPC_AD2
RTCX2 FWH2/LAD2 LPC_LAD3_PCH LPC_AD3
FWH3/LAD3 C37 4 5
RTC_RST# D20 RTCRST#
FWH4/LFRAME# D36 LPC_LFRAME#_PCH 1 R2136 2 LPC_FRAME# 27,71
SRTC_RST# G22 0R0402-PAD
R2104 SRTCRST#
84.07002.I31 E36
D
LDRQ0#
RTC
2nd = 84.2N702.W31 C2103 2 1 SM_INTRUDER# K22 K36 KB_DET# 69
SC1U6D3V2KX-GP 1M1R2J-GP INTRUDER# LDRQ1#/GPIO23
3rd = 84.2N702.J31 Q2102 PCH_INTVRMEN
RTC_AUX_S5 1 2 C17 V5 INT_SERIRQ 27
2
2N7002BK-GP INTVRMEN SERIRQ
27 RTCRST_ON G
w
R2105
330KR2J-L1-GP AM3 PCH_RXN_C_HDD_TXN0 56
SATA0RXN
w
1
2 1 HDA_BITCLK N34 AM1

R2122 29 HDA_CODEC_BITCLK R2126 HDA_BCLK SATA0RXP
AP7
PCH_RXP_C_HDD_TXP0 56
HDD1
SATA 6G
w
PCH_TXN_HDD_RXN0 56
S
33R2J-2-GP HDA_SYNC SATA0TXN

10KR2J-3-GP L34 HDA_SYNC SATA0TXP AP5 PCH_TXP_HDD_RXP0 56
.ro
29 HDA_SPKR T10 AM10
2
SPKR SATA1RXN
AM8
se
HDA_RST# SATA1RXP
29 HDA_CODEC_RST# 2 1 K34 HDA_RST# SATA1TXN AP11
R2125 AP10
SATA1TXP
fix
33R2J-2-GP
29 HDA_SDIN0 E34 HDA_SDIN0 SATA2RXN AD7
.c
SATA2RXP AD5
Layout Note: G34 AH5
HDA_SDIN1 SATA2TXN
om
C Place close together. AH4 C
SATA2TXP
C34 HDA_SDIN2
IHDA
SATA3RXN AB8
Layout Note: A34 AB10
HDA_SDO and HDA_BCLK must be R2123 HDA_SDIN3 SATA3RXP
SATA3TXN AF3
length matched to within 500 mils 33R2J-2-GP
SATA3TXP AF1
2 1 HDA_SDOUT A36
29 HDA_CODEC_SDOUT HDA_SDO
SATA
SATA4RXN Y7 PCH_RXN_C_ODD_TXN4 56
Layout Note: 27 ME_UNLOCK 1 2 SATA4RXP Y5 PCH_RXP_C_ODD_TXP4 56
R2107 TP2101 1PCH_GPIO33 C36 AD3
3D3V_S5
1KR2J-1-GP
TP2102
HDA_DOCK_EN#/GPIO33 SATA4TXN
SATA4TXP AD1
PCH_TXN_ODD_RXN4 56
PCH_TXP_ODD_RXP4 56 ODD
Flash Descriptor Security Overide/ 1PCH_GPIO13 N32 HDA_DOCK_RST#/GPIO13
Intel ME Debug Mode SATA5RXN Y3
Y1
Layout Note:
SATA5RXP
Low = Default * SATA5TXN AB3 HDD < 6000mil, mSATA < 6000mil, ODD < 12500mil
HDA_SDOUT High = Enable R2111 1 2 51R2J-2-GP PCH_JTAG_TCK_BUF J3 AB1
DY JTAG_TCK SATA5TXP
R2118 1 2 210R2F-L-GP PCH_JTAG_TMS H7 Y11 1D05V_PCH
DY JTAG_TMS SATAICOMPO
JTAG
Place at the separated point
R2119 1 2 210R2F-L-GP PCH_JTAG_TDI K5 Y10 SATA_COMP R2112 1 2 37D4R2F-GP
DY JTAG_TDI SATAICOMPI
3D3V_S0 R2120 1 2 210R2F-L-GP PCH_JTAG_TDO H1 1D05V_PCH
DY JTAG_TDO
AB12
R2106 1 SATA3RCOMPO
2 1KR2J-1-GP HDA_SPKR
DY AB13 SATA3_COMP R2113 1 2 49D9R2F-GP
SATA3COMPI
No Reboot Strap
27,60 SPI_CLK_R 1 2 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 R2114 1 2 750R2F-GP
R2108 33R2J-2-GP SPI_CLK SATA3RBIAS
B
Low = Default * B
HDA_SPKR High = No Reboot 27,60 SPI_CS0#_R 1 2 PCH_SPI_CS0# Y14 SPI_CS0#
R2109 33R2J-2-GP
T1 SPI_CS1# Layout Note:
SPI
P3 SATA_LED# SATA_LED# 68
+3VS_+1.5VS_HDA_IO SATALED#
Place close PCH(<500mil)
27,60 SPI_SI_R 1 2 PCH_SPI_SI V4 SPI_MOSI SATA0GP/GPIO21 V14 PCH_GPIO21 3D3V_S0
R2103 1 2 1KR2J-1-GP HDA_SYNC R2110 33R2J-2-GP
1 2 PCH_SPI_SO U3 P1 BBS_BIT0 R2116 1 2 10KR2J-3-GP
27,60 SPI_SO_R
R2115 33R2J-2-GP SPI_MISO SATA1GP/GPIO19 DY
PLL ODVR VOLTAGE
PANTHER-GP-NF
Low = 1.8V 71.PANTH.00U
HDA_SYNC High = 1.5V 36,37 RUN_ENABLE 3D3V_S0
* RN2103
INT_SERIRQ 1 4
PCH_GPIO21 2 3
G
SPI_CLK_R HDA_CODEC_RST# SRN10KJ-5-GP

R2124
29 HDA_CODEC_SYNC 2 1 HDA_CODEC_SYNC_R S D HDA_SYNC
2
EC2104 EC2105 RTC_X1

2
33R2J-2-GP
R2117 Q2101 DY SC10P50V2JN-4GP SCD1U10V2KX-5GP
1 2 RTC_X2
DY
1
1M1R2J-GP 2N7002BK-GP R2101 10MR2J-L-GP

84.07002.I31 X2101
2nd = 84.2N702.W31
1
3rd = 84.2N702.J31 HDA_CODEC_BITCLK HDA_CODEC_SDOUT 1 4

A M14 DIS A
2
HDA_SYNC:
SC15P50V2JN-2-GP
1
1
DY EC2102 EC2103
C2101
This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V SC4D7P50V2CN-1GP DY SC4D7P50V2CN-1GP
2 3
C2102 Wistron Corporation
1
VccVRM supply mode. 1K external pull-up resistor is required on this SC15P50V2JN-2-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2
2
X-32D768KHZ-65-GP Taipei Hsien 221, Taiwan, R.O.C.
signal on the board. Signal may have leakage paths via powered off devices (Audio
Codec) and hence contend with the external pull-up. A blocking FET is Title
recommended in such a case to isolate HDA_SYNC from the Audio Codec device reserve for EMI Request 82.30001.A41
PCH (SPI/RTC/LPC/SATA/IHDA)
2nd = 82.30001.841
until after the Strap sampling is complete. Size Document Number Rev
A3 A00
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
21 of 105
5 4 3 2 1
SSID = PCH
PCH1F 6 OF 10
PCH_GPIO00 T7 C40 SATA_ODD_PW RGT SATA_ODD_PW RGT 56

BMBUSY#/GPIO0 TACH4/GPIO68
27 EC_SMI# EC_SMI# A42 B41 BOARD_ID2 BOARD_ID2 20

TACH1/GPIO1 TACH5/GPIO69
PCH_GPIO6 H36 C41 PCH_GPIO70 1 TP2201 TPAD14-OP-GP
3D3V_S0 TACH2/GPIO6 TACH6/GPIO70
D D
RN2203 27 EC_SCI# EC_SCI# E38 A40 PCH_GPIO71 1 TP2202 TPAD14-OP-GP
SRN10KJ-5-GP TACH3/GPIO7 TACH7/GPIO71
1 4 H_A20GATE_PCH PCH_GPIO08 C10
H_RCIN# GPIO8
2 3
60 RTC_DET# RTC_DET# C4 LAN_PHY_PWR_CTRL/GPIO12
PCH_GPIO15 G2 P4 H_A20GATE_PCH 1 R2205 2 H_A20GATE 27
3D3V_S0 GPIO15 A20GATE 0R0402-PAD
AU16 H_PECI_R R2203 1 2 0R2J-2-GP
RN2205 56 SATA_ODD_PRSNT# SATA_ODD_PRSNT# U2
PECI DY H_PECI 5,27 VCCP_CPU
SRN10KJ-5-GP SATA4GP/GPIO16 H_RCIN#
RCIN# P5 H_RCIN# 27
1 4 SATA_ODD_PRSNT#
GPIO
2 3 PCH_GPIO00 DGPU_PW ROK D40 AY11 H_CPUPW RGD R2202 1 2 2K2R2J-2-GP
27,92,93 DGPU_PW ROK TACH0/GPIO17 PROCPWRGD H_CPUPW RGD 5 DY
CPU/MISC
w
49 DBC_EN DBC_EN T5 AY10 PCH_THERMTRIP_R R2204 1 2 390R2J-1-GP H_THERMTRIP# 5
SCLOCK/GPIO22 THRMTRIP#
w
PCH_GPIO24 E8 T14 INIT3_3V# 1 TP2213 TPAD14-OP-GP
3D3V_S0 GPIO24 INIT3_3V#
w
RN2206 TPAD14-OP-GP TP2209 1 PCH_GPIO27 E16 AY1 DF_TVS 1D8V_S0
GPIO27 DF_TVS
.ro
SRN10KJ-6-GP
1 8 PCH_GPIO49 PLL_ODVR_EN P8 GPIO28
1
2 7 PCH_GPIO34 AH8
se
PCH_GPIO38 PCH_GPIO34 TS_VSS1 R2207
3 6 K1 STP_PCI#/GPIO34
4 5 DBC_EN AK11 2K2R2J-2-GP
TS_VSS2
fix
TPAD14-OP-GP TP2210 1 PCH_GPIO35 K4 GPIO35
AH10 R2209
2
PCH_GPIO36 TS_VSS3
.c
V8 SATA2GP/GPIO36
3D3V_S0 AK10 DF_TVS 1 2
TS_VSS4 H_SNB_IVB# 5
om
C RN2201 PCH_GPIO37 1KR2J-1-GP C
SRN10KJ-6-GP
M5 SATA3GP/GPIO37 Layout Note:
1 8 EC_SMI# PCH_GPIO38 N2 SLOAD/GPIO38 NC_1 P37 Check these fuor balls are connected firstly, then to GND
2 7 EC_SCI#
3 6 PCH_GPIO6 83 DGPU_HOLD_RST# DGPU_HOLD_RST# M3
DGPU_PW ROK SDATAOUT0/GPIO39
4 5
93 DGPU_PW R_EN# DGPU_PW R_EN# V13 BG2 PCH_NCTF_BG2 1 TP2203 TPAD14-OP-GP
SDATAOUT1/GPIO48 VSS_NCTF_15#BG2
R2208 PCH_GPIO49 V3 BG48 PCH_NCTF_BG48 1 TP2204 TPAD14-OP-GP
10KR2J-3-GP SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16#BG48
3D3V_S5 2 1 VRAM_DET D6 BH3 PCH_NCTF_BH3 1 TP2205 TPAD14-OP-GP
GPIO57 VSS_NCTF_17#BH3
1
VRAM_1G_UMA BH47 PCH_NCTF_BH47 1 TP2206 TPAD14-OP-GP
3D3V_S5 R2210 VSS_NCTF_18#BH47
10KR2J-3-GP A4 VSS_NCTF_1#A4 VSS_NCTF_19#BJ4 BJ4
VRAM_2G
NCTF
2 A44 VSS_NCTF_2#A44 VSS_NCTF_20#BJ44 BJ44
R2206 1 2 RTC_DET# A45 BJ45

10KR2J-3-GP VSS_NCTF_3#A45 VSS_NCTF_21#BJ45
A46 VSS_NCTF_4#A46 VSS_NCTF_22#BJ46 BJ46
RN2207
4 1 PCH_GPIO24 A5 BJ5
PCH_GPIO08 VSS_NCTF_5#A5 VSS_NCTF_23#BJ5
3 DY 2
A6 VSS_NCTF_6#A6 VSS_NCTF_24#BJ6 BJ6
A4,A44,A45,A46,A5,A6,B3,B47,
BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
SRN10KJ-5-GP
BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
TPAD14-OP-GP TP2211 1 PCH_NCTF_B3 B3 C2 PCH_NCTF_C2 1 TP2207 TPAD14-OP-GP
PCH_GPIO15 VSS_NCTF_7#B3 VSS_NCTF_25#C2
2 1
R2201 DY 1KR2J-1-GP TPAD14-OP-GP TP2212 1 PCH_NCTF_B47 B47 C48 PCH_NCTF_C48 1 TP2208 TPAD14-OP-GP
B VSS_NCTF_8#B47 VSS_NCTF_26#C48 B
D49,E1,E49,F1,F49
BD1 VSS_NCTF_9#BD1 VSS_NCTF_27#D1 D1
NCTF TEST PIN:

BD49 VSS_NCTF_10#BD49 VSS_NCTF_28#D49 D49
3D3V_S0 BE1 E1
RN2208 SRN10KJ-5-GP VSS_NCTF_11#BE1 VSS_NCTF_29#E1
4 1 DGPU_PW R_EN# BE49 E49
DGPU_HOLD_RST# VSS_NCTF_12#BE49 VSS_NCTF_30#E49
3 DY 2
BF1 VSS_NCTF_13#BF1 VSS_NCTF_31#F1 F1
1 4 DGPU_PW R_EN# BF49 F49

DGPU_HOLD_RST# VSS_NCTF_14#BF49 VSS_NCTF_32#F49
2 3
RN2209 SRN10KJ-5-GP PANTHER-GP-NF

71.PANTH.00U
RN2202
SRN10KJ-5-GP
1 4 PCH_GPIO36
2 3 PCH_GPIO37
2 1 PLL_ODVR_EN
R2212 DY 1KR2J-1-GP
A M14 DIS A
Wistron Corporation
PLL ON DIE VR ENABLE Taipei Hsien 221, Taiwan, R.O.C.
Title
Weakly internal pull up 20k.
GPIO28 High - Enable PCH (GPIO/CPU)
(PLL_ODVR_EN) Size Document Number Rev
LOW - Disable A3
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
22 of 105
5 4 3 2 1
SSID = PCH Voltage Rail Voltage(V) Iccmax(A)

V_PROC_IO 1.05/1.0 0.002
V5REF 5 0.001
V5REF_Sus 5 0.001
1D05V_PCH
PCH1G POWER 7 OF 10 3D3V_S0
Vcc3_3 3.3 0.178
1.73A 0.063A
AA23 U48 VccADAC 3.3 0.063
SCD1U10V2KX-5GP
SCD01U16V2KX-3GP
VCCCORE1 VCCADAC
D AC23 VCCCORE2 D
1
C2313 C2314 VccADPLLA 1.05 0.075
C2301
C2302
C2303
C2304
AD21
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
CRT
VCCCORE3
1
AD23 U47
AF21
VCCCORE4 VSSADAC DY VccADPLLB 1.05 0.075
DY DY
2
VCC CORE
VCCCORE5
AF23
2
2
VCCCORE6 3D3V_S0
AG21 VCCCORE7
R2304 VccCore 1.05 1.73
AG23 0.001A 0R0603-PAD
VCCCORE8
AG24 AK36 +3VS_VCCA_LVDS 1 2 VccDMI 1.1 0.047
VCCCORE9 VCCALVDS
AG26 VCCCORE10
AG27 VCCCORE11 VSSALVDS AK37 VccIO 1.05 3.799
AG29 VCCCORE12
AJ23 VCCCORE13
VccASW 1.05 0.803
1D8V_S0
LVDS
AJ26 AM37 R2301
VCCCORE14 VCCTX_LVDS1
AJ27 VCCCORE15 0.04A 0R0603-PAD VccSPI 3.3 0.01
AJ29 AM38 +1.8VS_VCCTX_LVDS 1 2
SC10U6D3V3MX-GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
VCCCORE16 VCCTX_LVDS2
w
AJ31 VCCCORE17
VccDSW3_3 3.3 0.001
1D05V_PCH
C2316
C2317
C2318
VCCTX_LVDS3 AP36
1
VccDFTERM 1.8 0.002
AP37
w
VCCTX_LVDS4
AN19 VccRTC 3.3 6uA
2
VCCIO28
.ro
VccSus3_3 3.3 0.065
TP2301 1 VCCAPLLEXP BJ22 3D3V_S0
se
VCCAPLLEXP
0.178A VccSusHDA 3.3 0.01
VCC3_3_6 V33
fix
VccVRM 1.5 0.147
HVCMOS
AN16 VCCIO15
1
C2319
SCD1U10V2KX-5GP VccClkDMI 1.05 0.075
.c
AN17 VCCIO16
V34
2
VCC3_3_7
om
C VccSSC 1.05 0.095 C
AN21 VCCIO17
VccDIFFCLKN 1.05 0.05
1D05V_PCH VCCVRM R2307 1D5V_S0
3.799A AN26 VCCIO18
0.147A 0R0402-PAD VccALVDS 3.3 0.001
AN27 VCCIO19 VCCVRM3 AT16 1 2
VccTX_LVDS 1.8 0.04
1D05VS_VCC_DMI R2306 VCCP_CPU
C2305
C2306
C2307
C2308
C2309
AP21
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
VCCIO20
1
0.047A 0R0402-PAD
DY DY AP23 VCCIO21 VCCDMI1 AT20 1 2 Refer to chipset EDS V.1.8
2
1
DMI
AP24 VCCIO22
VCCIO
C2320
SC1U6D3V2KX-GP
AP26 AB36 check
2
VCCIO23 VCCCLKDMI
AT24 VCCIO24 R2308 1D05V_PCH
0.075A 0R0402-PAD
AN33 +1.05VS_VCC_DMI_CCI 1 2
VCCIO25
1
AN34 VCCIO26 VCCDFTERM1 AG16
3D3V_S0 C2321
0.178A SC1U6D3V2KX-GP
2
BH29 VCC3_3_3 VCCDFTERM2 AG17
DFT / SPI
1
VCCVRM
C2310
AJ16
SCD1U10V2KX-5GP
VCCDFTERM3 1D8V_S0
2
B
AP16 VCCVRM2 0.002A B
VCCDFTERM4 AJ17
1
TP2302 1VCCFDIPLL BG6 C2322
VCCAFDIPLL SCD1U10V2KX-5GP
1D05V_PCH
2
AP17 VCCIO27
V1
FDI
1D05VS_VCC_DMI VCCSPI 3D3V_S5

AU20 VCCDMI2 0.01A
PANTHER-GP-NF 1
71.PANTH.00U C2323
SC1U6D3V2KX-GP
2
A M14 DIS A
Wistron Corporation
Title
PCH (POWER1)
A3 A00
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
23 of 105
5 4 3 2 1
SSID = PCH
PCH1J POWER 10 OF 10 1D05V_PCH
TP2401 1 VCCACLK AD49 N26

3D3V_S5 VCCACLK VCCIO29
0.001A
1
VCCIO30 P26
3D3V_S5 T16 C2438
VCCDSW3_3 SC1U6D3V2KX-GP
P28
2
VCCIO31
1
3D3V_S0 TP2402 1 DCPSUSBYP V12 T27
C2416 DCPSUSBYP VCCIO32 3D3V_S5 5V_S5
D L2401 SCD1U10V2KX-5GP T29 D
2
+V3.3S_VCC_CLKF33 +V3.3S_VCC_CLKF33 VCCIO33 3D3V_S5
1 2 T38 VCC3_3_5
2
IND-10UH-218-GP 0.065A
1
68.10050.10Y 1D05V_PCH T23 D2401
C2402 TP2403 +VCCAPLL_CPY_PCH VCCSUS3_3_7
2nd = 68.1001E.10N DY 1 BH23 VCCAPLLDMI2 83.R0304.A8F CH751H-40PT-GP
1
C2401 SC1U6D3V2KX-GP T24 C2424 2nd = 83.R2004.B8F
2
SC10U6D3V5KX-1GP VCCSUS3_3_8 SCD1U10V2KX-5GP R2408
AL29
1
VCCIO14
V23 1 2
2
VCCSUS3_3_9
USB
TP2404 1 +VCCSUS1 AL24 V24 3D3V_S5 10R2J-2-GP
DCPSUS3 VCCSUS3_3_10
1
1D05V_PCH P24 C2426
VCCSUS3_3_6
0.803A (0.1uFx1) SCD1U10V2KX-5GP
2
1
AA19 VCCASW1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
T26 1D05V_PCH C2425
VCCIO34
C2403
C2404
C2406
SC1U6D3V2KX-GP
C2405
SC1U6D3V2KX-GP
C2419
SC1U6D3V2KX-GP
w
AA21 SCD1U10V2KX-5GP
2
VCCASW2
1
0.001A
w
AA24 M26 +5VA_PCH_VCC5REFSUS
DY DY VCCASW3 V5REF_SUS
w
2
DY
2
AA26 3D3V_S0 5V_S0
Clock and Miscellaneous

VCCASW4
.ro
AN23 +VCCA_USBSUS
DCPSUS4
AA27 VCCASW5
2
AN24 3D3V_S5
se
VCCSUS3_3_1 C2437 D2402
AA29 VCCASW6 DY SC1U10V2KX-1GP 83.R0304.A8F CH751H-40PT-GP
2
fix
AA31 VCCASW7 2nd = 83.R2004.B8F
0.001A R2407
1
+5VS_PCH_VCC5REF
.c
AC26 VCCASW8 V5REF P34 1 2
om
C AC27 10R2J-2-GP C
VCCASW9
1
1D05V_PCH N20 3D3V_S5
VCCSUS3_3_2 C2427
0.075A
PCI/GPIO/LPC
AC29 VCCASW10
L2402 N22 SC1U6D3V2KX-GP
2
+1.05VS_VCCA_A_DPL VCCSUS3_3_3
1 2 AC31 VCCASW11
1
IND-10UH-218-GP P20 3D3V_S0
VCCSUS3_3_4
1
68.10050.10Y C2408 AD29 C2428

VCCASW12
C2407 SC1U6D3V2KX-GP Voltage Rail Voltage(V) Iccmax(A)
SC10U6D3V3MX-GP
2nd = 68.1001E.10N P22
2
VCCSUS3_3_5
SC1U6D3V2KX-GP AD31
DY
2
VCCASW13
1
V_PROC_IO 1.05/1.0 0.002
W21 AA16 C2430
VCCASW14 VCC3_3_1 SCD1U10V2KX-5GP V5REF 5 0.001
2
W23 W16 3D3V_S0
VCCASW15 VCC3_3_8 V5REF_Sus 5 0.001
L2403
0.075A
W24 VCCASW16 VCC3_3_4 T34
1 2 +1.05VS_VCCA_B_DPL Vcc3_3 3.3 0.178
1
IND-10UH-218-GP W26 C2431
VCCASW17
1
68.10050.10Y C2409 SCD1U10V2KX-5GP VccADAC 3.3 0.063

C2410 3D3V_S0
SC10U6D3V3MX-GP
2nd = 68.1001E.10N W29
2
VCCASW18 VccADPLLA 1.05 0.075
SC1U6D3V2KX-GP
DY
2
W31 VCCASW19 VCC3_3_2 AJ2

VccADPLLB 1.05 0.075
1
W33 VCCASW20
VCCIO5 AF13 C2429 VccCore 1.05 1.73
SCD1U10V2KX-5GP
2
+VCCRTCEXT N16 DCPRTC
VccDMI 1.1 0.047
AH13 1D05V_PCH
VCCIO12
1
0.147A VccIO 1.05 3.799

C2411 VCCVRM Y49 AH14
B VCCVRM4 VCCIO13 B
SCD1U10V2KX-5GP VccASW 1.05 0.803
2
1
AF14 C2432 VccSPI 3.3 0.01
+1.05VS_VCCA_A_DPL BD47
VCCIO6 SC1U6D3V2KX-GP DY
2
VCCADPLLA
SATA
VCCAPLLSATA AK1 VccDSW3_3 3.3 0.001
+1.05VS_VCCA_B_DPL BF47 VCCADPLLB +V1.05S_VCCAPLL_SATA3 1 TP2406 VccDFTERM 1.8 0.002
1D05V_PCH R2412 +VCCDIFFCLKN AF11
VCCVRM1 VCCVRM
0.05A 0R0603-PAD +VCCDIFFCLK AF17 VCCIO7
VccRTC 3.3 6uA
1 2 AF33 VCCDIFFCLKN1
AF34 VCCDIFFCLKN2 VCCIO2 AC16 VccSus3_3 3.3 0.065
1
AG34 VCCDIFFCLKN3
C2414 AC17 1D05V_PCH VccSusHDA 3.3 0.01
SC1U6D3V2KX-GP VCCIO3
2
+V1.05S_SSCVCC AG33 VCCSSC VCCIO4 AD17 VccVRM 1.5 0.147
1
VccClkDMI 1.05 0.075
+VCCSST V16 C2435
DCPSST 1D05V_PCH SC1U6D3V2KX-GP VccSSC 1.05 0.095
2
1
C2415
SCD1U10V2KX-5GP T17 DCPSUS1 VCCASW22 T21 VccDIFFCLKN 1.05 0.05
TP2405 1 DCPSUS V19
2
DCPSUS2
VccALVDS 3.3 0.001
MISC
VCCP_CPU V21
1D05V_PCH VCCASW23
R2403 0.002A VccTX_LVDS 1.8 0.04
CPU
0R0402-PAD BJ8
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
+VCCDIFFCLK V_PROC_IO
C2418
C2420
1 2 VCCASW21 T19
1
+3VS_+1.5VS_HDA_IO
Refer to chipset EDS V.1.8
1
C2417 R2402 3D3V_S5

A M14 DIS A
C2412 SC4D7U6D3V3KX-GP 0.01A 0R0402-PAD
2
SC1U6D3V2KX-GP
HDA
A22 P32 1 2
RTC
2
RTC_AUX_S5 VCCRTC VCCSUSHDA

Wistron Corporation
1
1D05V_PCH R2404
6uA PANTHER-GP-NF 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
0R0402-PAD
0.095A C2433 Taipei Hsien 221, Taiwan, R.O.C.
71.PANTH.00U
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
+V1.05S_SSCVCC SCD1U10V2KX-5GP
C2421
C2422
1 2
1
Title
1
C2436
C2413 SC1U6D3V2KX-GP
DY VCCSUSHDA need to be at either 3.3V or 1.5V. PCH (POWER2)
2
SC1U6D3V2KX-GP All the CODEC I/O Voltages need to be at the same Size Document Number Rev
2
A3 A00
level either 3.3 V or 1.5 V. DNE40 14 CR DIS
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
24 of 105
5 4 3 2 1
SSID = PCH
PCH1I 9 OF 10
AY4 VSS159 VSS259 H46

AY42 VSS160 VSS260 K18
B11 VSS163 VSS263 K46
B15 VSS164 VSS264 K7
B19 VSS165 VSS265 L18
B23 VSS166 VSS266 L2
D B27 VSS167 VSS267 L20 D
PCH1H 8 OF 10 B31 L26
VSS168 VSS268
H5 VSS0 B35 VSS169 VSS269 L28
B39 VSS170 VSS270 L36
AA17 VSS1 VSS80 AK38 B7 VSS171 VSS271 L48
AA2 VSS2 VSS81 AK4 F45 VSS172 VSS272 M12
AA3 VSS3 VSS82 AK42 BB12 VSS173 VSS273 P16
AA33 VSS4 VSS83 AK46 BB16 VSS174 VSS274 M18
AA34 VSS5 VSS84 AK8 BB20 VSS175 VSS275 M22
AB11 VSS6 VSS85 AL16 BB22 VSS176 VSS276 M24
w
AC19 VSS13 VSS92 AL27 BC14 VSS183 VSS283 M46
w
AC2 VSS14 VSS93 AL31 BC18 VSS184 VSS284 M8
AC21 AL33 BC2 N18
w
AC24 VSS16 VSS95 AL34 BC22 VSS186 VSS286 P30
.ro
AC33 VSS17 VSS96 AL48 BC26 VSS187 VSS287 N47
AC34 VSS18 VSS97 AM11 BC32 VSS188 VSS288 P11
AC48 AM14 BC34 P18
se
AD10 VSS20 VSS99 AM36 BC36 VSS190 VSS290 T33
AD11 VSS21 VSS100 AM39 BC40 VSS191 VSS291 P40
fix
.c
AD19 VSS24 VSS103 AM46 BD46 VSS194 VSS294 P7
AD24 VSS25 VSS104 AM7 BD5 VSS195 VSS295 R2
om
C AD26 AN2 BE22 R48 C
AD27 VSS27 VSS106 AN29 BE26 VSS197 VSS297 T12
AD33 VSS28 VSS107 AN3 BE40 VSS198 VSS298 T31
AD34 VSS29 VSS108 AN31 BF10 VSS199 VSS299 T37
AD36 VSS30 VSS109 AP12 BF12 VSS200 VSS300 T4
AD37 VSS31 VSS110 AP19 BF16 VSS201 VSS301 W34
AD40 VSS35 VSS114 AP38 BF26 VSS205 VSS305 V11
AD43 VSS37 VSS116 AP42 BD3 VSS207 VSS307 V26
AD8 VSS40 VSS119 AR2 BF40 VSS210 VSS310 V31
AE2 VSS41 VSS120 AR48 BF8 VSS211 VSS311 V36
AE3 VSS42 VSS121 AT11 BG17 VSS212 VSS312 V39
AF10 VSS43 VSS122 AT13 BG21 VSS213 VSS313 V43
AF12 VSS44 VSS123 AT18 BG33 VSS214 VSS314 V7
AD14 VSS45 VSS124 AT22 BG44 VSS215 VSS315 W17
AD16 VSS46 VSS125 AT26 BG8 VSS216 VSS316 W19
AF16 VSS47 VSS126 AT28 BH11 VSS217 VSS317 W2
AF26 VSS50 VSS129 AT34 BH19 VSS220 VSS320 Y12
AF27 VSS51 VSS130 AT39 H10 VSS221 VSS321 Y38
B B
AF4 VSS55 VSS134 AU24 BH35 VSS225 VSS325 Y8
AF42 VSS56 VSS135 AU30 BH39 VSS226 VSS328 BG29
AF46 VSS57 VSS136 AV16 BH43 VSS227 VSS329 N24
AF5 VSS58 VSS137 AV20 BH7 VSS228 VSS330 AJ3
AF7 VSS59 VSS138 AV24 D3 VSS229 VSS331 AD47
AF8 VSS60 VSS139 AV30 D12 VSS230 VSS333 B43
AG19 VSS61 VSS140 AV38 D16 VSS231 VSS334 BE10
AG2 VSS62 VSS141 AV4 D18 VSS232 VSS335 BG41
AG31 VSS63 VSS142 AV43 D22 VSS233 VSS337 G14
AG48 VSS64 VSS143 AV8 D24 VSS234 VSS338 H16
AH11 VSS65 VSS144 AW14 D26 VSS235 VSS340 T36
AH3 VSS66 VSS145 AW18 D30 VSS236 VSS342 BG22
AH36 VSS67 VSS146 AW2 D32 VSS237 VSS343 BG24
AH39 VSS68 VSS147 AW22 D34 VSS238 VSS344 C22
AH40 VSS69 VSS148 AW26 D38 VSS239 VSS345 AP13
AH42 VSS70 VSS149 AW28 D42 VSS240 VSS346 M14
AH46 VSS71 VSS150 AW32 D8 VSS241 VSS347 AP3
AH7 VSS72 VSS151 AW34 E18 VSS242 VSS348 AP1
AJ19 VSS73 VSS152 AW36 E26 VSS243 VSS349 BE16
AJ21 VSS74 VSS153 AW40 G18 VSS244 VSS350 BC16
AJ24 VSS75 VSS154 AW48 G20 VSS245 VSS351 BG28
AJ33 VSS76 VSS155 AV11 G26 VSS246 VSS352 BJ28
AJ34 VSS77 VSS156 AY12 G28 VSS247
AK12 VSS78 VSS157 AY22 G36 VSS248
AK3 VSS79 VSS158 AY28 G48 VSS249
H12 VSS250
PANTHER-GP-NF H18 VSS251
71.PANTH.00U H22 VSS252
A H24 VSS253 M14 DIS A
H26 VSS254
H30 VSS255
H32
H34
VSS256
VSS257
Wistron Corporation
F3 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
VSS258 Taipei Hsien 221, Taiwan, R.O.C.
Title
PANTHER-GP-NF
71.PANTH.00U PCH (VSS)
A3 A00
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
25 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
26 of 105
SSID = KBC 5 4 3 2 VBAT 1
VBAT A00
0905
PCB VER AD(GPIO91) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
1
VBAT 3D3V_S0 X00 100.0K 10.0K 3.0V OAK14_UMA 100.0K 10.0K(64.10025.6DL) 3.0V
3D3V_AUX_KBC R2724
N13MR2713 R2710
N13PR2712 OAK14_DIS_N13P 100.0K 20.0K(64.20025.6DL) 2.75V
33KR2F-GP
20KR2F-L-GP
10KR2F-2-GP
R2702 47KR2F-GP X01 100.0K 20.0K 2.75V OAK14_DIS_N13M 100.0K 33.0K(64.33025.6DL) 2.48V
0R0603-PAD TBD 100.0K 47.0K(64.47025.6DL) 2.24V
1 2 VBAT X02 100.0K 33.0K 2.48V UMA TBD 100.0K 64.9K(64.64925.6DL) 2.0V
2
1
1
PCB_VER_AD MODEL_ID_DET TBD 100.0K 76.8K(64.76825.6DL) 1.87V
2
C2702 C2703 A00 100.0K 47.0K 2.24V TBD 100.0K 100.0K(64.10035.6DL) 1.65V
DY
1
R2771 SCD1U10V2KX-5GP SC2D2U10V3KX-1GP R2726 TBD 100.0K 143.0K(64.14335.6DL) 1.358V
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
2
2D2R3-1-U-GP C2717 100KR2F-L1-GP Reserved 100.0K 64.9K 2.0V C2718 R2739 TBD 100.0K 174.0K(64.17435.6DL) 1.204V
2
100KR2F-L1-GP TBD 100.0K 215.0K(64.21535.6DL) 1.048V
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3D3V_AUX_KBC_VCC Reserved 100.0K 76.8 1.87V
DY DY
1
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3D3V_AUX_S5
2
C2701
C2704
C2705
C2706
C2707
C2708
Reserved 100.0K 100.0K 1.65V
1
1
EC_VBKUP 1
C2709
C2710
2 RTC_AUX_S5
0R0402-PAD R2794 Reserved 100.0K 143.0K 1.358V
DY DY DY
D EC_AGND
D
2
115
102
114
C2711 Reserved 100.0K 174.0K 1.204V EC_AGND
19
46
76
88
75
4
U2701A 1 0F 2 SC220P50V2KX-3GP
1 2 Reserved 100.0K 215.0K 1.048V
DY
VCC1
VCC2
VCC3
VCC4
VCC5
VSBY
VBKUP
AVCC
VDD
EC_AGND
C2714 1 2 SCD1U10V2KX-5GP 104 7 PLT_RST#_EC 1 R2778 2

EC_AGND VREF LRESET#/GPIOF7 PLT_RST# 5,18,31,65,71,83
2 0R0402-PAD CLK_PCI_KBC 18
LCLK/GPIOF5
40 AD_IA 97 3 LPC_FRAME# 21,71 LPC_AD[3..0] 21,71
PCB_VER_AD GPIO90/AD0 LFRAME#/GPIOF6 LPC_AD3
98 1
3D3V_AUX_KBC GPIO91/AD1 LAD3/GPIOF4 LPC_AD2
38 PSID_EC 99 128
GPIO92/AD2 LAD2/GPIOF3 LPC_AD1
100 127
SERIES_ID GPIO93/AD3 LAD1/GPIOF2 LPC_AD0
108 126
VGA_THRM GPIO5/AD4 LAD0/GPIOF1
96 125 INT_SERIRQ 21
GPIO4/AD5 SERIRQ/GPIOF0
1
1 USBCHARGER_CB0 95 8
TP2720 GPIO3/AD6 GPIO11/CLKRUN# PM_CLKRUN#_EC 19
R2737 MODEL_ID_DET 94 9 PANEL_BLEN 1 R2761 2
GPIO7/AD7 GPIO65/SMI# L_BKLT_EN 17
Ins 100KR2J-1-GP 29 ECSCI#_KBC 0R0402-PAD U2701B 2 0F 2
ECSCI#/GPIO54 KCOL[16..0] 69
101 124 BOOST_MODE# 40
28 FAN1_DAC GPIO94/DA0 GPIO10/LPCPD# KCOL0
40 AD_IA_HW 105 121 H_A20GATE 22 28 FAN_TACH1 31 53
2
GPIO95/DA1 GPIO85/GA20 GPIO56/TA1 KBSOUT0/GPOB0/JENK# KCOL1

106 122 H_RCIN# 22 31 PCIE_WAKE# 63 52
SERIES_ID GPIO96/DA2 KBRST#/GPIO86 GPIO14/TB1 KBSOUT1/GPIOB1/TCK KCOL2
36,42 IMVP_PWRGD 107 19,36,37,47 PM_SLP_S3# 64 51
GPIO97/DA3 GPIO1/TB2 KBSOUT2/GPIOB2/TMS
w
50 KCOL3
1
KBSOUT3/GPIOB3/TDI KCOL4
68 PWRLED# 32 49
R2738 R2793 1 BATLOW#_EC GPIO15/A_PWM KBSOUT4/GPOB4/JEN0# KCOL5
2 0R2J-2-GP 79 27 118 48
DY
w
19 BATLOW# GPIO02 GPIO52/PSDAT3/RDY# BLON_OUT 49 29 KBC_BEEP GPIO21/B_PWM KBSOUT5/GPIOB5/TDO
Vos 100KR2J-1-GP ECSMI#_KBC 6 25 AD_IA_HW2 OVER_CURRENT_P8# 62 47 KCOL6
GPIO24 GPIO50/PSCLK3/TDO AD_IA_HW2 40 86 OVER_CURRENT_P8# GPIO13/C_PWM KBSOUT6/GPIOB6/RDY#
109 11 AC_IN_KBC# 65 43 KCOL7
69 CAP_LED# PWR_CHG_AD_OFF 38 38 AC_IN_KBC#
w
GPIO30/F_WP# GPIO27/PSDAT2 GPIO32/D_PWM KBSOUT7/GPIOB7 KCOL8
36 S5_ENABLE 14 10 CARD_WLAN_OUT# 65 68 WLAN_LED# 22 42
2
GPIO34/CIRRXL GPIO26/PSCLK2 GPIO45/E_PWM KBSOUT8/GPIOC0

68 BATT_WHITE_LED# 15 71 TPDATA 69 TP2721 1KB_BL_CTRL 81 41 KCOL9
GPIO36 GPIO35/PSDAT1 GPIO66/G_PWM KBSOUT9/GPOC1/SDP_VIS#
.ro
KCOL10
39 BAT_IN# 80
17
GPIO41/F_WP# GPIO37/PSCLK1
72 TPCLK 69 <------ TP 49 KBC_BKLT 66
16
GPIO33/H_PWM KBSOUT10&P80_CLK/GPIOC2
40
39 KCOL11
70 LID_CLOSE# GPIO42/TCK 68 CHG_AMBER_LED# GPIO40/F_PWM KBSOUT11&P80_DAT/GPIOC3
20 38 KCOL12
19 RSMRST#_KBC GPIO43/TMS KBSOUT12/GPIO64 KCOL13
19,46 PM_SLP_S4# 21 70 BAT_SCL 39,40 <------ BATTERY / CHARGER 37
se
GPIO44/TDI GPIO17/SCL1/N2TCK KBSOUT13/GPIO63 KCOL14
22,92,93 DGPU_PWROK 26 69 BAT_SDA 39,40 21 ME_UNLOCK 23 36
ECSWI#_KBC GPIO51/N2TCK GPIO22/SDA1/N2TMS GPIO46/CIRRXM/TRIST# KBSOUT14/GPIO62 KCOL15
123 67 SML1_CLK 20,28,86 65 E51_RxD 113 35
GPIO67N2TMS GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR KBSOUT15/GPIO61/XOR_OUT KCOL16
65 WIFI_RF_EN 82
GPIO75 GPIO74/SDA2
68 SML1_DATA 20,28,86 <------PCH / eDP 65 E51_TxD 111
GP/I/O83/SOUT_CR/TRIST# GPIO60/KBSOUT16
34
fix
BLUETOOTH_EN 83 119 PROCHOT_EC 33 KBC_GPIO57 1
65 BLUETOOTH_EN GPIO76 GPIO23/SCL3 GPIO57/KBSOUT17 TP2717
Layout Note: 19,36 S0_PWR_GOOD 84
GPIO77 GPIO31/SDA3
120
24
RTCRST_ON 21
PM_LAN_ENABLE 31 19 PCH_SUSCLK_KBC 77 54 KROW0
KROW[7..0] 69
GPIO47/SCL4 GPIO0/EXTCLK KBSIN0/GPIOA0/N2TCK KROW1
Need very close to EC 28 30 55
.c
GPIO53/SDA4 LCD_TST_EN 49 29 AMP_MUTE# GPIO55/CLKOUT/IOX_DIN_DIO KBSIN1/GPIOA1/N2TMS
33R2J-2-GP 1 R2736 2 EC_SPI_CS#_C 90 1 R2792 2 56 KROW2
21,60 SPI_CS0#_R F_CS0# LCD_TST 49 KBSIN2/GPIOA2
33R2J-2-GP 1 R2719 2 EC_SPI_CLK_C 92 0R0402-PAD ECRST# 85 57 KROW3
C 21,60 SPI_CLK_R F_SCK VCC_POR# KBSIN3/GPIOA3
C
om
33R2J-2-GP 1 R2725 2 EC_SPI_DI_C 86 74 PSL_OUT# R2721 58 KROW4
21,60 SPI_SO_R F_SDI&F_SDIO1 PSL_OUT_GPIO71# VCCP_CPU KBSIN4/GPIOA4
33R2J-2-GP 1 R2722 2 EC_SPI_DO_C 87 93 PSL_IN2# 43R2J-GP 59 KROW5
21,60 SPI_SI_R F_SDIO&F_SDIO0 PSL_IN2_GPI06# KBSIN5/GPIOA5
91 73 PSL_IN1# 1 2 PECI 13 60 KROW6
65 CARD_WPAN_OUT# GPIO81/F_WP# PSL_IN1_GPI70# 5,22 H_PECI PECI KBSIN6/GPIOA6
1 R2720 2 EC_VTT 12 61 KROW7
0R0402-PAD VTT KBSIN7/GPIOA7
1
19 PM_PWRBTN# 117 C2716
GPIO20/TA2/IOX_DIN_DIO NPCE885PA0DX-GP
19,86 AC_PRESENT 112
GP/I/O84/IOX_SCLK/XORTR#
SCD1U10V2KX-5GP
110 44 KBC_VCORF
61 USB_PWR_EN#
2
GPO82/IOX_LDSH/TEST# VCORF R2766
1
0R0402-PAD
AGND
GND1
GND2
GND3
GND4
GND5
GND6
C2712
SC1U10V3KX-4GP-U Layout Note: 1 2
2
Need very close to EC D2702
NPCE885PA0DX-GP 20 EC_SWI# 1
18
45
78
89
116
5
103
ECSWI#_KBC
Layout Note: DY 3
EC_AGND
Need very close to EC 2

83.00016.K11
BAS16-6-GP
2nd = 83.00016.F11
R2765 Layout Note: R2764
1 2 Connect GND and AGND planes via either 0R0402-PAD
0R0402-PAD 3D3V_AUX_S5 1 2
0R resistor or connect directly.
D2703
1
EC_AGND ECRST# 1
22 EC_SCI#
R2705
ECSCI#_KBC
10KR2J-3-GP
DY 3
EC_GPIO23 High Active 2

83.00016.K11
1
C2715
E
SC1U6D3V2KX-GP BAS16-6-GP
PROCHOT_EC
28,36,86 PURE_HW_SHUTDOWN# B
2nd = 83.00016.F11
2
Q2701 R2723
MMBT3906-4-GP DY 0R0402-PAD
C
84.T3906.A11 1 2
G
Q2702 2nd = 84.03906.F11

2N7002BK-GP R2733 D2704
1
0R0402-PAD 1
100KR2J-1-GP
22 EC_SMI#
R2732 S D H_PROCHOT#_EC 1 2 H_PROCHOT# 5,38,40,42
B DY 3 ECSMI#_KBC
B
1
84.07002.I31 2
83.00016.K11
2
C2720
SC47P50V2JN-3GP BAS16-6-GP
2nd = 84.2N702.W31 2nd = 83.00016.F11
2
3rd = 84.2N702.J31 C502 : check list 1.5
3D3V_AUX_S5
Power Switch Logic(PSL) EC GPIO standard PH/PL 3D3V_AUX_KBC

2
3D3V_AUX_S5
3D3V_AUX_S5 RN2701
R2734
330KR2J-L1-GP C2722 BAT_SCL 3 2
SCD1U10V2KX-5GP BAT_SDA 4 1
2
1 2
1
R2704
SRN4K7J-8-GP
330KR2J-L1-GP
R2767 RN2708
S
R2735
0R0402-PAD BAT_IN# 4 1
1
1 2 PSL_IN2# PSL_OUT# 1 2 KBC_ON#_GATE G Q2703 VGA_THRM R2708 1 2 10KR2J-3-GP PCIE_WAKE# 3 2

68 KBC_PWRBTN# G
R2791 DY
20KR2F-L-GP D
DMP2130L-7-GP
DY 0R2J-2-GP SRN100KJ-6-GP
R2768
0R0402-PAD 84.02130.031 EC_AGND ECRST# R2707 1 2 10KR2J-3-GP
1
D
1 2 PSL_IN1# 3D3V_AUX_KBC
40 AC_IN#
2nd = 84.00102.031 BOOST_MODE# R2711 1 2 10KR2J-3-GP
DY
2
BLUETOOTH_EN R2714 1 2 10KR2J-3-GP

R2709
3rd = 84.03413.A31 3D3V_AUX_KBC DY
4th = 84.02301.G31 OVER_CURRENT_P8# R2716 1 2 100KR2J-1-GP
10KR2J-3-GP
DY
AC_IN_KBC# R2717 1 2 100KR2J-1-GP
S5_ENABLE 1
RN2706 X00 0608

RSMRST#_KBC 4 1 3D3V_S0
S0_PWR_GOOD 3
DY 2
A SRN100KJ-6-GP E51_RxD R2715 1

DY 2 10KR2J-3-GP
A
D
G M14 DIS
Q2706
2N7002BK-GP Wistron Corporation
84.07002.I31 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
S
2nd = 84.2N702.W31 Taipei Hsien 221, Taiwan, R.O.C.

3rd = 84.2N702.J31
Title
KBC Nuvoton NPCE885

http://vinafix.vn
A2
5 4 03-05-1512:40:57
03-05-151:22:21
3 PM
PM 2
1
Sheet 27 of 105
5 4 3 2 1
3D3V_S0
SSID = Thermal 2
RN2801
3 Fan controller
1 4
Thermal sensor NCT7718W SRN2K2J-1-GP

NCT3940S-A
6 1 THM_SML1_DATA
20,27,86 SML1_DATA
D D
3D3V_S0 5 2
84.2N702.A3F
4 3 2nd = 84.DM601.03F
1
C2805 C2802 3rd = 84.2N702.E3F
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
Q2804 4th = 84.2N702.F3F U2802
2N7002KDW -GP R2802
2
THM_SML1_CLK 1 DY 2 FON# 1 8
FON# GND
5V_S0 5V_S0 0R2J-2-GP 2 VIN GND 7
FAN_VCC 3 6
20,27,86 SML1_CLK VOUT GND
27 FAN1_DAC 4 VSET GND 5
*Layout* 10 mil
NCT7718_DXP NCT3940S-A-GP
For linear FAN
1
U2801
1
2ND = 84.03904.P11
w
C2803 C2804
3
1
84.03904.L06 74.03940.A71
DY C2806 1 8 THM_SML1_CLK SC4D7U6D3V3KX-GP SCD1U10V2KX-5GP
2
VDD SCL
w
R2808 SC470P50V2KX-3GP C2807 THM_SML1_DATA
DY 1 2 7
2
NTC-100K-8-GP Q2801 SC2200P50V2KX-2GP D+ SDA ALERT#

3 6
w
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
D- ALERT#
PMBS3904-1-GP X02 0730 change main source
C2808
C2812
4 5
2
T_CRIT# GND
.ro
NCT7718_DXN Reserved for
2.System Sensor, Put on palm rest NCT7718W -GP DY DY signal quality

improvement.
se
2
2
R2813
0R0402-PAD 74.07718.0B9
fix
THERM_SYS_SHDN# 1 2 T_CRIT#
.c
om
C C
3D3V_S0
ALERT# R2815 1
R5 2 18K7R2F-GP
T_CRIT# R2814 1 2 2KR2F-3-GP
R7
3D3V_S0
Fan Connecter
2
R2820
Layout notice : 10KR2J-3-GP
Both DXN and DXP routing 10 mil FAN1
trace width and 10 mil spacing. and route has to be away from the high noise area. R2807
1
0R0402-PAD AFTP2803 1 5
B Put the C2807 2200pF to close the NCT7718W FAN_TACH1_C B
27 FAN_TACH1 1 2 3
2
*Layout* 15 mil
FAN_VCC 1
4
SC2200P50V2KX-2GP
SCD1U16V2KX-3GP
CH551H-30PT-GP
2
D2802
EC2801
3D3V_S0 ETY-CON3-8-GP
C2810
1
1
C2809 DY 20.F1841.003
SC4D7U6D3V3KX-GP DY DY
1
2
Q2802 R2809
2N7002BK-GP 100KR2J-1-GP
DY
83.R5003.C8F
AFTP2802 1FAN_TACH1_C 2nd = 83.R5003.G8H
2
27,36,86 PURE_HW _SHUTDOW N# D S THERM_SYS_SHDN# AFTP2801 1FAN_VCC 3rd = 83.R5003.H8H

4th = 83.5R003.08F
84.07002.I31
1
C2811 2nd = 84.2N702.W31

G
SCD1U10V2KX-5GPDY 3rd = 84.2N702.J31

2
3D3V_S0
A M14 DIS A
Wistron Corporation
Title
Thermal NCT7718W/Fan Controllor P2793
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
28 of 105
5 4 3 2 1
AUD_AGND
AUD_AGND
SSID = AUDIO
HV mode : performance up , chip power consumption up 58 MIC2-VREFO AUD_EAPD#
LV mode : performance down , chip power consumption down
3D3V_S0 25mA +3V_AVDD 58 AUD_HP1_JACK_L +5V_AVDD 5V_S0
3D3V_S0 +3V_1D5V_AVDD 58 AUD_HP1_JACK_R R2911
R2906 1 2 0R0402-PAD 0R0603-PAD
SC2D2U6D3V2MX-GP
R2902 1 DY 2 0R2J-2-GP 1 2
SC10U6D3V3MX-GP
SC1U6D3V2KX-GP
2
1D5V_S0
1
D C2920 C2914 C2915 D
R2903 1 2 0R0402-PAD
1 C2917
1 C2916
SC4D7U6D3V3KX-GP
Layout Note:
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
1
2
1
Place close to Pin 26
+3V_AVDD
C2903
SC4D7U6D3V3KX-GP
1
60mA close to pin 36
2
5V_S0 +5V_PVDD
CPVEE 2
R2912 AUD_AGND AUD_AGND
AUD_VREF
LDO1_CAP
+5V_AVDD
0R0603-PAD close to pin 40
C2918
CBN
1 2 AUD_AGND
1
C2921
R2913 C2904 C2905 C2907 C2906 SC1U10V2KX-1GP
1
1
0R0603-PAD
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
w
36
35
34
33
32
31
30
29
28
27
26
25
1 2
U2901
2
HP_OUT_L
LINE1/MIC1_VREFO-L
AVDD1
AVSS1
MIC2_VREFO
CPVDD
CBN
HP_OUT_R
LINE1/MIC1_VREFO-R
CPVEE
LDO1_CAP
VREF
w
.ro
AUD_AGND CBP 37 24
CBP LINE2_L
Layout Note: 38 23
se
SC10U6D3V3MX-GP AVSS2 LINE2_R
Layout Note: AUD_AGND 2 1 C2901 LDO2_CAP 39 LDO2_CAP LINE1_L 22
Close PIN41 Close PIN46 Analog +3V_1D5V_AVDD 40 AVDD2 LINE1_R 21
fix
+5V_PVDD 41 PVDD1 CPVREF/MIC1_R 20
AUD_SPK_L+ C2902 R2924
DigiTal 58 AUD_SPK_L+ AUD_SPK_L-
42 SPK_L+ MIC_CAP/MIC1_L 19
SC4D7U6D3V3KX-GP 1KR2J-1-GP
.c
58 AUD_SPK_L- 43 SPK_L- SLEEVE/MIC2_R 18
R2908 1 2 0R0603-PAD AUD_SPK_R- 44 17 RING2_R 1 2 RING2_C 1 2
58 AUD_SPK_R- SPK_R- RING2/MIC2_L SLEEVE 58
om
C AUD_SPK_R+ 45 16 C
58 AUD_SPK_R+ SPK_R+ MONO_OUT
GPIO0/DMIC_DATA
+5V_PVDD 46 15 JDREF 1 2 AUD_AGND
PVDD2 JDREF
GPIO1/DMIC_CLK
R2909 1 2 0R0603-PAD CH751H-40PT-GP 1 2 D2901 EAPD# 47 14 R2916 20KR2F-L-GP
27 AMP_MUTE# COMBO-GPI PDB SENSEB AUD_SENSE_A 1
83.R0304.A8F 48 SPDIFO/GPIO2 SENSEA 13 2 AUD_SENSE AUD_SENSE 58
SDATA_OUT
2nd = 83.R2004.B8F 49
LDO3_CAP
GND
SDATA_IN
R2910 2 0R0603-PAD DY R2917
1 1 2
Layout Note:
DVDD_IO
PCBEEP
BIT_CLK
RESET#
R2921 0R2J-2-GP 39K2R2F-L-GP
DVDD
SYNC
DVSS
1 DY 2 Place close to Pin 13
R2923
10KR2J-3-GP
AUD_AGND Layout Note: ALC3221-CG-GP
Analog
3D3V_S0 1 DY 2 71.03221.A03
1
2
3
4
5
6
7
8
9
10
11
12
Tied at point only under R2918
DigiTal
Codec or near the Codec 1KR2J-1-GP
1 LDO3_CAP
58 COMBO-GPI
3D3V_S0 3D3V_S0
ALC3221 : 71.03221.A03
1
C2909 C2908 AUD_PC_BEEP 2SB_SPKR_R
C2911
C2910
1 2 1 HDA_SPKR 21
Azalia I/F EMI R2914
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
1
C2912 1KR2J-1-GP
2
SCD1U10V2KX-5GP
1
2
2
ER2902 EC2924 C2922 DY R2919
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
47R2J-2-GP SCD1U10V2KX-5GP SC100P50V2JN-3GP DY 10KR2J-3-GP
2
DMIC: > 5mil and keep out the analog signal
HDA_CODEC_SDOUT
1 2PCH_AZ_CODEC_SDOUT1
1 DY 2
DY
2
HDA_CODEC_BITCLK
2 1HDA_CODEC_BITCLK_C 1 DY 2 R2904 1 2 DMIC_DATA_R
DY close to pin 3
49 DMIC_DATA R2905 1 20R2J-2-GP DMIC_CLK_R
B ER2901 EC2922 49 DMIC_CLK 0R2J-2-GP B
21 HDA_CODEC_SDOUT 1 2KBC_BEEP_R 2 1 KBC_BEEP 27
47R2J-2-GP SC22P50V2JN-4GP R2915
DMIC_CLK 21 HDA_CODEC_BITCLK C2913 1KR2J-1-GP
R2907 SCD1U10V2KX-5GP
2
1
1 2 HDA_CODEC_SDIN0
C2919 21 HDA_SDIN0 33R2J-2-GP C2923 DY R2920
SC22P50V2JN-4GP HDA_CODEC_SYNC SC100P50V2JN-3GP DY 10KR2J-3-GP
1
2
21 HDA_CODEC_SYNC HDA_CODEC_RST#
21 HDA_CODEC_RST#
2
3D3V_S0 2
R2922 DY 1
10KR2J-3-GP
D2902 Depop sound
27 AMP_MUTE# 1
3D3V_S0
3 58 AUD_HP1_JACK_R1 AUD_HP1_JACK_R1
1
AUD_EAPD#
POP R2926 AUD_HP1_JACK_L1
2 58 AUD_HP1_JACK_L1
POP 220KR2J-L2-GP
BAT54A-7-F-GP
R2925
E
83.BAT54.V01
2
AUD_PD#_C 2 POP 1 AUD_PD#_C1 B POP

Q2901
C
22KR2J-GP MMBT3906-4-GP
C
1
84.T3906.A11 HP_MUTE 2 1HP_MUTE_R R2928 2 POP 1 1KR2J-1-GP HP_MUTE_RC2 B POPQ2902

POP BTD2040N3S-GP
POP C2950 2nd = 84.03906.F11
C
R2927
SC10U6D3V3MX-GP
2
E
4K7R2J-2-GP
1
A R2929 2 POP 1 1KR2J-1-GP HP_MUTE_RC1 B POPQ2903 M14 DIS A

C2949 BTD2040N3S-GP
DY SC10U6D3V3MX-GP
84.02043.011
2
E
84.02043.011 Wistron Corporation
AUD_AGND AUD_AGND AUD_AGND 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
Audio Codec ALC3221

A3
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
29 of 105
5 4 3 2 1
D D
w
w
w
(Blanking)
.ro
se
fix
.c
om
C C
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
30 of 105
5 4 3 2 1
3D3V_LAN_S5
EVDD10 R3115 DVDD10

0R0603-PAD
LAN CHIP
1
1 2
C3106 R3101
1
C3113 C3109 C3114 C3117 10KR2J-3-GP
1
SC1U10V3ZY-6GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
R3104
2
10KR2J-3-GP
CLK_LAN_REQ#_EN
X5R
2
D D
84.03904.L06
2ND = 84.03904.P11
1
Q3101
1mS < +3D3V_LAN_S5 Rising time (10%~90%) <100mS PMBS3904-1-GP
3D3V_LAN_S5
3D3V_LAN_S5
3D3V_LAN_S5
20 PCIE_CLK_LAN_REQ# 3 2 CLK_LAN_REQ#_R
LANXOUT
R3117
40 mils
DVDD10
LANXIN
3D3V_LAN_S5 close to pin 27 39 47 48 2 1
DY
GPO
0R2J-2-GP
R3113
w
2K49R2F-GP
1
C3118 C3121 C3119 C3129 1 2 EESK 1 TP3102 TPAD14-OP-GP
w
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U10V2KX-5GP
For Switch Regulator enable
w
2
3D3V_LAN_S5
.ro
48
47
46
45
44
43
42
41
40
39
38
37
U3101
2
49
AVDD33
AVDD33
AVDD10
CKXTAL2
CKXTAL1
NC#42
NC#41
LED0
DVDD3
EESK/LED1
GPO
RSET
se
GND R3105
DY 0R2J-2-GP
fix
R3124 DVDD10
0R2J-2-GP R3106
1
2 R3108 1 0R0402-PAD LAN_MDI0P_1 1 REGOUT 0R0402-PAD
.c
59 LAN_MDI0P
2 R3111 1 0R0402-PAD LAN_MDI0N_1 2 MDIP0 REGOUT 36
35 AVDD33_REG
1
DY 2
1 2
59 LAN_MDI0N MDIN0 VDDREG
om
C 3 34 AVDD33_REG C
NC#3 VDDREG
59 LAN_MDI1P 2 R3112 1 0R0402-PAD LAN_MDI1P_1 4
MDIP1 ENSWREG 33 ENSW REG
59 LAN_MDI1N 2 R3116 1 0R0402-PAD LAN_MDI1N_1 5
MDIN1 EEDI 32 EEDI/SDA
3D3V_LAN_S5 6 31
NC#6 EEDO/LED3 R3107 1 2 10KR2J-3-GP
7
8
NC#7 EECS 30
29 DVDD10 DY
NC#8 DVDD10 3D3V_S0
9 NC#9 LANWAKE# 28 PCIE_W AKE# 27
2
1
10 27 3D3V_LAN_S5
RN3101 NC#10 DVDD33 ISOLATE#
11 NC#11 ISOLATE# 26 2 1
SRN10KJ-5-GP 12 25 PLT_RST#_LAN R3110
DY NC#12 PERST#
1
LAN_MDI0P 1KR2J-1-GP
LAN_MDI0N R3109
REFCLK_N
REFCLK_P
LAN_MDI1P
CLKREQ#
1Q402_13
4
DVDD10
EVDD10
LAN_MDI1N 15KR2F-GP
NC#14
NC#15
HSON
HSOP
HSIN
HSIP
GND
2
1
1
EC3101 EC3102 EC3103 EC3104 RTL8105E-VD-CGT-GP
13
14
15
16
17
18
19
20
21
22
23
24
2 3 PLT_RST#_LAN DY DY DY DY 71.08105.B03
5,18,27,65,71,83 PLT_RST# DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2
Q3104 DVDD10
PMBS3904-1-GP C3102
R3123 LANXOUT 1 2
1 2
CLK_LAN_REQ#_R SC18P50V2JN-1-GP
0R0402-PAD LAN_RXP_C_PCH_TXP6
LAN_RXN_C_PCH_TXN6
CLK_PCIE_LAN
3
CLK_PCIE_LAN#
B X3102 B
251mA EVDD10 XTAL-25MHZ-155-GP
3D3V_S0 3D3V_LAN_S5
R3119
LAN_TXP_C_PCH_RXP6
1
C3131 LAN_TXN_C_PCH_RXN6
1
DY 2
2
0R3J-0-U-GP
SCD1U10V2KX-5GP
R3120
2
DY
1 2
3D3V_LAN_S5
0R3J-0-U-GP C3103
3D3V_S5 PA102FMG-GP-U LANXIN 1 2
Q3103 main: 84.00102.031 R3103 1
DY 2 1KR2J-1-GP GPO
SC18P50V2JN-1-GP
2nd: 84.03403.031 R3114
S D 1 2 EEDI/SDA
1
C3105 SCD1U10V2KX-5GP
1
R3121 10KR2J-3-GP LAN_TXP_C_PCH_RXP6 1 2 PCH_RXP_C_LAN_TXP6 20

1
C3130 10KR2J-3-GP C3128 LAN_TXN_C_PCH_RXN6 1 2 PCH_RXN_C_LAN_TXN6 20

G
SCD1U10V2KX-4GP
SCD1U10V2KX-5GP C3125 close to pin 21 22 C3104 SCD1U10V2KX-5GP

2
DY
1
R3118 SC1U10V2KX-1GP LAN_RXP_C_PCH_TXP6

LAN_RXP_C_PCH_TXP6 20
2
20KR2F-L-GP LAN_RXN_C_PCH_TXN6
1 2 PM_LAN_ENABLE_R
DY LAN_RXN_C_PCH_TXN6 20
2
CLK_PCIE_LAN 20
LAN_ENABLE_R_C
CLK_PCIE_LAN# 20
A M14 DIS A
Q3102
27 PM_LAN_ENABLE G
Wistron Corporation
1
D
R3122 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
100KR2J-1-GP S Taipei Hsien 221, Taiwan, R.O.C.
2N7002K-2-GP Title
2
LOM
A3
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03-05-151:22:21 PM 3 2
1
31 of 105
5 4 3 2 1
SSID = SDIO
D D
3D3V_S0 250mA
3D3V_CARD_S0 C3208
43mA
SDREG 1 2
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
C3211
1 SC1U6D3V2KX-GP
1
V18
C3204
C3203
2 1
w
SC1U6D3V2KX-GP
2
w
24
23
w
4
7
U3201
.ro
V18
CARD_3V3
XD_D7
XD_CD#
SDREG
3V3_IN
R3208
0R0402-PAD
se
74 XD_RDY/SD_W P/MS_CLK 1 2 XD_RDY/SD_W P/MS_CLK_R 8 15 XD_D0/SD_CLK/MS_D2 R3209 2 1 33R2J-2-GP
SP1 SP8 XD_D0/SD_CLK/MS_D2_R 74
74 XD_RE#/MS_INS# XD_RE#/MS_INS# 9 16 XD_D1/SD_D5/MS_D0 XD_D1/SD_D5/MS_D0 74
SP2 SP9
fix
74 XD_CE#/SD_D1 XD_CE#/SD_D1 10 18 XD_D2/SD_CMD XD_D2/SD_CMD 74
SP3 SP10
2
XD_CLE/SD_D0/MS_D7
74 XD_CLE/SD_D0/MS_D7
XD_ALE/SD_D7/MS_D3
11 SP4 SP11 19
XD_D4/SD_D3/MS_D1
For EMI EC3201
.c
12 20
74 XD_ALE/SD_D7/MS_D3
74 XD_W E#/SD_CD# XD_W E#/SD_CD# 13
SP5 SP12
21 XD_D5/SD_D2/MS_D5
XD_D4/SD_D3/MS_D1 74
XD_D5/SD_D2/MS_D5 74
DY SC10P50V2JN-4GP
1
SP6 SP13
om
C 14 22 XD_D6/MS_BS XD_D6/MS_BS 74
C
SP7 SP14
GPIO0
RREF
GND
DM
DP
RTS5170-GR-GP 71.05170.003
2
3
17
25
RREF
USB_PN10_R
2
USB_PP10_R CR_GPIO0 1
R3201 TP3201
6K2R2F-GP
B Close U3201 B
R3212
0R0603-PAD
USB_PN10_R 1 2 USB_PN10 USB_PN10 18
R3211
0R0603-PAD
USB_PP10_R 1 2 USB_PP10 USB_PP10 18
M14 DIS
A A
Wistron Corporation
Title
Size
Card Reader-RTS5170
Document Number Rev
A3
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03-05-1512:40:57 PM
5 4 03-05-151:22:21 PM 3 2 1
A B C D E
4 4
w
w
w
.ro
se
fix
.c
om
3 3
(Blanking)
2 2
1 M14 DIS 1
Wistron Corporation
Title
Reserved
A3
A B http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
C D
E
33 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
34 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
35 of 105
5 4 3 2 1
SSID = Reset.Suspend
BAS16-6-GP
2
83.00016.K11
19,27 S0_PW R_GOOD 3
2nd = 83.00016.F11
D 1
83.00016.K11 2 D
R3614
D3602
0R0402-PAD 2nd = 83.00016.F11 3 PURE_HW _SHUTDOW N# 27,28,86
27,42 IMVP_PW RGD 1 2 SYS_PW ROK SYS_PW ROK 19 41 3V_5V_EN 1 D3601

BAS16-6-GP
200KR2J-L1-GP
1
1 2 S5_ENABLE 27
1
R3603 1KR2J-1-GP
R3602
D
Q3603 C3612 DY DY
2N7002BK-GP SCD01U50V2KX-1GP
2
PS_S3CNTRL G
84.07002.I31
w
2nd = 84.2N702.W31
w
3rd = 84.2N702.J31
w
.ro
se
15V_S5
AO4468 MAX 11.6A
fix
Rds(on) = 14m ohm
5V_S0
ROSA Run Power
.c
5V_S5 5V_S0
2
om
C +5V_RUN Comsumption C
R3604 U3601
100KR2J-1-GP 8 D S 1
Peak current ?A
7 D S 2 Design current ?A
6 D S 3
1
5 D G 4
1
1 2 5V_RUN_ENABLE AO4468-GP C3603
3D3V_AUX_S5 R3605 0R2J-2-GP SC10U10V5ZY-1GP
2
1
84.04468.037
C3608 2nd = 84.02659.037
PS_S3CNTRL 37 SCD01U50V2KX-1GP 3rd = 84.04178.037
2
4th = 84.04496.037
1 R3606 2 PS_S3CNTRL 5th = 84.04800.D37
100KR2J-1-GP
D G S
6
4
D2
G1
S1
Q3602 AO4468 MAX 11.6A

ME2N7002DKW -G-GP Rds(on) = 14m ohm 3D3V_S0
D1
S2
G2
84.2N702.F3F 3D3V_S5 3D3V_S0

1
2nd = 84.2N702.A3F +3.3V_RUN Comsumption

S G D U3602
3rd = 84.DMN66.03F 8 D S 1
Peak current ?A
6 D S 3
5 D G 4
19,27,37,47 PM_SLP_S3#
1
B B
21,37 RUN_ENABLE 1 2 3.3V_RUN_ENABLE AO4468-GP C3604

R3607 100KR2J-1-GP SC10U6D3V5KX-1GP
2
1
84.04468.037
C3605 2nd = 84.02659.037
SCD01U50V2KX-1GP 3rd = 84.04178.037
2
4th = 84.04496.037
5th = 84.04800.D37
AO4468 MAX 11.6A 1D5V_S0

Rds(on) = 14m ohm
1D5V_S3 1D5V_S0 +1.5V_RUN Comsumption
U3606 Peak current ?A
7 D S 2
6 D S 3
5 D G 4
1
M14 DIS
A AO4468-GP C3609 A
1 2 1.5V_RUN_ENABLE SC10U6D3V5KX-1GP
2
R3630 100KR2J-1-GP 84.04468.037

2nd = 84.02659.037 Wistron Corporation
1
3rd = 84.04178.037 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

C3610 4th = 84.04496.037 Taipei Hsien 221, Taiwan, R.O.C.
SCD047U25V2KX-GP 5th = 84.04800.D37
2
Title
Power Plane Enable

A3
http://vinafix.vn
03-05-1512:40:57 PM
Date: W ednesday, September 05, 2012Sheet 36 of 105
5 4 03-05-151:22:21 PM 3 2 1
5 4 3 2 1
Close to DIMM
Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK
S3 Power Reduction Circuit Processor VREF_DQ Implementation 0D75V_S0
R3707 1D5V_S0
0R2J-2-GP
1
1 DY 2
1
R3703
Q3708
2N7002BK-GP
22R2J-2-GP
2 DY
R3704
220R2J-L2-GP
2
D R3708 +V_SM_VREF_CNT D
Q3702_D2
Q3701_D
0R0402-PAD
2
M_VREF_DQ_DIMMA 1 2 +V_SM_VREF D S
R3705
100KR2J-1-GP 84.07002.I31 84.07002.I31
2nd = 84.2N702.W31 2nd = 84.2N702.W31
D
1
G
84.07002.I31 Q3701 Q3702
3rd = 84.2N702.J31 2N7002BK-GP 2N7002BK-GP 3rd = 84.2N702.J31
2nd = 84.2N702.W31 PS_S3CNTRL
36 PS_S3CNTRL G G
21,36 RUN_ENABLE 3rd = 84.2N702.J31 DY
45,48 1D05V_VTT_PW RGD
S
w
1
w
R3710
0R0402-PAD
w
.ro
2
1 DY22R2J-2-GP
2 0D75V_EN 46
se
19,27,36,47 PM_SLP_S3# R3716
0D75V_EN
fix
Close to CPU
S3 Power Reduction Circuit SM_DRAMPWROK
1
C3705
.c
DY SCD1U10V2KX-5GP
om
C 1D5V_S3 C
1
Q3704
2N7002BK-GP R3706
G 1KR2J-1-GP
36 PS_S3CNTRL R3709
84.07002.I31 0R2J-2-GP
2
2nd = 84.2N702.W31
1
DY2
S
S3 Power Reduction Circuit
3rd = 84.2N702.J31 SM_DRAMRST#
Q3703
2N7002BK-GP R3718
5 SM_DRAMRST# S D SM_DRAMRST#_D 1 2 DDR3_DRAMRST# 14,15
1
84.07002.I31 1KR2J-1-GP
Close to CPU C3702
SC100P50V2JN-3GP
2nd = 84.2N702.W31
2
G
S3 Power Reduction Circuit SM_DRAMPWROK
3D3V_S0 3rd = 84.2N702.J31
3D3V_S0
1
1D5V_S0 DRAMRST_CNTRL_PCH
20 DRAMRST_CNTRL_PCH
R3713 CEKLT V1.0: PCH to 1K,CUP to 200R
10KR2J-3-GP
1
1
B R3702 C3703 B
U3701
2
1 5 200R2F-L-GP
19 PM_DRAM_PW RGD DY SCD047U16V2KX-1-GP
2
A VCC
0D75V_EN 2
2
B
3 4 VDDPW RGOOD_R 1R3719 2 VDDPW RGOOD 5
GND Y 910R2F-GP
1
U74LVC1G08G-AL5-R-GP-U
R3721
73.01G08.EHG 39R2J-L-GP
DY
1
2nd = 73.7SZ08.EAH R3720

2
Q3707_D 750R2F-GP
3rd = 73.7SZ08.DAH
4th = 73.01G08.L04
2
R3717
19 PM_DRAM_PW RGD 1 DY 2 VDDPW RGOOD_R
0R2J-2-GP
D
Q3707
2N7002BK-GP
SM_DRAMPWROK must have a maximum of 15ns rise or fall time
over VDDQ * 0.55 200mV and the edge must be monotonic PS_S3CNTRL G 84.07002.I31
DY 2nd = 84.2N702.W31
3rd = 84.2N702.J31
S
A M14 DIS A
Wistron Corporation
Title
S3 Reduction Circuit
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
37 of 105
5 4 3 2 1
SSID = PWR.Support 5V_S5
2
84.03904.L06
1
PR3802 2nd = 84.03904.P11 3D3V_S5
15KR2F-GP PR3803
2
10KR2J-3-GP
1
PQ3802_1 1 PMBS3904-1-GP 3D3V_S5
1
PQ3802
2
2
D PD3803 D
1
PR3811 PSID_DISABLE#_R_C BAV99-5-GP-U
100KR2J-1-GP PR3806
2K2R2J-2-GP
83.00099.T11
G
1
3
PQ3801 2nd = 83.3X101.011
2
FDV301N-NL-GP
PR3819 PR3807
PS_ID_R 1 2 PS_ID_R2 D S PS_ID 1 2
D
PSID_EC 27
0R3J-0-U-GP 33R2J-2-GP
Layout Note: 84.00301.A31
2nd = 84.3K329.031
PSID Layout width > 25mil
1
PD3804 PR3808
DY
w
PESD24VS2UT-GP 1 2
DY
w
33R2J-2-GP
w
3
JGND
.ro
se
DCIN1
NP2
fix
7 1 AFTP3803
6
+DC_IN AD+
.c
5
4 PU3801
om
C 3 +DC_IN_C 1 S D 8 C
S D
PC3805
PC3803
PC3804
PC3806
2 2 7
SC1U25V5KX-1GP
SC10U25V5KX-GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
1
S D
PC3801
240KR3-GP
3 6
K
1
1
1 PR3816 G D
PR3809
4 5
NP1 EC3801 EC3802 EC3803 PD3801 PC3802
SC10U25V5KX-GP
SC1KP50V2KX-1GP
3K3R6J-GP SCD1U25V3KX-GP 1SMB22AT3G-GP-U1 SCD1U25V3KX-GP SI7121DN-T1-GE3-GP

DY DY
2
2
ACES-CON7-3-GP-U1 83.22R03.03G
2
20.F1643.007
A
PQ3809_D
PQ3805
1
1
R2
JGND JGND PQ3804 E Id=-9.6A
D
PR3814 C AD_OFF_L B PR3810
100KR2J-1-GP PQ3809 B R1 R1
C AD_OFF_R 47KR3J-L-GP Qg=-25nC
2N7002BK-GP E Rdson=18~30mohm
G R2 PDTA124EU-1-GP
2
2
PDTC124EU-1-GP 84.00124.K1K
84.00124.H1K 2nd = 84.05124.A11
84.07002.I31 2nd = 84.05124.011
2nd = 84.2N702.W31
S
3rd = 84.2N702.J31
PC3808
SC1U25V3KX-1-GP
1
AC_IN#_G
27 PW R_CHG_AD_OFF 1 2 PQ3808
PR3812 PR3817
2
1KR2J-1-GP G PQ3808G1 2
G
3D3V_S5 1KR2J-1-GP
PQ3808D D
B B
1
27 AC_IN_KBC# AC_IN_KBC# D S S PC3809
PR3813
DY
SCD01U50V2KX-1GP
DT MODE 10KR2J-3-GP
2
2N7002K-2-GP
1
PQ3810 84.2N702.J31
1
2N7002BK-GP PR3815
100KR2J-1-GP
84.07002.I31
2
2nd = 84.2N702.W31
3rd = 84.2N702.J31
AFTP3801 1 +DC_IN
AFTP3802 1 PS_ID_R PBAT_PRES1#
PQ3803
1 6
PR3818
2 1 2 5
DY PBAT_PRES1# 39
100KR2J-1-GP 3 4
A M14 DIS A
5,27,40,42 H_PROCHOT# 1 2 PQ3807D
DMN66D0LDW -7-GP
PC3807 Wistron Corporation

SC1U6D3V2ZY-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
Size Document Number

DCIN Rev
A3
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03-05-151:22:21 PM 3 2
1
38 of 105
5 4 3 2 1
SSID = PWR.Support
BT+
PBAT_PRES1# 1 AFTP3902
D PBAT_SMBDAT1 1 AFTP3903 D
Batt Connecter
K
PBAT_SMBCLK1 1 AFTP3904
1
BT+ 1 AFTP3905
EC3903 PD3902
EC3904
SCD1U50V3KX-GP
2
SC2200P50V2KX-2GP DY SMF18AT1G-GP
A
BATT1
10
1
w
PN3901 2
PBAT_SMBCLK1
w
27,40 BAT_SCL 4 5 3
3 6 PBAT_SMBDAT1 4
w
27,40 BAT_SDA
2 7 PBAT_PRES1# 5
.ro
27 BAT_IN#
1 8 6
AFTP3901 BAT_ALERT
se
1 7
SRN33J-7-GP 8
fix
38 PBAT_PRES1# 9
11
.c
om
C ALP-CON9-6-GP-U C
2
20.81925.009
1
1
EC3905 EC3901 EC3902
SC10P50V2JN-4GP DY SC10P50V2JN-4GP
DY DY SC10P50V2JN-4GP 1 AFTP3906
1
Placement: Close to Batt Connector
BAT_SCL
BAT_IN#
BAT_SDA
B B
3
D3902 D3903 D3901

DA3X101F0L-GP DA3X101F0L-GP DA3X101F0L-GP
1
M14 DIS
3D3V_AUX_KBC
Wistron Corporation
A
83.3X101.011 83.3X101.011 83.3X101.011 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
2nd = 83.BAV99.H11 2nd = 83.BAV99.H11 2nd = 83.BAV99.H11
Title
3rd = 83.00099.M11 3rd = 83.00099.M11 3rd = 83.00099.M11
BATT CONN
A4
5 4
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03-05-1512:40:57 PM
03-05-151:22:21 PM
3
2
Sheet 39
1
of 105
5 4 3 2 1
SSID = Charger
AD+_TO_SYS DCBATOUT BT+

D PU4003 D
PU4002 1 S D 8
8 D S 1 PR4002 2 S D 7
AD+
7 D S 2 1 2 3 S D 6
1
6 D S 3 D01R3721F-GP-U AD+ 4 G D 5
100KR2J-1-GP
PR4003
5 D G 4
GAP-CLOSE-PWR-3-GP
SI7121DN-T1-GE3-GP
SI7121DN-T1-GE3-GP Id= -10A
1
Qg= -22nC
1
PR4004 AD+_G_2
PG4002
3KR5J-GP Id= -10A PG4003 PR4005 Rdson=15~18mohm
10KR2F-2-GP
GAP-CLOSE-PWR-3-GP 470KR2J-2-GP
Qg= -22nC
PR4001
PR4006
2
Rdson=15~18mohm 0R2J-2-GP
2
DC_IN_D
2
DY 1
1
PQ4002
AD+_G_1
1 2
w
3 4
SC1U25V3KX-1-GP
D1 S1
PC4002
w
PWR_CHG_ACOK 2 G2 G1 5 SCD1U25V2KX-GP
w
DCBATOUT
PC4004
1 6
SC1U25V3KX-1-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
S2 D2
SCD1U50V3KX-GP
SCD1U25V3KX-GP
83.1R504.A8F
.ro
SC2200P50V2KX-2GP
AD+
PC4008
PC4006
PC4026
PC4009
ME2N7002DKW-G-GP
2nd = 83.1R004.H8F
PC4024
EC4002
84.2N702.F3F
PWR_CHG_ACN
PWR_CHG_ACP
2nd = 84.2N702.A3F 3rd = 83.1R504.B8F
se
1
EC4001
3rd = 84.DMN66.03F 4th = 83.2R004.08F
1
PWR_CHG_REGN
DY
fix
PR4008 CHG_AGND
2
1
PD4001 84.00412.037
PWR_CHG_BTST_R
2
5
6
7
8
SCD47U25V3KX-3-GP
PR4007 1 2 PWR_CHG_VCC PR4009 SD103AWS-1-GP 2nd = 84.08884.A37
D
D
D
D
.c
309KR2F-GP CHG_AGND 0R3J-0-U-GP
PC4010
1 2 K A 1 2 PU4004
10R5J-GP
1
C PC4007 SIS412DN-T1-GE3-GP C
om
2
1
PU4005 SC1U25V3KX-1-GP
PWR_CHG_CMPIN
Charger Current=1.4~3.6A
ACP
ACN
2
PWR_CHG_REGN
SCD047U25V2KX-GP
G
S
S
S
PWR_CHG_IOUT CHG_AGND 20 VCC
1
4
3
2
1
PR4031
PC4011
PR4029 PR4011 PR4030
1
3D3V_AUX_KBC100KR2J-1-GP
SCD01U50V2KX-1GP
54K9R2F-L-GP 19K1R2F-GP PWR_CHG_ACDET 6 17 PWR_CHG_BTST

PWR_CHG_CMPIN_R
ACDET BTST
1
PR4010 PC4014
1
PC4012
0R3J-0-U-GP SCD1U50V3KX-GP
2
2
PWR_CHG_CMPOUT 16 1 2PWR_CHG_SNUB 1 2
47KR2F-GP
REGN
1
1
PR4015
DY DY
2
1
PR4012 PR4014 3
2
PR4013 3K3R2F-2-GP 3K3R2F-2-GP CMPOUT PWR_CHG_HIDRV

18 PL4001
49K9R2F-L-GP 3D3MR2J-GP HIDRV BT+
PQ4007 DY DY PR4032
4
1 2 PR4016
DY
2
2 CMPIN
3 4 CHG_AGND 120KR2F-L-GP 19 PWR_CHG_PHASE 1 2 BT+_R 1 2
PC4013
2
2
PHASE
GAP-CLOSE-PWR-3-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
D1 S1
SCD1U50V3KX-GP
GAP-CLOSE-PWR-3-GP
CHG_AGND PWR_CHG_CMPIN SC3300P50V3KX-1GP D01R3721F-GP-U
PC4015
PC4016
PC4017
PC4018
PC4019
2 5 IND-5D6UH-48-GP-U1
27 AD_IA_HW2 G2 G1
AD_IA_HW 27
2 1 PWR_CHG_BAT_SCL 9 15 PWR_CHG_LODRV
2
27,39 BAT_SCL SCL LODRV
2
1 6 CHG_AGND PG4007 GAP-CLOSE-PWR-3-GP PU4006
PG4010
1
PG4009
S2 D2
SCD1U25V2KX-GP
PWR_CHG_CMPIN_RR
SIS412DN-T1-GE3-GP
5
6
7
8
ME2N7002DKW-G-GP 2 1 PWR_CHG_BAT_SDA 8 DY
27,39 BAT_SDA SDA
D
D
D
D
84.2N702.F3F 3D3V_AUX_S5 PG4008 GAP-CLOSE-PWR-3-GP
1
1
2
PC4020
CHG_AGND 2nd = 84.2N702.A3F
3rd = 84.DMN66.03F 13 PWR_CHG_SRP 1 PR4021 2
SRP
1
PWR_CHG_ILIM 10 10R2F-L-GP
ILIM
1
PR4017 12 PWR_CHG_SRN 1 PR4020 2
SRN
G
S
S
S
100KR2J-1-GP 7D5R2F-GP DY
2
2 1PWR_CHG_IFAULT
DY 11
4
3
2
1
19K6R2F-GP
27 BOOST_MODE# NC#11 84.00412.037
2
PR4027 PR4018 CHG_AGND 2nd = 84.08884.A37

0R2J-2-GP
1
2
1
10KR2F-2-GP
SCD1U25V2KX-GP
PR4023 5 7 PWR_CHG_IOUT 1 PR4022 2
PR4035
B PWR_CHG_CMPIN ACOK# IOUT AD_IA 27 B

59KR2F-GP 0R2J-2-GP PWR_CHG_CSOP_1
DY
GND
GND
DY
SC220P50V2JN-3GP
3D3V_AUX_S5
PC4021
2
8K45R2F-2-GP
BQ24727RGRR-1-GP
1 PR4024
21
14
GAP-CLOSE-PWR-3-GP
1
PC4022
CHG_AGND 2 1
CHG_AGND
2
1
SCD1U25V2KX-GP
PG4011 PWR_CHG_CSON_1
CHG_AGND DY
PC4023
2
1
ROSA EE need check pull high
2
CHG_AGND
Adapter type PR4023 CHG_AGND
PWR_CHG_REGN 3D3V_AUX_S5 3D3V_AUX_S5 PWR_CHG_REGN

65W 24K
1
1
1
PR4019
PR4025 PR4034
DYPR4028
100KR2J-1-GP 100KR2J-1-GP
90W 33.2K
DY 100KR2J-1-GP 100KR2J-1-GP
PQ4008
2
2
130W 59K PWR_CHG_ACOK 3 4
2
D1 S1
PR4037
27 AC_IN# 3D3V_AUX_S5 1 2PWR_CHG_CMPOUT 2 5 AC_IN#
EE need pull high and net name
DY G2 G1
SCD1U25V3KX-GP
1
PC4001
100KR2J-1-GP 1 6
1
H_PROCHOT# 5,27,38,42
S2 D2
PR4033
DY DY120KR2F-L-GP DY PR4036
EC code only BQ24707 120KR2F-L-GP ME2N7002DKW-G-GP
2
A A
84.2N702.F3F
2
2nd = 84.2N702.A3F M14 DIS

2
H_PROCHOT# AD_IA_HW AD_IA_HW2 3rd = 84.DMN66.03F
65W 0 0 Wistron Corporation

90W 1 0
Title
130W 0 1 CHARGER BQ24727

Custom
DNE40 14 CR DIS A00
http://vinafix.vn
03-05-1512:40:57 PM
5 4
03-05-151:22:21 PM 3 2 1
A B C D E
SSID = PWR.Plane.Regulator_5v3p3v
PWR_5V_VCLK
PC4104 PC4102 PC4103

3D3V_AUX_S5 DCBATOUT PWR_DCBATOUT_5V
1
SC1KP50V2KX-1GP
SCD1U25V3KX-GP
SCD1U25V3KX-GP
1
1
PG4128
1
1 2
2
PR4123
3BST15V_2 2
3BST15V_1 2
DY 0R2J-2-GP GAP-CLOSE-PWR-3-GP
PG4129
1 2
2
PD4103 PD4101
DCBATOUT PR4124
4 PWR_DCBATOUT_3D3V GAP-CLOSE-PWR-3-GP 4
PR4121
PWR_5V_EN1 2 1 PWR_5V_EN1_R 1 DY 2 PG4130 83.0R203.081 83.0R203.081
PG4102 1 2
BAT54SPT-GP
BAT54SPT-GP
1 2 0R0402-PAD 0R2J-2-GP 2nd = 83.00054.Y81 2nd = 83.00054.Y81
1
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP PR4122 PG4131 3rd = 83.BAT54.P81 3rd = 83.BAT54.P81
PG4103 0R0402-PAD 1 2
1
1 2 15V_S5 5V_PWR
GAP-CLOSE-PWR-3-GP PG4105
2
GAP-CLOSE-PWR-3-GP PG4132 GAP-CLOSE-PWR-3-GP
PG4104 PWR_3D3V_EN2 2 PR4127 1 1 2
3V_5V_EN 36 15V_PWR BOOST_10V
1 2 1 2
0R0402-PAD GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP PG4133
1
PG4106 1 2 PC4106
1 2 PD4104 SC1U25V3KX-1-GP PC4108 PC4107
GAP-CLOSE-PWR-3-GP BZT52C15S-GP SCD1U25V3KX-GP SCD1U25V3KX-GP
DY
2
GAP-CLOSE-PWR-3-GP
A
w
w
DCBATOUT
PWR_DCBATOUT_3D3V
w
PC4112 PC4113 TC4101
PWR_DCBATOUT_5V
.ro
SC10U25V5KX-GP
SCD01U50V2KX-1GP
SE47U25VM-14-GP
PC4109 PC4110 PC4111
1
1
1
SC10U25V5KX-GP
SCD1U50V3KX-GP
SC10U25V5KX-GP
DY DY 84.00412.037 PC4114 PC4115 PC4116
se
D 84.00412.037 2nd = 84.08884.A37
2
8
7
6
5
5
6
7
8
1
5V_S5
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U50V3KX-GP
Design Current=3.74A 2nd = 84.08884.A37 Design Current=9.15A 5V_PWR
D
D
D
D
D
D
D
D
D
PU4101 PG4119
5.61A<OCP>6.73A 13.73A<OCP>16.47A
fix
PU4104 SIS412DN-T1-GE3-GP
12
1 2
2
SIS412DN-T1-GE3-GP PU4103
GAP-CLOSE-PWR-3-GP
VIN
PG4120
.c
G
S
S
S
SCD1U25V3KX-GP 1 2
S
S
S
G
3D3V_S5 3D3V_PWR PC4117 PR4108 PR4109 PC4118

3
G S 3
1
2
3
4
4
3
2
1
om
PG4108 S G 2 1PWR_3D3V_VBST2_1
1 2 PWR_3D3V_VBST29 17 PWR_5V_VBST1 1 2PWR_5V_VBST1_1 1 2 GAP-CLOSE-PWR-3-GP
SCD1U25V3KX-GP 1D5R3F-GP VBST2 VBST1 1D5R3F-GP PG4121
1 2
3D3V_PWR 68.2R210.20B PWR_3D3V_DRVH210 16 PWR_5V_DRVH1 68.2R210.20B 5V_PWR 1 2
PL4102 DRVH2 DRVH1 PL4101
GAP-CLOSE-PWR-3-GP 2nd = 68.2R21B.10J 2nd = 68.2R21B.10J
1 2 PWR_3D3V_LL2 8 18 PWR_5V_LL1 1 2 GAP-CLOSE-PWR-3-GP
PG4109 SW2 SW1 PG4122
1
1
1 2 IND-2D2UH-46-GP-U PWR_3D3V_DRVL211 PWR_5V_DRVL1
D DRVL2 DRVL1
15 IND-2D2UH-46-GP-U 1 2
GAP-CLOSE-PWR-3-GP DPU4102 PR4111 77.52271.09L
8
7
6
5
5
6
7
8
77.52271.09L PR4110 DY 2D2R5F-2-GP PG4117 PC4120 GAP-CLOSE-PWR-3-GP
DY
D
D
D
D
D
D
D
D
PG4110 PC4119 PG4116 2D2R5F-2-GP PU4105 14 PWR_5V_VO1 PT4101 PG4123

1
1
VO1
SIS406DN-T1-GE3-GP
GAP-CLOSE-PWR-3-GP
SCD1U10V2KX-4GP
1 2 PT4102 SIS406DN-T1-GE3-GP 1 2
2
2
1
1
SCD1U10V2KX-4GP
GAP-CLOSE-PWR-3-GP
SE220U6D3VM-30-GP
PWR_3D3V_FB2 4 2 PWR_5V_FB1 DY
VFB2 VFB1
SE220U6D3VM-30-GP
GAP-CLOSE-PWR-3-GP DY GAP-CLOSE-PWR-3-GP
1PWR_3D3V_SNUB
2
PG4124
1PWR_5V_SNUB
2
2
S
S
S
PG4111
G
1 2
1 S
2 S
3 S
4 G
PWR_3D3V_EN2 PWR_5V_EN1
1 2 6 20 G S
4
3
2
1
EN2 EN1
GAP-CLOSE-PWR-3-GP
S G GAP-CLOSE-PWR-3-GP
PG4125
PWR_3D3V_CS2 5 1 PWR_5V_CS1 1 2
PG4112 CS2 CS1
3V_FEEDBACK
1
1 2 GAP-CLOSE-PWR-3-GP
DY 84.00406.037 PR4101 19 PWR_5V_VCLK PR4102 84.00406.037 DY PC4123 PG4126
GAP-CLOSE-PWR-3-GP PC4121 45K3R2F-L-GP VCLK 115KR2F-GP SC560P50V-GP
2nd = 84.08878.A30 2nd = 84.08878.A30 1 2
2
2
SC330P50V3KX-GP
PWR_5V3D3V_PGOOD 7 21 GAP-CLOSE-PWR-3-GP
2
2
PGOOD VREG3 GND PG4134
VREG5
1 2
X01 0613
GAP-CLOSE-PWR-3-GP
1
1
TPS51225RUKR-GP PG4135
3
13
PR4113 5V_PWR_2 PR4114 1 2
1
PR4112 3D3V_PWR_2
DY0R2J-2-GP 0R2J-2-GP DY
PWR_5V3D3V_VREG3
6K65R2F-GP PG4101 PR4115 GAP-CLOSE-PWR-3-GP

1 2 15KR2F-GP
2
1 2
1 2
PWR_3D3V_FB2_R PWR_5V_FB1_R
PC4124 GAP-CLOSE-PWR-3-GP
2
DYSC18P50V2JN-1-GP PC4125 DY
SC18P50V2JN-1-GP
2
2
X01 change PR4120 to 9.76K to solve 5V
1
1
2 3D3V_S5 voltage fall issue while on heavy loading 2
PR4117 PR4120
1
10KR2F-2-GP 9K76R2F-1-GP
1
PC4127 PC4126 3D3V_PWR_2 3D3V_AUX_S5

PR4119 SC4D7U6D3V5KX-3GP SC4D7U6D3V5KX-3GP Close to VFB Pin (pin2)
PR4116
2
2
100KR2J-1-GP
1 2
2
0R0402-PAD
Close to VFB Pin (pin5)
I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A
O/P cap: CHIP CAP POL 220U 6.3V M 6.3*4.5 /Matsuti/ 17mOhm / 77.52271.09L O/P cap: CHIP CAP POL 220U 6.3V M 6.3*4.5 /Matsuti/ 17mOhm / 77.52271.09L
H/S:SIS412DN-T1-GE3 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 H/S:SIS412DN-T1-GE3 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
L/S:SIS406DN-T1-GE3 / 11.5mOhm/14.5mOhm@4.5Vgs / 84.00406.037 L/S:SIS406DN-T1-GE3 / 11.5mOhm/14.5mOhm@4.5Vgs / 84.00406.037
1 1
M14 DIS
Wistron Corporation
Title
3V/5V TPS51225
A2
http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
A B C D E
5 4 3 2 1
SSID = CPU.Regulator
5V_S5 5V_S5
2
PR4209 PR4210
0R0402-PAD 0R0402-PAD
1
PWR_VCORE_VCCP PWR_VCORE_VDD
D D
PR4202 confirm with EE have 75ohm or not
SC1U10V3KX-3GP
SC1U10V3KX-3GP
1
1
PC4202 PC4203
2
VCCP_CPU
PR4201 1 PWR_VCORE_SDA
22
21
2
130R2F-1-GP PU4201
PR4202 1 2 PWR_VCORE_ALERT#
DY
VDD
VCCP
SC1U10V3KX-3GP
1
PC4201 75R2F-2-GP
PR4203 1 2 PWR_VCORE_SCLK PR4205 0R0402-PAD
54D9R2F-L1-GP 48 D85V_PWRGD 2 1 PWR_VCORE_VR_ON P 2 20
2
PR4206 0R0402-PAD VR_ON PWM2
1
8 H_CPU_SVIDCLK 2 1 PWR_VCORE_SCLK 3
PR4207 0R0402-PAD SCLK
PR4204
499R2F-2-GP 8 VR_SVID_ALERT# 2 1 PWR_VCORE_ALERT# 4
ALERT#
w
PR4208 0R0402-PAD 16 PWR_VCORE_BOOT1 43
PWR_VCORE_SDA BOOT1
8 H_CPU_SVIDDAT 2 1 5
2
SDA
w
5,27,38,40 H_PROCHOT# 6 19 PWR_VCORE_LGATE1 43
VR_HOT# LGATE1
w
PR4211 PR4212 18
.ro
PHASE1 PWR_VCORE_PHASE1 43
2 1 NTCG_RC 1 2 PWR_VCORE_NTCG 1
NTCG
3K83R2F-GP 16KR2F-GP PWR_VCORE_NTC 7
se
PR4213 NTC
17 PWR_VCORE_UGATE1 43
5V_S5 UGATE1
1 2 9
PR4217 0R0402-PAD ISEN1
fix
NTC-470K-8-GP 2 1PWR_VCORE_ISEN2 8
NTC place near high side MOSFET of AXG Phase1 2nd = 69.60013.141
ISEN2
PR4214 PR4215
.c
2 1 NTC_RC 1 2 14 PWR_VCORE_COMP 43
COMP
om
C 3K83R2F-GP 16K9R2F-GP 10 C
PR4216 ISUMP
13 PWR_VCORE_FB 43
PWR_VCORE_ISUMN FB
1 2 11
ISUMN
NTC-470K-8-GP 12 PWR_VCORE_RTN 43
NTC Place near high side MOSFET of Phase1 2nd = 69.60013.141
RTN
43 PWR_VCORE_VSUM+
SCD068U16V2KX-GP
SCD1U16V2JX-1-GP
PWR_VCORE_ISUMNG 31
2K61R2F-1-GP
ISUMNG
1
1
11KR2F-L-GP
1
Place near choke of Phase1 PR4218 PR4219 PC4204 PC4205 32
ISUMPG
26 PWR_VCORE_BOOTG 44
2
2
BOOTG
2
15
VSUM_R PGOOD
25 PWR_VCORE_UGATEG 44
UGATEG
1
PR4220 27
NTC-10K-26-GP PGOODG
24 PWR_VCORE_PHASEG 44
PHASEG
COMPG
2nd = 69.60013.131 PR4221
2
RTNG
23
GND
PWR_VCORE_LGATEG 44
FBG
LGATEG
1 2
43 PWR_VCORE_VSUM-
ISL95833HRTZ-GP
SCD1U16V2JX-1-GP
33
28
29
30
475R2F-L1-GP
1
PC4206
PR4222 PC4207
ISUMN_RC
2
DY 1 2
DY1
2
649R2F-GP PWR_VCORE_RTNG 44
SC2200P50V2KX-2GP
PWR_VCORE_FBG 44
44 PWR_VCORE_VSUMG+
SCD068U16V2KX-GP
SCD1U16V2JX-1-GP
B B
2K61R2F-1-GP
1
1
11KR2F-L-GP
Place near choke of AXG Phase1 PWR_VCORE_COMPG 44

1
PR4223 PR4224 PC4208 PC4209

2
3D3V_S5 3D3V_S5
2
VSUMG_R
1
PR4225
1
1
NTC-10K-26-GP
PR4228
PR4229
1K91R2F-1-GP
1K91R2F-1-GP
2nd = 69.60013.131 PR4226
2
1 2
2
2
44 PWR_VCORE_VSUMG-
SCD1U16V2JX-1-GP
475R2F-L1-GP
1
PC4210
PR4230
2
PR4227 PC4211
ISUMNG_RC
2
DY 1 2
DY 1 1 DY 2 IMVP_PWRGD 27,36 For GFX
649R2F-GP
SC2200P50V2KX-2GP 0R2J-2-GP
IMVP_PWRGD 27,36 For VCCCORE
A A
M14 DIS
Wistron Corporation
Title
ISL95833_CPU_CORE(1/3)
http://vinafix.vn
03-05-1512:40:57 PM
5 4
03-05-151:22:21 PM 3 2
1
Sheet 42 of 105
5 4 3 2 1
DCBATOUT PWR_VCCCORE_DCBATOUT
PG4301
1 2 PWR_VCCCORE_DCBATOUT
GAP-CLOSE-PWR-3-GP
PG4302
D
1 2 D
GAP-CLOSE-PWR-3-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
PG4303
1
1 2 PC4302 PC4303 PC4304 PC4305
GAP-CLOSE-PWR-3-GP
2
PG4304
1 2
GAP-CLOSE-PWR-3-GP
PG4305
1 2
Iccmax=33A
PU4302
5
6
7
8
GAP-CLOSE-PWR-3-GP PU4301 IccTDC=25A
5
6
7
8
D
D
D
D
PG4306 PR4301 PC4301
D
D
D
D
RJK03J6DPA-00-J5A-GP
OCP>40A
1 2 1 2 BOOT1_RC 1 2
42 PWR_VCORE_BOOT1
GAP-CLOSE-PWR-3-GP 2D2R3-1-U-GP SCD22U50V3ZY-1GP
PG4307
G
4
G
4
S
S
S
1 2
S
S
S
3
2
1
w
GAP-CLOSE-PWR-3-GP
3
2
1
PG4308
w
1 2
VCC_CORE
GAP-CLOSE-PWR-3-GP 42 PWR_VCORE_UGATE1 PL4301 68.R3610.20S
.ro
PG4309 2nd = 68.R3610.20A
1 2 1 2
42 PWR_VCORE_PHASE1 COIL-D36UH-3-GP-U
se
GAP-CLOSE-PWR-3-GP PT4301 PT4303 PT4304
1
PG4310
ST470U2VDM-7-GP-U
ST470U2VDM-7-GP-U
ST470U2VDM-7-GP-U
1 2 PU4303 PU4304 2 2 2
fix
5
6
7
8
5
6
7
8
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
3
D
D
D
D
D
D
D
D
RJK03K5DPA-00-J5A-GP
PG4311 PG4312
.c
1
om
C C
G
4 4
2
S
S
S
S
S
S
3
2
1
3
2
1
42 PWR_VCORE_LGATE1
PR4302
42 PWR_VCORE_VSUM+ 2 1 PWR_VCORE_VSUM+_GAP
3K65R2F-1-GP
PR4303
42 PWR_VCORE_VSUM- 2 1 PWR_VCORE_VSUM-_GAP
1R2F-GP
PR4304
1 2
42 PWR_VCORE_COMP
42K2R2F-L-GP
42 PWR_VCORE_FB
PR4305 PC4306 PC4307

2 1 FB_RC 1 2 2 1
499R2F-2-GP SC470P50V-2-GP SC47P50V2JN-3GP
PR4306 PR4307 PC4308

B
1 2 2 1COMP_RC 2 1 B
1K91R2F-1-GP 267KR2F-GP SC150P50V2JN-3GP

PC4309
PR4308
1 2COMP_R 1 2
2KR2F-3-GP SC680P50V2KX-2GP
VCCSENSE 8
PC4310
1
DY2
SC330P50V2JC-2-GP
PC4311
1 2
SCD01U50V2KX-1GP
R4301 0R0402-PAD
2 1 VSSSENSE 8
42 PWR_VCORE_RTN
A A
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L

Inductor: CHIP CHK 0.36UH PCMC104T-R36MH 1.05mohm/ Isat =60A rms68.R3610.20S M14 DIS
O/P cap: CHIP CAP EL 470U 2V 7.3*4.3 ESR=0.0045 3.8Arms Panasonic/79.47719.9BL
H/S: RJK03J6DPA-00#J5A / 10mohm/13mOhm@4.5Vgs/ 84.00036.037 Wistron Corporation
L/S: RJK03K5DPA-00#J5A / 3mohm/3.9mOhm@4.5Vgs/ 84.00035.037 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
ISL95833_CPU_CORE(2/3)
http://vinafix.vn
03-05-1512:40:57 PM
5 4
03-05-151:22:21 PM 3 2
1
Sheet 43 of 105
5 4 3 2 1
DCBATOUT PWR_GFXCORE_DCBATOUT
PG4401
1 2
GAP-CLOSE-PWR-3-GP
PG4402
1 2
PWR_GFXCORE_DCBATOUT
GAP-CLOSE-PWR-3-GP
PG4403
D
1 2 D
GAP-CLOSE-PWR-3-GP
PG4404
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
1 2
1
PC4402 PC4403 PC4404 PC4405
GAP-CLOSE-PWR-3-GP
PG4405
2
1 2
GAP-CLOSE-PWR-3-GP
PG4406
1 2
PU4401 PU4402
5
6
7
8
5
6
7
8
GAP-CLOSE-PWR-3-GP
D
D
D
D
D
D
D
D
PG4407
1 2
DY Iccmax=33A
GAP-CLOSE-PWR-3-GP
PG4408 IccTDC=22A
G
PC4401 4 4
S
S
S
S
S
S
1 2 PR4401 OCP>40A
1 2 BOOTG_RC 1 2
3
2
1
3
2
1
42 PWR_VCORE_BOOTG
w
GAP-CLOSE-PWR-3-GP
2D2R3-1-U-GP
SCD22U50V3ZY-1GP
68.R3610.20S
w
VCC_GFXCORE
2nd = 68.R3610.20A
.ro
42 PWR_VCORE_UGATEG PL4401
1 2
se
42 PWR_VCORE_PHASEG
COIL-D36UH-3-GP-U PT4401 PT4402
1
fix
PT4403
PU4403 PU4404
ST330U2VDM-4-GP
ST330U2VDM-4-GP
2
2
5
6
7
8
5
6
7
8
SE330U2D5VM-8-GP
.c
D
D
D
D
D
D
D
D
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
om
C C
PG4409 PG4410
1
G
G
4 4
S
S
S
S
S
S
3
2
1
3
2
1
2
77.53371.18L
2nd = 77.93971.03L
42 PWR_VCORE_LGATEG
PR4402
42 PWR_VCORE_VSUMG+ 2 1 PWR_VCORE_VSUMG+_GAP
3K65R2F-1-GP
PR4403
42 PWR_VCORE_VSUMG- 2 1 PWR_VCORE_VSUMG-_GAP
1R2F-GP
PR4404
1 2
42 PWR_VCORE_COMPG
150KR2F-L-GP
42 PWR_VCORE_FBG
B B
PR4405 PC4406 PC4407
2 1FBG_RC 1 2 2 1
499R2F-2-GP SC470P50V-2-GP SC47P50V2JN-3GP
PR4406 PR4407 PC4408

AXG Loadline PR4064 1 2 2 1COMPG_RC2 1
2K55R2F-GP 267KR2F-GP SC150P50V2JN-3GP

GT1 4.6mohm 237ohm
PR4408 PC4409
1 2COMPG_R 1 2
GT2 3.9mohm 432ohm 2KR2F-3-GP SC330P50V2KX-3GP
VCC_AXG_SENSE 9
PC4410
1 2
DY
SC330P50V2JC-2-GP
PC4411
1 2
42 PWR_VCORE_RTNG
SCD01U50V2KX-1GP
R4401 0R0402-PAD
2 1 VSS_AXG_SENSE 9
A A
M14 DIS
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L Wistron Corporation

Inductor: CHIP CHK 0.36UH PCMC104T-R36MH 1.05mohm/ Isat =60A rms68.R3610.20S Taipei Hsien 221, Taiwan, R.O.C.
O/P cap: CHIP CAP 330U 2V EEFSX0D331XE 3.5Arms Panasonic/79.33719.20L
H/S: RJK03J6DPA-00#J5A / 10mohm/13mOhm@4.5Vgs/ 84.00036.037 Title
L/S: RJK03K3DPA-00#J5A / 4.9mohm/6.1mOhm@4.5Vgs/ 84.003K3.037 ISL95833_CPU_CORE(3/3)
http://vinafix.vn
03-05-1512:40:57 PM
5 4
03-05-151:22:21 PM 3 2
1
Sheet 44 of 105
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p05v_pch/vccp_cpu
1D05V_PCH 1D05_VTT_PW R VCCP_CPU
PG4512 PG4520
1 2 1 2
D TPS51219 for 1D05V_VTT GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PG4513 PG4521
D
1 2 1 2
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
DCBATOUT PW R_DCBATOUT_1D05V PG4514 PG4522

1 2 1 2
PD4501 GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
SDMK0340L-7-F-GP
PG4501 PG4515 PG4523
K A
1 2
DY 1 2 1 2
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP

1 2 51219_EN
w
19,46,47,93 RUNPW ROK
PG4502 PG4524
w
PR4501
1 2 100KR2F-L1-GP 1 2
w
1
PC4501
.ro
PG4503
3D3V_S0 SC1U6D3V2KX-L-1-GP DY PR4502 PG4525
2
1KR2F-3-GP
1 2 1 2
se
1 2
1
PW R_DCBATOUT_1D05V
fix
PG4504 PG4526
PR4567
.c
1 2 10KR2J-3-GP 1 2
om
C GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP C
2
1
PC4502 PC4512
1
PC4503 PG4527
37,48 1D05V_VTT_PW RGD 84.00036.037 1 2
SC10U25V5KX-GP
SCD1U25V3KX-GP
SC10U25V5KX-GP
PU4502
2nd = 84.07698.037 D
2
2
5
6
7
8
GAP-CLOSE-PW R-3-GP
D
D
D
D
51219_MODE
3D3V_S5 PC4504
PR4505
PW R_VBST 1 2 PW R_LL_1 1 2
Design Current = 13A
G
PR4504 2D2R3-1-U-GP 4
1 2
S
S
S
SCD1U25V3KX-GP
19.5A<OCP<23.4A
3
2
1
10KR2J-3-GP
G S
17
16
15
14
13
PU4501
1D05_VTT_PW R
GND
PGOOD
EN
MODE
BST
51219_VREF
PL4501
68.R3610.20S
1
1 12 51219_SW 2nd = 68.R3610.20A 1 2

PR4506 VREF SW
51219_REFIN 2 11 51219_DH COIL-D36UH-3-GP-U
8K25R2F-1-GP REFIN DH
DY 3 GSNS DL 10 51219_DL
4 VSNS V5 9 DPU4503
2
5
6
7
8
1
PC4506
COMP
1
PGND
PC4505
D
D
D
D
TRIP
GND
PR4524
51219_VCCIO_VSNS
PT4501
DY DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2D2R5J-1-GP
2
SE330U2D5VM-8-GP
TPS51219RTER-GP
1
PR4507 PC4507
5
6
7
8
51219_GND_VCCP
G
10K5R2F-GP SC2200P50V2KX-2GP
2
4
B DY DY PC4508 B
S
S
S
2
G S
3
2
1
251219_COMP 5V_S5
2
1
51219_VSSP_GSNS 84.003K3.037
SCD1U10V2KX-4GP 2nd = 84.00312.037
1
PR4508
3D3R2F-GP
77.53371.18L
1
DY PC4524
151219_TRIP
SC2200P50V2KX-YK-GP 2nd = 77.93971.03L
1 2
51219_V5FILT
2
1
PC4510
PC4509
SC1KP50V2KX-1GP
2 SC1U10V2KX-1GP
2
PR4510
88K7R2F-GP
1
PR4509
2
10R2F-L-GP
1
PC4511
DY
2
SC1KP50V2KX-1GP
2
VCCIO_SENSE_1 2 1
PG4505 GAP-CLOSE-PW R-3-GP VCCIO_SENSE 8
A M14 DIS A
2 1 VSSIO_SENSE 8
PG4506 GAP-CLOSE-PW R-3-GP
Wistron Corporation
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Inductor: CHIP CHK 0.36UH PCMC104T-R36MH 1.05mohm/ Isat =60A rms68.R3610.20S
O/P cap: CHIP CAP POL 330U 2.5V M 6.3*4.5 2.3Arms Matsuti/77.53371.18L Title
H/S: RJK03J6DPA-00#J5A / 10mohm/13mOhm@4.5Vgs/ 84.00036.037 TPS51219 1D05V_VTT
L/S: RJK03K3DPA-00#J5A / 4.9mohm/6.1mOhm@4.5Vgs/ 84.003K3.037 Size Document Number Rev
A3
DNE40 14 CR DIS A00
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
45 of 105
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p5v0p75v
1D5V_PW R 1D5V_S3
D PG4608 D
1 2
DCBATOUT +PW R_SRC_1D5V
1 2 PG4609
1 2
GAP-CLOSE-PW R-3-GP
1 2 PG4610
+PW R_SRC_1D5V 1 2
GAP-CLOSE-PW R-3-GP
5V_S5 1 2 PG4611
1 2
GAP-CLOSE-PW R-3-GP
PC4614
SC1U10V3KX-3GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U50V3KX-GP
SC4D7U25V5KX-GP
w
PC4613
84.00036.037
1
PG4612
PC4601
PC4609
PC4611
PC4612
2nd = 84.07698.037 1 2
w
3D3V_S0
84.00172.037 1 2
1
GAP-CLOSE-PW R-3-GP
2
BSZ115N03MSC PU4602 GAP-CLOSE-PW R-3-GP
5
6
7
8
.ro
PG4613
Id=20A, Qg=9.8nC,
2
1
D
D
D
D
1 2
Rdson=8.9 mohm
PR4604
se
20KR2F-L-GP GAP-CLOSE-PW R-3-GP
PG4614
fix
PU4601 68.R6810.20G
G
4 1 2
2
PR4605_2
S
S
S
20 12 PC4619
19,45,47,93 RUNPW ROK PGOOD V5IN SCD1U25V3KX-GP Id=22~39A Design Current=13.5A GAP-CLOSE-PW R-3-GP
3
2
1
.c
37 0D75V_EN 17 VTTEN
PR4605 DCR=2.4~2.7mohm 20.25A<OCP>24.3A
PG4615
om
C 15 PW R_1D5V_VBST1 2 1 2 1 2 C
PW R_1D5V_EN VBST Size=10X11.5X4
16 EN/PSV 2D2R3-1-U-GP GAP-CLOSE-PW R-3-GP
PW R_1D5V_VREF 6 14 PW R_1D5V_DRVH 1D5V_PW R PG4616
VREF DRVH
1
PL4601 68.1R01C.10Q 1 2
PR4603 2nd = 68.1R01B.10J
10KR2F-2-GP 13 PW R_1D5V_SW 1 2 GAP-CLOSE-PW R-3-GP
SW PG4617
PU4603 COIL-1UH-51-GP-U 1 2
SCD1U10V2KX-5GP
SC4D7U6D3V5KX-3GP
2
5
6
7
8
PW R_1D5V_REFIN 8 11 PW R_1D5V_DRVL
PC4621
REFIN DRVL
1
D
D
D
D
GAP-CLOSE-PW R-3-GP
PC4620
1
1
X01 0605 PG4618
PG4607
10
DY
240R2F-1-GP 57K6R2F-GP
SCD1U50V3KX-GP
SCD1U10V2KX-4GP
SCD01U16V2KX-3GP
PGND
1 PR4601 2
PW R_1D5V_MODE 19 PR4612 PT4603

DY 1 2
GAP-CLOSE-PWR-3-GP
2
MODE
1
2D2R5F-2-GP
PC4603
EC4601
200KR2F-L-GP
SE330U2D5VM-8-GP
GAP-CLOSE-PW R-3-GP
G
PC4602
2
1 PR4608 2
S
S
S
PW R_1D5V_TRIP 18 9 PW R_1D5V_VDDQS PG4619
2
TRIP VDDQS
1 2
97K6R2F-GP
PWR_1D5V_VDDQS
3
2
1
1
TPS51216_PHS_SET
PR4601_1
PR4602
PW R_1D5V_VTTREF5 VTTIN 2
+0D75V_DDR_P 84.003K3.037 GAP-CLOSE-PW R-3-GP
VTTREF 2nd = 84.00312.037
2 PR4606 1
1
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
3 77.53371.18L PG4620
VTT
1
PC4618 PC4622
DY 1 2
PC4616
PC4617
1
1
SCD22U10V2KX-1GP SC330P50V2KX-3GP
PC4615
1 2nd = 77.93971.03L
2
2
VTTS GAP-CLOSE-PW R-3-GP
21 GND DY
2
4 PG4621
2
VTTGND
7 GND 1 2
TPS51216RUKR-GP GAP-CLOSE-PW R-3-GP

74.51216.073 1D5V_PW R
B B
SC1U10V3KX-3GP
PC4604
1
+0D75V_DDR_P 0D75V_S0
PR4607
PG4601
1 2 DDR_VREF_S3 1 2 PW R_1D5V_EN
2
19,27 PM_SLP_S4#
GAP-CLOSE-PW R-3-GP PW R_1D5V_VTTREF 1 PR4611 2
0R0402-PAD
1
PG4602 0R3J-0-U-GP PC4606
1 2 DY SCD1U10V2KX-5GP
2
GAP-CLOSE-PW R-3-GP
State S3 S5 VDDR VTTREF VTT

S0 Hi Hi On On On
S3 Lo Hi On On Off(Hi-Z)
S4/S5 Lo Lo Off Off Off
A MODE M14 DIS A
PR4608 Frequency Discharge Mode I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
200k ohm 400kHz Inductor: CHIP CHOKE 1.0UH PCMB104T-1R0M/ 3.3mohm/ Isat =28A rms /68.1R01C.10Q Wistron Corporation
Tracking Discharge 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
O/P cap: CHIP CAP POL 330U 2.5V M 6.3*4.5 2.3Arms Matsuti/77.53371.18L Taipei Hsien 221, Taiwan, R.O.C.
100k ohm 300kHz
H/S: RJK03J6DPA-00#J5A / 10mohm/13mOhm@4.5Vgs/ 84.00036.037
68k ohm 300kHz Title
L/S: RJK03K3DPA-00#J5A / 4.9mohm/6.1mOhm@4.5Vgs/ 84.003K3.037
Non-tracking Discharge TPS51216_+1.5V_SUS
47k ohm 400kHz
A3
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03-05-151:22:21 PM 3 2
1
46 of 105
5 4 3 2 1
D D
3D3V_S5
SYW231 for 1D8V_S0 D.C. =0.87A
1.29A < OCP <1.52A
w
PG4701
w
1 2
1D8V_PW R 1D8V_S0
PU4701
w
GAP-CLOSE-PW R-3-GP
PL4701
PG4702 PG4704
.ro
1 2 PW R_1D8V_VIN 4 3 PW R_1D8V_PHASE 1 2 1 2
IN LX IND-1D5UH-71-GP-U
5 PG GND 2
se
GAP-CLOSE-PW R-3-GP 6 1 PR4703 GAP-CLOSE-PW R-3-GP
FB EN
1
PG4703 68.1R510.20J 102KR2F-GP PG4705
SC22P50V2JN-4GP
PC4705
1
1
1 2 2nd = 68.1R51B.10Q 1 2
fix
PC4701 PC4702
R1
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SYW 231ABC-GP
1
GAP-CLOSE-PW R-3-GP PC4706 PC4707 GAP-CLOSE-PW R-3-GP
.c
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
PG4706
2
2
1 2
om
C C
2
PW R_1D8V_FB GAP-CLOSE-PW R-3-GP
PG4707
1 2
1
GAP-CLOSE-PW R-3-GP
PR4707
49K9R2F-L-GP
19,45,46,93 RUNPW ROK
PR4702
R2
2
1 2 PW R_1D8V_EN
19,27,36,37 PM_SLP_S3#
1
0R0402-PAD
1
PR4705
PC4704 1MR2F-GP
DY SC22P50V2GN-GP
2
Vo=0.6*(1+(R1/R2))
2
B B
M14 DIS
A A
Wistron Corporation
Title
SYW231_1D8V_S0
A3
http://vinafix.vn
03-05-1512:40:57 PM
5 4 03-05-151:22:21 PM 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_0p85v
3D3V_S0
5V_S5
1
D PR4809 D
4K7R2J-2-GP
PC4812
1
PC4814
1
PR4808 SCD1U10V2KX-L1-GP
2
SC1U6D3V2KX-GP
2
PR4806 DY
2
1R2F-GP 1 2 D85V_PW RGD 42
1
0R0402-PAD PR4804
SC2D2U10V3KX-1GP
0R0402-PAD
PW R_VCCSA_VID1 1 2 VCCSA_SEL1 9
PWR_VCCSA_PGOOD
PR4805
PC4816
PW R_VCCSA_VID0 1 2 VCCSA_SEL0 9
0R0402-PAD
w
PR4801
1
w
PW R_VCCSA_EN 1 2 PC4818
1D05V_VTT_PW RGD 37,45 SCD1U10V2KX-L1-GP
2
DY
1
PWR_VCCSA_V5DRV 0R0402-PAD
.ro
DY
2
D.C. =4.2A
se
PC4810
18
17
16
15
14
13
PU4801 SC1U6D3V2KX-GP 6.6A < OCP < 7.8A
fix
VID1
VID0
PGOOD
EN
V5DRV
V5FILT
PR4807
PC4811
0R3J-0-U-GP
SCD1U25V3KX-GP
.c
19 PGND
5V_S5 20 12 PW R_VCCSA_BST 1 2 PW R_VCCSA_BST_R 1 2
om
C PGND BST C
21 11 0D85V_S0
PGND SW#11
22 VIN SW#10 10 PL4801
23 VIN SW#9 9
24 VIN SW#8 8
2
1
1
PC4815 PC4813 25 7 PW R_VCCSA_SW 1 2

GND SW#7
PC4803
PC4804
PC4806
PC4808
PC4807 COIL-D2UH-2-GP
COMP
MODE
1
SLEW
SC10U6D3V5KX-1GP
VOUT
SC10U10V5KX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SCD1U25V3KX-GP
VREF
SCD1U25V3KX-GP
GND
1
2
2
68.R2010.20B
1
2nd = 68.R2010.10Q
1 PR4813
100KR2F-L1-GP
DY PR4803 DY
2
3
4
5
6
0D85V_S0
1PWR_VCCSA_SNUB
TPS51463RGER-GP 2D2R5F-2-GP
2
PU4801_MODE 1 2
74.51463.043
PWR_VCCSA_VREF
PWR_VCCSA_COMP
PW R_VCCSA_VOUT 1 2
PR4811 100R2F-L1-GP-U
PW R_VCCSA_SLEW PR4812 PR4810
1 2VCCSA_SENSE_L 1 2 VCCSA_SENSE 9
0R0402-PAD 0R0402-PAD
PC4809
DY
1
SC560P50V-GP
2
1
PR4802
2
PR4814
4K99R2F-L-GP
PC4801 10KR2F-2-GP
SCD01U50V2KX-1GP DY
1
2 PWR_VCCSA_COMP_1
VCCSA_SEL Voltage Selection Table
2
B B
XE, QC, SV ULV Only VID[0] VID[1]
0.9 V 0.9 V 0 0
0.8 V 0.85 V 0 1
1
PC4817
SC3300P50V3KX-1GP
0.725 V 0.775 V 1 0
2
0.675 V 0.750 V 1 1
2
PC4802
VID0=0;VID1=1 SCD22U10V2KX-1GP
1
SW frq PR4813
TPS51463 (V)
for ULV 700KHz 100K 0.85
A
1MHz Open 0.85 M14 DIS A
Wistron Corporation
Title
TPS51463_VCCSA
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
48 of 105
SSID = VIDEO
R4910
0R2J-2-GP
LCD1 DBC_EN_R 1 2 LCDVDD
DBC_EN 22 RN4902
41
LVDS_DDC_DATA_R 4 1
1 LVDS_DDC_CLK_R 3 2 3D3V_S0
2
C4901 C4904
2
SRN2K2J-1-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
3
1
4 3D3V_LCD_ROM RN4903
5 LCD_TST_C SRN33J-5-GP-U
6 LVDS_DDC_CLK 3 2 LVDS_DDC_CLK_R 17
7 LVDS_DDC_DATA 4 1 LVDS_DDC_DATA_R 17
8 LVDSA_DATA0#_C
9 LVDSA_DATA0_C
10
11 LVDSA_DATA1#_C RN4907
12 LVDSA_DATA1_C DMIC_CLK_C 1 4
DMIC_DATA_C
13
LVDSA_DATA2#_C
2 FFC 3
14
15 LVDSA_DATA2_C SRN0J-6-GP
16
17 LVDSA_CLK#_C
18 LVDSA_CLK_C
19
20 LVDSB_DATA0#_C RN4908
21 LVDSB_DATA0_C DMIC_CLK_C 2 3
Wire DMIC_CLK 29
22 DMIC_CLK_C DMIC_DATA_C 1 4 DMIC_DATA 29
23 LVDSB_DATA1#_C
24 LVDSB_DATA1_C SRN33J-5-GP-U
25 DMIC_DATA_C RN4904
26 LVDSB_DATA2#_C USB_CAMERA# 2 3 USB_PN13 18
27 LVDSB_DATA2_C USB_CAMERA 1 Wire 4 USB_PP13 18
28
29 LVDSB_CLK#_C SRN0J-6-GP
30 LVDSB_CLK_C
31 RN4906
32 USB_CAMERA#_R 2 3
33 USB_CAMERA_R 1 FFC 4
w
3D3V_CAMERA_S0_R R4927 1 20R2J-2-GP
34
35 LCD_BRIGHTNESS
Wire SRN0J-6-GP
3D3V_CAMERA_S0
INVERTER POWER
36 BLON_OUT_C
w
37
38 DCBATOUT 800mA DCBATOUT_LCD
w
39 DCBATOUT_LCD
40 F4901
.ro
R4905 POLYSW-1D1A24V-GP-U
42 100KR2J-1-GP 1 2
1 2
ACES-CON40-10-GP
se
2
1
20.K0617.040 RN4901 69.50007.A31 C4906
LCD_TST_C C4905
1 8 LCD_TST 27 DY
SC1KP50V2KX-1GP
Close to LCD connector LCD_BRIGHTNESS BKLT_CTRL SCD1U50V3KX-GP
2 7 2nd = 69.50007.D31
fix
BLON_OUT_C 3 6 BLON_OUT 27
USB_CAMERA#_R USB_CAMERA#
4 5 3rd = 69.50007.A41
SRN100J-4-GP
.c
om
TR4901 3D3V_CAMERA_S0
3 4 R4932 1 DY 20R2J-2-GP CAM1
Wire 10
2 1 D4902
1 8 3D3V_S0 5V_S0
L_BKLT_CTRL 17
7 RN4909
FILTER-4P-6-GP BKLT_CTRL DMIC_DATA_C_IO
3 6 2 3 DMIC_DATA 29
69.10103.041 5 DMIC_CLK_C_IO 1 FFC 4 DMIC_CLK 29
1
1
2 KBC_BKLT 27 4
USB_CAMERA_R USB_CAMERA 3 USB_CAMERA#_C_IO SRN33J-5-GP-U R4909 R4928
R4931 BAT54CPT-GP 2 USB_CAMERA_C_IO DY 0R3J-0-U-GP 0R3J-0-U-GP
10KR2J-3-GP RN4905 TPNL1 USB_PN5_TPNL 2 1 USB_PN5 18
83.R2003.E81 1 USB_CAMERA#_C 1 4 USB_PN13 18 7
2
2
USB_CAMERA_C R4930
2ND = 83.00054.Q81 2 FFC 3 USB_PP13 18
TPNL_PWR 0R3J-0-U-GP
9 1
SRN0J-6-GP
ACES-CON8-4-GP-U1 2
3 USB_PN5_TPNL
Close to LVDS connector For EMI request USB_PP5_TPNL
3D3V_S0 3D3V_LCD_ROM 20.F0772.008 4
5
6
R4901 1 2 0R3J-0-U-GP Close to Camera connector 8

LVDSA_CLK LCD_BRIGHTNESS
F4902 1 2 FUSE-2A32V-16-GP ETY-CON6-21-GP
LVDSA_CLK# LCD_TST_C DY USB_PP5_TPNL 2 1 USB_PP5 18
USB_CAMERA#_C_IO USB_CAMERA#_C
LCD_TST R4929
0R3J-0-U-GP
1
EC4907 EC4908 EC4905 EC4901 EC4902 3D3V_S0 3D3V_CAMERA_S0

DY DY
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
TR4910
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
R4906
2
3 FFC 4
1 2
2 1
0R3J-0-U-GP
1
EC4903 DY C4903 FILTER-4P-6-GP

SC33P50V2JN-3GP SC4D7U6D3V3KX-GP
69.10103.041 SSID = VIDEO
2
USB_CAMERA_C_IO USB_CAMERA_C
R4911 R4913 R4915 R4917

LVDSB_CLK#_C 2 1 LVDSB_DATA2#_C 2 1 LVDSB_DATA1#_C 2 1 LVDSB_DATA0#_C 2 1
LVDSB_CLK# 17 LVDSB_DATA2# 17 LVDSB_DATA1# 17 LVDSB_DATA0# 17
0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD D4901
17 LVDS_VDD_EN 1
3 LCDVDD_EN
600mA
27 LCD_TST_EN 2
2
3D3V_S0
BAT54CPT-GP R4907
100KR2J-1-GP
83.R2003.E81 U4901
2ND = 83.00054.Q81 LCDVDD
1
1 5
EN VIN#5
2
R4912 R4914 R4916 R4918 GND
3 4
LVDSB_CLK_C LVDSB_DATA2_C LVDSB_DATA1_C LVDSB_DATA0_C VOUT VIN#4
2 1 LVDSB_CLK 17 2 1 LVDSB_DATA2 17 2 1 LVDSB_DATA1 17 2 1 LVDSB_DATA0 17
1
C4908
0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD RT9724GB-GP SC4D7U6D3V3KX-GP
1
C4909
2
SC4D7U6D3V3KX-GP EC4909
Layout Note: SCD1U25V2KX-GP 74.09724.09F
DY
2
Trace width = 80mil
R4921 R4919 R4923 R4925

LVDSA_CLK#_C 2 1 LVDSA_DATA2#_C 2 1 LVDSA_DATA1#_C 2 1 LVDSA_DATA0#_C 2 1
LVDSA_CLK# 17 LVDSA_DATA2# 17 LVDSA_DATA1# 17 LVDSA_DATA0# 17
0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD
M14 DIS
Wistron Corporation
R4922 R4920 R4924 R4926
LVDSA_CLK_C 2 1 LVDSA_CLK 17 LVDSA_DATA2_C 2 1 LVDSA_DATA2 17 LVDSA_DATA1_C 2 1 LVDSA_DATA1 17 LVDSA_DATA0_C 2 1 LVDSA_DATA0 17 Title
0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD LCD Connector
A2
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03-05-151:22:21 PM
5 4 3 2 1
D D
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.c
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C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
CRT Connector
A3 A00
03-05-1512:40:57
3 PM
03-05-151:22:21 PM 2
1
50 of 105
5 4 3 2 1
SSID = VIDEO
R5101 R5103
HDMI_CLK_R_C# 2 1 HDMI_CLK_R_C#_CON HDMI_DATA0_R_C# 2 1 HDMI_DATA0_R_C#_CON
HDMI Level Shifter 0R0402-PAD 0R0402-PAD
C5103 1 2 SCD1U10V2KX-5GP HDMI_CLK_R_C#

17 HDMI_CLK_R#
1
C5104 1 2 SCD1U10V2KX-5GP HDMI_CLK_R_C
17 HDMI_CLK_R R5114 R5116
C5105 1 2 SCD1U10V2KX-5GP HDMI_DATA0_R_C# 150R2F-1-GP 150R2F-1-GP
17 HDMI_DATA0_R# C5106 SCD1U10V2KX-5GP HDMI_DATA0_R_C
D
17 HDMI_DATA0_R 1 2 D
2
C5110 1 2 SCD1U10V2KX-5GP HDMI_DATA1_R_C#
17 HDMI_DATA1_R 1 2
R5102 R5104
C5108 1 2 SCD1U10V2KX-5GP HDMI_DATA2_R_C# HDMI_CLK_R_C 2 1 HDMI_CLK_R_C_CON HDMI_DATA0_R_C 2 1 HDMI_DATA0_R_C_CON
17 HDMI_DATA2_R 1 2
0R0402-PAD 0R0402-PAD
R5105 R5107
8
7
6
5
8
7
6
5
HDMI_DATA2_R_C# 2 1 HDMI_DATA2_R_C#_CON HDMI_DATA1_R_C# 2 1 HDMI_DATA1_R_C#_CON
w
RN5106 RN5107
SRN680J-GP SRN680J-GP 0R0402-PAD 0R0402-PAD
w
w
1
2
3
4
1
2
3
4
1
.ro
HDMI_PLL_GND
R5115 R5117
150R2F-1-GP 150R2F-1-GP
se
2
R5123
2
fix
DY 0R2J-2-GP
D
Q5105
5V_S0 2N7002BK-GP
.c
1
84.07002.I31
om
C C
G 2nd = 84.2N702.W31 R5106 R5108
3rd = 84.2N702.J31
1
HDMI_DATA2_R_C 2 1 HDMI_DATA2_R_C_CON HDMI_DATA1_R_C 2 1 HDMI_DATA1_R_C_CON

R5113
DY 100KR2J-1-GP 0R0402-PAD 0R0402-PAD HDMI CONN
S
2
5V_S0
HDMI1
3
22
D5101 20
BAW 56-2-GP HDMI_DATA2_R_C_CON 1
83.00056.G11 HDMI_DATA2_R_C#_CON
2
3
2
3DDC_DATA_PH2 1
2nd = 83.00056.N11 HDMI_DATA1_R_C_CON 4

5
DDC_CLK_PH1
HDMI_DATA1_R_C#_CON 6
HDMI_DATA0_R_C_CON 7
8
HDMI_DATA0_R_C#_CON 9
HDMI_CLK_R_C_CON 10
11
4
HDMI_CLK_R_C#_CON 12
3D3V_S0 13
RN5101 14
SRN2K2J-1-GP DDC_CLK_HDMI 15
5V_S0 5V_HDMI_S0 5V_HDMI_S0_R 5V_HDMI_S0_R DDC_DATA_HDMI 16
B B
Q5104 R5109 F5101 17
1
2
18
4 3 DDC_CLK_HDMI 1 2 1 2 19
17 PCH_HDMI_CLK
21
1
5 2 FUSE-1D1A6V-4GP-U C5102 23
0R0603-PAD SCD1U10V2KX-5GP
69.50007.691
6 1 2nd = 69.50007.771 SKT-HDMI23P-2-GP
2
22.10296.311
HPD_HDMI_CON
2N7002KDW -GP
17 PCH_HDMI_DATA
DDC_DATA_HDMI
3D3V_S0
84.2N702.A3F
2nd = 84.DM601.03F R5111
3
3rd = 84.2N702.E3F 150KR2F-L-GP
4th = 84.2N702.F3F Q5102 1 HDMI_HPD_B 2 1
PMBS3904-1-GP
R5125
1
0R0402-PAD
17 HDMI_PCH_DET 1 2 HDMI_HPD_E 84.03904.L06 R5110
2nd = 84.03904.P11 DY 200KR2J-L1-GP
1
R5112
2
10KR2J-3-GP
M14 DIS
2
A A
Wistron Corporation
Title
HDMI Level Shifter/Connector

A3 A00
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03-05-1512:40:57 PM
5 4 03-05-151:22:21 PM 3 2 1
5 4 3 2 1
D D
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C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
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03-05-151:22:21 PM
3 2
1
52 of 105
5 4 3 2 1
D D
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w
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.ro
se
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.c
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C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
LVDS_Switch
A3
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03-05-151:22:21 PM
3 2
1
53 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
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.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
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03-05-151:22:21 PM
3 2
1
54 of 105
5 4 3 2 1
SSID = User.Interface
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Size
ITP/Fan Connector
Document Number Rev
A3
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3 2
1
55 of 105
SSID = SATA
SATA HDD Connector

HDD1
3D3V_S0 P1 V33 23 23
P2 24
P3
V33 24 1A 550mA
V33
NP1 NP1
P7 NP2 5V_S0 3D3V_S0
5V_S0 V5 NP2
P8 V5
P9 V5
C5605
C5606
C5601
C5604
P13 S1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
V12 GND
P14 V12 GND S4
1
P15 V12 GND S7
GND P4 DY DY
w
P5
2
SCD01U16V2KX-3GP GND
21 PCH_TXP_HDD_RXP0 2 1 C5602 HDD_RXP_C_PCH_TXP0 S2 A+ GND P6
w
21 PCH_TXN_HDD_RXN0 SCD01U16V2KX-3GP 2 1 C5603 HDD_RXN_C_PCH_TXN0 S3 P10
A- GND
P12
w
SCD01U16V2KX-3GP GND
21 PCH_RXP_C_HDD_TXP0 1 2C5615 HDD_TXP_PCH_RXP0 S6 B+
.ro
SCD01U16V2KX-3GP 1 2C5616 HDD_TXN_PCH_RXN0 S5 P11
21 PCH_RXN_C_HDD_TXN0 B- DAS/DSS
se
SKT-SATA7P-15P-27-GP-U
Close to HDD1
fix
22.10300.991
.c
om
ODD Connector ODD_PW R_5V
SATA Zero Power ODD
ODD1
14 3D3V_S0
NP1
22 SATA_ODD_PW RGT 2.5A
U5601
R5607 SY6288CCAC-GP ODD_PW R_5V
6
5 SATA_ODD_PW RGT 2 1 5V_S0
4 SATA_ODD_DA#_C 1 2R5602 SATA_ODD_DA# 18 4 5
0R2J-2-GP EN/EN# OCB ODD_PW R_5V
3 100KR2J-1-GP 3 IN#3 OUT#6 6 100 mil
2 2 IN#2 OUT#7 7
1 GND OUT#8 8
1
1 SATA_ODD_PRSNT# SATA_ODD_PRSNT# 22 follow CKL1.5 C5609
1
SC10U6D3V5KX-1GP C5610
S7 SC10U6D3V5KX-1GP
SUPPORT ZERO SATA 74.02001.079
2
S6 ODD_TXP_PCH_RXP4 C5608 1 2SCD01U16V2KX-3GP PCH_RXP_C_ODD_TXP4 21
2
ODD_TXN_PCH_RXN4 C5607 1 2SCD01U16V2KX-3GP
S5
S4
PCH_RXN_C_ODD_TXN4 21 ODD 2nd = 74.06288.079
ODD_RXN_C_PCH_TXN4 C5611 1 2 SCD01U16V2KX-3GP
S3
S2 ODD_RXP_C_PCH_TXP4 C5612 1 2 SCD01U16V2KX-3GP
PCH_TXN_ODD_RXN4 21
PCH_TXP_ODD_RXP4 21
3rd = 74.02311.079
S1
1
NP2 R5604 Current limit

15 DY 10KR2J-3-GP Active High
SKT-SATA7P-6P-130-GP
typ =>2.5A
2
22.10300.581 When the drive is powered on, the FET to the MD/DA pin drive is OFF.
When the drive is powered off, the FET to the MD/DA pin is ON
3D3V_S0 3D3V_S0
A00-0408 Add R5606 to pull high 3.3V_S0

2
R5605 R5606 Change pull high to 3.3V_S0

100KR2J-1-GP
DY DY 10KR2J-3-GP
A00-0415 Dummy R5606
1
SATA_ODD_DA#_C
ODD_PWRGT#
6
4
D2
G1
S1
Q5601 M14 DIS

DY ME2N7002DKW -G-GP
D1
S2
G2
84.2N702.F3F
Wistron Corporation
1
2nd = 84.2N702.A3F 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

3rd = 84.DMN66.03F Taipei Hsien 221, Taiwan, R.O.C.
Title
SATA_ODD_PW RGT SATA_ODD_DA#
HDD/ODD
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03-05-1512:40:57 PM
A3
5 4 3 2 1
SSID = ESATA
D D
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.c
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C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
ESATA
A3
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3 2
1
57 of 105
5 4 3 2 1
SSID = AUDIO
X01 0605
Layout Note: MIC_JACK_R

D Speaker trace width=30mil D
AUD_PORTA_L_R_B
R5801~R5804 and EC5804~EC5806
near codec as possible AUD_PORTA_R_R_B
SPK1
6 AUD_SENSE
4 AUD_SPK_L-_C R5801 1 2 0R0603-PAD
AUD_SPK_L+_C R5802 1 AUD_SPK_L- 29
3 2 0R0603-PAD AUD_SPK_L+ 29
2 AUD_SPK_R-_C R5803 1 2 0R0603-PAD AUD_SPK_R- 29
2
w
1 AUD_SPK_R+_C R5804 1 2 0R0603-PAD AUD_SPK_R+ 29 D5801 D5802 D5803 D5804
w
5
AZ2025-01H-GP-U
AZ2025-01H-GP-U
AZ2025-01H-GP-U
AZ2025-01H-GP-U
ACES-CON4-7-GP-U
.ro
20.F0772.004
se
2
2
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
DY DY DY DY
fix
DY DY DY DY
EC5804
EC5803
EC5802
EC5806
.c
1
1
AFTP5801 1 AUD_SPK_L-_C
om
C AFTP5802 1 AUD_SPK_L+_C C
AFTP5803 1 AUD_SPK_R-_C
AFTP5804 1 AUD_SPK_R+_C
AUD_AGND
Combo Jack change to 22.10270.P81, but symble not change R5808 1 2 2K2R2J-2-GP MIC2-VREFO 29
HPMIC1
3 MIC_JACK_R R5814 1 2 0R3J-0-U-GP SLEEVE 29
1 AUD_PORTA_L_R_B R5806 1 2 0R3J-0-U-GP AUD_HP1_JACK_L1 R5810 1 218R2F-1-GP AUD_HP1_JACK_L 29
5 JACK_POWER R5809 1 DY 2 20KR2F-L-GP 3D3V_S0
6
2 AUD_PORTA_R_R_B R5807 1 2 0R3J-0-U-GP AUD_HP1_JACK_R1 R5811 1 218R2F-1-GP AUD_HP1_JACK_R 29
B 4 29 AUD_HP1_JACK_L1 B
7 R5813 1 20R3J-0-U-GP AUD_AGND SLEEVE 1 2 COMBO-GPI 29
R5817
29 AUD_HP1_JACK_R1
1
AUDIO-JK363-GP JACK_JD 22KR2J-GP
1
1
EC5808 EC5805 EC5807 R5816
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
22KR2J-GP C5805
G
22.10270.P81
1
C5806 R5805 SC10U6D3V3MX-GP

2
2
AUD_AGND Q5801
SC10U6D3V3MX-GP
DY
2
47KR2F-GP
DY 2N7002K-2-GP
2
AUD_AGND
AUD_AGND
2
DY
D
AUD_AGND
M14 DIS
AUD_AGND AUD_AGND
R5812 1 2 AUD_SENSE 29
A
0R3J-0-U-GP
Wistron Corporation A
Title
Speaker/HPMIC CONN
A4
5 4
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03-05-151:22:21 PM
3
2
Sheet 58
1
of 105
5 4 3 2 1
SSID = LOM
D D
LAN TransFormer
XF5901 X01 0605
Rx Side
9 8 MDO1-
31 LAN_MDI1N
U5901
TVLST2304AD0-GP
w
11 6 MCT1 MCT1
w
10 7 MDO1+
w
31 LAN_MDI1P
LAN_MDI1N 6
.ro
1CT:1CT
Tx Side LAN_MDI1P 4
15 2 MDO0-
se
31 LAN_MDI0N
LAN_MDI0N 3
fix
14 3 MCT0 MCT0 LAN_MDI0P 1
DY
.c
5
MDO0+
LOM_TCT
31 LAN_MDI0P 16 1
om
C C
1CT:1CT
XFORM-12P-36-GP 83.02304.0AE
68.HD081.30B 2nd = 83.42236.0AE
1
C5902
SCD1U10V2KX-5GP 3rd = 83.08902.0AE
2
4th = 83.09904.AAE
B B
RJ45
RJ45
9 CHASSIS
MDO0+ 1
MDO0- 2
MDO1+ 3 MDO1+ 1 AFTP5901
MCT0 4 MDO1- 1 AFTP5904
5 MDO0+ 1 AFTP5907
MCT1 MDO1- 6 MDO0- 1 AFTP5908
A 7 <Core Design> A
8
10
5
6
7
8
RN5901
CHASSIS
RJ45-8P-123-GP Wistron Corporation
SRN75J-1-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
22.10019.161
Title
4
3
2
1
C5907 2 1 MCT XFOM&RJ45

SC100P3KV8JN-GP Size Document Number Rev
A3
78.1013N.14L OAK14 Chief River DIS A00
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03-05-151:22:21 PM 3 2
1
59 of 105
5 4 3 2 1
SSID = Flash.ROM
SPI Flash ROM(8M) for PCH
3D3V_S5
3D3V_S5
1
D C6001 D
SC10U6D3V3MX-GP C6002
SCD1U10V2KX-5GP
DY
2
2
4
3
R6003 RN6001
4K7R2J-2-GP SRN4K7J-8-GP
PCH
1
2
SPI_HOLD_0#
U6001 3D3V_S5 SPI
w
21,27 SPI_CS0#_R 1 CS# VCC 8
21,27 SPI_SO_R 2 DO/IO1 HOLD#/IO3 7
w
SPI_W P# 3 6 SPI_CLK_R 21,27
WP#/IO2 CLK
4 5
w
SPI_SI_R 21,27
GND DI/IO0 KBC
.ro
1
1
W 25Q64CVSSIG-GP
EC6002 EC6001
DY DY DY
se
SC4D7P50V2CN-1GP 72.25Q64.B01 SC10P50V2JN-4GP
2
2
2nd = 72.25640.D01 Layout Note:
fix
3rd = 72.25Q64.F01 EC6003
4th = 72.25Q64.D01 SC4D7P50V2CN-1GP KBC----10"----PCH
.c
KBC----1.5"~6.5"----SPI
PCH----0.5"~6.5"----SPI
om
C C
SSID = RBATT
3D3V_AUX_S5
B B
RTC_AUX_S5 D6001
2
+RTC_VCC
3 R6002 RTC1
1KR2J-1-GP
1 RTC_PW R 1 2 1 PWR
2
1 2 GND
C6003 CH715FPT-GP TP6001 NP1
SC1U6D3V2KX-GP NP1
NP2
1
NP2
83.R0304.B81
2nd = 83.00040.E81
BAT-AAA-BAT-054-P04-GP-U1
62.70001.061
+RTC_VCC 1 TP6002
R6006
100R2J-2-GP
1 2
DY
RTC_PW R
G
1
R6007
A 10MR2J-L-GP M14 DIS A
S D RTC_DET# 22
2
Q6002 Wistron Corporation

2N7002BK-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
84.07002.I31
2nd = 84.2N702.W31 Title
3rd = 84.2N702.J31
Flash/RTC
A3 A00
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03-05-151:22:21 PM 3 2
1
60 of 105
5 4 3 2 1
USB30_VCCA
2A
5V_S5 U6102
1 8 USB_OC#0_1 18
GND FLG1 USB3.0 Port1
1
2 7 USB30_VCCB TC6105 C6111
IN OUT1
SE220U6D3VM-30-GP
SC1U10V3KX-3GP
D 3 6 D
EN1# OUT2 USB30_VCCA
1
C6102 27 USB_PWR_EN# 4 5
2
SC1U10V3ZY-6GP EN2# FLG2
2
AP2182SG-13-GP
74.02182.071
77.52271.09L
w
USB30_VCCB
w
2A
w
.ro
C6107
SCD1U10V2KX-4GP
C6108
SC1U10V3KX-3GP
C6109
SCD1U10V2KX-4GP
TC6104
se
USB3.0 Port2
1
fix
SC100U6D3V6MX-GP
78.10710.52L
.c
2
om
C C
Right USB Power x1

5V_S5
Support 2A
+5V_USB1
U6101 2A
at least 80 mil at least 40 mil
2 IN#2 OUT#6 6
SC1U10V3KX-3GP
SCD1U10V2KX-5GP
100KR2J-1-GP
3 IN#3 OUT#7 7
1
R6101
C6121
C6122
8 TC6102
OUT#8
1
1
SC100U6D3V6MX-GP
C6101
27 USB_PWR_EN# 4 EN/EN# DY 78.10710.52L
B 1
DY B
2
2
GND
SCD1U10V2KX-5GP
5 9
2
18 USB_OC#4_5 FLT# GND
TPS2000CDGNR-GP
74.02000.B71
M14 DIS
A
Title
USB Power SW
5 4
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03-05-151:22:21 PM
3
2
Sheet 61
1
of 105
5 4 3 2 1
SSID = USB USB3.0 Port1
18 USB_PN1 USB20_DN1_C
USB20_DN1_C 1 AFTP6204
U6204 USB30_VCCA USB30_VCCA 1 AFTP6205
USB20_DP1_C 1 AFTP6209
USB20_DN1_C 1 8
TR6204 USB20_DP1_C I/O_1 VDD
2 I/O_2 GND 7
D 1 2 USB30_RXDP2_C 3 6 USB30_TXDP2_C D
USB30_RXDN2_C I/O_3 I/O_6 USB30_TXDN2_C
4 I/O_4 I/O_5 5
4 3 DY USB30_VCCA
FILTER-4P-6-GP TVW MSOP06AD0-GP
69.10103.041
USB1
83.00060.0AJ
1 2 USB20_DN1_C
USB20_DP1_C VBUS D- USB20_DP1_C
18 USB_PP1 D+ 3
USB30_RXDN2_C 5
USB30_RXDP2_C STDA_SSRX-
6 STDA_SSRX+ GND_DRAIN 7
C6222
R6281 R6283 USB30_TXDN2_C 8 STDA_SSTX-
w
1 2 USB30_TXDP2_R 2 1 USB30_TXDP2_C 18 USB3_RX2_P 2 1 USB30_RXDP2_C USB30_TXDP2_C 9 10
18 USB3_TX2_P STDA_SSTX+ GND
GND 11
w
0R0402-PAD 0R0402-PAD 12 4
SCD1U10V2KX-5GP CHASSIS#12 GND
13
w
CHASSIS#13
.ro
SKT-USB13-18-GP-U
22.10339.331
se
fix
AFTP6218 1
.c
om
C C
C6223
R6282 R6284
1 2 USB30_TXDN2_R 2 1 USB30_TXDN2_C 18 USB3_RX2_N 2 1 USB30_RXDN2_C
18 USB3_TX2_N
0R0402-PAD 0R0402-PAD
SCD1U10V2KX-5GP
USB3.0 Port2
18 USB_PN0 USB20_DN0_C USB30_VCCB 1 AFTP6210

USB30_VCCB USB20_DN0_C 1 AFTP6211
U6205 USB20_DP0_C 1 AFTP6212
USB20_DN0_C 1 8
TR6207 USB20_DP0_C I/O_1 VDD
2 I/O_2 GND 7
1 2 USB30_RXDP1_C 3 6 USB30_TXDP1_C
USB30_RXDN1_C I/O_3 I/O_6 USB30_TXDN1_C
4 I/O_4 I/O_5 5
4 3 DY USB30_VCCB
FILTER-4P-6-GP TVW MSOP06AD0-GP

69.10103.041 USB2
83.00060.0AJ 1 2 USB20_DN0_C
B VBUS D- USB20_DP0_C B
D+ 3
18 USB_PP0 USB20_DP0_C
USB30_RXDN1_C 5
USB30_RXDP1_C STDA_SSRX-
6 STDA_SSRX+ GND_DRAIN 7
USB30_TXDN1_C 8
USB30_TXDP1_C STDA_SSTX-
9 STDA_SSTX+ GND 10
GND 11
12 CHASSIS#12 GND 4
13 CHASSIS#13
C6225
R6287 R6289 SKT-USB13-18-GP-U
1 2 USB30_TXDP1_R 2 1 USB30_TXDP1_C 18 USB3_RX1_P 2 1 USB30_RXDP1_C 22.10339.331
18 USB3_TX1_P
0R0402-PAD 0R0402-PAD
SCD1U10V2KX-5GP
AFTP6217 1
A M14 DIS A
C6224
R6288 R6290
USB30_TXDN1_R USB30_TXDN1_C USB30_RXDN1_C
18 USB3_TX1_N 1 2 2 1 18 USB3_RX1_N 2 1
Wistron Corporation
0R0402-PAD 0R0402-PAD 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
SCD1U10V2KX-5GP Taipei Hsien 221, Taiwan, R.O.C.
Title
USB 3.0
A3
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03-05-151:22:21 PM 3 2
1
62 of 105
5 4 3 2 1
SSID = USB
D D
w
w
w
.ro
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fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
USB3.0 PORT
A3
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03-05-151:22:21 PM
3 2
1
63 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
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C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Size
RESERVED
Document Number Rev
A3 OAK14 Chief River DIS A00
03-05-1512:40:57
3 PM
03-05-151:22:21 PM 2
1
64 of 105
5 4 3 2 1
SSID = Wireless Mini Card Connector(802.11a/b/g) WLAN1
1D5V_S0 6 1.5V REFCLK+ 13 CLK_PCIE_WLAN 20

REFCLK- 11 CLK_PCIE_WLAN# 20
3D3V_S0 2 3.3V
PERN0 23 PCIE_RXN3 20
D 28 25 D
1D5V_S0 +1.5V PERP0 PCIE_RXP3 20
48 +1.5V
PETN0 31 PCIE_TXN3 20
3D3V_S0 52 +3.3V PETP0 33 PCIE_TXP3 20
24 36 USB_PN11_R
+3.3VAUX USB_D- USB_PP11_R
USB_D+ 38
TP6506 1 WLAN_ACT 3 30
BT_ACT RESERVED#3 SMB_CLK
5 RESERVED#5 SMB_DATA 32
w
8 RESERVED#8
w
10 RESERVED#10
12 1
w
RESERVED#12 WAKE#
14 7
.ro
RESERVED#14 CLKREQ# CLK_PCIE_WLAN_REQ# 20
16 RESERVED#16 PERST# 22 PLT_RST# 5,18,27,31,71,83
R6513 1 20R2J-2-GP E51_RX
se
27 E51_RXD 17 RESERVED#17
27 E51_TXD R6512 1 20R2J-2-GP E51_TX 19 RESERVED#19
fix
R6515 27 WIFI_RF_EN 20 4
0R2J-2-GP RESERVED#20 GND
37 9
.c
BT_ACT 1 RESERVED#37 GND
2 3D3V_S0 39 RESERVED#39 GND 15
om
C 41 RESERVED#41 GND 18 C
43 RESERVED#43 GND 21
27 BLUETOOTH_EN 1 2 R6516 45 26
R6514 0R2J-2-GP 0R2J-2-GP RESERVED#45 GND
47 RESERVED#47 GND 27
1 2 DEBUG 49 29
RESERVED#49 GND
5V_S0 1 DY 2+5V_MINI_DEBUG 51 RESERVED#51 GND 34
R6504 0R2J-2-GP 35
GND
GND 40
42 LED_WWAN# GND 50
27 CARD_WLAN_OUT# 44 LED_WLAN# GND 53
27 CARD_WPAN_OUT# 46 54
NP1
NP2
LED_WPAN# GND
SKT-MINI52P-81-GP
NP1
NP2
62.10043.C81
1.1A 375mA
3D3V_S0 1D5V_S0 R6506
B 0R0603-PAD B
USB_PN11_R 1 2 USB_PN11 18
1
C6502 C6503 C6504 C6505 C6506

DY
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
SC10U6D3V5KX-1GP
2
5V_S5 R6505
WLAN_ACT 0R0603-PAD
SCD1U25V2KX-GP
SCD1U25V2KX-GP
USB_PP11_R 1 2 M14 DIS

USB_PP11 18
1
C6501 C6508
DY DY
Wistron Corporation
2
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A

Title
MINICARD(WLAN)/ITP CONN
A4
5 4
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03-05-151:22:21 PM
3
2
Sheet 65
1
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5 4 3 2 1
D D
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w
w
.ro
se
fix
.c
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C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
66 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
67 of 105
5 4 3 2 1
Wireless LED
FRONT POWER LED Low actived from KBC GPIO
Low actived from KBC GPIO
5V_S0
5V_S5
D Q6805 W LED1 D
R2
Q6801 PLED1 E R6808
3
R2
E R6806 27 W LAN_LED# B
3
R1
27 PW RLED# B R1 C W LAN_LED_R 2 1 W LAN_LED_A 1A K2
C LED_PW R 2 1 FPOW ER_LED_A 1 A K2
PDTA144VT-GP 330R2J-3-GP LED-W -27-GP
PDTA144VT-GP 330R2J-3-GP LED-W -27-GP 84.00144.P11 83.01221.R70
1
84.00144.P11 83.01221.R70 2nd = 84.DT144.A11
1
DY EC6806
2nd = 84.DT144.A11 2nd = 83.00110.R70
DY EC6801 2nd = 83.00110.R70 SCD1U25V2KX-GP
2
SC220P50V2KX-3GP
3rd = 83.01105.070
2
3rd = 83.01105.070
Place EC6806 near WLED1
w
w
w
.ro
se
SATA HDD LED(White) Power button
fix
.c
Low actived from PCH GPIO
om
C C
PW RBT1
5V_S0 6
Q6802 HDLED1 1 2 KBC_PW RBTN#_C 4

R2 27 KBC_PW RBTN# R6802
E R6812 3
3
21 SATA_LED# B 100R2J-2-GP 2
R1
C SATA_LED_R 2 1 HDD_LED_A 1A K2
1
AFTP6801 1 1
PDTA144VT-GP 330R2J-3-GP LED-W -27-GP DY EC6808
SCD1U25V2KX-GP
84.00144.P11 83.01221.R70 5
2
1
2nd = 84.DT144.A11
DY EC6810
SC220P50V2KX-3GP
2nd = 83.00110.R70 ETY-CON4-34-GP
2
3rd = 83.01105.070 20.K0465.004 AFTP6802

1
Battery LED1 (AMBER_LED)

B
Low actived from KBC GPIO B
5V_S5
Q6804
R2
E
27 CHG_AMBER_LED# B R6803
R1
C AMBER_LED_BAT 2 1 BAT_AMBER
PDTA144VT-GP 499R2F-2-GP
84.00144.P11 AMBER
1
2nd = 84.DT144.A11
DY EC6809
SC220P50V2KX-3GP
CHLED1
2
1 ORANGE
+
- 3
2 +
WHITE
5V_S5
LED-OW -8-GP
Q6803 83.01222.X80
R2
E R6801
B
27 BATT_W HITE_LED# R1
C W HITE_LED_BAT 2 1 BAT_W HITE WHITE
PDTA144VT-GP 330R2J-3-GP
84.00144.P11
1
2nd = 84.DT144.A11 M14 DIS

A DY EC6807
SC220P50V2KX-3GP
A
2
Wistron Corporation
Title
Battery LED2 (WHITE_LED) LED Bard/Power Button
Low actived from KBC GPIO A3
http://vinafix.vn
03-05-1512:40:57 PM
5 4 03-05-151:22:21 PM 3 2 1
5 4 3 2 1
SSID = KBC SSID = Touch.Pad

TP_VDD 1 AFTP6906
TPCLK_C 1 AFTP6907
TPDATA_C 1 AFTP6908
PCH_SMBCLK 1 AFTP6933
Internal Keyboard Connector Touch Pad Connector PCH_SMBDATA 1 AFTP6937
D D
KB1 1 AFTP6901 TP_VDD TP_VDD

31 TP_VDD R6909 3D3V_S0
1 0R0402-PAD
KB_DET# 21
1 2
2 KROW7 1 AFTP6909
1
2
1
3 KROW6 1 AFTP6910 C6901
w
4 KROW4 1 AFTP6911 RN6901 SCD1U10V2KX-5GP
KROW2 AFTP6913 SRN10KJ-5-GP
w
5 1
2
6 KROW5 1 AFTP6912
w
7 KROW1 1 AFTP6914 TPAD1
.ro
8 KROW3 1 AFTP6916 7
4
3
KROW0 AFTP6915
se
9 1 1
10 KCOL5 1 AFTP6917
fix
11 KCOL4 1 AFTP6919 27 TPCLK R6911 1 2 0R2J-2-GP TPCLK_C 2
12 KCOL7 1 AFTP6918 R6910 1 2 0R2J-2-GP TPDATA_C 3
.c
27 TPDATA
13 KCOL6 1 AFTP6920 4
om
C 14 KCOL8 1 AFTP6922 KROW[7..0] 27 14,15,20 PCH_SMBCLK 5 C
1
1
15 KCOL3 1 AFTP6921 14,15,20 PCH_SMBDATA 6
16 KCOL1 1 AFTP6923 EC6917 DY DY EC6918 8
17 KCOL2 1 AFTP6925 KCOL[16..0] 27 SC33P50V2JN-3GP SC33P50V2JN-3GP
2
2
18 KCOL0 1 AFTP6924 1 PTWO-CON6-12-GP
KCOL12 AFTP6926 AFTP6935
19
20 KCOL16
1
1 AFTP6928 20.K0382.006
21 KCOL15 1 AFTP6927
24 KCOL9 1 AFTP6930
27 CAP_LED
28
29 CAP LED Control
30 1 AFTP6902
32
LOW actived from KBC GPIO
ACES-CON30-10-GP
B B
20.K0592.030 5V_S0
Q6902 R2
E
B R6906
27 CAP_LED# R1
CAP_LED_Q CAP_LED
C 1 2
PDTA144VT-GP 1KR2J-1-GP
1
EC690284.00144.P11
SCD1U25V2KX-GP
DY 2nd = 84.DT144.A11
2
M14 DIS
A
Title
Key Board/Touch Pad

A4 A00
5 4
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3
2
Sheet 69
1
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5 4 3 2 1
D D
3D3V_S5
3D3V_S5
w
w
2
w
R7001 C7001
.ro
100KR2J-1-GP SCD1U10V2KX-5GP LIDSW1
se
1
1
VSS
fix
2 VDD
LID_CLOSE# 3
.c
27 LID_CLOSE# OUT
om
C C
S-5712ACDL1-M3T1U-GP
1
C7002
DY SCD047U16V2KX-1-GP 74.05712.0BB
2
B B
M14 DIS
A
Title
Hall Sensor
A4 A00
5 4
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3
2
Sheet 70
1
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5 4 3 2 1
SSID = DEBUG PORT

Layout Note: Debug Connector
Place near trace separated point 3D3V_S0
DB1
11
LPC_AD[3..0] RN7101 1
21,27 LPC_AD[3..0]
SRN0J-7-GP
LPC_AD0 1 8 LPC_LAD0_R 2
D LPC_AD3 4
DY 5 LPC_LAD3_R 5 D
LPC_FRAME#_DEBUG 6
1 2 PLT_RST#_DEBUG 7
21,27 LPC_FRAME#
R7101 1
DY 2 0R2J-2-GP 8
5,18,27,31,65,83 PLT_RST#
R7102 DY 0R2J-2-GP 9
18 CLK_PCI_LPC
10
12
PAD-10P-177042-GP
ZZ.00PAD.Y41
w
w
SSID = CPU
w
.ro
se
fix
.c
om
C C
CPU XDP
XDP_PREQ# 1 TP7101
5 XDP_PREQ# XDP_PRDY# TP7102
5 XDP_PRDY# 1
5 XDP_BPM0 XDP_BPM0 1 TP7103




B CFG0 TP7111 B
7 CFG0 1
M14 DIS
A A
Wistron Corporation
Title
Dubug connector
A3
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5 4 03-05-151:22:21 PM 3 2 1
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
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C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
72 of 105
5 4 3 2 1
D D
w
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.ro
se
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.c
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C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
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03-05-151:22:21 PM
3 2
1
73 of 105
5 4 3 2 1
SSID = SDIO
3D3V_CARD_S0
CARD1
11 SD_VDD/MMC_VDD MS_DATA0 12 XD_D1/SD_D5/MS_D0 32

MS_DATA1 13 XD_D4/SD_D3/MS_D1 32
4 10 XD_D0/SD_CLK/MS_D2_R XD_D0/SD_CLK/MS_D2_R 32
MS_VCC MS_DATA2
MS_DATA3 7 XD_ALE/SD_D7/MS_D3 32
D 3D3V_CARD_S0 32 XD_W E#/SD_CD# 20 8 XD_RE#/MS_INS# 32 D

SD_CD MS_INS
32 XD_D4/SD_D3/MS_D1 3 SD_CD/DAT3/MMC_RSV MS_BS 15 XD_D6/MS_BS 32
MS_SCLK 5 XD_RDY/SD_W P/MS_CLK 32
XD_D0/SD_CLK/MS_D2_R 14
SC2D2U6D3V3KX-GP
32 XD_D0/SD_CLK/MS_D2_R SD_CLK/MMC_CLK
6 23
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
32 XD_D2/SD_CMD SD_CMD/MMC_CMD 23
C7404
C7405
24 24
1
1
C7401
C7402
C7403
32 XD_CLE/SD_D0/MS_D7 18 SD_DAT0/MMC_DAT
DY DY DY 32 XD_CE#/SD_D1
32 XD_D5/SD_D2/MS_D5
19
1
SD_DAT1
21
2
2
SD_DAT2 SD_GND
32 XD_RDY/SD_W P/MS_CLK 22 SD_WP/SW MS_VSS 16
MS_VSS 2
NP1 NP1 SD_VSS/MMC_VSS1 9

NP2 NP2 SD_VSS/MMC_VSS2 17
w
w
SKT-CARDREADER26-GP
w
62.10051.C21
.ro
se
fix
Close to Socket
.c
om
C 3D3V_CARD_S0 Vendor recommand C
XD_ALE/SD_D7/MS_D3
XD_D1/SD_D5/MS_D0
XD_CLE/SD_D0/MS_D7
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
XD_CE#/SD_D1
1
XD_D5/SD_D2/MS_D5
C7406
C7407
XD_D4/SD_D3/MS_D1
XD_D2/SD_CMD
2
XD_D0/SD_CLK/MS_D2_R
XD_W E#/SD_CD#
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
XD_RDY/SD_W P/MS_CLK
EC7401
EC7402
EC7403
EC7404
EC7405
EC7406
EC7407
EC7408
EC7409
EC7410
1
1
For EMI
2
B B
A M14 DIS A
Wistron Corporation
Title
SD/XD/MS/MMC Card CONN

A3
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03-05-151:22:21 PM 3 2
1
74 of 105
5 4 3 2 1
D D
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.c
(Blanking)
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C C
B B
M14 DIS
A A
Wistron Corporation
Title
Express Card
A3
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5 4 03-05-151:22:21 PM
3 2 1
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
76 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
77 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
78 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Free Fall Sensor

A3
03-05-1512:40:57
3 PM
03-05-151:22:21 PM 2
1
79 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
80 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
Reserved
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
81 of 105
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
USB_PN2_R
18 USB_PN2
TR8201
4 3
1 2
IOBD1 +5V_USB1
7 FILTER-4P-6-GP
1 1 AFTP8201
2 USB_PP2_R
18 USB_PP2
3 USB_PN2_R
4 USB_PP2_R
5
6
8
B PTW O-CON6-13-GP B
20.K0397.006
1 AFTP8204
U8202
USB_PP2_R 1 6 USB_PN2_R
USB_PN2_R AFTP8203 VI/O#1 VIO#6
1
USB_PP2_R 1 AFTP8202 2 5 +5V_USB1
GROUND VBUS
DY
3 VIO#3 VIO#4 4
IP4223CZ6-GP
A M14 DIS A
Wistron Corporation
Title
Size
IO Board Connector
Document Number Rev
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
82 of 105
5 4 3 2 1
dGPU Reset
3D3V_VGA_S0
U8301
22 DGPU_HOLD_RST# 1 5
A VCC
5,18,27,31,65,71 PLT_RST# 2
B OPS
3 4
GND Y
U74LVC1G08G-AL5-R-GP-U 1D05V_VGA_S0
73.01G08.EHG
1
2ND = 73.7SZ08.EAH
D 3RD = 73.01G08.L04 R8309 D
R8306 1 DY 2 0R2J-2-GP OPS 100KR2F-L1-GP
1
3D3V_VGA_S0 OPS OPS OPS OPS OPS OPS OPS
C8332 C8331 C8319 C8321 C8322 C8334 C8335
2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V3MX-GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
GPU1A 1 OF 17
2
1/17 PCI_EXPRESS
R8310
OPS 10KR2J-3-GP AJ11
G
PEX_WAKE#
AG19
VGA_RST# PEX_IOVDD_1
AJ12 AG21
1
PEX_RST# PEX_IOVDD_2
AG22
PEX_CLKREQ# PEX_IOVDD_3
20 PEG_CLKREQ# D S AK12 AG24
PEX_CLKREQ# PEX_IOVDD_4
Q8301 OPS AL13
PEX_IOVDD_5
AH21
AH25
1.05V +/- 5%
20 CLK_PCIE_VGA PEX_REFCLK PEX_IOVDD_6
2N7002BK-GP
20 CLK_PCIE_VGA# AK13
PEX_REFCLK# 1.97A
84.07002.I31
w
CPU_RXP_C_dGPU_TXP0 C8301 1OPS 2SCD22U10V2KX-1GP dGPU_TXP_CPU_RXP15
2nd = 84.2N702.W31 CPU_RXN_C_dGPU_TXN0 C8302 1OPS dGPU_TXN_CPU_RXN15
AK14
PEX_TX0 1D05V_VGA_S0
3rd = 84.2N702.J31 2SCD22U10V2KX-1GP AJ14
PEX_TX0#
w
1 DY 2 dGPU_RXP_C_CPU_TXP15 AN12
dGPU_RXN_C_CPU_TXN15 PEX_RX0
AM12 AG13
w
R8307 PEX_RX0# PEX_IOVDDQ_1
AG15
0R2J-2-GP CPU_RXP_C_dGPU_TXP1 C8303 1OPS dGPU_TXP_CPU_RXP14 PEX_IOVDDQ_2
2SCD22U10V2KX-1GP AH14 AG16
PEX_TX1 PEX_IOVDDQ_3
.ro
CPU_RXN_C_dGPU_TXN1 C8304 1OPS 2SCD22U10V2KX-1GP dGPU_TXN_CPU_RXN14 AG14 AG18
PEX_TX1# PEX_IOVDDQ_4
AG25
PEX_IOVDDQ_5
1
dGPU_RXP_C_CPU_TXP14 AN14 AH15
dGPU_RXN_C_CPU_TXN14 PEX_RX1 PEX_IOVDDQ_6 OPS DY OPS OPS OPS OPS OPS
AM14 AH18
se
PEX_RX1# PEX_IOVDDQ_7 C8329 C8330 C8318 C8320 C8323 C8336 C8337
AH26
2
PEX_IOVDDQ_8
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC4D7U6D3V3KX-GP
SC1U10V2KX-1GP
SCD1U10V2KX-4GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
CPU_RXP_C_dGPU_TXP2 C8305 1OPS 2SCD22U10V2KX-1GP dGPU_TXP_CPU_RXP13 AK15 AH27
CPU_RXN_C_dGPU_TXN2 C8306 1OPS dGPU_TXN_CPU_RXN13 PEX_TX2 PEX_IOVDDQ_9
2SCD22U10V2KX-1GP AJ15 AJ27
PEX_TX2# PEX_IOVDDQ_10
fix
AK27
dGPU_RXP_C_CPU_TXP13 PEX_IOVDDQ_11
AP14 AL27
dGPU_RXN_C_CPU_TXN13 PEX_RX2 PEX_IOVDDQ_12
AP15 AM28
PEX_RX2# PEX_IOVDDQ_13
AN28
.c
CPU_RXP_C_dGPU_TXP3 C8307 1OPS dGPU_TXP_CPU_RXP12 PEX_IOVDDQ_14
4 dGPU_RXP_C_CPU_TXP[8..15] 2SCD22U10V2KX-1GP AL16
CPU_RXN_C_dGPU_TXN3 C8308 1OPS dGPU_TXN_CPU_RXN12 PEX_TX3
C 2SCD22U10V2KX-1GP AK16 C
PEX_TX3#
om
4 dGPU_RXN_C_CPU_TXN[8..15]
dGPU_RXP_C_CPU_TXP12 AN15
AM15
PEX_RX3#
4 CPU_RXP_C_dGPU_TXP[7..0]
CPU_RXP_C_dGPU_TXP4
CPU_RXN_C_dGPU_TXN4
C8309 1OPS
C8310 1OPS
2SCD22U10V2KX-1GP
2SCD22U10V2KX-1GP
dGPU_TXP_CPU_RXP11
dGPU_TXN_CPU_RXN11
AK17
AJ17
PEX_TX4
PEX_TX4#
GPU
4 CPU_RXN_C_dGPU_TXN[7..0] PEX_RX4
dGPU_RXN_C_CPU_TXN11 AM17
PEX_RX4#
CPU_RXP_C_dGPU_TXP5 C8311 1OPS 2SCD22U10V2KX-1GP dGPU_TXP_CPU_RXP10 AH17
3.3V +/- 5%
2SCD22U10V2KX-1GP AG17 22mA
PEX_TX5#
AH12 3D3V_VGA_S0
dGPU_RXP_C_CPU_TXP10 PEX_PLL_HVDD
AP17
AP18 AG12
PEX_RX5# PEX_SVDD_3V3
CPU_RXP_C_dGPU_TXP6 C8313 1OPS 2SCD22U10V2KX-1GP dGPU_TXP_CPU_RXP9 AK18
2SCD22U10V2KX-1GP AJ18
1
PEX_TX6# C8325 C8324 C8333
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
dGPU_RXP_C_CPU_TXP9 AN18 OPS OPS OPS
AM18
2
PEX_RX6#
CPU_RXP_C_dGPU_TXP7 C8315 1OPS 2SCD22U10V2KX-1GP dGPU_TXP_CPU_RXP8 AL19
2SCD22U10V2KX-1GP AK19
PEX_TX7#
dGPU_RXN_C_CPU_TXN8 AM20
PEX_RX7
PEX_RX7#
X7R, Under GPU.
AK20
PEX_TX8
AJ20
PEX_TX8#
L4 VGA_SENSE 92
VDD_SENSE
AP20
AP21
PEX_RX8
PEX_RX8#
POWER IC
L5 GND_SENSE 92
GND_SENSE
AH20
PEX_TX9
AG20
PEX_TX9#
AN21
PEX_RX9
AM21
PEX_RX9#
B AK21 B
PEX_TX10
AJ21
PEX_TX10#
P8
NC_3V3AUX
AN23
PEX_RX10
AM23
PEX_RX10#
AL22
PEX_TX11
AK22
PEX_TX11#
AP23 R8304
PEX_RX11 100R2J-2-GP
AP24
PEX_RX11#
AJ26 PEXTSTCLK_OUT 1 DY 2
1.05V +/- 3%
PEX_TSTCLK_OUT
AK26 PEXTSTCLK_OUT#
AK23
AJ23
PEX_TX12 PEX_TSTCLK_OUT# 130mA
PEX_TX12#
AN24
PEX_RX12 1D05V_VGA_S0
AM24
PEX_RX12# L8301
AH23 MHC1608S121PBP-GP
PEX_TX13 VCC1R05VIDEO_PEX_PLLVDD
AG23
PEX_TX13# PEX_PLLVDD
AG26 1 OPS 2
AN26
PEX_RX13 68.00335.151
AM26
1
PEX_RX13# C8327 C8326 C8328
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
SC1U10V2KX-1GP
AK24 R8303 OPS OPS OPS
PEX_TX14
AJ24 AK11 TESTMODE 1 OPS 2
2
PEX_TX14# TESTMODE 10KR2J-3-GP
AP26
PEX_RX14
AP27
PEX_RX14#
AL25
PEX_TX15
AK25
PEX_TX15# R8301
AN27 AP29 PEX_TERMP 1 OPS 2
PEX_RX15 PEX_TERMP 2K49R2F-GP
AM27
PEX_RX15#
N13P-GS-A1-GP
71.0N13P.00U
A A
M14 DIS
Wistron Corporation
Title
GPU_PCIE/STRAPPING(1/5)
A2
5 4
http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2 1
5 4 3 2 1
LVDS Interface
D GPU1J 10 OF 17 D
5/17 IFPAB
GPU1K 11 OF 17
ALL PINS NC FOR GF117
6/17 IFPC
AN6
IFPA_TXC# ALL PINS NC FOR GF117
AM6
IFPA_TXC
AJ8
IFPAB_RSET
AF8
IFPC_RSET
AN3 DVI/HDMI DP
IFPA_TXD0#
AP3
IFPA_TXD0
IFPAB_PLLVDD AH8 IFPC_PLLVDD AF7 I2CW_SDA AG2
IFPAB_PLLVDD IFPC_PLLVDD IFPC_AUX_I2CW_SDA#
AM5 I2CW_SCL AG3
IFPA_TXD1# IFPC_AUX_I2CW_SCL
AN5
IFPA_TXD1
IFPA_TXD2#
AK6
GPU TXC
TXC
IFPC_L3#
IFPC_L3
AG4
AG5
AL6
IFPA_TXD2
AH4
GPU IFPC TXD0
TXD0
IFPC_L2#
IFPC_L2
AH3
w
AH6
IFPA_TXD3#
AJ6 TXD1 AJ2
IFPA_TXD3 IFPC_L1#
AJ3
w
TXD1 IFPC_L1
AH9 AJ1
w
IFPB_TXC# TXD2 IFPC_L0#
AJ9 TXD2 AK1
IFPB_TXC IFPC_L0
.ro
IFPAB_IOVDD AG8
IFPA_IOVDD
AP5
IFPB_TXD4# IFPC_IOVDD
AG9 AP6 AF6 P2
IFPB_IOVDD IFPB_TXD4 IFPC_IOVDD GPIO15
se
4
3
AL7 N13P-GS-A1-GP
4
3
IFPB_TXD5# RN8401
IFPB_TXD5
AM7 71.0N13P.00U
fix
RN8402 SRN10KJ-5-GP
OPS SRN10KJ-5-GP OPS
AM8
IFPB_TXD6#
AN8
.c
1
2
IFPB_TXD6
1
2
C C
om
AL8
IFPB_TXD7#
AK8
IFPB_TXD7
N4
GPIO14
IFPAB
N13P-GS-A1-GP
71.0N13P.00U
GPU1M 13 OF 17
8/17 IFPEF
ALL PINS NC FOR GF117
DVI-DL DVI-SL/HDMI DP
I2CY_SDA I2CY_SDA AB4

IFPE_AUX_I2CY_SDA#
I2CY_SCL I2CY_SCL AB3
IFPEF_PLLVDD IFPE_AUX_I2CY_SCL
AB8
IFPEF_PLLVDD
HDMI Interface AD6

IFPEF_RSET
TXC
TXC
TXC
TXC
IFPE_L3#
IFPE_L3
AC5
AC4
GPU1L 12 OF 17 AC3
TXD0 TXD0 IFPE_L2#
7/17 IFPD AC2
TXD0 TXD0 IFPE_L2
AC1
ALL PINS NC FOR GF117 TXD1 TXD1 IFPE_L1#
AD1
IFPE TXD1 TXD1 IFPE_L1
B AN2 AD3 B
IFPD_RSET TXD2 TXD2 IFPE_L0#
DVI/HDMI DP AD2
TXD2 TXD2 IFPE_L0
IFPD_PLLVDD AG7 I2CX_SDA AK2

IFPD_PLLVDD IFPD_AUX_I2CX_SDA#
I2CX_SCL AK3
IFPD_AUX_I2CX_SCL
HPD_E HPD_E R1
GPU TXC
TXC
IFPD_L3#
IFPD_L3
AK5
AK4
GPIO18
TXD0 AL4
IFPD IFPD_L2#
TXD0 AL3
IFPD_L2
TXD1
TXD1
IFPD_L1#
IFPD_L1
AM4
AM3 IFPEF_IOVDD AC7
IFPE_IOVDD
GPU
I2CZ_SDA AF2
IFPF_AUX_I2CZ_SDA#
TXD2 AM2 I2CZ_SCL AF3
IFPD_L0# IFPF_AUX_I2CZ_SCL
TXD2 AM1 AC8
IFPD_L0 IFPF_IOVDD
TXC AF1
IFPF_L3#
TXC AG1
4
3
IFPD_IOVDD IFPF_L3
AG6 M6
IFPD_IOVDD GPIO17 RN8403 TXD3 TXD0 AD5
IFPF_L2#
OPS SRN10KJ-5-GP TXD3 TXD0 AD4
4
3
N13P-GS-A1-GP IFPF_L2
RN8404 71.0N13P.00U TXD4 TXD1 AF5
OPS SRN10KJ-5-GP IFPF TXD4 TXD1
IFPF_L1#
AF4
1
2
IFPF_L1
TXD5 TXD2 AE4
IFPF_L0#
TXD5 TXD2 AE3
1
2
IFPF_L0
HPD_F P3
GPIO19
N13P-GS-A1-GP
A
71.0N13P.00U A
M14 DIS
Wistron Corporation
Title
GPU Memory(2/5)
A2
http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
5 4 3 2 1
5 4 3 2 1
GPU1B 2 OF 17
2/17 FBA DA-05691-001_V05 P7
GPU1C 3 OF 17
Pull Down 10K : N13P-GS
88 FBA_D[0..7] 3/17 FBB
90 FBB_D[0..7]
FBA_D0 L28 E1 R8519 1 2 10KR2J-3-GP
FBA_D1 FBA_D0 FB_CLAMP OPS
M29
FBA_D2 FBA_D1 FBB_D0
L29 G9
FBA_D3 FBA_D2 FBB_D1 FBB_D0
M28 E9
N31 G8
FBA_D5 FBA_D4 FBA_PLL_AVDD FBB_D3 FBB_D2
P29 K27 F9
FBA_D6 FBA_D5 FB_DLL_AVDD FBB_D4 FBB_D3
R29 F11
D
88 FBA_D[8..15] P28
FBA_D7 Layout note:FBA_PLL_AVDD=16mil G11
FBB_D5 D
FBA_D8 J28 FBB_D6 F12
FBA_D9 FBA_D8 C8509 FBB_D7 FBB_D6
H29
FBA_D9 X7R 90 FBB_D[8..15] G12
FBB_D7
1
FBA_D10 J29 DA-05691-001_V05 P7 FBB_D8 G6
SCD1U10V2KX-5GP
H28
FBA_D11 OPS Colay: N13P - GS connected to power F5
FBB_D9
FBA_D12 G29 FBB_D10 E6
2
E31 F6
E32
FBA_D14 Place close to Ball F4
FBB_D12
88 FBA_D[16..23] FBA_D15 F30 FBB_D13 G4
C34 E2
D32 90 FBB_D[16..23] F3
B33 C2
C33 D4
F33 D3
F32 C1
H33 B3
88 FBA_D[24..31] H32 C4
P34 B5
P32 90 FBB_D[24..31] C5
P31 A11
P33 C11
L31 D11
L34 B11
L32 D8
89 FBA_D[32..39] L33 A8
AG28 C8
FBA_D33 FBA_D32 FBA_CMD0 FBB_D31 FBB_D30 FBA_CMD19 FBB_CMD19
AF29 U30 91 FBB_D[32..39] B8
FBA_D34 FBA_D33 FBA_CMD0 FBA_CMD1 FBA_CMD0 88 FBB_D32 FBB_D31
AG29 T31 1 F24
FBA_D35 FBA_D34 FBA_CMD1 FBA_CMD2 TP8505 FBB_D33 FBB_D32
AF28 U29 G23 D13
FBA_D35 FBA_CMD2 FBA_CMD2 88 FBB_D33 FBB_CMD0 FBB_CMD0 90
2
FBA_D36 AD30 R34 FBA_CMD3 FBB_D34 E24 E14 FBB_CMD1 1
FBA_D37 FBA_D36 FBA_CMD3 FBA_CMD3 88 FBB_D35 FBB_D34 FBB_CMD1 TP8515 R8517 R8518
AD29 R33 G24 F14
FBA_D38 FBA_D37
GPU FBA_CMD4 FBA_CMD4 88,89 FBB_D36 FBB_D35
GPU FBB_CMD2 FBB_CMD2 90
w
AC29
FBA_D38 FBA_CMD5
U32
FBA_CMD5 88,89
D21
FBB_D36 FBB_CMD3
A12
FBB_CMD3 90 OPS 10KR2J-3-GP OPS 10KR2J-3-GP
89 FBA_D[40..47] FBA_D39 AD28 U33 FBB_D37 E21 B12
FBA_D40 FBA_D39 FBA_CMD6 FBA_CMD6 88,89 FBB_D38 FBB_D37 FBB_CMD4 FBB_CMD4 90,91
AJ29 U28 G21 C14
1
AK29 V28 F21 B14
w
FBA_D41 FBA_CMD8 FBA_CMD8 88,89 91 FBB_D[40..47] FBB_D39 FBB_CMD6 FBB_CMD6 90,91
FBA_D42 AJ30 V29 FBB_D40 G27 G15
AK28 V30 D27 F15
AM29 U34 G26 E15
w
FBA_D45 FBA_D44 FBA_CMD11 FBA_CMD11 88,89 FBB_D43 FBB_D42 FBB_CMD9 FBB_CMD9 90,91 FBB_CMD2
AM31 U31 E27 D15
FBA_D46 FBA_D45 FBA_CMD12 FBA_CMD12 88,89 FBB_D44 FBB_D43 FBB_CMD10 FBB_CMD10 90,91 FBB_CMD3
AN29 V34 E29 A14
FBA_D47 FBA_D46 FBA_CMD13 FBA_CMD13 88,89 FBB_D45 FBB_D44 FBB_CMD11 FBB_CMD11 90,91 FBA_CMD2 FBB_CMD5
89 FBA_D[48..55] AM30 V33 F29 D14
FBA_D47 FBA_CMD14 FBA_CMD14 88,89 FBB_D45 FBB_CMD12 FBB_CMD12 90,91
.ro
FBA_D48 AN31 Y32 FBB_D46 E30 A15 FBA_CMD3 FBB_CMD18
FBA_D49 FBA_D48 FBA_CMD15 FBA_CMD15 88,89 FBB_D47 FBB_D46 FBB_CMD13 FBB_CMD13 90,91 FBA_CMD5
AN32 AA31 91 FBB_D[48..55] D30 B15
FBA_D50 FBA_D49 FBA_CMD16 FBA_CMD17 FBA_CMD16 89 FBB_D48 FBB_D47 FBB_CMD14 FBB_CMD14 90,91 FBA_CMD18
AP30 AA29 1 A32 C17
FBA_D51 FBA_D50 FBA_CMD17 TP8508 FBB_D49 FBB_D48 FBB_CMD15 FBB_CMD15 90,91
AP32 AA28 C31 D18
FBA_D52 FBA_D51 FBA_CMD18 FBA_CMD18 89 FBB_D50 FBB_D49 FBB_CMD16 FBB_CMD17 FBB_CMD16 91
AM33 AC34 C32 E18 1
FBA_D53 FBA_D52 FBA_CMD19 FBA_CMD19 89 FBB_D51 FBB_D50 FBB_CMD17 TP8513
se
AL31 AC33 B32 F18
FBA_D54 FBA_D53 FBA_CMD20 FBA_CMD20 88,89 FBB_D52 FBB_D51 FBB_CMD18 FBB_CMD18 91
AK33 AA32 D29 A20
FBA_D55 FBA_D54 FBA_CMD21 FBA_CMD21 88,89 FBB_D53 FBB_D52 FBB_CMD19 FBB_CMD19 91
89 FBA_D[56..63] AK32 AA33 A29 B20
2
FBA_D56 AD34 Y28 FBB_D54 C29 C18
FBA_D57 FBA_D56 FBA_CMD23 FBA_CMD23 88,89 FBB_D55 FBB_D54 FBB_CMD21 FBB_CMD21 90,91 R8507 R8508 R8511 R8512 R8513 R8514 R8515 R8516
AD32 Y29 91 FBB_D[56..63] B29 B18
fix
FBA_D58 AC30 W 31 FBB_D56 B21 G18 OPS OPS OPS OPS OPS OPS OPS OPS
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
AD33 Y30 C23 G17
AF31 AA34 A21 F17
1
AG34 Y31 C21 D16
AG32 Y34 B24 A18
.c
AG33 Y33 C24 D17
FBA_D63 FBA_CMD30 FBA_CMD31 FBA_CMD30 88,89 FBB_D62 FBB_D61 FBB_CMD28 FBB_CMD28 90,91
V31 1 B26 A17
FBA_CMD31 TP8509 FBB_D63 FBB_D62 FBB_CMD29 FBB_CMD29 90,91
C26 B17
FBB_D63 FBB_CMD30 FBB_CMD30 90,91
om
C FBB_CMD31 C
P30 R32 E17 1
88 FBA_DQM0 FBA_DQM0 FBA_CMD_RFU0 FBB_CMD31 TP8512
F31 AC32
88 FBA_DQM1 FBA_DQM1 FBA_CMD_RFU1
F34 E11 C12
88 FBA_DQM2 FBA_DQM2 90 FBB_DQM0 FBB_DQM0 FBB_CMD_RFU0
M32 E3 C20
88 FBA_DQM3 FBA_DQM3 90 FBB_DQM1 FBB_DQM1 FBB_CMD_RFU1
AD31 1D5V_VGA_S0 A3
89 FBA_DQM4 FBA_DQM4 90 FBB_DQM2 FBB_DQM2
AL29 C9 1D5V_VGA_S0
89 FBA_DQM5 FBA_DQM5 90 FBB_DQM3 FBB_DQM3
AM32 F23
89 FBA_DQM6 FBA_DQM6 R8503 1 91 FBB_DQM4 FBB_DQM4
AF34 R28 OPS 2 60D4R2F-GP F27
89 FBA_DQM7 FBA_DQM7 FBA_DEBUG0 R8506 1 91 FBB_DQM5 FBB_DQM5
AC28 OPS 2 10KR2J-3-GP C30
FBA_DEBUG1 91 FBB_DQM6 FBB_DQM6 R8509 1
A24 G14 OPS 2 60D4R2F-GP
91 FBB_DQM7 FBB_DQM7 FBB_DEBUG0 R8510 1
M31 G20 OPS 2 10KR2J-3-GP
88 FBA_DQS_WP0 FBA_DQS_W P0 FBB_DEBUG1
G31
88 FBA_DQS_WP1 FBA_DQS_W P1
E33 R30 D10
88 FBA_DQS_WP2 FBA_DQS_W P2 FBA_CLK0 FBA_CLK0 88 90 FBB_DQS_WP0 FBB_DQS_W P0
M33 R31 D5
88 FBA_DQS_WP3 FBA_DQS_W P3 FBA_CLK0# FBA_CLK0# 88 90 FBB_DQS_WP1 FBB_DQS_W P1
AE31 AB31 C3 D12
89 FBA_DQS_WP4 FBA_DQS_W P4 FBA_CLK1 FBA_CLK1 89 90 FBB_DQS_WP2 FBB_DQS_W P2 FBB_CLK0 FBB_CLK0 90
AK30 AC31 B9 E12
89 FBA_DQS_WP5 FBA_DQS_W P5 FBA_CLK1# FBA_CLK1# 89 90 FBB_DQS_WP3 FBB_DQS_W P3 FBB_CLK0# FBB_CLK0# 90
AN33 E23 E20
89 FBA_DQS_WP6 FBA_DQS_W P6 91 FBB_DQS_WP4 FBB_DQS_W P4 FBB_CLK1 FBB_CLK1 91
AF33 E28 F20
89 FBA_DQS_WP7 FBA_DQS_W P7 91 FBB_DQS_WP5 FBB_DQS_W P5 FBB_CLK1# FBB_CLK1# 91
B30
91 FBB_DQS_WP6 FBB_DQS_W P6
A23
91 FBB_DQS_WP7 FBB_DQS_W P7
M30 K31
88 FBA_DQS_RN0 FBA_DQS_RN0 FBA_WCK1
H30 L30
88 FBA_DQS_RN1 FBA_DQS_RN1 FBA_WCK1#
E34 H34 D9 F8
88 FBA_DQS_RN2 FBA_DQS_RN2 FBA_WCK23 90 FBB_DQS_RN0 FBB_DQS_RN0 FBB_WCK1
M34 J34 E4 E8
88 FBA_DQS_RN3 FBA_DQS_RN3 FBA_WCK23# 90 FBB_DQS_RN1 FBB_DQS_RN1 FBB_WCK1#
AF30 AG30 B2 A5
AK31 AG31 A9 A6
AM34 AJ34 D22 D24
AF32 AK34 D28 D25
A30 B27
91 FBB_DQS_RN6 FBB_DQS_RN6 FBB_WCK67
J30 B23 C27
FBA_WCKB1 91 FBB_DQS_RN7 FBB_DQS_RN7 FBB_WCK67#
J31
THE FBA_WCKBxx
PINS ARE USED
FBA_WCKB1#
J32 DA-05691-001_V05 P7 X02 0730 change source D6
FBA_WCKB23 FBB_WCKB1
ONLY ON GK107 J33 NC : N13P-GL THE FBB_WCKBxx D7
FBA_WCKB23# FBB_WCKB1#
THEY ARE NC AH31 PINS ARE USED C6
FBA_WCKB45 FBB_WCKB23
FOR GF108 AJ31 1D05V_VGA_S0 ONLY ON GK107 B6
FBA_WCKB45# FBB_WCKB23#
AND FOR GF117 AJ32 THEY ARE NC F26
FBA_WCKB67 L8501 FBB_WCKB45
AJ33 FOR GF108 E26
FBA_WCKB67# MHC1608S300QBP-GP FBB_WCKB45#
AND FOR GF117 A26
TP8503 FB_VREF FBA_PLL_AVDD FBB_WCKB67
1 H26
FB_VREF FBA_PLL_AVDD
U27 1 OPS 2
FBB_WCKB67#
A27
68.00335.051 30ohm@100MHz ESR=0.2 H17 FBA_PLL_AVDD 1.5V +/- 5%

FBB_PLL_AVDD
N13P-GS-A1-GP
4.88A
1
71.0N13P.00U C8520 C8505 C8506 GPU FBVDDQ Decoupling

OPS 1D5V_VGA_S0
OPS OPS N13P-GS-A1-GP
SC1U16V3KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
71.0N13P.00U C8510 X7R DA-05691-001_V05 P14 PLACE CLOSE TO GPU BALLS

2
1
4 OF 17 GPU1D
SCD1U10V2KX-5GP
Colay: N13P - GS connected to power
OPS 14/17 FBVDDQ
2
AA27
FBVDDQ_1
Place under GPU near FBVDDQ_2
AA30
2
AB27 C8501 C8502 C8528 C8507 C8508 C8527 C8525 C8513 C8514 C8519 C8523 C8531 C8532
FBVDDQ_3
AB33 OPS OPS OPS OPS DY DY DY DY OPS DY DY DY DY
SC1U16V3KX-5GP
SC1U16V3KX-5GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
FBVDDQ_4
AC27
1
FBVDDQ_5
Place under GPU near FBVDDQ_6
AD27
AE27
FBVDDQ_7
AF27
FBVDDQ_8
AG27
FBVDDQ_9
B13
B FBVDDQ_10 B
B16
FBVDDQ_11
B19
FBVDDQ_12
E13 1D5V_VGA_S0
FBVDDQ_13
E16
FBVDDQ_14
FBVDDQ_15
E19 PLACE CLOSE TO GPU BALLS
H10
FBVDDQ_16
H11
FBVDDQ_17
H12
FBVDDQ_18
H13
FBVDDQ_19
H14
FBVDDQ_20
2
H15 C8503 C8504 C8529 C8511 C8512 C8530 C8526 C8515 C8516 C8521 C8524 C8533 C8534
FBVDDQ_21
H16 OPS OPS DY OPS OPS DY DY DY OPS DY DY DY DY
SC1U16V3KX-5GP
SC1U16V3KX-5GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC1U6D3V2KX-GP
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
GPU
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
FBVDDQ_22
H18
1
FBVDDQ_23
H19
FBVDDQ_24
H20
FBVDDQ_25
H21
FBVDDQ_26
H22
FBVDDQ_27
H23
FBVDDQ_28
H24
FBVDDQ_29
H8
FBVDDQ_30
H9
FBVDDQ_31
L27
FBVDDQ_32
M27
FBVDDQ_33
N27
FBVDDQ_34
P27
FBVDDQ_35
R27
FBVDDQ_36
T27
FBVDDQ_37
T30
FBVDDQ_38
T33
FBVDDQ_39
V27
FBVDDQ_40
W 27
FBVDDQ_41
W 30
FBVDDQ_42
W 33
FBVDDQ_43
Y27
FBVDDQ_44
TP8501 1 FBVDDQ_SENSE F1
FB_VDDQ_SENSE
1D5V_VGA_S0
TP8502 1 FB_GND_SENSE F2
FB_GND_SENSE
R8501
2 OPS 1 FB_CAL_PD_VDDQ J27
FB_CAL_PD_VDDQ
40D2R2F-GP
FB_CAL_PU_GND H27
FB_CAL_PU_GND
FB_CAL_TERM_GND H25
FB_CAL_TERM_GND
N13P-GS-A1-GP
71.0N13P.00U
2
R8504 R8502
OPS OPS
51R2J-2-GP
42D2R2F-GP
A A
1
M14 DIS
Wistron Corporation
Title
GPU_DP/LVDS/CRT/GPIO(3/5)
http://vinafix.vn
03-05-1512:40:57 PM
A1
03-05-151:22:21 PM Date: Wednesday, September 05, 2012 Sheet 85 of 105
5 4 3 2 1
5 4 3 2 1
1D05V_VGA_S0
3D3V_VGA_S0
GPU1N 14 OF 17 L8601
4/17 DACA MHC1608S181NBP-GP 52mA NV request to need to be keeped
GF108/GKx GF117 GF117 GF108/GKx
1 OPS 2
DACA_VDD 1 RN8603 GPU1O 15 OF 17

AG10
DACA_VDD NC NC I2CA_SCL
R4 4 OPS 68.00335.081
1
NC R5 3 2 SRN2K2J-1-GP C8606 11/17 XTAL_PLL
I2CA_SDA C8605 OPS
AP9
DACA_VREF TSEN_VREF OPS SC2D2U6D3V2MX-GP
SCD1U10V2KX-5GP
2
1
AP8 NC NC AM9 GPU_PLL_VDD AD8

DACA_RSET DACA_HSYNC L8602 SP_PLLVDD PLLVDD
AN9 AE8
OPS R8612
NC DACA_VSYNC MCB1608S181FBP-GP 108mA SP_PLLVDD
10KR2J-3-GP
AK9
1 OPS 2 AD7
VID_PLLVDD NC
GPU N13P-GS1
GPU NC
2
D DACA_RED D
68.00909.261 GF108/GKx GF117
NC AL10
DACA_GREEN
1
AL9 C8601 C8603 C8604 C8602
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
NC DACA_BLUE
OPS OPS OPS OPS VIDEO_CLK_XTAL_SS H1 J4 N12P_XTAL_OUTBUFF
XTAL_SSIN XTAL_OUTBUFF
2
N13P-GS-A1-GP
71.0N13P.00U H3
XTAL_IN XTAL_OUT
H2
1
N13P-GS-A1-GP
1
71.0N13P.00U 20PF 5% 50V +/-0.25PF 0402 R8608
R8607 R8609
OPS10KR2J-3-GP
OPS 10KR2J-3-GP 1MR2J-1-GP
2
27MHZ_IN 1 DY 2 27MHZ_OUT
2
3D3V_VGA_S0
X8601
1
1 4 R8610
3D3V_VGA_S0 1K5R2F-2-GP
4
3
R8630
OPS
2
1 OPS 2 RN8601 2 3 27MHZ_OUT_R
0R2J-2-GP
OPS SRN4K7J-8-GP OPS
1
XTAL-27MHZ-85-GP
1
2
C8607 82.30034.641 C8608
SC18P50V2JN-1-GP 2ND = 82.30034.651 SC18P50V2JN-1-GP
2
Q8601 3RD = 82.30034.681
3 4 SMBD_THERM_NV OPS OPS
20,27,28 SML1_DATA
w
2 5
OPS
1 6
w
2N7002KDW-GP
84.2N702.A3F
w
2nd = 84.2N702.E3F
3RD = 84.2N702.F3F
SMBC_THERM_NV
.ro
20,27,28 SML1_CLK
se
GPU1Q 17 OF 17 3D3V_VGA_S0
10/19 MISC1
fix
T4 SMBC_THERM_NV
I2CS_SCL SMBD_THERM_NV
T3
I2CS_SDA
R2 4 OPS 1 RN8604
I2CC_SCL
R3 3 2 SRN2K2J-1-GP
.c
I2CC_SDA
R7 4 OPS 1 RN8605
P2800_VGA_DXN I2CB_SCL
1 K4 R6 3 2 SRN2K2J-1-GP
THERMDN I2CB_SDA
om
C TP8603 C
1 P2800_VGA_DXP K3
TP8604 THERMDP
N12P_JTAG_TCK AM10 3D3V_VGA_S0

N12P_JTAG_TMS JTAG_TCK
1 AP11
TP8602 N12P_JTAG_TDI JTAG_TMS
1 AM11
TP8606 N12P_JTAG_TDO JTAG_TDI
1 AP12
TP8601 N12P_JTAG_TRST JTAG_TDO
AN11 P6 NV_VID4 92
JTAG_TRST# GPIO0
1
M3 NV_VID3 92
GPIO1 R8617
L6
GPU GPIO2
4
3
P5 10KR2J-3-GP OPS
G
GPIO3 3D3V_VGA_S0
RN8602 P7
GPIO4
SRN10KJ-5-GP L7 NV_VID1 92
2
GPIO5
OPS GPIO6
M7 NV_VID2 92
1
N8 GPIO8_OVERT# S D PURE_HW_SHUTDOWN# 27,28,36

GPIO7 3D3V_VGA_S0
M1 GPIO8_OVERT# R8611 OPS
1
2
GPIO8 GPIO9_ALERT R8635 1

M2 OPS 210KR2J-3-GP OPS 10KR2J-3-GP Q8604
GPIO9 2N7002BK-GP
L1
GPIO10
M5 NV_VID0 92 D8601 84.07002.I31
2
GPIO11 PWR_LEVEL
GPIO12
N3 A DY K AC_PRESENT 19,27 2nd = 84.2N702.W31
GPIO13
M4 NV_VID5 92 3rd = 84.2N702.J31
R8 1SS400GPT-GP
GPIO16
GPIO20
P4 83.00400.C1F
GPIO21
P1 DA-05691-001_V05 P15 2ND = 83.27101.01F
GPIO20/21 NC : for ALL
3RD = 83.01426.01F
D8602
A OPS K OVER_CURRENT_P8# 27
1SS400GPT-GP
83.00400.C1F
N13P-GS-A1-GP
2ND = 83.27101.01F
71.0N13P.00U
3RD = 83.01426.01F
N13M-GSR
3D3V_VGA_S0
GPU1P 16 OF 17
12/17 MISC2
2
R8632
DY 10KR2J-3-GP
H6 ROM_CS#
1
ROM_CS#
H5 ROM_SI_D3
ROM_SI ROM_SO_C4
H7
STRAP0 ROM_SO ROM_SLK_D4
J2 H4
STRAP1
STRAP2
STRAP3
J7
J6
STRAP0
STRAP1
STRAP2
GPU ROM_SCLK
J5
STRAP4 STRAP3
J3
B STRAP4 B
R8634
BUFRST#
L2 2 OPS 1
10KR2J-3-GP
STRAP_REF0_GND_N9 J1 L3
MULTI_STRAP_REF0_GND CEC
DA-05691-001_V05 P6
1
N13P_MULTI_STRAP
R8613
NC : N13P-GS
40K2R2F-GP
N13P-GS-A1-GP N13M-GSR 3D3V_VGA_S0
2
71.0N13P.00U
1
R8628 R8618 R8624 R8626

10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP
STRAP0
N13M_STRAP1_U N13M_128M
2
STRAP1 N13M_STRAP0_U N13M_Other

STRAP2
STRAP3
STRAP4
1
R8633 R8636 R8623 R8637 R8638

10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP
N13M_STRAP1_D N13M_256M N13M_STRAP4
2
N13M_STRAP0_D N13M_Samsung
N13M-GS / N13P-GS 3D3V_VGA_S0
R8620
3D3V_VGA_S0
R8619 4K99R2F-L-GP
N13P-GS1 3D3V_VGA_S0
1
10KR2F-2-GP
1
N13P_ROM_SCLK
1
N13P_ROM_SO
1
R8622
2
R8629 45K3R2F-L-GP
2
4K99R2F-L-GP N13P_STRAP0
ROM_SI_D3 DY
2
A ROM_SO_C4 STRAP3 STRAP0 A

2
ROM_SLK_D4 STRAP4 STRAP1

STRAP2
1
R8640 R8639 R8621 R8614 R8615

10KR2J-3-GP 30KR2F-GP 24K9R2F-L-GP 10KR2J-3-GP 10KR2J-3-GP R8631 R8616 R8625 R8627
N13P_Hynix N13M_ROM_SO 4K99R2F-L-GP 45K3R2F-L-GP 4K99R2F-L-GP 15KR2F-GP
N13P_STRAP4 N13P_STRAP3 N13P_STRAP1 N13P_STRAP2
2
N13M_ROM_SI N13P_Samsung N13M_ROM_CLK

2
M14 DIS
4/9 update GPU strappin
Wistron Corporation
Title
GPU_POWER(4/5)
http://vinafix.vn
03-05-1512:40:57 PM
A1
03-05-151:22:21 PM Date: Wednesday, September 05, 2012 Sheet 86 of 105
5 4 3 2 1
5 4 3 2 1
GPU1I 9 OF 17 GPU1H 8 OF 17
15/17 GND_1/2 16/17 GND_2/2
A2 AM25
N13P-GS : 27A VGA_CORE AA17
GND_1
GND_5
GND_71
GND_72
AN1 N19
GND_141 GND_170
T28
AA18 AN10 N2 T32
GND_6 GND_73 GND_142 GND_171
AA20 GND_7 GND_74 AN13 N21 GND_143 GND_172 T5
AA22 GND_8 GND_75 AN16 N23 GND_144 GND_173 T7
GPU1F 6 OF 17 AB12 AN19 N28 U12
Under GPU 13/17 NVVDD AB14
GND_9 GND_76
AN22 N30
GND_145 GND_174
U14
GND_10 GND_77 GND_146 GND_175
AB16 GND_11 GND_78 AN25 N32 GND_147 GND_176 U16
AA12 VDD_1 AB19 GND_12 GND_79 AN30 N33 GND_148 GND_177 U19
C8714 C8712 C8713 C8711 C8702 C8701 AA19 A33 AN7 P13 V12
VDD_4 GND_2 GND_82 GND_151 GND_180
1
AA21 VDD_5 AB23 GND_15 GND_83 AP2 P15 GND_152 GND_181 V14
SC10U6D3V3MX-GP
OPS
SC4D7U6D3V3KX-GP OPS OPS OPS OPS OPS
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
AA23 VDD_6 AB28 GND_16 GND_84 AP33 P17 GND_153 GND_182 V16
SC10U6D3V3MX-GP
D 2 AB13 AB30 B1 P18 V19 D
2
AB15 VDD_8 AB32 GND_18 GND_86 B10 P20 GND_155 GND_184 V21
AB17 VDD_9 AB5 GND_19 GND_87 B22 P22 GND_156 GND_185 V23
AB18 VDD_10 AB7 GND_20 GND_88 B25 R12 GND_157 GND_186 W13
AB20 VDD_11 AC13 GND_21 GND_89 B28 R14 GND_158 GND_187 W15
AB22 VDD_12 AC15 GND_22 GND_90 B31 R16 GND_159 GND_188 W17
AC12 VDD_13 AC17 GND_23 GND_91 B34 R19 GND_160 GND_189 W18
AC14 VDD_14 AC18 GND_24 GND_92 B4 R21 GND_161 GND_190 W20
AC16 VDD_15 AA13 GND_3 GND_93 B7 R23 GND_162 GND_191 W22
AC19 VDD_16 AC20 GND_25 GND_94 C10 T13 GND_163 GND_192 W28
AC21 VDD_17 AC22 GND_26 GND_95 C13 T15 GND_164 GND_193 Y12
AC23 VDD_18 AE2 GND_27 GND_96 C19 T17 GND_165 GND_194 Y14
M12 VDD_19 AE28 GND_28 GND_97 C22 T18 GND_166 GND_195 Y16
C8731 C8728 C8729 C8730 C8727 C8726 C8725 M14 AE30 C25 T2 Y19
2
1
M16 AE32 C28 T20 Y21
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
OPS OPS OPS OPS OPS OPS OPS

SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
M19 AE33 C7 T22 Y23
M21 AE5 D2
1
2
VDD_23 GND_32 GND_101
M23 AE7 D31
N13 AH10 D33
N15
VDD_25
AA15
GND_34 GND_103
E10
GPU
w
N17 AH13 E22
N18 AH16 E25
w
N20 AH19 E5 AG11 AH11
VDD_29 GND_37 GND_107 GND_F GND_H
N22 AH2 E7
w
P12 AH22 F28
P14 AH24 F7
GPU
.ro
P16 AH28 G10
P19 AH29 G13
P21 AH30 G16
VDD_35 GND_43
GPU GND_113
se
C8722 C8721 C8724 C8723 C8720 C8719 C8718 C8717 P23 AH32 G19
1
R13 AH33 G2 C16

VDD_37 GND_45 GND_115 GND_OPT_1
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
OPS OPS OPS OPS OPS OPS OPS OPS R15

VDD_38
AH5
GND_46 GND_116
G22
GND_OPT_2
W32
fix
R17 AH7 G25
2

R18 AJ7 G28 Optional CMD GNDs (2)
R20 AK10 G3 NC for 4-Lyr cards
.c
R22 AK7 G30
VDD_42 GND_50 GND_120 N13P-GS-A1-GP
T12 AL12 G32
om
C T14
VDD_44
AL14
GND_52 GND_122
G33 71.0N13P.00U C
T16 AL15 G5
T19 AL17 G7
T21 AL18 K2
T23 AL2 K28
U13 AL20 K30
U15 AL21 K32
U17 AL23 K33
U18 AL24 K5
NEAR TO GPU U20
VDD_52
AL26
GND_60 GND_130
K7
U22 AL28 M13
V13 AL30 M15
V15 AL32 M17
V17 AL33 M18
V18 AL5 M20
C8707 C8710 C8715 VDD_58 GND_66 GND_136
V20 AM13 M22
2
R8701 V22 AM16 N12

SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
OPS OPS OPS W12

VDD_61
AM19
GND_69 GND_139
N14
0R3J-0-U-GP
UMA W14 AM22 N16

1

W16
VDD_63
W19
2
VDD_64
W21
VDD_65 N13P-GS-A1-GP
W23
VDD_66
Y13
VDD_67 71.0N13P.00U
Y15
VDD_68
Y17
VDD_69
Y18
VDD_70
Y20
VDD_71 GPU1E 5 OF 17
Y22
VDD_72
9/17 XVDD
N13P-GS-A1-GP CONFIGURABLE
71.0N13P.00U POWER
CHANNELS
U1
XVDD_1
U2
XVDD_2
U3
XVDD_3
B U4 B
XVDD_4
U5
XVDD_5
XVDD_6
XVDD_7
U6
U7
XVDD_1~38
U8
XVDD_8
NC : N13P-GL
V1
XVDD_9
V2
XVDD_10
V3
XVDD_11
3.3V +/- 5% V4
GPU1G 7 OF 17
DA-05691-001_V05 P20
3V3MISC : N13P-GS 85mA 3D3V_VGA_S0
GPU XVDD_12
XVDD_13
XVDD_14
V5
V6
V7
XVDD_15
17/17 NC/VDD33 V8
XVDD_16
AC6 J8
NC#AC6 VDD33_1
AJ28 K8 W2
NC#AJ28 VDD33_2 XVDD_17
AJ4 L8 W3
AJ5 M8 W4
AL11
NC#AL11 X7R X7R XVDD_20
W5
1
C15 C8709 C8734 C8732 C8733 W7

NC#C15 XVDD_21
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
D19 OPS OPS OPS OPS W8

D20
NC#D19
GPU XVDD_22
2
NC#D20
D23
NC#D23
D26
NC#D26
H31
NC#H31
T8 Y1
NC#T8 XVDD_23
V32 Y2
NC#V32 XVDD_24
Y3
XVDD_25
Y4
XVDD_26
0.1U Under GPU Y5
N13P-GS-A1-GP XVDD_27
Y6
XVDD_28
71.0N13P.00U XVDD_29
Y7
4.7U NEAR TO GPU Y8
XVDD_30
A AA1 A
1U NEAR TO GPU XVDD_31
AA2
XVDD_32
XVDD_33 AA3
XVDD_34 AA4 M14 DIS
XVDD_35 AA5
XVDD_36 AA6
AA7
XVDD_37
XVDD_38 AA8 Wistron Corporation
N13P-GS-A1-GP Taipei Hsien 221, Taiwan, R.O.C.
71.0N13P.00U
Title
GPU_DPPWR/GND(5/5)
http://vinafix.vn
03-05-1512:40:57 PM
Custom
5 4
03-05-151:22:21 PM 3 2
Date: Wednesday, September 05, 2012 Sheet
1
87 of 105
5 4 3 2 1
Frame Buffer Patition A-Lower Half
D D
1D5V_VGA_S0 1D5V_VGA_S0
VRAM1 VRAM2
FBA_D[24..31] 85 FBA_D[16..23] 85
1
1
C8816 C8821 C8815 C8814 K8 E3 FBA_D28 C8808 C8809 C8807 C8806 K8 E3 FBA_D17
VDD DQL0 FBA_D29 VDD DQL0 FBA_D21
OPS OPS OPS OPS K2 VDD DQL1 F7 OPS OPS OPS OPS K2 VDD DQL1 F7
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
N1 F2 FBA_D31 N1 F2 FBA_D19
2
2
R9 VDD DQL3 F8 R9 VDD DQL3 F8
B2 H3 FBA_D27 B2 H3 FBA_D18
VDD DQL4 VDD DQL4
w
D9 H8 FBA_D24 D9 H8 FBA_D22
G7 VDD DQL6 G2 G7 VDD DQL6 G2
w
R1 H7 FBA_D26 R1 H7 FBA_D23
VDD DQL7 VDD DQL7
N9 N9
w
VDD FBA_D[8..15] 85 VDD FBA_D[0..7] 85
D7 FBA_D14 D7 FBA_D5
DQU0 DQU0
.ro
A8 C3 FBA_D10 A8 C3 FBA_D1
VDDQ DQU1 FBA_D12 VDDQ DQU1 FBA_D6
A1 VDDQ DQU2 C8 A1 VDDQ DQU2 C8
1
1
C8834 C8833 C8830 C8820 C1 C2 FBA_D8 C8832 C8811 C8829 C8827 C1 C2 FBA_D2
se
OPS OPS OPS OPS C9 VDDQ DQU4 A7 OPS OPS OPS OPS C9 VDDQ DQU4 A7
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
D2 A2 FBA_D11 D2 A2 FBA_D3
2
2
VDDQ DQU5 VDDQ DQU5
fix
E9 B8 FBA_D15 E9 B8 FBA_D7
F1 VDDQ DQU7 A3 F1 VDDQ DQU7 A3
.c
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 FBA_DQS_W P1 85 H2 VDDQ DQSU C7 FBA_DQS_W P0 85
om
C B7 B7 C
DQSU# FBA_DQS_RN1 85 DQSU# FBA_DQS_RN0 85
VRAM1_VREF H1 VRAM1_VREF H1
VRAM2_VREF VREFDQ VRAM2_VREF M8 VREFDQ
M8 VREFCA DQSL F3 FBA_DQS_W P3 85 VREFCA DQSL F3 FBA_DQS_W P2 85
1 OPS 2 VRAM_ZQ2 L8 G3 FBA_DQS_RN3 85 1 OPS 2 VRAM_ZQ1 L8 G3 FBA_DQS_RN2 85
R8802 243R2F-2-GP ZQ DQSL# R8801 243R2F-2-GP ZQ DQSL#
ODT K1 FBA_CMD2 85 ODT K1 FBA_CMD2 85

85,89 FBA_CMD9 N3 A0 85,89 FBA_CMD9 N3 A0
85,89 FBA_CMD11 P7 A1 85,89 FBA_CMD11 P7 A1
85,89 FBA_CMD8 P3 A2 CS# L2 FBA_CMD0 85 85,89 FBA_CMD8 P3 A2 CS# L2 FBA_CMD0 85
85,89 FBA_CMD25 N2 A3 RESET# T2 FBA_CMD5 85,89 85,89 FBA_CMD25 N2 A3 RESET# T2 FBA_CMD5 85,89
85,89 FBA_CMD22 R8 A6 NC#M7 M7 FBA_CMD14 85,89 85,89 FBA_CMD22 R8 A6 NC#M7 M7 FBA_CMD14 85,89
85,89 FBA_CMD7 R2 A7 NC#L9 L9 85,89 FBA_CMD7 R2 A7 NC#L9 L9
85,89 FBA_CMD21 T8 A8 NC#L1 L1 85,89 FBA_CMD21 T8 A8 NC#L1 L1
85,89 FBA_CMD6 R3 A9 NC#J9 J9 85,89 FBA_CMD6 R3 A9 NC#J9 J9
85,89 FBA_CMD29 L7 A10/AP NC#J1 J1 85,89 FBA_CMD29 L7 A10/AP NC#J1 J1
85,89 FBA_CMD23 R7 A11 85,89 FBA_CMD23 R7 A11
85,89 FBA_CMD28 N7 A12/BC# 85,89 FBA_CMD28 N7 A12/BC#
85,89 FBA_CMD20 T3 A13 VSS J8 85,89 FBA_CMD20 T3 A13 VSS J8
85,89 FBA_CMD4 T7 A14 VSS M1 85,89 FBA_CMD4 T7 A14 VSS M1
VSS M9 VSS M9
VSS J2 VSS J2
85,89 FBA_CMD12 M2 BA0 VSS P9 85,89 FBA_CMD12 M2 BA0 VSS P9
85,89 FBA_CMD27 N8 BA1 VSS G8 85,89 FBA_CMD27 N8 BA1 VSS G8
85,89 FBA_CMD26 M3 BA2 VSS B3 85,89 FBA_CMD26 M3 BA2 VSS B3
VSS T1 VSS T1
VSS A9 VSS A9
85 FBA_CLK0 J7 CK VSS T9 85 FBA_CLK0 J7 CK VSS T9
B B
85 FBA_CLK0# K7 CK# VSS E1 85 FBA_CLK0# K7 CK# VSS E1
VSS P1 VSS P1
85 FBA_CMD3 K9 CKE 85 FBA_CMD3 K9 CKE
VSSQ G1 VSSQ G1
VSSQ F9 VSSQ F9
85 FBA_DQM1 D3 DMU VSSQ E8 85 FBA_DQM0 D3 DMU VSSQ E8
85 FBA_DQM3 E7 DML VSSQ E2 85 FBA_DQM2 E7 DML VSSQ E2
VSSQ D8 VSSQ D8
VSSQ D1 VSSQ D1
85,89 FBA_CMD13 L3 WE# OPS VSSQ B9 85,89 FBA_CMD13 L3 WE# OPS VSSQ B9
85,89 FBA_CMD15 K3 CAS# VSSQ B1 85,89 FBA_CMD15 K3 CAS# VSSQ B1
85,89 FBA_CMD30 J3 RAS# VSSQ G9 85,89 FBA_CMD30 J3 RAS# VSSQ G9
K4W 4G1646B-HC11-GP K4W 4G1646B-HC11-GP
72.41646.00U 72.41646.00U
FBA_CLK0
1
R8805 OPS R8808 OPS

1
1K33R2F-GP 1K33R2F-GP
A R8809 M14 DIS A
2
OPS 162R2F-GP
VRAM1_VREF VRAM2_VREF
Wistron Corporation
2
1
1

FBA_CLK0# R8806 OPS C8803 R8807 OPS Taipei Hsien 221, Taiwan, R.O.C.
1K33R2F-GP
OPS SCD1U10V2KX-5GP 1K33R2F-GP
OPS C8805
SCD1U10V2KX-5GP
2
Title
2
GPU-VRAM1,2 (1/4)
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
88 of 105
5 4 3 2 1
Frame Buffer Patition A-Upper Half
D D
1D5V_VGA_S0
1D5V_VGA_S0
VRAM3 VRAM4
FBA_D[56..63] 85 FBA_D[48..55] 85
1
1
C8920 C8929 C8928 C8913 K8 E3 FBA_D62 C8917 C8906 C8915 C8907 K8 E3 FBA_D49
OPS OPS OPS OPS K2 VDD DQL1 F7 OPS OPS OPS OPS K2 VDD DQL1 F7
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
N1 F2 FBA_D58 N1 F2 FBA_D51
2
2
B2 H3 FBA_D57 B2 H3 FBA_D50
D9 VDD DQL5 H8 D9 VDD DQL5 H8
w
G7 G2 FBA_D60 G7 G2 FBA_D48
R1 VDD DQL7 H7 R1 VDD DQL7 H7
w
N9 VDD FBA_D[32..39] 85 N9 VDD FBA_D[40..47] 85
D7 FBA_D32 D7 FBA_D40
w
DQU0 FBA_D36 DQU0 FBA_D47
.ro
A1 C8 FBA_D34 A1 C8 FBA_D41
VDDQ DQU2 VDDQ DQU2
1
1
C8927 C8926 C8925 C8908 C1 C2 FBA_D38 C8921 C8922 C8923 C8918 C1 C2 FBA_D42
OPS OPS OPS OPS C9 A7 OPS OPS OPS OPS C9 A7
se
VDDQ DQU4 VDDQ DQU4
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
D2 A2 FBA_D37 D2 A2 FBA_D43
2
2
E9 VDDQ DQU6 B8 E9 VDDQ DQU6 B8
fix
F1 A3 FBA_D35 F1 A3 FBA_D45
VDDQ DQU7 VDDQ DQU7
H9 VDDQ H9 VDDQ
.c
H2 VDDQ DQSU C7 FBA_DQS_W P4 85 H2 VDDQ DQSU C7 FBA_DQS_W P5 85
DQSU# B7 FBA_DQS_RN4 85 DQSU# B7 FBA_DQS_RN5 85
om
C VRAM3_VREF H1 VRAM3_VREF H1 C
VRAM4_VREF VREFDQ VRAM4_VREF VREFDQ
M8 VREFCA DQSL F3 FBA_DQS_W P7 85 M8 VREFCA DQSL F3 FBA_DQS_W P6 85
1 OPS 2 VRAM_ZQ3 L8 G3 FBA_DQS_RN7 85 1 OPS 2 VRAM_ZQ4 L8 G3 FBA_DQS_RN6 85
ODT K1 FBA_CMD18 85 ODT K1 FBA_CMD18 85

85,88 FBA_CMD9 N3 A0 85,88 FBA_CMD9 N3 A0
85,88 FBA_CMD8 P3 A2 CS# L2 FBA_CMD16 85 85,88 FBA_CMD8 P3 A2 CS# L2 FBA_CMD16 85
85,88 FBA_CMD25 N2 A3 RESET# T2 FBA_CMD5 85,88 85,88 FBA_CMD25 N2 A3 RESET# T2 FBA_CMD5 85,88
85,88 FBA_CMD22 R8 A6 NC#M7 M7 FBA_CMD14 85,88 85,88 FBA_CMD22 R8 A6 NC#M7 M7 FBA_CMD14 85,88
85,88 FBA_CMD7 R2 A7 NC#L9 L9 85,88 FBA_CMD7 R2 A7 NC#L9 L9
85,88 FBA_CMD21 T8 A8 NC#L1 L1 85,88 FBA_CMD21 T8 A8 NC#L1 L1
85,88 FBA_CMD6 R3 A9 NC#J9 J9 85,88 FBA_CMD6 R3 A9 NC#J9 J9
85,88 FBA_CMD29 L7 A10/AP NC#J1 J1 85,88 FBA_CMD29 L7 A10/AP NC#J1 J1
85,88 FBA_CMD23 R7 A11 85,88 FBA_CMD23 R7 A11
85,88 FBA_CMD28 N7 A12/BC# 85,88 FBA_CMD28 N7 A12/BC#
85,88 FBA_CMD20 T3 A13 VSS J8 85,88 FBA_CMD20 T3 A13 VSS J8
85,88 FBA_CMD4 T7 A14 VSS M1 85,88 FBA_CMD4 T7 A14 VSS M1
VSS M9 VSS M9
VSS J2 VSS J2
85,88 FBA_CMD12 M2 BA0 VSS P9 85,88 FBA_CMD12 M2 BA0 VSS P9
85,88 FBA_CMD27 N8 BA1 VSS G8 85,88 FBA_CMD27 N8 BA1 VSS G8
85,88 FBA_CMD26 M3 BA2 VSS B3 85,88 FBA_CMD26 M3 BA2 VSS B3
VSS T1 VSS T1
VSS A9 VSS A9
85 FBA_CLK1 J7 CK VSS T9 85 FBA_CLK1 J7 CK VSS T9
85 FBA_CLK1# K7 CK# VSS E1 85 FBA_CLK1# K7 CK# VSS E1
B B
VSS P1 VSS P1
85 FBA_CMD19 K9 CKE 85 FBA_CMD19 K9 CKE
VSSQ G1 VSSQ G1
VSSQ F9 VSSQ F9
85 FBA_DQM4 D3 DMU VSSQ E8 85 FBA_DQM5 D3 DMU VSSQ E8
85 FBA_DQM7 E7 DML VSSQ E2 85 FBA_DQM6 E7 DML VSSQ E2
VSSQ D8 VSSQ D8
VSSQ D1 VSSQ D1
85,88 FBA_CMD13 L3 WE# VSSQ B9 85,88 FBA_CMD13 L3 WE# VSSQ B9
85,88 FBA_CMD15 K3 CAS# OPS VSSQ B1 85,88 FBA_CMD15 K3 CAS# OPS VSSQ B1
85,88 FBA_CMD30 J3 RAS# VSSQ G9 85,88 FBA_CMD30 J3 RAS# VSSQ G9
72.41646.00U 72.41646.00U
1
FBA_CLK1 R8904 OPS R8906 OPS

2
2
1
VRAM3_VREF VRAM4_VREF
A R8909 M14 DIS A
1
OPS 162R2F-GP
1
R8905 OPS OPS C8911 R8903 OPS OPS C8914 Wistron Corporation
2
1K33R2F-GP SCD1U10V2KX-5GP 1K33R2F-GP SCD1U10V2KX-5GP

2

2
FBA_CLK1# Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU-VRAM3,4 (2/4)
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
89 of 105
5 4 3 2 1
Frame Buffer Patition B-Lower Half
D D
1D5V_VGA_S0
1D5V_VGA_S0
VRAM6
VRAM5 FBB_D[16..23] 85
1
FBB_D[0..7] 85 C9007 C9003 C9002 C9001 K8 E3 FBB_D16
VDD DQL0
1
C9016 C9018 C9021 C9015 K8 E3 FBB_D3 8VRAM DY 8VRAM 8VRAM K2 F7 FBB_D20

VDD DQL0 VDD DQL1
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
8VRAM 8VRAM DY 8VRAM K2 F7 FBB_D0 N1 F2 FBB_D19
2
VDD DQL1 VDD DQL2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
N1 F2 FBB_D7 R9 F8 FBB_D21
2
VDD DQL2 FBB_D2 VDD DQL3 FBB_D17

R9 VDD DQL3 F8 B2 VDD DQL4 H3
B2 H3 FBB_D6 D9 H8 FBB_D22
D9 VDD DQL5 H8 G7 VDD DQL6 G2
w
G7 G2 FBB_D5 R1 H7 FBB_D23
VDD DQL6 FBB_D1 VDD DQL7
R1 VDD DQL7 H7 N9 VDD FBB_D[24..31] 85
w
N9 FBB_D[8..15] 85 D7 FBB_D24
VDD FBB_D12 DQU0 FBB_D30
D7 A8 C3
w
DQU0 FBB_D9 VDDQ DQU1 FBB_D27
1
.ro
A1 C8 FBB_D14 C9023 C9024 C9008 C9009 C1 C2 FBB_D28
VDDQ DQU2 VDDQ DQU3
1
C9026 C9004 C9012 C9022 C1 C2 FBB_D8 8VRAM 8VRAM 8VRAM 8VRAM C9 A7 FBB_D26
VDDQ DQU3 VDDQ DQU4
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
8VRAM 8VRAM 8VRAM 8VRAM C9 A7 FBB_D13 D2 A2 FBB_D29
se
2
2
VDDQ DQU4 VDDQ DQU5
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
D2 A2 FBB_D10 E9 B8 FBB_D25
2
VDDQ DQU5 FBB_D15 VDDQ DQU6 FBB_D31

E9 VDDQ DQU6 B8 F1 VDDQ DQU7 A3
fix
F1 A3 FBB_D11 H9
VDDQ DQU7 VDDQ
H9 VDDQ H2 VDDQ DQSU C7 FBB_DQS_W P3 85
.c
H2 VDDQ DQSU C7 FBB_DQS_W P1 85 DQSU# B7 FBB_DQS_RN3 85
B7 FBB_DQS_RN1 85 VRAM5_VREF H1
DQSU# VREFDQ
om
C VRAM5_VREF H1 VRAM6_VREF M8 F3 FBB_DQS_W P2 85
C
VRAM6_VREF VREFDQ VRAM_ZQ5 VREFCA DQSL
VRAM_ZQ6
M8 VREFCA DQSL F3 FBB_DQS_W P0 85 1
R9004
8VRAM
2
243R2F-2-GP
L8 ZQ DQSL# G3 FBB_DQS_RN2 85
1
R9001
8VRAM
2
243R2F-2-GP
L8 ZQ DQSL# G3 FBB_DQS_RN0 85
ODT K1 FBB_CMD2 85
ODT K1 FBB_CMD2 85 85,91 FBB_CMD9 N3 A0
85,91 FBB_CMD9 N3 A0 85,91 FBB_CMD11 P7 A1
85,91 FBB_CMD11 P7 A1 85,91 FBB_CMD8 P3 A2 CS# L2 FBB_CMD0 85
85,91 FBB_CMD8 P3 A2 CS# L2 FBB_CMD0 85 85,91 FBB_CMD25 N2 A3 RESET# T2 FBB_CMD5 85,91
85,91 FBB_CMD25 N2 A3 RESET# T2 FBB_CMD5 85,91 85,91 FBB_CMD10 P8 A4
85,91 FBB_CMD10 P8 A4 85,91 FBB_CMD24 P2 A5
85,91 FBB_CMD24 P2 A5 85,91 FBB_CMD22 R8 A6 NC#M7 M7 FBB_CMD14 85,91
85,91 FBB_CMD22 R8 A6 NC#M7 M7 FBB_CMD14 85,91 85,91 FBB_CMD7 R2 A7 NC#L9 L9
85,91 FBB_CMD7 R2 A7 NC#L9 L9 85,91 FBB_CMD21 T8 A8 NC#L1 L1
85,91 FBB_CMD21 T8 A8 NC#L1 L1 85,91 FBB_CMD6 R3 A9 NC#J9 J9
85,91 FBB_CMD6 R3 A9 NC#J9 J9 85,91 FBB_CMD29 L7 A10/AP NC#J1 J1
85,91 FBB_CMD29 L7 A10/AP NC#J1 J1 85,91 FBB_CMD23 R7 A11
85,91 FBB_CMD23 R7 A11 85,91 FBB_CMD28 N7 A12/BC#
85,91 FBB_CMD28 N7 A12/BC# 85,91 FBB_CMD20 T3 A13 VSS J8
85,91 FBB_CMD20 T3 A13 VSS J8 85,91 FBB_CMD4 T7 A14 VSS M1
85,91 FBB_CMD4 T7 A14 VSS M1 VSS M9
VSS M9 VSS J2
VSS J2 85,91 FBB_CMD12 M2 BA0 VSS P9
85,91 FBB_CMD12 M2 BA0 VSS P9 85,91 FBB_CMD27 N8 BA1 VSS G8
85,91 FBB_CMD27 N8 BA1 VSS G8 85,91 FBB_CMD26 M3 BA2 VSS B3
85,91 FBB_CMD26 M3 BA2 VSS B3 VSS T1
VSS T1 VSS A9
VSS A9 85 FBB_CLK0 J7 CK VSS T9
85 FBB_CLK0 J7 CK VSS T9 85 FBB_CLK0# K7 CK# VSS E1
85 FBB_CLK0# K7 CK# VSS E1 VSS P1
B B
VSS P1 85 FBB_CMD3 K9 CKE
85 FBB_CMD3 K9 CKE VSSQ G1
VSSQ G1 VSSQ F9
VSSQ F9 85 FBB_DQM3 D3 DMU VSSQ E8
85 FBB_DQM1 D3 DMU VSSQ E8 85 FBB_DQM2 E7 DML VSSQ E2
85 FBB_DQM0 E7 DML VSSQ E2 VSSQ D8
VSSQ D8 VSSQ D1
VSSQ D1 85,91 FBB_CMD13 L3 WE# VSSQ B9
85,91 FBB_CMD13 L3 WE# VSSQ B9 85,91 FBB_CMD15 K3 CAS# 8VRAM VSSQ B1
85,91 FBB_CMD15 K3 CAS# 8VRAM VSSQ B1 85,91 FBB_CMD30 J3 RAS# VSSQ G9
85,91 FBB_CMD30 J3 RAS# VSSQ G9
K4W 4G1646B-HC11-GP
K4W 4G1646B-HC11-GP
72.41646.00U
72.41646.00U
1
FBB_CLK0 R9006
R9003 8VRAM 1K33R2F-GP8VRAM
1K33R2F-GP
2
2
1
R9009 VRAM5_VREF VRAM6_VREF

A 8VRAM162R2F-GP M14 DIS A
1
1
1
R9005 C9011 R9002 C9014

2
1K33R2F-GP8VRAM SCD1U10V2KX-5GP
8VRAM 1K33R2F-GP8VRAM SCD1U10V2KX-5GP
8VRAM Wistron Corporation
2
FBB_CLK0# 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

2
Title
GPU-VRAM5,6 (3/4)
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM 3 2
1
90 of 105
5 4 3 2 1
Frame Buffer Patition B-Upper Half
D D
VRAM7 VRAM8
FBB_D[56..63] 85 FBB_D[32..39] 85
1
1
C9109 C9107 C9128 C9119 K8 E3 FBB_D56 C9105 C9104 C9115 C9106 K8 E3 FBB_D35
8VRAM 8VRAM 8VRAM 8VRAM K2 VDD DQL1 F7 8VRAM 8VRAM 8VRAM DY K2 VDD DQL1 F7
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
N1 F2 FBB_D58 N1 F2 FBB_D34
2
2
B2 H3 FBB_D59 B2 H3 FBB_D33
D9 VDD DQL5 H8 D9 VDD DQL5 H8
w
G7 G2 FBB_D57 G7 G2 FBB_D32
R1 VDD DQL7 H7 R1 VDD DQL7 H7
w
N9 VDD FBB_D[40..47] 85 N9 VDD FBB_D[48..55] 85
D7 FBB_D47 D7 FBB_D52
w
DQU0 FBB_D41 DQU0 FBB_D49
.ro
A1 C8 FBB_D45 A1 C8 FBB_D54
VDDQ DQU2 VDDQ DQU2
1
1
C9127 C9126 C9120 C9130 C1 C2 FBB_D42 C9123 C9124 C9122 C9117 C1 C2 FBB_D51
8VRAM 8VRAM 8VRAM 8VRAM C9 A7 8VRAM 8VRAM 8VRAM 8VRAM C9 A7
se
VDDQ DQU4 VDDQ DQU4
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
D2 A2 FBB_D40 D2 A2 FBB_D50
2
2
E9 VDDQ DQU6 B8 E9 VDDQ DQU6 B8
fix
F1 A3 FBB_D43 F1 A3 FBB_D48
VDDQ DQU7 VDDQ DQU7
H9 VDDQ H9 VDDQ
.c
H2 VDDQ DQSU C7 FBB_DQS_W P5 85 H2 VDDQ DQSU C7 FBB_DQS_W P6 85
DQSU# B7 FBB_DQS_RN5 85 DQSU# B7 FBB_DQS_RN6 85
om
C VRAM7_VREF H1 VRAM7_VREF H1 C
VRAM8_VREF VREFDQ VRAM8_VREF VREFDQ
M8 VREFCA DQSL F3 FBB_DQS_W P7 85 M8 VREFCA DQSL F3 FBB_DQS_W P4 85
1 8VRAM
2 VRAM_ZQ7 L8 G3 FBB_DQS_RN7 85 1 8VRAM
2 VRAM_ZQ8 L8 G3 FBB_DQS_RN4 85
ODT K1 FBB_CMD18 85 ODT K1 FBB_CMD18 85

85,90 FBB_CMD9 N3 A0 85,90 FBB_CMD9 N3 A0
85,90 FBB_CMD8 P3 A2 CS# L2 FBB_CMD16 85 85,90 FBB_CMD8 P3 A2 CS# L2 FBB_CMD16 85
85,90 FBB_CMD25 N2 A3 RESET# T2 FBB_CMD5 85,90 85,90 FBB_CMD25 N2 A3 RESET# T2 FBB_CMD5 85,90
85,90 FBB_CMD22 R8 A6 NC#M7 M7 FBB_CMD14 85,90 85,90 FBB_CMD22 R8 A6 NC#M7 M7 FBB_CMD14 85,90
85,90 FBB_CMD7 R2 A7 NC#L9 L9 85,90 FBB_CMD7 R2 A7 NC#L9 L9
85,90 FBB_CMD21 T8 A8 NC#L1 L1 85,90 FBB_CMD21 T8 A8 NC#L1 L1
85,90 FBB_CMD6 R3 A9 NC#J9 J9 85,90 FBB_CMD6 R3 A9 NC#J9 J9
85,90 FBB_CMD29 L7 A10/AP NC#J1 J1 85,90 FBB_CMD29 L7 A10/AP NC#J1 J1
85,90 FBB_CMD23 R7 A11 85,90 FBB_CMD23 R7 A11
85,90 FBB_CMD28 N7 A12/BC# 85,90 FBB_CMD28 N7 A12/BC#
85,90 FBB_CMD20 T3 A13 VSS J8 85,90 FBB_CMD20 T3 A13 VSS J8
85,90 FBB_CMD4 T7 A14 VSS M1 85,90 FBB_CMD4 T7 A14 VSS M1
VSS M9 VSS M9
VSS J2 VSS J2
85,90 FBB_CMD12 M2 BA0 VSS P9 85,90 FBB_CMD12 M2 BA0 VSS P9
85,90 FBB_CMD27 N8 BA1 VSS G8 85,90 FBB_CMD27 N8 BA1 VSS G8
85,90 FBB_CMD26 M3 BA2 VSS B3 85,90 FBB_CMD26 M3 BA2 VSS B3
VSS T1 VSS T1
VSS A9 VSS A9
85 FBB_CLK1 J7 CK VSS T9 85 FBB_CLK1 J7 CK VSS T9
85 FBB_CLK1# K7 CK# VSS E1 85 FBB_CLK1# K7 CK# VSS E1
B B
VSS P1 VSS P1
85 FBB_CMD19 K9 CKE 85 FBB_CMD19 K9 CKE
VSSQ G1 VSSQ G1
VSSQ F9 VSSQ F9
85 FBB_DQM5 D3 DMU VSSQ E8 85 FBB_DQM6 D3 DMU VSSQ E8
85 FBB_DQM7 E7 DML VSSQ E2 85 FBB_DQM4 E7 DML VSSQ E2
VSSQ D8 VSSQ D8
VSSQ D1 VSSQ D1
85,90 FBB_CMD13 L3 WE# 8VRAMVSSQ B9 85,90 FBB_CMD13 L3 WE# 8VRAMVSSQ B9
85,90 FBB_CMD15 K3 CAS# VSSQ B1 85,90 FBB_CMD15 K3 CAS# VSSQ B1
85,90 FBB_CMD30 J3 RAS# VSSQ G9 85,90 FBB_CMD30 J3 RAS# VSSQ G9
72.41646.00U 72.41646.00U
1
FBB_CLK1
R9103 8VRAM R9106 8VRAM
2
2
1
R9109 VRAM7_VREF VRAM8_VREF

M14 DIS
A 162R2F-GP
8VRAM A
1
1
1
C9111 C9114
Wistron Corporation
2
R9105 8VRAM SCD1U10V2KX-5GP

8VRAM R9101 8VRAM SCD1U10V2KX-5GP
8VRAM
1K33R2F-GP 1K33R2F-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2
FBB_CLK1# Taipei Hsien 221, Taiwan, R.O.C.

2
Title
GPU-VRAM7,8 (4/4)
A3
http://vinafix.vn
03-05-1512:40:57 PM
5 4 03-05-151:22:21 PM 3 2 1
5 4 3 2 1
V-BOOT VID0 VID1 VID2 VID3 VID4 VID5 VID6
D D
0.9000V 0 0 0 0 1 1 0
3D3V_S0
1
PR9201 PR9202 PR9203 PR9204 PR9205 PR9206 PR9207
DY OPS OPS DY DY DY DY
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
2
2
PWR_VGA_CORE_VID6
86 NV_VID5
NV_VID5 1 OPS 2 PWR_VGA_CORE_VID5
NV_VID4 PR92151 2 0R0402-PAD PWR_VGA_CORE_VID4
86 NV_VID4
NV_VID3 PR92161
OPS 2 0R0402-PAD PWR_VGA_CORE_VID3
86 NV_VID3
NV_VID2 PR92171 OPS 2 0R0402-PAD PWR_VGA_CORE_VID2
86 NV_VID2 OPS
NV_VID1 PR92181 2 0R0402-PAD PWR_VGA_CORE_VID1
86 NV_VID1
NV_VID0 PR92411
OPS 2 0R0402-PAD PWR_VGA_CORE_VID0
86 NV_VID0 OPS
PR9242 0R0402-PAD
1
PR9208 PR9209 PR9210 PR9211 PR9212 PR9213 PR9214
OPS OPS OPS OPS OPS
w
DY DY
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
2
w
w
5V_S0
83.R5003.C8F
.ro
Please confirm with H/W for resistor pull high and pull GND 2nd = 83.R5003.G8H
3rd = 83.R5003.H8H
1
4th = 83.5R003.08F
PD9201 PR9220
10R2J-2-GP
se
2 1
OPS
93 DGPU_PWR_EN DY
2
CH551H-30PT-GP
DCBATOUT
fix
3D3V_VGA_S0 1 OPS 2 PWR_VGA_CORE_VR_ON
PR9219 0R0402-PAD
1
PC9201 DY PC9213 PC9214 PC9216 PC9215
.c
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD01U50V2KX-1GP
SCD1U25V3KX-GP
1
PWR_VGA_CORE_VCC
C OPS PC9202 C
SC1U10V2KX-1GP
1
om
2
OPS OPS OPS OPS Design Current = 27A
PU9202 PU9205
2
5
6
7
8
5
6
7
8
OCP>40A
D
D
D
D
D
D
D
D
GND_3211
VGA_CORE
32
31
30
29
28
27
26
25
OPS OPS
G
PU9201 4 4
S
S
S
S
S
S
EN
VID0
VID1
VID2
VID3
VID4
VID5
VID6
PC9203
1
GND_3211 OPS 2
3
2
1
3
2
1
SC1KP50V2KX-1GP PR9240
0R2J-2-GP PC9211
PR9222 1 24 SCD22U25V3KX-GP
22,27,93 DGPU_PWROK PW RGD VCC PWR_VGA_CORE_UG
1 DY 2 2 23 PWR_VGA_CORE_BOOT 1 OPS 2 PWR_VGA_CORE_BOOT_R 1 PL9201
3
IMON BST
22 PWR_VGA_CORE_UG OPS 2
CLKEN# DRVH
66K5R2F-GP PWR_VGA_CORE_FBRTN
PWR_VGA_CORE_FB
PWR_VGA_CORE_COMP
4
5
6
FBRTN
FB
OPS SW
PVCC
21
20
19
PWR_VGA_CORE_SW
PWR_VGA_CORE_LG
5V_S0
PWR_VGA_CORE_SW 1 OPS 2
COMP DRVL IND-D22UH-31-GP

SC100P50V2JN-3GP
SE470UF2VDM-GP
SE470UF2VDM-GP
7 18
SC22P50V2JN-4GP
PR9225 5V_S0 GPU PGND
PC9204 1 2 PWR_VGA_CORE_ILIM 8 17 PU9203 PU9204
ILIM GND
1
5
6
7
8
5
6
7
8
1
OPS
PT9201
PT9202
PC9206 33
OPS OPS OPS
CSCOMP
GND
D
D
D
D
D
D
D
D
1 1K65R2F-GP
PC9212
CSREF
OPS OPS 79.47719.2BL 79.47719.2BL
RAMP
LLINE
08/01 PG9206 PG9207
CSFB
SC2D2U10V3KX-1GP
IREF
RPM
2ND = 77.24771.13L 2ND = 77.24771.13L
2
2
RT
2
PC9205 PWR_VGA_CORE_CSCOMP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
OPS OPS
1
SC470P50V2KX-3GP
G
ADP3211MNR2G-GP 4 4
9
10
11
12
13
14
15
16
S
S
S
S
S
S
1 2 1 2 1 2
OPS OPS OPS 74.03211.033
PWR_VGA_CORE_FB_L
3
2
1
3
2
1
PR9223 PR9224 GND_3211
84.00035.037 84.00035.037
2
1KR2F-3-GP 20KR2F-L-GP PWR_VGA_CORE_IREF
PWR_VGA_CORE_RPM
PWR_VGA_CORE_RT
PWR_VGA_CORE_CSCOMP
PWR_VGA_CORE_FB_R
PWR_VGA_CORE_CSREF
PWR_VGA_CORE_LLINE
PWR_VGA_CORE_CSFB
PWR_VGA_CORE_RAMP
1 2 PWR_VGA_CORE_CSCOMP_R
OPS
1
PR9229 PR9230 PWR_VGA_CORE_LG

PR9228 69.60029.001
1
2
PR9235
0R0402-PAD
0R0402-PAD
2nd = 69.60028.001
OPS
OPS OPS OPS OPS PR9231 NTC-220K-2-GP

OPS
300KR2F-L-GP
300KR2F-L-GP
80K6R2F-GP
PR9226
PR9227
422KR2F-1-GP
PR9237 PR9238
2
2
2
1 OPS 2 1 OPS 2 1 2 PWR_VGA_CORE_L_L

PWR_VGA_CORE_RAMP_1
PR9236
76K8R2F-GP 174KR2F-GP 240KR3-GP
1
PC9209
1
PR9233 OPS PC9210
SC330P50V2KX-3GP
OPS
SC1200P50V2KX-1GP
GND_3211 20KR2F-L-GP
OPS OPS
2
2
DCBATOUT
B B
1
1 OPS 2
PR9234 OPS
PR9232 20KR2F-L-GP
1KR2F-3-GP
2
1
OPS PC9207
PWR_VGA_CORE_CSCOMP
SC1KP50V2KX-1GP
GND_SENSE
VGA_SENSE
GND_3211 PC9208
OPS
SC1KP50V2KX-1GP
2
83 GND_SENSE VGA_SENSE 83
GND_3211
PR9239
1 OPS 2
0R0402-PAD
Please confirm on H/W side whether have resistor pull high and pull GND by 100 ohm
GND_3211
A A
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L

Inductor: CHIP CHK 0.36UH PCMC104T-R36MH 1.05mohm/ Isat =60A rms68.R3610.20S
O/P cap: CHIP CAP 470UF 2V EEFSX0D471X/ 3.5Arms Panasonic/79.47719.2BL M14 DIS
H/S: RJK03J6DPA-00#J5A / 10mohm/13mOhm@4.5Vgs/ 84.00036.037
L/S: RJK03K5DPA-00#J5A / 3mohm/3.9mOhm@4.5Vgs/ 84.00035.037 Wistron Corporation
Title
ADP3211_+VGA_CORE
Custom
DNE40 14 CR DIS A00
http://vinafix.vn
03-05-1512:40:57 PM
5 4 3 2 1
03-05-151:22:21 PM
5 4 3 2 1
3D3V_VGA_S0 should ramp-up before VGA_Core
3.3V +/- 5% 3D3V_VGA_S0
VGA_Core should ramp-up before 1D5V_VGA_S0
274mA 1D5V_VGA_S0 should ramp-up before 1D05V_VGA_S0
PR9301 1 DY 2 0R2J-2-GP
1.05V +/- 5%
3D3V_S0 VCCP_CPU 1D05V_VGA_S0
DMP2130L-7-GP 2.872A
D PU9303 D
2
S AO4468, SO-8 8 D S 1
1
PR9303 PQ9301 D S
D Id=?A, Qg=9~12nC 7 2 Decap
D
OPS 10KR2F-2-GP PC9301 OPS 6 D S 3
1
G
SCD1U10V2KX-5GP Rdson=17.4~22m ohm D G
DY PC9308
1D05V_ENABLE_RC
OPS 84.02130.031 5 4
1
2
OPS SC10U6D3V3MX-GP
1
G
2nd = 84.00102.031 PC9305 OPS AO4468-GP
2
SC10U6D3V3MX-GP 84.04468.037
2
3rd = 84.03413.A31 3D3V_VGA discharge 2nd = 84.02659.037
1 OPS 2 PQ9302_G 3rd = 84.04178.037
4th = 84.02301.G31 4th = 84.04496.037
PR9304 5th = 84.04800.D37
10KR2F-2-GP
PR9319_1 1D05V_VGA_S0
PR9312
1 2
OPS Discharge Circuit
1
6
4
PQ9302 PR9302 0R0402-PAD
1
OPS 220R2J-L2-GP PR9316
D2
G1
S1
ME2N7002DKW-G-GP
3D3V_AUX_S5 PC9304 OPS 470R2J-2-GP OPS
84.2N702.F3F
w
OPS SCD01U50V2KX-1GP
2nd = 84.2N702.A3F
D1
S2
G2
2
2
1 OPS 2 1D05V_VGA_EN#
3rd = 84.DMN66.03F
DIS_1D05V_VGA_S0 2
1
3
PR9311
PR9315 100KR2J-1-GP D G S
.ro
100KR2J-1-GP
1 OPS 2 3.3V_RUN_VGA_1
4
19,45,46,47 RUNPWROK PQ9305
83.R5003.C8F
se
15V_S5
D2
G1
S1
PR9305 2nd = 83.R5003.G8H ME2N7002DKW-G-GP
10KR2J-3-GP 3rd = 83.R5003.H8H 84.2N702.F3F
4th = 83.5R003.08F OPS
1 DY 2 2nd = 84.2N702.A3F
fix
D1
S2
G2
3D3V_S0
3rd = 84.DMN66.03F
2
PD9302
.c
2 DY 1 S G D PR9313
92 DGPU_PWR_EN
OPS 100KR2J-1-GP
D
DGPU_PWR_EN
C CH551H-30PT-GP C
om
1
22 DGPU_PWR_EN# PR9307 1
22,27,92 DGPU_PWROK OPS 2 1KR2J-1-GP 1D05V_VGA_EN
1D05V_VGA_EN# G
G
1D05V_ENABLE OPS
PQ9307
DGPU_PWR_EN# 2N7002BK-GP
1
S D PC9306 84.07002.I31
DGPU_PWR_EN 92
S
dGPU mode L OPS SCD1U25V2KX-GP OPS 2nd = 84.2N702.W31
3rd = 84.2N702.J31
2
IGPU H PQ9303
2N7002BK-GP
84.07002.I31
IGPU with BACO L 2nd = 84.2N702.W31
3rd = 84.2N702.J31
1D5V_VGA_S0 3.3V +/- 5%

NV do not need 1.8V
1D5V_PWR 1D5V_VGA_S0
PU9302 4.88A
AO4468, SO-8 8 D S 1
7 D S 2
Id=?A, Qg=9~12nC 6 D S 3
1
Rdson=17.4~22m ohm 5 D G 4 PC9307

1D5V_ENABLE_RC
1
OPS OPS SC10U6D3V3MX-GP

PC9303 OPS AO4468-GP
2
SC10U6D3V3MX-GP 84.04468.037
2
B B
2nd = 84.02659.037
3rd = 84.04178.037
4th = 84.04496.037
5th = 84.04800.D37
PR9308
1 OPS 2
1D5V_VGA_S0
0R0402-PAD
Discharge Circuit
1
PC9302
3D3V_AUX_S5 SCD01U50V2KX-1GP OPS
1
2
1 OPS 2 1D5V_VGA_EN# PR9314

470R2J-2-GP OPS
PR9310 D G S
100KR2J-1-GP
DIS_1D5V_VGA_S0
2
6
83.R5003.C8F
15V_S5
D2
G1
S1
2nd = 83.R5003.G8H PQ9304 OPS

3rd = 83.R5003.H8H ME2N7002DKW-G-GP
4th = 83.5R003.08F 84.2N702.F3F
D1
S2
G2
PD9301 2nd = 84.2N702.A3F

1
3rd = 84.DMN66.03F PR9309

92 DGPU_PWR_EN 2 DY 1 S G D 100KR2J-1-GP
OPS
CH551H-30PT-GP
PR9306
1
1 OPS 2 1D5V_VGA_EN
D
22,27,92 DGPU_PWROK
0R0402-PAD 1D5V_ENABLE
1D5V_VGA_EN# G
OPS
A A
PQ9306
2N7002BK-GP
M14 DIS
84.07002.I31
S
2nd = 84.2N702.W31
3rd = 84.2N702.J31 Wistron Corporation
Title
DISCRETE VGA POWER
Custom OAK14 Chief River DIS A00
http://vinafix.vn
03-05-1512:40:57 PM
5 4
03-05-151:22:21 PM 3 2 1
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
M14 DIS
A A
Wistron Corporation
Title
LVDS_Switch
A3
http://vinafix.vn
03-05-1512:40:57 PM
Date: W ednesday, September 05, 2012
Sheet 94 of 105
5 4 03-05-151:22:21 PM
3 2 1
5 4 3 2 1
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
M14 DIS
A A
Wistron Corporation
Title
CRT_Switch
A3
http://vinafix.vn
03-05-1512:40:57 PM
Date: W ednesday, September 05, 2012
Sheet 95 of 105
5 4 03-05-151:22:21 PM
3 2 1
5 4 3 2 1
SSID = SDIO
D D
w
w
w
.ro
se
fix
.c
om
C C
(Blanking)
B B
A M14 DIS A
Wistron Corporation
Title
TOUCH PANEL
A3
03-05-1512:40:57 PM
03-05-151:22:21 PM
3 2
1
96 of 105
5 4 3 2 1
SSID = Mechanical
S1 S2 S3
STF237R117H83-1-GP STF237R117H83-1-GP STF237R113H111-GP
34.4V802.001
1
34.4CK01.001 34.4CK01.001
D D
H4 H9 H8
H2 H3 H5 HOLE237R95-GP HOLE237R95-GP
H1 HT85BE85R29-U-5-GP HOLE335R115-GP HOLE256R115-GP HT85BE85R29-U-5-GP H6
HOLE335R115-GP ZZ.00PAD.D41 ZZ.00PAD.D01 ZZ.00PAD.D11 ZZ.00PAD.D41 HT85BE85R29-U-5-GP
ZZ.00PAD.D01 ZZ.00PAD.D41
1
1
1
ZZ.00PAD.921 ZZ.00PAD.921
w
w
w
C1 C2 C3
.ro
HOLE197R166-1-GP HOLE197R166-1-GP HOLE197R166-1-GP
SPR2 SPR3
SPRING-102-GP SPRING-102-GP
se
fix
1
.c
ZZ.00PAD.V71 ZZ.00PAD.V71 ZZ.00PAD.V71
om
C C
34.41V01.001 34.41V01.001
CPU BRACKET
SSID = EMI
DCBATOUT 1D5V_VGA_S0
1
1
EC9701 EC9702 EC9703 EC9704 EC9705 EC9706 EC9707 EC9708 EC9709 EC9710 EC9727 EC9725 EC9726 EC9730 EC9728 EC9729 EC9731 EC9739 EC9743 EC9744 EC9745
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
DY DY DY DY DY DY DY DY AUD_AGND
2
2
1
EC9711 EC9712 EC9713 EC9714 EC9716 EC9715 EC9717

B B
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
DY DY DY DY DY DY
2
DCBATOUT
1
EC9740 EC9741 EC9742 EC9746 EC9747 EC9748 EC9749 EC9750
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
DY DY DY
2
2
5V_S0
1
EC9720 EC9719 EC9718 EC9723 EC9721 EC9722 EC9724

SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DY DY DY DY DY
2
3D3V_S0 5V_S5
1
1
A EC9737 EC9735 EC9736 EC9738 EC9734 EC9732 EC9733 A
M14 DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DY DY DY DY DY DY DY
2
2
Wistron Corporation
Title
UNUSED PARTS/EMI Capacitors

A3
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03-05-151:22:21 PM 3 2
1
97 of 105
5 4 3 2 1
Chief River Platform Power Sequence

(AC mode) Red Words: Controlled by EC GPIO
(DC mode) Red Words: Controlled by EC GPIO
+RTC_VCC t01 >9ms

+RTC_VCC
t01 >9ms
RTC_RST#
RTC_RST#
DCBATOUT
DCBATOUT
Within logic high level and disable if

3D3V_AUX_S5
D it is less than the logic low level.
3D3V_AUX_S5 D
KBC GPIO34 control power on by 3V_5V_EN
S5_ENABLE Sense the power button status
Press Power button
KBC_PWRBTN# Platform to KBC PSL_IN2
Ta 5V_S5
V5REF_Sus must be powered up before PSL_OUT#(GPIO71) keep low
VccSus3_3, or after VccSus3_3 within 3D3V_S5 Ta 3D3V_AUX_KBC
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before KBC GPIO34 control power on by 3V_5V_EN
VccSus3_3 within 0.7 V.
+5VA_PCH_VCC5REFSUS S5_ENABLE
KBC GPIO43 to PCH
PM_RSMRST#(EC Delay 40ms) t05 >10ms 5V_S5
PCH to KBC GPIO00 V5REF_Sus must be powered up before
5V_S5 & 3D3V_S5 need meet 0.7V difference
PCH_SUSCLK_KBC t07 >5ms VccSus3_3, or after VccSus3_3 within 3D3V_S5
0.7 V. Also, V5REF_Sus must power
KBC GPO84 to PCH down after VccSus3_3, or before
5V_S5 & 3D3V_S5 need meet 0.7V difference
Not floating. VccSus3_3 within 0.7 V.
AC_PRESENT 0ms<t08a<90ms +5VA_PCH_VCC5REFSUS Ta
KBC GPIO43 to PCH
PM_RSMRST#(RSMRST#_RST) t05 >10ms
In case of a non-Deep S4/S5 Platform
t07 >100ms PCH to KBC GPIO00
timing t42 should be added to t07
Press Power Button which will make it 100mS minimum.
PCH_SUSCLK_KBC
3D3V_AUX_KBC
Platform to KBC PSL_IN2
w
Sense the power button status KBC GPIO20 to PCH
AC KBC_PWRBTN#
PM_PWRBTN#
w
This signal has an internal
pull-up resistor and has an KBC GPIO20 to PCH
internal 16 ms de-bounce on the
AC PM_PWRBTN#
w
input.
.ro
DC PM_PWRBTN#
After Power Button After Power Button
PCH to KBC GPIO44 PCH to KBC GPIO44
se
PM_SLP_S4# PM_SLP_S4#
t10 PCH to KBC GPIO01 t10 PCH to KBC GPIO01
PM_SLP_S3# >30us PM_SLP_S3# >30us
fix
KBC GPIO47 to LAN KBC GPIO47 to LAN
PM_LAN_ENABLE PM_LAN_ENABLE
Enable by PM_SLP_S4# Enable by PM_SLP_S4#
.c
1D5V_S3 1D5V_S3
om
C C
DDR_VREF_S3(0.75V) DDR_VREF_S3(0.75V)
5V_S0 & 3D3V_S0 need meet 0.7V difference 5V_S0 & 3D3V_S0 need meet 0.7V difference
5V_S0 5V_S0
Tb
V5REF must be powered up before 3D3V_S0 V5REF must be powered up before 3D3V_S0
Vcc3_3, or after Vcc3_3 within 0.7 Vcc3_3, or after Vcc3_3 within 0.7
V. Also, V5REF must power down V. Also, V5REF must power down
after Vcc3_3, or before Vcc3_3 after Vcc3_3, or before Vcc3_3
within 0.7 V. +5VS_PCH_VCC5REF Tb within 0.7 V. +5VS_PCH_VCC5REF Tb
1D5V_S0 1D5V_S0
1D8V_S0 1D8V_S0
0D75V_S0 0D75V_S0
1D8V_S0 & 1D5V_S3 power ready 1D8V_S0 & 1D5V_S3 power ready
RUNPWROK RUNPWROK
VCCP_CPU 1D05V_PCH
1D05_VTT_PWRGD VCCP_CPU
0D85V_S0 1D05_VTT_PWRGD
0D85V_S0
0D85V_S0 0D85V_S0
D85V_PWRGD D85V_PWRGD
CPU SVID BUS SetVID ACK SetVID ACK

50us< t36 <2000us CPU SVID BUS 50us< t36 <2000us
VCC_CORE VCC_CORE
VCC_GFXCORE VCC_GFXCORE
t37 t37
<5ms <5ms
IMVP_PWRGD IMVP_PWRGD
B B
PCH_CLOCK_OUT PCH_CLOCK_OUT
This signal represents the Power

ALL_SYS_PWRGD=D85V_PWRGD t14 >99ms KBC GPIO77 to PCH This signal represents the Power
ALL_SYS_PWRGD=D85V_PWRGD t14 >99ms KBC GPIO77 to PCH
Good for all the non-CORE and PWROK(S0_PWR_GOOD) Good for all the non-CORE and PWROK(S0_PWR_GOOD)
non-graphics power rails. non-graphics power rails.
t18 t18
D85V_PWRGD >0us PCH to CPU D85V_PWRGD >0us PCH to CPU
DRAMPWROK(VDDPWRGOOD) 2ms<t17 <650ms DRAMPWROK(VDDPWRGOOD) 2ms<t17 <650ms
t19 >1ms t19 >1ms
t20 >2ms t20 >2ms
1D8V_S0 1D8V_S0
5ms<t13 <650ms PCH to CPU 5ms<t13 <650ms PCH to CPU
UNCOREPWRGOOD(H_CPUPWRGD) UNCOREPWRGOOD(H_CPUPWRGD)
SYS_PWROK t21+t22 >1ms+60us SYS_PWROK t21+t22 >1ms+60us

1ms< t25 <100ms PCH to all system 1ms< t25 <100ms PCH to all system
PLT_RST# PLT_RST#
t39 <200us t39 <200us
DMI DMI
N13M-GS Power-Up/Down Sequence
3D3V_S0
PCH GPIO54 output
DGPU_PWR_EN#(Discrete only)
3D3V_VGA_S0(VDD33)
A
8209A_EN/DEM_VGA(Discrete only) A
VGA_CORE(NVVDD) tNVVDD >0ms

RT8208 PGOOD
DGPU_PWROK(Discrete only)
1D5V_VGA_S0(FBVDDQ) tNV-FBVDDQ >0ms
1D05V_VGA_S0(PEX_VDD) tNV-PEX_VDD >0ms
First rail to power down VGA_CORE,1D05V_VGA_S0 M14 DIS

1D5V_VGA_S0,3D3V_VGA_S0
Last rail to power down Wistron Corporation
tPOWER-OFF <10ms Taipei Hsien 221, Taiwan, R.O.C.
Title
Power Sequence
http://vinafix.vn
03-05-1512:40:57 PM
For power-down, reversing the ramp-up sequence is recommended. A1
03-05-151:22:21 PM
5 4 3 2 1
5 4 3 2 1
OAK14 Chief River POWER UP SEQUENCE DIAGRAM

5V_S5 DCBATOUT
-6
AC AD+
Adapter in
Page38
-3.1 -3.1 -3.1
VDDP VIN 1D5V_S3
D PWR_5V3D3V_ENC 3V_5V_EN S5_ENABLE VOUT D
3
PM_SLP_S4#
EN
-3.2 -3.3 DDR_VREF_S3
PWR_CHG_ACOK REF
SWITCH ENC 5V_S5 15V_S5
LL1 PUMP
Page40
3D3V_S5 TPS51216RUK
LL2
0D75V_S0
5V_AUX_S5 VTT
TPS51125 VREG5
DC/DC 3D3V_AUX_S5 -5
-6.1 (3V/5V) VREG3 3 RUNPWROK
PGD
DCBATOUT 3V_5V_POK PM_SLP_S4#

VIN PGOOD -2 Page46
5
w
Page41
w
4 5V_S5 3D3V_S5
w
DC BQ24707 5V_S0
BT+ PM_SLP_S3#
Battery
.ro
Charger SWITCH
Page39 -3 BJT Page37
3D3V_AUX_KBC -3.1 VDD VIN 1D8V_S0
se
VOUT
Page40 ACOK 3D3V_S0 4
S5_ENABLE SWITCH
SYW231ABC
fix
PM_SLP_S3#
-4 Page37 EN
RUNPWROK
AC_IN# GPIO34 PGD
.c
GPIO70 1D5V_S0
Page47
C SWITCH C
om
Page37 5
1 SLP_S4# SLP_S3#
-1 KBC
KBC_PWRBTN#
GPIO6 NPCE885P -2.1
11 AND GATE
Power Button PM_RSMRST# 0D75V_EN
PM_SLP_S4# GPIO43 RSMRST# B VDDPWRGOOD
GPIO44 PM_PWRBTN# PM_DRAM_PWRGD Y SM_DRAMPWROK
PM_SLP_S3# GPIO20 PWRBTN# DRAMPWRGD A
GPIO01
2 H_CPUPWRGD H_CPUPWRGD_R
PROCPWRGD UNCOREPWRGOOD
Page27 Pather Point 12
GPIO77 PCH Ivy Bridge
13 CPU
S0_PWR_GOOD
APWROK
PWROK PLT_RST# BUF_CPU_RST#
PLTRST# RSTIN#
SYS_PWROK SVID
SYS_PWROK
SVID
10
8
5V_S5 DCBATOUT
B V5IN VIN B
1D05_VTT
VOUT
5 AND GATE 10
S0_PWR_GOOD
RUNPWROK TPS51219RTER A SYS_PWROK
EN 1.05VTT_PWRGD IMVP_PWRGD Y
Page45 PGOOD B
5V_S5 DCBATOUT 5a
VDDP VIN 0D85_S0 -5

VOUT
5a -7 3D3V_AUX_S5
1.05VTT_PWRGD TPS51463 RTC_AUX_S5
EN D85V_PWRGD
Page48 PGOOD -8
+RTC_VCC
6
DCBATOUT
RTC battery
8 VIN VCC_CORE
OUTPUT
SVID
SVID VCC_GFXCORE
A VR OUTPUT A
6 7 VT1318+1323
D85V_PWRGD IMVP_VR_ON 9 M14 DIS
VR_ON IMVP_PWRGD
Page42 & 43 & 44 PGOOD
Wistron Corporation
Power Up Sequence: -8 ~ 13 Title
Size Document Number

Power Sequence Diagram
Rev
A2
http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
5 4 3 2 1
5 4 3 2 1
DCBATOUT
Adapter
TPS51219DSCR TPS51216RUKR ADP3211

D AO4407A D
Charger
BQ24707 1D05V_VTT
Battery +PBATT 1D5V_S3 0D75V_S0 VGA_CORE
AO4468
w
TPCA8062 AO4468
w
w
1D05V_VGA_S0
.ro
se
1D5V_S0 1D5V_VGA_S0
fix
.c
om
C C
TPS51225ARGER
15V_S5 3D3V_AUX_S5 5V_AUX_S5 5V_S5 3D3V_S5
TPS51463 G547F2P81 AO4468 ISL95833 ADP3211 AO4468

AO3403
SYW231
0D85V_S0 5V_USB2_S0 5V_S0 3D3V_S0

3D3V_LAN_S5
1D8V_S0
VCC_CORE VCC_GFXCORE
B B
SY6288
ODD_PWR_5V G5285T11 RT9724 DMP2130L
LCDVDD 3D3V_CARD_S0 3D3V_VGA_S0
Power Shape
A M14 DIS A
Regulator LDO Switch Wistron Corporation

Title
Size
Power Block Diagram
Document Number Rev
A3
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03-05-151:22:21 PM 3 2
1
100 of 105
A B C D E
PCH SMBus Block Diagram 3D3V_S5 3D3V_S0 KBC SMBus Block Diagram
3D3V_S0
3D3V_S0
SRN2K2J-1-GP
SRN2K2J-1-GP
DIMM 1

SRN10KJ-5-GP

SMBCLK SMB_CLK PCH_SMBCLK SCL
TouchPad Conn.

1 1
SMBDATA SMB_DATA PCH_SMBDATA
SDA

PSDAT1 TPDATA TPDATA TPDATA
3D3V_S5
PSCLK1 TPCLK TPCLK TPCLK
SMBus Address:A0
2N7002SPT
3D3V_S5
3D3V_AUX_KBC

SRN2K2J-8-GP
DIMM 2

PCH_SMBCLK
SCL

PCH_SMBDATA SDA
SML1CLK SML1_CLK
SRN4K7J-8-GP
SML1DATA SML1_DATA To KBC SRN2K2J-1-GP
SMBus Address:A4
Battery Conn.
SRN33J-7-GP

SML0CLK SML0_CLK GPIO17/SCL1 BAT_SCL PBAT_SMBCLK1 CLK_SMB
w
SMBus address:16
SML0DATA SML0_DATA TPAD GPIO22/SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB
w
w
PCH_SMBCLK SMB_CLK
.ro
PCH_SMBDATA
SMB_DATA
BQ24707
KBC SCL
se
SMBus address:12
NPCE885P SDA
fix
.c
2 2
om
3D3V_AUX_KBC
PCH SCL
NCT7718W

3D3V_S5 3D3V_S0 SDA
SRN2K2J-8-GP
3D3V_S0

SRN2K2J-8-GP
SRN4K7J-8-GP
GPIO73/SCL2 SML1_CLK SCL
PCH
Thermal
GPIO74/SDA2 SML1_DATA SDA

SML1_CLK THM_SML1_CLK
SML1CLK SCL
SML1_DATA THM_SML1_DATA SDL
SML1DATA
SMBus Address:98
2N7002SPT
3D3V_VGA_S0
SRN4K7J-8-GP
3D3V_VGA_S0
VGA

3 3
SMBus Address:9E
THM_SML1_CLK SMBC_Therm_NV I2CS_SCL
THM_SML1_DATA SMBD_Therm_NV I2CS_SDA
3D3V_S0 5V_HDMI_S0_R

3D3V_S0
SRN2K2J-1-GP
SRN1K5J-GP

SDVO_CTRLCLK PCH_HDMI_CLK DDC_CLK_HDMI
SDVO_CTRLDATA PCH_HDMI_DATA DDC_DATA_HDMI

HDMI CONN
2N7002DW-1-GP
3D3V_S0
4
4
SRN2K2J-1-GP
M14 DIS

L_DDC_CLK LVDS_DDC_CLK_R LVDS_DDC_CLK CLK
L_DDC_DATA LVDS_DDC_DATA_R LVDS_DDC_DATA DATA LCD CONN Wistron Corporation

Title
SMBUS Block Diagram

http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
A B C D E
5 4 3 2 1
OAK14 DIS CLK Block Diagram

CPU PCH
M_A_DIMA_CLK_DDR0
Ivy & Sandy Panther Point CLK_PCH_48M Card Reader
D CK0 SA_CK0 CLKOUTFLEX1/GPIO65 CLK_IN
D
CK0#
M_A_DIMA_CLK_DDR#0
SA_CLK#0
RTS5170
DDR3 DIMM1
M_A_DIMA_CLK_DDR1 CLK_EXP_P
CK1 SA_CK1 BCLK CLKOUT_DMI_P
M_A_DIMA_CLK_DDR#1 CLK_EXP_N
CK1# SA_CLK#1 BCLK# CLKOUT_DMI_N
CLK_PCIE_WLAN#
CLKOUT_PCIE2N PIN 11
M_B_DIMB_CLK_DDR0
WLAN
CK0 SB_CK0 CLK_PCIE_WLAN
CLKOUT_PCIE2P PIN 13
w
M_B_DIMB_CLK_DDR#0
CK0# SB_CLK#0
w
DDR3 DIMM2
w
M_B_DIMB_CLK_DDR1
CK1 SB_CK1
.ro
M_B_DIMB_CLK_DDR#1
CK1# SB_CLK#1 LAN
se
RTL8105E-VD
fix
CLK_PCIE_LAN
CLKOUT_PCIE5P PIN 19
.c
FBA_CLK0 CLK_PCIE_LAN#
CK0 CLKOUT_PCIE5N PIN 20
C VGA C
om
VRAM1 CK0#
FBA_CLK0#
N13M-GSR
LANXIN
FBA_CLK0
N13P-GS-OP CKXTAL1
CLK_PCIE_VGA#
CK0 FBA_CLK0 PEX_REFCLK# CLKOUT_PEG_A_N
FBA_CLK0#
VRAM2 CK0#
FBA_CLK0# X3101
25MHz
CLK_PCIE_VGA
PEX_REFCLK CLKOUT_PEG_A_P
LANXOUT
CKXTAL2
FBA_CLK1
CK0 27MHZ_IN
XTAL_IN
VRAM3 CK0#
FBA_CLK1#
X8601
27MHz
FBA_CLK1
CK0
FBA_CLK1#
FBA_CLK1
27MHZ_OUT
Audio
VRAM4 CK0#
FBA_CLK1# XTAL_OUT
ALC3221
RN2102
HDA_BITCLK HDA_CODEC_BITCLK
HDA_BCLK BITCLK
SRN33J-5-GP-U
B RTC_X1 B
RTCX1
X2101
KBC
32.768KHz
NPCE885P
RTC_X2 PCH_SUSCLK_KBC
RTCX2 SUSCLK/GPIO62 GPIO0/EXTCLK
Regulatory Model: P22G R1806 CLK_PCI_KBC
CLKOUT_PCI2 LCLK/GPIOF5
Regulatory Type: P22G004 22R2J-2-GP
XTAL25_IN
XTAL25_IN
CLK_PCI_FB_R R1805
X2001 CLKOUT_PCI1
25MHz 22R2J-2-GP
XTAL25_OUT CLK_PCI_FB
XTAL25_OUT CLKIN_PCILOOPBACK
A A
M14 DIS
Wistron Corporation
Title
CLK Block Diagram
A2
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5 4 03-05-1512:40:57
03-05-151:22:21
3 PM
PM 2
1
Sheet 102 of 105
A B C D E
Thermal Block Diagram Audio Block Diagram

1 1
3D3V_S5 3D3V_S0
PAGE28 D+ NCT7718_DXP
PCH MMBT3904-3-GP
SPKR_L+
SPKR_L-
SC2200P50V2KX-2GP SPKR_R-
SPKR_R+ SPEAKER
Pather DIS
D- NCT7718_DXN
Place near CPU

Point Thermal

PWM CORE
Codec
w
SML1_DATA THM_SML1_DATA SDA
GPIO75
NCT7718

2N7002
w
SML1_CLK THM_SML1_CLK
ALC3221
w
GPIO58 SCL
.ro
MMBT3904-3-GP
T8 AUD_HP1_JACK_L HP MIC
se
SML1_DATA AUD_HP1_JACK_R
3D3V_VGA_S0 PURE_HW_SHUTDOWN#
COMBO
fix
SML1_CLK T_CRIT# THERM_SYS_SHDN#
2N7002
D EN 3V/5V SLEEVE

PAGE20 S 3D3V_S0
.c
G RING2
Put under CPU(T8 HW shutdown) (IPhone
om
2 2
THM_SML1_DATA
THM_SML1_CLK Only)

PAGE27 PAGE86
GPIO74
KBC GPIO73
NPCE885P 2N7002
SMBC_Therm_NV I2CS_SCL
VGA
SMBD_Therm_NV I2CS_SDA
N13M-GSR
GPIO94 GPIO56
GPIO4 N13P-GS-OP
FAN_TACH1
FAN1_DAC
TACH
3 3
FAN
5V VIN
VSET VOUT DMIC_CLK Digital

VIN
FAN CONTROL
DMIC_DATA
MIC
NCT3940S-A
PAGE28
4 4
M14 DIS
Wistron Corporation
Title
Size
Thermal/Audio Block Diagram
Document Number Rev
http://vinafix.vn
Custom
A00
03-05-1512:40:57 PM
A B
03-05-151:22:21 PM C D
Date: Wednesday, September 05, 2012 Sheet
E
103 of 105
5 4 3 2 1
Version Date PAGE Description of Required Change
X01 5/10 P38 Dummy R3818 R3813 for DT Mode
X01 5/10 P20 Change CLK_PCIE_WLAN_REQ# PU from 3D3V_S5 to 3D3V_S0 & change port 3 to port 2(non AOAC)
X01 5/10 P86 Dummy R8613 (for N13M-GS1 strappin)

D D
X01 5/28 Update connector list(5/28) for X01
X01 5/30 P49 Add TPNL1 (USB20 port#3)
X01 5/30 P29 Add delay circuit for Audio Jack JD pin
X01 5/30 P59 Change RJ45 Conn
X01 6/1 P38 Stuff PQ3801 PR3814 PR3815 for DT mode
w
X01 6/1 P37 Change R3713 to 10k for sequence timming
w
w
X01 6/1 P31 Change R3118 to 20k for sequence timming
.ro
X01 6/1 P69 Add KBL1 and keyboard backlight function
se
fix
X01 6/1 P27 Change PCB version from X00 to X01
.c
X01 6/5 P46 Fine tune the level of 1d5v_vga_s0: PR4601 (47K -> 57.6K)
om
C C
X01 6/5 P58 Add TVS at combo JACK & RJ45 for EMI request
X01 6/5 P18 Move the KB_LED_BL_DET from GPIO5 to GPIO4
X01 6/11 Implement EMI change request 6/11
X01 6/11 P27 Delete RN2702 , DY R2716, Stuff R2717 For DT Mode
X01 6/11 P21 Add VRAM detect circuit at PCH_GPIO57
X01 6/11 P51 Change D5101 to 83.00056.G11 for lower internal cap
X01 6/12 P18 Move USB2.0 from port4# to port2#
X01 6/12 P49 Modify CAMERA1 to CAM1
X01 6/13 P61 Separate the USB3.0 PWR to USB30_VCCA & USB30_VCCB
B B
X01 6/14 P49 Add LCD Back Light control circuit from KBC GPIO33
X01 6/14 P40 implement Power team request item
X01 6/15 P31 Change C3102=C3103=18pf for Xtal vendor request
X01 6/15 P62 Modify cap value for USB30_VCCA & USB30_VCCB
X01 6/18 P69 DY the Keyboard back light parts, add R6916 for PU
X01 6/18 P61 Change TC6102 & TC6104 to 78.10710.52L; TC6103 to 79.10710.60L
X01 6/18 P20 Move WLAN from PCIE 4# to PCIE 3#
X01 6/18 P51 implement EMI team request item (6/15)
X01 6/18 P69 Remove R6916 Stuff R6912
X01 6/18 P69 Change Q6801~Q6805 & Q6902 to 84.00144.P11 M14 DIS
A A
Wistron Corporation
Title
Change History
A3
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03-05-1512:40:57 PM
5 4 03-05-151:22:21 PM 3 2 1
5 4 3 2 1
X02 7/30 P58 Add delay circuit at Audio Combo Jack
X02 7/30 update the connector symble, base on ME connector list 7/16
X02 7/30 P69 Remove the Key board back ligh circuit
D X02 7/31 Modify 0 ohm to short PAD D

X02 7/31 P71 Dummy DB1 circuit
X02 8/1 P58 Change HPMIC1 source and related circuit
X02 8/1 update power team request change 8/1
X02 8/6 P27 Move SERIES_ID to GPIO5
w
w
w
.ro
se
fix
.c
om
C C
B B
M14 DIS
A A
Wistron Corporation
Title
Change History
A3
http://vinafix.vn
03-05-1512:40:57 PM
03-05-151:22:21 PM
5 4 3 2 1
A00 9/4 change 0 ohm to short pad
A00 9/4 combine CM choke & 0 ohm
A00 9/4 change close gap & DB1 to symble with solder mask
D D
A00 9/4 27 change PCB version from SC to -1
A00 9/4 74 Replace EC7401 ~ EC7410 from 10p to 6.8p
A00 9/4 61 Remove CM Choke at USB3.0 side, dummy U6204 U6205
w
w
w
.ro
se
fix
.c
om
C C
B B
M14 DIS
A A
Wistron Corporation
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Change History
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Dell Inspiron 143421 Dne40cr 122041 A00 Schematics

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Dell Inspiron 143421 Dne40cr 122041 A00 Schematics

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5 4 3 2 1

Essentials Oak 14 Schematic

OPS: DISCRTE OPTIMUS installed Title

802.11 b/g/n Intel CPU_VCCSA

PS2 Flash ROM

Touch PAD SMBUS

Name Schematics Notes Power Plane

CPU Core Rail

PCI EXPRESS -- GRAPHICS

JTAG & BPM

R510 J61 XDP_BPM7 XDP_BPM7 71

H_CPUPW RGD PLT_RST# XDP_DBRESET#

EC501 EC502 EC503

reserve for EMI Request

DDR SYSTEM MEMORY B

M_A_DQ38 AT48 AK55 M_A_DQS#7 M_B_DQ39 BE53

RSVD45 N50 CFG6 PCIE Port Bifurcation Straps

PEG IO AND DDR IO

Refer to CPU EDS V.1.7.5

A13 VSS1 VSS91 AM38 BG17 VSS181 VSS250 M4

NCTF TEST PIN

M_A_DQ2 DQ1 DM3

M_A_DQ13 DQ12 VDDSPD

M_A_DQ14 DQ13 SA0_DIMA

M_A_DQ31 DQ30 VDD10

M_A_DQ38 DQ37 VDD17

M_A_DQ59 DQ58 VSS

M_A_DQ60 DQ59 VSS

M_A_DQ63 DQ62 VSS

SSID = MEMORY DM2

M_B_DQ3 DQ2 DM4

M_B_DQ9 DQ8 SCL PCH_SMBCLK 14,20,69

M_B_DQ10 DQ9 3D3V_S0

M_B_DQ24 DQ23 VDD3

M_B_DQ29 DQ28 VDD8

M_B_DQ33 DQ32 VDD12

M_B_DQ35 DQ34 VDD14

VTT2. M_B_DQ53 DQ52 VSS

M_B_DQ56 DQ55 VSS

SRN2K2J-1-GP 49 L_BKLT_CTRL P45 L_BKLTCTL SDVO_STALLN AM42

Digital Display Interface

Layout Note: R1702 DDPD_3P BG42

Place near PCH; 1KR2J-1-GP PANTHER-GP-NF

RSVD26 AY5 0 USB3.0 port2

A16 Swap Override jumper EC1802

Taipei Hsien 221, Taiwan, R.O.C.

Size Document Number Rev

DSW ODVREN RTC_AUX_S5

System Power Management

36 SYS_PW ROK P12 N3 PM_CLKRUN# 1 R1929 2 PM_CLKRUN#_EC 27

37 PM_DRAM_PW RGD B13 D10 PM_SLP_S5# 1 TP1902 TPAD14-OP-GP

SUS_PW R_ACK K16 F4 PM_SLP_S3# PM_SLP_S3# 27,36,37,47

27 PM_PW RBTN# PM_PW RBTN# E20 G10 PM_SLP_A# 1 TP1903

27,86 AC_PRESENT AC_PRESENT H20 G16 PM_SLP_SUS# 1 TP1904

27 BATLOW # BATLOW # E10 AP14 H_PM_SYNC H_PM_SYNC 5

PM_RI# A10 K14 PM_SLP_LAN# 1 TP1905

7 2 PM_RI# EC1907 EC1902 EC1903

R1909 1 2 100KR2J-1-GP AC_PRESENT

EC1904 EC1905 EC1906

R1908 2 1 10KR2J-3-GP PM_RSMRST#

reserve for EMI Request PCH (DM I/FDI/PM)

SSID = PCH S5 power rail CLKREQ#: 3D3V_S5

PCIECLKRQ[0]# SMB_CLK 4 1 RN2003