EE141

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Hw 6 posted.
Project phase 1 underway. Mail your group
composition (list of names) to
ee141@cory.eecs.berkeley.edu
No lecture on Fr
Make-up on Tu March 16 at 3:30pm

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Last lecture
Optimizing complex logic
Pass transistor logic
Todays lecture
Pass transistor logic continued
CMOS Layout
Pseudo-NMOS
Reading (Ch 6)

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Advantage: Full Swing

Restorer adds capacitance, takes away pull down current at X
Ratio problem

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Upper limit on restorer size

Pass-transistor pull-down
can have several transistors in
stack

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B
A
C

D
OUT = D + A (B + C)
A
D
B C

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Standard Cells
General purpose logic
Used to synthesize RTL/HDL
Same height, varying width
Datapath Cells
For regular, structured designs (arithmetic)
Includes some wiring in the cell

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Mirrored Cell

No routing VDD
channels
VDD

M2

M3
GND

Mirrored Cell GND

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N Well
VDD Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch =
repetitive distance between objects

Cell height is 12 Mn pitch

Out
In
2

Rails ~10
GND
Cell boundary

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With minimal VDD With silicided VDD

diffusion diffusion
routing

Out In Out
In

GND GND

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VDD 2-input NAND gate

A B

Out

GND

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Contains no dimensions
Represents relative positions of transistors

VDD VDD

Inverter
NAND2

Out Out

In A B
GND GND

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A C B A B C

VDD VDD

X X

GND GND

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Logic Graph X PUN

A
j C
B C

X i VDD
X = C (A + B)
C
i B j A

A B
PDN
A GND
B
C

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X
A B C
Has PDN and PUN C

X i VDD
B C A
Has PUN, but no PDN
B j A

GND

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X PUN
A C

B D D C

X VDD
X = (A+B)(C+D)

C D
B A

A B PDN
A GND
B
C
D

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One finger Two fingers (folded)

Less diffusion capacitance

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Goal: build gates faster/smaller than static

complementary CMOS
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Rising and falling delays arent the same

Calculate LE for the two edges separately

For tpLH:
Cgate = WCG Cinv = (3/2)WCG LELH =

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What is LE for tpHL?

Switch model would predict Reff = Rn||Rp
Would that give the right answer for LE?

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vo(t)/VDD

Rp=Rn

Rp=2Rn
Rp=4Rn
Rp=

t
Time constant is smaller, but it takes more time
to complete 50% VDD transient (arguably)
Rp actually takes some current away from
discharging C
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Think in terms of the current driving Cload

When you have a conflict between currents

Available current is the difference between the two
In pseudo-nMOS case:

(Works because Rp >> Rn for good noise margin)

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For tpHL (assuming Rsqp = 2Rsqn):

Rgate = Rn/(1-Rn/Rp) = 2Rn Rinv = Rn
Cgate = WCG Cinv = 3WCG
LEHL =
LE is lower than an inverter!
But have static power dissipation

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Differential Cascode Voltage Switch Logic (DCVSL)

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XOR/XNOR gate

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