K.L.E.

Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Laboratory Plan FMTC0302/Rev.1.1

Semester: III Year: 2015
Laboratory Title: Logic Design Lab Lab. Code: 10ESL38
Total Hours: 42 Duration of Exam: 3 Hrs
Total Exam Marks: 50 Total IA. Marks: 25
Lab. Plan Author: Prof. Kumarswamy S V Date: 1/8/2015
Checked By: Prof. Vinoda.S Date: 10/8/2015

Pre-requisites:
i. Types of Basic gates
ii. Types of Universal Gates
iii. Operation of Half Adder
iv. Operation of Full Adder
v. Construction and operation of Integrated circuits

Course Learning Outcomes-CLO

At the end of the course students will be able to:

i. Simplify and realize the given Boolean expression.

ii. Verify the truth table of decoder, encoder and multiplexer
iii. Verify the transition table of flip flops and shift registers.
iv. Design and implement counters using flip flops.

Course Articulation Matrix: Mapping of Course Learning Outcomes (CLO) Program

outcomes

Page 1 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Laboratory Title: Logic Design LAB Laboratory (Course) code:10ESL38

Semester: III Year: 2015
1 2 3 4 5

solutionsDesign/development of
Engineering knowledge

Problem analysis

complex problemsConduct investigations of

Modern tool usage

Course Learning Outcomes-CLO

Simplify and realize the given Boolean expression. M

Verify the truth table of decoder, encoder and multiplexer M

Verify the transition table of flip flops and shift registers. M M

Design and implement counters using flip flops. L M H

Degree of compliance L: Low M: Medium H: High

Program Outcome elements addressed in the Course and corresponding Performance

Indicators

Outcome Element:
PI Code PI

PI Code will be of the form CSPO number CSOE code - Performance Indicator number
Ex. 12a2 i.e.,
Life Long Learning - Recognition of the need for and an Ability to engage in lifelong learning - Ability to learn
independently

Page 2 of 28
 Course Code: 10EEL38 Course Title: LOGIC DESIGN LAB

K.L.E. Societys
L-T-P: 3-0-0 Teaching Hrs:52 USE Duration:03
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
IA Marks: 25 USE Marks:50 TotalEngg.
Marks: 75
Dept of Electrical and Electronics
Content
K.L.E.S.
Experiment Title Hrs
No

Simplification, realization of Boolean expressions using

1 logic gates/Universal gates. 03

Realization of Half/Full adder and Half/Full Subtractors

2 using logic gates. 03

(i) Realization of parallel adder/Subtractors using

7483 chip.
3 (ii) (ii) BCD to Excess-3 code conversion and vice 03
versa.

Course
Content Realization of Binary to Gray code conversion and vice
4 versa 03

5 MUX/DEMUX use of 74153, 74139 for arithmetic 03

circuits and code converter.
6 Realization of One/Two bit comparator and study of 7485 03
magnitude comparator.
Use of a) Decoder chip to drive LED display
7 b) Priority encoder. 03

Truth table verification of Flip-Flops: (i) JK Master slave

8 (ii) T type 03
(iii) D type.
Realization of 3 bit counters as a sequential circuit and
9 03
MOD N counter design

10 Shift left, Shift right, SIPO, SISO, PISO, PIPO operations 03

using 74S95.
11 Wiring and testing Ring counter/Johnson counter. 03
12 Wiring and testing of Sequence generator. 03

1. Materials and Resources Required:

Books/References:

1. Digital Logic Applications and principles- John

Yarbrough, Pearson Education.
2. Digital Principles and Design- Donald Givone, Tata
Mc Graw Hill
3. Digital logic and computer design- Morris Mano,
Prentice Hall

Manuals: College Manual Page 3 of 28

Others: Trainer Kit, ICs, Patch Chord and Power supply.
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Experiment wise Plan

Course Code and Title: 10ESL38 and Logic Design Lab

Exp Number and Title:01 - Verification of Gates Planned Hours:03
Hrs/Batch

Learning Outcomes:

At the end of the topic student should be able to:

Sr.No TLOs CLO BL PI Code

s
1 Verify the truth table of basic and universal gates. i L1 1c5
2 Realize the basic gates using universal gates. i L2 1c5
Simplification and realization of given Boolean
3 i L3 2b1
expression

Lab Schedule
Class No. Portion covered per batch
1. Verify the truth table of basic and universal gates.
2. Realize the basic gates using universal gates.
3. Simplification and realization of given Boolean expression

Page 4 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Review Questions

Sr.no Viva voce Questions TLO BL PI Code

1 Define cell. 1 L1 1b1

2 Difference between Minterm and Maxterm 2 L2 1b1

3 State the difference between SOP and POS. 1 L2 1b1

4 What is the need for simplification of

3 L2 1c1
Boolean expression?

5 Define truth table. 2 L1 1c1

6 In K-Map what type of coding is used? Why

3 L1 1c1
other codes are not used.

7 What is the difference between Prime

3 L2 1c1
implicants and essential prime implicants?

8 What is the need for simplification of

2 L1 1b1
Boolean expression?

9 Using K-map, to how many variables

3 L1 1b1
maximum can be simplified.

10 What are the different methods to obtain

3 L1 1b1
minimal expression?

Page 5 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Experiment wise Plan

Course Code and Title: 10ESL38 and Logic Design Lab

Exp Number and Title:02 - Realization of Half adder / Planned Hours:03
Full adder and Half subtractor Hrs/Batch
/
Full subtractor using logic
gates

Learning Outcomes:

At the end of the topic student should be able to:

Sr.No TLOs CLO BL PI Code

s
1 Verify the truth table of Half adder and Full adder. i L1 1c5
Realize the half adder and full adder using basic gates
2 i L2 1c5
and universal gates.
Verify and realize the truth table of Half subtractor and
3 i L1 1c5
Full subtractor.

Lab Schedule
Class No. Portion covered per batch
1. Verify the truth table of half adder and full adder using basic and universal
gates.
2. Realize the half adder and full adder using basic gates and universal gates.
3. Verify and realize truth table of half subtractor and full subtractor.

Page 6 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Review Questions

Sr.no Viva voce Questions TLO BL PI Code

1 What is a half adder? 1 L1 1b1

2 What is a full adder? 2 L2 1b1

3 What is a half subtractor? 1 L2 1b1

4 What is a full subtractor? 3 L2 1c1

5 What are the applications of adders and

2 L1 1c1
subtractor?

6 What is a ripple Adder? What are its

3 L1 1c1
disadvantages?

7 What is the difference between carry and

3 L2 1c1
overflow?

8 Define the function of half adder, Full adder,

2 L1 1b1
half Subtractor, and full Subtractor.

9 What is the need for complements? 3 L1 1b1

10 Classify the types of complements. 3 L1 1b1

Page 7 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Experiment wise Plan

Course Code and Title: 10ESL38 and Logic Design Lab

Exp Number and Title :03 - To realize a parallel Planned Hours:03
adder/subtractor using 7483 chip and To perform the Hrs/Batch
following code conversions
a. BCD to Excess-3 code
b. Excess-3 to BCD Code conversions

Learning Outcomes:

At the end of the topic student should be able to:

Sr.No TLOs CLO BL PI Code

s
Verify the truth table of adder and subtractor logic
1 i L1 1c5
circuit using IC-7483.
Realize and verify the truth table of BCD to Excess-3
2 i L2 1c5
using IC-7483.
Realize and verify the truth table of Exces-3 to BCD
3 i L3 2b1
using IC-7483.

Lab Schedule
Class No. Portion covered per batch
1. Verify the truth table of adder and subtractor logic circuit using IC-7483.
2. Realize and verify the truth table of BCD to Excess-3 using IC-7483.
3. Realize and verify the truth table of Exces-3 to BCD using IC-7483.

Page 8 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Review Questions

Sr.no Viva voce Questions TLO BL PI Code

1 Explain the need for code conversion. 1 L1 1b1

2 What are the steps involved to convert a

2 L2 1b1
binary number into a Excess-3 Code?

3 What are the steps involved to convert a

1 L2 1b1
Excess-3 number into a binary Code?

4 Is Excess-3 a weighted code? 3 L2 1c1

5 What is weighted code? Give examples 2 L1 1c1

6 What is Non weighted codes, give

3 L1 1c1
example?

7 What are reflected codes give examples? 3 L2 1c1

8 What are self-complementary codes give

2 L1 1b1
examples?

9 What is BCD code? 3 L1 1b1

10 Where are BCD codes used? 3 L1 1b1

Page 9 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Experiment wise Plan

Course Code and Title: 10ESL38 and Logic Design Lab

Exp Number and Title:04 - Binary TO Gray conversion Planned Hours:03
and vice versa. Hrs/Batch

Learning Outcomes:

At the end of the topic student should be able to:

Sr.No TLOs CLO BL PI Code

s
Verify the truth table of Binary to gray code converter
1 i L1 1c5
using only NAND ICS.
Verify the truth table of gray code to Binary converter
2 i L2 1c5
using only NAND ICS.
Implement and realize the truth table of Binary to gray
3 i L3 2b1
code converter and vice versa using only NAND ICS.

Lab Schedule
Class No. Portion covered per batch
1. Verify the truth table of Binary to gray code converter using only NAND ICS.
2. Verify the truth table of gray code to Binary converter using only NAND ICS.
3. Implement and realize the truth table of Binary to gray code converter and vice
versa using only NAND ICS.

Page 10 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Review Questions

Sr.no Viva voce Questions TLO BL PI Code

1 1. Explain the need for code conversion. 1 L1 1b1

2 2. What are the steps involved to convert

2 L2 1b1
a binary number into a Gray Code?

3 3. What are the steps involved to convert

1 L2 1b1
a Gray number into a binary Code?

4 4. Is gray code a weighted code? 3 L2 1c1

5 5. What is weighted code? Give examples 2 L1 1c1

6 6. What is Non weighted codes, give

3 L1 1c1
example?

7 7. What are reflected codes give

3 L2 1c1
examples?

8 8. What are self-complementary codes

2 L1 1b1
give examples?

9 9. What is BCD code? 3 L1 1b1

10 10. Where are BCD codes used? 3 L1 1b1

Experiment wise Plan

Course Code and Title: 10ESL38 and Logic Design Lab

Page 11 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Exp Number and Title:05 - Multiplexer and Demultiplexer Planned Hours:03

Hrs/Batch

Learning Outcomes:

At the end of the topic student should be able to:

Sr.No TLOs CLO BL PI Code

s
Design half adder and full adder using Mux and
1 i L1 1c5
De-MUX logic circuit.
Design half subtractor and full subtractor using Mux
2 i L2 1c5
and De-MUX logic circuit.
Realize the truth table of adder and subtractor logic
3 i L3 2b1
circuit using MUX and De-MUX.

Lab Schedule
Class No. Portion covered per batch
1. Design half adder and full adder using Mux and De-MUX logic circuit..
2. Design half subtractor and full subtractor using Mux and De-MUX logic
circuit.
3. Realize the truth table of adder and subtractor logic circuit using MUX and
De-
MUX.

Page 12 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Review Questions

Sr.no Viva voce Questions TLO BL PI Code

1 What is a multiplexer? 1 L1 1b1

2 What is a de-multiplexer? 2 L2 1b1

3 What are the applications of multiplexer and

1 L2 1b1
de-multiplexer?

4 What is the need for simplification of

3 L2 1c1
Boolean expression?

5 What is the difference between multiplexer

2 L1 1c1
& demultiplexer?

6 What is the need for select lines or control

3 L1 1c1
lines

7 Define the function of Multiplier. 3 L2 1c1

8 Derive the Boolean expression for

2 L1 1b1
multiplexer and de-multiplexer.

9 How to get higher order multiplexers? 3 L1 1b1

10 Implement an 8:1 mux using 4:1 muxes? 3 L1 1b1

Experiment wise Plan

Course Code and Title: 10ESL38 and Logic Design Lab

Page 13 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Exp Number and Title:06 - Magnitude Comparator Planned Hours:03

Hrs/Batch

Learning Outcomes:

At the end of the topic student should be able to:

Sr.No TLOs CLO BL PI Code

s
Verify the truth table of one bit comparator and two
1 i L1 1c5
comparator using basic gates.
Verify the truth table of one bit comparator, two and
2 i L2 1c5
four bit comparator using IC-7485.

Lab Schedule
Class No. Portion covered per batch
1. Verify the truth table of one bit comparator and two comparator using basic gates.
2. Verify the truth table of one bit comparator, two and four bit comparator using IC-
7485.
3. Realization of logic circuits constructed for magnitude comparator using basic
gates and Ic-7485.

Review Questions

Page 14 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Sr.no Viva voce Questions TLO BL PI Code

1 What is magnitude of a number? 1 L1 1b1

2 What is a comparator? 2 L2 1b1

3 What are the applications of comparator? 1 L2 1b1

4 Derive the Boolean expressions of one bit

3 L2 1c1
comparator and two bit comparators.

5 How do you realize a higher magnitude

2 L1 1c1
comparator using lower bit comparator

6 What is meant by cascading inputs? 3 L1 1c1

7 Define Logic 1 and logic 0? 3 L2 1c1

8 Let A be a 2 bit number and B be another 2

bit number, if A > B, then Cout = ------ and 2 L1 1b1
S

9 Is it possible to perform comparison of two,

3 L1 1b1
8-bit number using magnitude comparator?

10 Design an 8 bit comparator using a two

3 L1 1b1
numbers of IC 7485?

Experiment wise Plan

Course Code and Title: 10ESL38 and Logic Design Lab

Page 15 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Exp Number and Title:07 - BCD- to -7 segment Planned Hours:03

Decoder/driver and Priority Encoder Hrs/Batch

Learning Outcomes:

At the end of the topic student should be able to:

Sr.No TLOs CLO BL PI Code

s
Verify the truth table of seven segment decoder logic
1 i L1 1c5
circuit using IC-7447.
Verify the truth table of decimal to BCD priority
2 i L2 1c5
encoder using IC-74147
Verify the truth table of octal to binary logic circuit
3 i L3 2b1
using IC-74148.

Lab Schedule
Class No. Portion covered per batch
1. Verify the truth table of seven segment decoder logic circuit using IC-7447.
2. Verify the truth table of decimal to BCD priority encoder using IC-74147.
3. Verify the truth table of octal to binary logic circuit using IC-74148

Review Questions

Sr.no Viva voce Questions TLO BL PI Code

Page 16 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

1 What is an decoder ? 1 L1 1b1

2 What is an Encoder? 2 L2 1b1

3 What is priority encoder? 1 L2 1b1

4 What is the difference between decoder &

3 L2 1c1
encoder?

5 Draw the internal logic diagram of an LED. 2 L1 1c1

6 What is the difference between common

cathode configuration and common anode 3 L1 1c1
configuration?

7 Give the difference between LED and LCD. 3 L2 1c1

8 What is the role of an encoder in

2 L1 1b1
communication?

9 What is the advantage of using an encoder? 3 L1 1b1

10 What are the uses of validating outputs? 3 L1 1b1

Experiment wise Plan

Course Code and Title: 10ESL38 and Logic Design Lab

Exp Number and Title:08 - Master Slave J-K flip flops Planned Hours:03
Hrs/Batch

Page 17 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Learning Outcomes:

At the end of the topic student should be able to:

Sr.No TLOs CLO BL PI Code

s
Verify the truth table of master slave J-K flip flop
1 i L1 1c5
using NAND gates.
2 Verify the truth table of D flip flop using NAND gates. i L2 1c5

3 Verify the truth table of T flip flop using NAND gates. i L3 2b1

Lab Schedule
Class No. Portion covered per batch
1. Verify the truth table of master slave J-K flip flop using NAND gates.
2. Verify the truth table of D flip flop using NAND gates.
3. Verify the truth table of T flip flop using NAND gates.

Review Questions

Sr.no Viva voce Questions TLO BL PI Code

1 What is a Flip-flop? 1 L1 1b1

2 What is the difference between Flip-Flop & 2 L2 1b1

Page 18 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

latch?

3 How J-k flip-flop can be converted into T &

1 L2 1b1
D types?

4 What is the difference between Synchronous

3 L2 1c1
and Asynchronous clock pulse.

5 What are the applications of different Flip-

2 L1 1c1
Flops?

6 What is the advantage of Edge triggering

3 L1 1c1
over level triggering?

7 What is the relation between propagation

3 L2 1c1
delay & clock frequency of flip-flop?

8 What is race around in flip-flop & how to

2 L1 1b1
over come it?

9 Convert the J K Flip-Flop into D flip-flop

3 L1 1b1
and T flip-flop?

10 List the functions of asynchronous inputs? 3 L1 1b1

Experiment wise Plan

Course Code and Title: 10ESL38 and Logic Design Lab

Exp Number and Title:09 - 3 BIT SYNCHRONOUS Planned Hours:03
COUNTER Hrs/Batch

Learning Outcomes:

At the end of the topic student should be able to:

Sr.No TLOs CLO BL PI Code

s

Page 19 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

1 Design a MOD-5 and MOD-7 synchronous counter. i L1 1c5

2 Realize MOD-5 and MOD-7synchronous counter i L2 1c5

Lab Schedule
Class No. Portion covered per batch
1. Design MOD-5 synchronous counter.
2. Design MOD-7 synchronous counter.
3. Realize MOD-5 and MOD-7 synchronous counter.

Review Questions

Sr.no Viva voce Questions TLO BL PI Code

1 What are synchronous counters? 1 L1 1b1

2 How to design a Mod-N counter? 2 L2 1b1

3 How addition and subtraction is done in a

1 L2 1b1
parallel adder circuits.

4 Give the difference between sequential and

3 L2 1c1
combinational circuit.

Page 20 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

5 What is a shift register? 2 L1 1c1

6 What are the different modes of operation in

3 L1 1c1
a shift register?

7 What is the function of mode-control pin? 3 L2 1c1

8 What is an excitation table? 2 L1 1b1

9 Write the excitation table for D, T FF 3 L1 1b1

10 Design mod-5 synchronous counter using T

3 L1 1b1
Flip flop.

Experiment wise Plan

Course Code and Title: 10ESL38 and Logic Design Lab

Exp Number and Title:10 - Shift Register Planned Hours:03
Hrs/Batch

Learning Outcomes:

At the end of the topic student should be able to:

Sr.No TLOs CLO BL PI Code

s
1 Verify the truth table of shift registers i L1 1c5

Page 21 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Lab Schedule
Class No. Portion covered per batch
1. Develop the logic circuit for shift registers
2. Realize the SISO, SIPO, PIPO, PISO shift registers
3. Realize the Left shift and right shift registers.

Review Questions

Sr.no Viva voce Questions TLO BL PI Code

1 Define register. 1 L1 1b1

2 What do you mean by shift register? 2 L2 1b1

3 What are the applications of shift registers? 1 L2 1b1

4 What are PISO, SIPO, and SISO with respect

3 L2 1c1
to shift register?

5 Differentiate between serial data & parallel

2 L1 1c1
data with respect to shift register.

6 What is the significance of Mode control bit? 3 L1 1c1

Page 22 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Experiment wise Plan

Course Code and Title: 10ESL38 and Logic Design Lab

Exp Number and Title:11 - Ring counter & Johnson Planned Hours:03
Hrs/Batch
counter

Learning Outcomes:

At the end of the topic student should be able to:

Sr.No TLOs CLO BL PI Code

s
Verify the truth table of Ring counter and Johnson
1 i L1 1c5
counter.

Page 23 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Lab Schedule
Class No. Portion covered per batch
1. Develop the logic circuit for Ring counter and Johnson counter
2. Realize the Ring counter
3. Realize the Johnson counter

Review Questions

Sr.no Viva voce Questions TLO BL PI Code

1 Define counter 1 L1 1b1

2 List different types of counter 2 L2 1b1

3 What are the applications of counter? 1 L2 1b1

4 What do you mean by Ring counter? 3 L2 1c1

5 What do you mean by Johnson counter? 2 L1 1c1

Page 24 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Experiment wise Plan

Course Code and Title: 10ESL38 and Logic Design Lab

Exp Number and Title:12 - Sequence Generator Planned Hours:03
Hrs/Batch

Learning Outcomes:

At the end of the topic student should be able to:

Sr.No TLOs CLO BL PI Code

s
1 Design a sequence generator for a given sequence. i L1 1c5
2 Develop and Realize the sequence generator i L1 1c5

Page 25 of 28
 K.L.E. Societys
K.L.E. INSTITUTE OF TECHNOLOGY, HUBLI
Dept of Electrical and Electronics Engg.
K.L.E.S.

Lab Schedule
Class No. Portion covered per batch
1. Design a sequence generator for a given sequence.
2. Develop a logic circuit for a defined sequence.
3. Realize sequence generator.

Review Questions

Sr.no Viva voce Questions TLO BL PI Code

1 Define sequence generator. 1 L1 1b1

2 What are the applications of sequence

2 L2 1b1
generators?
3 What is the need of sequence generator? 1 L2 1b1

4 What is difference between sequence

3 L2 1c1
generator and signal generator?

5 Can a sequence generator replaced by a

2 L1 1c1
signal generator readily in the circuit?

Page 26 of 28
Evaluation:
Students Assessment (IA + USE)
Internal Assessments. Weightage in Marks
25
TEST FINAL
AVG GRADE
MARKS MARKS

Semester End Examination 50

Total Marks 75
Faculty In-charge. Head of Department

Date: