Fundamentals Of FPGA Design

Lab 1
Startup Design
Lab Objective
The objective of the labs today is to give you a basic understanding of FPGA design and enough
experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP
1800A Starter Kit. This first lab is intended to provide a simple, hands-on introduction to the ISE 10.1
tools and the Spartan-3A DSP 1800A Starter Kit. The design used in Lab 1 is a simple binary counter
which is displayed on the LEDs.

When this lab is complete, you will understand how to do the following:

• Create a new project in ISE 10.1

• Create a new HDL source

• Use a language template for a counter code example

• Add an existing source

• Synthesize and Implement the design

• Download the design to the Spartan-3A DSP FPGA and verify the operation of the design in
hardware

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Lab Setup
This lab will require the following software and hardware setups.

Software
The software used on the machines is as follows:

• WindowsXP Professional 32-bit with Service Pack 2

• Xilinx ISE Foundation 10.1 with Service Pack 2 and IP Update #2

Hardware
The machines contain 1 GB of system RAM. Xilinx recommends a minimum of 680 MB to complete an
XC3SD1800A design (see http://www.xilinx.com/ise/products/memory.htm).

The target hardware consists of the following:

• Xilinx Spartan-3A DSP 1800A Starter Kit with 5V AC/DC adapter

• Xilinx JTAG Cable

• Verify that the jumper settings are correct for this lab

o JP1 Vcc
o JP2 3.3V
o JP3 3.3V
o JP4 two vertical
o JP5 two vertical
o JP6 two vertical
o JP9 M1
o JP10 two vertical
o JP11 OFF

• A blue LED that will light up to indicate the FPGA is operational

• Eight green LEDs will display a simple binary counter

Lab Instruction Notes

Throughout the lab, a generalized instruction is given. If you’re comfortable completing the task based on
that instruction, feel free to do so. If not, step-by-step instructions are provided.

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Experiment 1: Create the ISE Project
ISE Project Navigator will be used to create a project for this lab. An HDL source is created, and a
constraint file (which contains the correct FPGA pin assignments for the design) is added. The design
itself is a simple binary counter.

Experiment 1 General Instruction:

Create a new ISE Project located at C:\training\FPGA_Intro\Lab1\<vlog or vhdl>, targeting a

XC3SD1800A-4FG676 device. Create a new HDL source and use a language template to bring in a 32-
bit counter with the upper 8-bits tied to output ports. Add an existing UCF source located in the
.\Lab1\Sources directory.

Experiment 1 Step-by-Step Instruction:

1. Launch ISE by selecting Start à Programs à Xilinx ISE Design Suite 10.1 à ISE à Project
Navigator.

By default ISE will open the last opened project. Regardless of what happens, select File à New
Project… Select your project location based on your language preference as shown below. Set the
Project Name to ISE_Proj. Then click Next >.

VHDL:

C:\training\FPGA_Intro\Lab1\vhdl

Figure 1 – Create New Project

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2. Choose the Spartan-3A DSP XC3SD1800A-4FG676 for the device. Select XST (VHDL/Verilog)
for the Synthesis Tool. Leave the Simulator selection as the ISE Simulator. Based on your
Preferred Language, choose VHDL . Click Next>.

Figure 2 – Device Properties

3. For the “Create New Source” Dialog: no new sources will be added at this time. Click Next >
again.

4. For the “Add Existing Source” Dialog: no new sources will be added at this time. Click Next >
again.

5. A summary is displayed. Click Finish.

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 Figure 3 – Project Summary

The new ISE Project is now displayed.

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 Figure 4 – Lab 1 ISE Project Created

6. In the Processes window, click the Create New Source.

7. Select VHDL Module and give the File name as FPGA_Intro. Click Next>.

Figure 5 – New Source: Select Source Type

8. Add the following ports.

Inputs: Clk_125mhz_pin, Rst_n_pin, Counter_ce_n_pin
Outputs: Led_pin (Bus, 7:0)

Take care to use the exact names as shown since this will need to match with the existing UCF that
will be added later. Note that the direction on Led must be manually changed to “out” and the Bus
box checked. Change the MSB to 7. Click Next>.

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 Figure 6 – New Source: Define Module Ports

9. A summary dialogue is shown. Click Finish.

Figure 7 – New Source: Summary

ISE generates the module, building a syntactically correct shell. The module is automatically added to
project and opened in the text editor. The VHDL version is shown below. Notice that ISE has created a
module header at the beginning of the file. This is a very good record-keeping practice to maintain.
During normal development, it is highly recommended that this section is fully populated. To save time,
this is not done today. The next step is to add functioning code to the design.

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 Figure 8 – Generated HDL from New Source Wizard

10. Click with the mouse to place the cursor in the functioning code area.

VHDL: Between begin and end Behavioral;

11. Open the Language Templates by selecting Edit à Language Templates or by clicking the
Language Template light bulb icon . Take a minute to browse through the many helpful
examples provided by the Language Templates.

12. In the Language Templates, browse to VHDL .Then expand Synthesis Constructs à Coding
Examples à Counters à Binary à Up Counters. Right-click on “/w CE and Sync Active Low
Reset” and select Use in file. The code is inserted into the module where your cursor was.

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 Figure 9 – Language Templates Up Counter

13. Edit the code to make the following substitutions:

Replace with This

<clock> Clk_125mhz_pin
<reset> Rst_n_pin
<clock_enable> Counter_ce_n_pin

Also make the following changes specific for your language choice.

VHDL:

• Replace “<count>” with “count”

• Add the following line between the Architecture and Begin statements
signal count : std_logic_vector (31 downto 0);

• Change “Counter_ce_n_pin='1'” to “Counter_ce_n_pin='0'”

• Add the following process in the body:

AssignLED_PROCESS:

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 process (count)
begin
Led_pin <= count (31 downto 24);
end process AssignLED_PROCESS;

14. Save the code. Select the FPGA_Intro module in the Sources window. Expand the Synthesize –
XST process and double-click Check Syntax. If you do not get the message “Process "Check
Syntax" completed successfully” in the Transcript window, go back and correct any syntax errors.

Figure 10 – Check Syntax

15. Click on Add Existing Source in the Processes window. Browse up two directories, then into the
Lab1\sources directory. Select and open FPGA_Intro.ucf. A source file status dialogue
opens. This will be explained later. Click OK.

Figure 11 – Source File Status

Notice that the UCF is now listed as a sub-module to our top-level HDL.

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 Figure 12 – UCF Added to Sources

Questions:
Open (double-click) the UCF and review the FPGA_Intro source HDL.

• How many I/Os does the design have? _________________________________

• How many flip-flops do you think the design will have? ______________

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Experiment 2: Synthesize and implement the design
The system clock runs at 125 MHz, and is used to clock the 32-bit counter. The eight bits in the upper
byte of this counter toggle slowly enough that they can be seen by the human eye. These eight bits are
mapped to the eight green LEDs on the board. Two push buttons are used to control the counter. The
Rst_n_pin button (SW4) is low when pushed. The Counter_ce_n_pin button (SW5) is high when pushed.
The code was designed in the previous step such that the counter would run normally when neither button
is pushed.

There are several steps involved to move from the source HDL to a working design in the FPGA. These
steps are called Synthesis, Implementation, Program File Generation, and Device Configuration. These
steps will be discussed in detail during today’s seminar. For this lab, we will use a “push-button”
approach to have ISE 10.1 automatically run these steps and configure the FPGA.

Experiment 2 General Instruction:

Synthesize and implement the design.

Experiment 2 Step-by-Step Instructions:

1. In the Project Navigator window, locate and click the Implement Top Module icon to launch
the synthesis and implementation processes.

Figure 13 – Implement Top Module

2. Review the results shown in the Design Summary.

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 Figure 14 – Synthesized and Implemented Project

Questions:
View the Design Summary in the Project Navigator

• Verify the number of I/Os and flip-flops. I/Os_________

Flip-flops________

• How many Global Clock Buffers (BUFGMUX) are in the design?_________________

• How did the BUFGMUXS get into the design?

_____________________________________________________________

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Experiment 3: Generate and download the configuration file
The next step after synthesis and implementation is to generate a configuration file. A configuration file
(also referred to as a bitstream) is a binary data stream that is loaded into the FPGA after power-up. Each
bit in the bitstream controls a small piece of logic or interconnect in the FPGA. Once the bitstream has
been loaded, the FPGA becomes operational.

For this lab, we will be using the JTAG port on the FPGA to load the bitstream. A JTAG download cable
is required. A tool call iMPACT is used to download the bitstream.

Experiment 3 General Instruction:

Generate and download the design to the FPGA via JTAG. Verify that the binary counter is correctly
displayed on the LEDs on the Spartan-3A DSP 1800A Starter Kit.

Experiment 3 Step-by-Step Instructions:

1. Turn on the power switch on the Spartan-3A DSP board.

2. We can accomplish both bitstream generation and launch the iMPACT tool with a single action.
Double-click the process Configure Target Device. After the bitstream is generated, the iMPACT
tool attempts to launch. Click OK to acknowledge the warning about the iMPACT project file.

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 Figure 15 – Generate Programming File & Launch iMPACT

Figure 16 – iMPACT Project File Warning

3. iMPACT provides a dialog which allows the user to select various configuration actions. The
default action is Configure devices using Boundary-Scan (JTAG), which is exactly what we intend
to do. Click Finish.

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 Figure 17 – iMPACT options dialog

4. iMPACT automatically scans the JTAG chain. After identifying the chain, a dialog appears
allowing you to assign a bitstream to the FPGA. Click the fpga_intro.bit file and assign it to the
FPGA by clicking Open.

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 Figure 18 – Assigning a bitstream to the Spartan-3A DSP FPGA

5. iMPACT displays the Programming Properties dialog. The default options are acceptable. Click
OK.

Figure 19 – Programming Properties

6. Single click the FPGA to select it. Note a new Configuration Operations tab appears in the
Processes window.

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 Figure 20 – Available Operations for FPGA configuration

7. To begin the download process, double-click the Program operation in Configuration Operations.

8. A progress bar appears briefly. When completed, a Programming Succeeded banner will display
in the iMPACT window. (See Figure 21). On the board, verify that a blue LED is illuminated.
This LED is controlled by the “Done” signal from the FPGA. Also, verify that green LEDs (D7 to
D14) are showing a binary counter pattern.

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 Figure 21 – Successful bitstream download

9. Before leaving iMPACT, we’ll set it up for automatic configuration the next time. Right-click on
the FPGA icon and select Set Target Device.

Figure 22 – Set iMPACT’s Target Device

10. Now close iMPACT by selecting File à Close. Save the project with the default name. With the
Target Device designated and the iMPACT project saved, clicking Configure Target Device will
automatically configure the FPGA without the dialogue the next time.

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Exploring Further
1. On the Spartan-3A DSP 1800A Starter Kit, locate the push-button labeled “SW4” to the left of the
counting LEDs. This button connects to the FPGA, and the design in the FPGA is interpreting this
signal as RST. Press the button and observe the operation of the counter.

2. Now locate push-button “SW5” to the right of the LEDs. This is the clock enable button. Press
the button and observe the operation of the counter.

3. Push-button SW2 is labeled “PROG”. This button is located slightly up and to the left of the blue
LED. Press PROG and observe the operation of the counter.

4. Notice that the counter is counting left-to-right. To change this to be right-to-left, simply modify
the order of the Led_pin bus in the UCF. Open the UCF. Hold down the <Alt> key and select the
bus member number for all eight elements. This takes advantage of the column edit mode of in
ISE Text Editor. Press the <Delete> key to erase the bus member numbers. Now position the
cursor at the first Led_pin and type 7 down to 0 to reverse the order of the bus. Repeat the
configuration process.

Figure 23 – Column Select in ISE Text Editor

Figure 24 – Led_pin Bus Reversed

Questions:
• What effect did the RST button have on the design in the FPGA?

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 _____________________________________________________________

• What effect did the Clock Enable button have on the design in the FPGA?

_____________________________________________________________

• What effect did the PROG button have on the design in the FPGA?

_____________________________________________________________

• After reversing the Led_pin bus, what was different when configuring the FPGA?

_____________________________________________________________

This concludes Lab 1. Please close ISE in preparation for Lab 2.

Answers to questions:
Experiment #1
• How many I/Os? 11: clock, reset, clock_enable, and 8-bit LED
• How many flip-flops? 32 for the counter

Experiment #2
• I/Os: 11 I/Os
• Flip-flops: 32 flops for the counter
• BUFGMUXs: 1 global clock buffer
• How did the BUFGMUX get into the design? Automatically added during synthesis

Experiment #3
• RST function? Resets the logic in the design. LEDs blank.
• Clock Enable function? Holds the counter at the current position.
• PROG function? Erases the design from the FPGA program memory.
• After reversing the Led_pin bus, what was different when configuring the FPGA? After
nd
setting the target device and saving the iMPACT project during the first run, the 2 configuration
operation happens automatically, without dialogue or user interaction.

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