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5 4 3 2 1

BOM
=47$=46$&596<67(0%/2&.',$*5$0 IV@ : iGPU
EV@ : dGPU
OP@ : Optimus
DO@ : Discrete only
SP@ : Special
SNP@: N13PGS/GL
IV@: UMA
DIS._eDP
D
GL@: N13PGL D

GS@: N13P/MGS

eDP Con. INT._eDP eDP Optimus : IV@ + EV@ + OP@


eDP
P22 N13P-GS VRAM Discrete only : EV@ + DO@
P20,P21
IVY Bridge N13P-GL
PEG N13M-GS
Dual Channel DDR III rPGA 989 TX/RX
DDRIII-SODIMM1 DIS._HDMI
1066/1333/1600 MHZ IMC GFX GPU
DDRIII-SODIMM2
P13, 14 Display
DIS._CRT
P3, 4, 5, 6
P15~P19
DIS._LVDS
FDI DMI Int. MIC
DMI(x4) USB-8 LVDS/CCD/MIC
Con. P22
FDI DMI
INT_LVDS

CLK
INT_CRT
CRT Con. P22
SATA 0 Display
SATA - HDD
C C
P25
SATA INT_HDMI
HDMI Con. P23
SATA - ODD SATA 1 USB3.0/2.0 USB3-2/USB2-1
P25
USB Charger USB3 Port
P29 MB side P29
Panther Point
PCH
SATA5
SATA MINI-SSD
USB-9
USB2-1,3 P7, 8, 9, 10, 11, 12 P24

PCI-E x1 PCIE-8

USB-10
MINI CARD
USB2-4 WLAN
Small Board Bluetooth Con. USB2.0 X'TAL P25
32.768KHz
CONNECTOR P31
RJ45
USB2-8 PCIE-3
RTL8411 P28
CCD(Camera) X'TAL 25MHz 10/100/1G
P31
P22
Cardreader Cardreader
P8 BATTERY RTC SPI SPI ROM CONN.
P28 P29
B P8 B
Azalia IHDA
CLK
LPC

EC
Int. MIC ALC271X-VB6
AUDIO CODEC P26 NPCE885L BQ24707A TPS51216 Discharger
P32 Batery Charger P33 +1.5V_SUS P37 Thermal Protection
P41
RT8223P RT8241A
3V/5V P33 VCCSA P38
MIC JACK
P27
ISL95836 TPS51728
HP Speaker CPU core/VAXG P35 VGPU Core P39
P27 P27
EM-6781-T3 Touch Pad Fan Driver
K/B Con. HALL SENSOR Board Con. (PWM Type)
TPS51219 MDV1660URH
P31 P22 P31 P31 +1.05V_PCH / +1.05V_VTT +1.5V_GFX/1.05V_GFX/3V_GFX
P36 P40

A A

Quanta Computer Inc.


PROJECT : ZQTA/ZQSA
Size Document Number Rev
1A
Block Diagram
Date: Friday, November 11, 2011 Sheet 1 of 44
5 4 3 2 1
1 2 3 4 5 6 7 8

VGA power up sequence

+3V
EC
MOSFET +3V_GFX
A A
dGPU_RWR_EN

VIN
+VGACORE
+1.05V
PWM
dGPU_VRON VGA_PG DGPU_PWROK
MOSFET +1.05V_GFX
MOSFET +1.5V_GFX
+1.5VSUS
VGA_VID

VGA_PG

MOSFET +1.8V_GFX
B B
+1.8V

Power States
CONTROL
POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN
SIGNAL
VIN +10V~+19V MAIN POWER ALWAYS ALWAYS

+3V_RTC +3V~+3.3V RTC POWER ALWAYS ALWAYS

+3VPCU +3.3V EC POWER ALWAYS ALWAYS


Thermal Follow Chart
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS

+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS

+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 NTC


Thermal
C +5V_S5 +5V USB POWER S5_ON S0-S5 C
Protection
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0

+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0

+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3 CPU 3V/5 V


H_PROCHOT# PM_THRMTRIP# SYS_SHDN#
CORE PWR
CPU WIRE-AND SYS PWR
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0 H/W Throttling

+VGFX_AXG variation Internal GPU POWER VRON S0

+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0


SML1ALERT#
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0
PCH FAN Driver FAN
+1.05V +1.05V PCH CORE POWER/IVY/SNB bridge VCCIO MAINON S0

+VCCSA +0.9V CPU POWER HWPG_VTT S0


SM-Bus
+VCC_CORE variation CPU CORE POWER VRON S0

LCDVCC +3.3V LCD POWER LVDS_VDDEN S0


EC
MAINON S0 CPUFAN#
D D

Quanta Computer Inc.


PROJECT : ZQTA/ZQSA
Size Document Number Rev
1A
PWR Status & GPU PWR CRL & THRM
Date: Friday, November 11, 2011 Sheet 2 of 44
1 2 3 4 5 6 7 8
5 4 3 2 1

For Sandy Bridge processor only implementation:


PROC_SELECT can be left NC. IVY Bridge Processor (CLK,MISC,JTAG) wo eDP and dGPU
IVY Bridge Processor (DMI,PEG,FDI) For IVY/Sandy processor compatibility:
Needs a pull-up resistor to PCH VccDFTERM rail (1.8V) through a 2.2 K5% pull-up resistor.
Connect DPLL_REF_SSCLK on Processor to GND through 1K 5% resistor.
U16A Connect to the DF_TVS of PCH though a 1K5% series resistor. U16B Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K 5% resistor
J22 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO J21
[7] DMI_TXN0 B27
DMI_RX#[0] PEG_RCOMPO
H22 PEG_COMP connect to PIN H22&J22 W:4mils/S:15mils/L: 500mils.
[7] DMI_TXN1 B25 DMI_RX#[1] PEG_COMP connect to PIN J21 W:12mils/S:15mils/L: 500mils. BCLK A28 CLK_CPU_BCLKP CLK_CPU_BCLKP [9]

MISC

CLOCKS
D H_SNB_IVB# D
[7] DMI_TXN2 A25 [8] H_SNB_IVB# C26 A27 CLK_CPU_BCLKN CLK_CPU_BCLKN [9]
DMI_RX#[2] PROC_SELECT# BCLK#
[7] DMI_TXN3 B24 K33 PEG_RX#0 [15]
DMI_RX#[3] PEG_RX#[0]
M35 PEG_RX#1 [15]
PEG_RX#[1] SKTOCC#
[7] DMI_TXP0 B28 DMI_RX[0] PEG_RX#[2] L34 PEG_RX#2 [15] TP45 AN34 SKTOCC# Ra
[7] DMI_TXP1 B26 DMI_RX[1] PEG_RX#[3] J35 PEG_RX#3 [15] DPLL_REF_CLK A16 CLK_DPLL_SSCLKP_R 3 4 CLK_DPLL_SSCLKP [9]

DMI
[7] DMI_TXP2 A24 J32 PEG_RX#4 [15] A15 CLK_DPLL_SSCLKN_R 1 2 CLK_DPLL_SSCLKN [9]
DMI_RX[2] PEG_RX#[4] DPLL_REF_CLK# R440 IV@0_4P2R
[7] DMI_TXP3 B23 H34 PEG_RX#5 [15]
DMI_RX[3] PEG_RX#[5]
H31 PEG_RX#6 [15] Rb
PEG_RX#[6] TP_CATERR# R442 DO@1K_4
[7] DMI_RXN0 G21 G33 PEG_RX#7 [15] TP11 AL33 +1.05V
DMI_TX#[0] PEG_RX#[7] CATERR#
[7] DMI_RXN1 E22 DMI_TX#[1] PEG_RX#[8] G30 PEG_RX#8 [15] Rc
F21 F35 PEG_RX#9 [15] R438 DO@1K_4
[7] DMI_RXN2 DMI_TX#[2] PEG_RX#[9]

THERMAL
[7] DMI_RXN3 D21 DMI_TX#[3] PEG_RX#[10] E34 PEG_RX#10 [15] EV UMA/OPT.
E32 AN33 R8 CPU_DRAMRST#
PEG_RX#[11] PEG_RX#11 [15] [32] EC_PECI PECI SM_DRAMRST# CPU_DRAMRST# [4]
[7] DMI_RXP0 G22 D33 PEG_RX#12 [15] Ra NA 0 ohm

DDR3
MISC
DMI_TX[0] PEG_RX#[12]
[7] DMI_RXP1 D22 D31 PEG_RX#13 [15]
DMI_TX[1] PEG_RX#[13]
F20 B33 PEG_RX#14 [15] Rb 1K NA

PCI EXPRESS* - GRAPHICS


[7] DMI_RXP2 DMI_TX[2] PEG_RX#[14] H_PROCHOT# H_PROCHOT#_R SM_RCOMP_0
C21 C32 PEG_RX#15 [15] [32,35] H_PROCHOT# R124 56_4 AL32 AK1 R173 140/F_4
[7] DMI_RXP3 DMI_TX[3] PEG_RX#[15] PROCHOT# SM_RCOMP[0] SM_RCOMP_1
A5 R458 25.5./F_4 Rc 1K NA
SM_RCOMP[1] SM_RCOMP_2 R460 200/F_4
J33 PEG_RX0 [15] A4
PEG_RX[0] SM_RCOMP[2]
PEG_RX[1] L35 PEG_RX1 [15]
K34 PM_THRMTRIP# AN32 CRB 1.0 : SM_RCOMP[2..0] W:20mils, S:15mils, L 500mils
PEG_RX[2] PEG_RX2 [15] [10] PM_THRMTRIP# THERMTRIP#
[7] FDI_TXN0 A21 FDI0_TX#[0] PEG_RX[3] H35 PEG_RX3 [15]
[7] FDI_TXN1 H19 FDI0_TX#[1] PEG_RX[4] H32 PEG_RX4 [15]
[7] FDI_TXN2 E19 G34 PEG_RX5 [15]
FDI0_TX#[2] PEG_RX[5]
F18 G31
Intel(R) FDI

[7] FDI_TXN3 FDI0_TX#[3] PEG_RX[6] PEG_RX6 [15]


B21 F33 Intel recommended UNCOREPWRGOOD AP29 XDP_PRDY#
[7] FDI_TXN4 FDI1_TX#[0] PEG_RX[7] PEG_RX7 [15] PRDY# TP53
C20 F30 PEG_RX8 [15] AP27 XDP_PREQ#
[7] FDI_TXN5 FDI1_TX#[1] PEG_RX[8] routing on one layer PREQ# TP18
[7] FDI_TXN6 D18 FDI1_TX#[2] PEG_RX[9] E35 PEG_RX9 [15]
E17 E33 PEG_RX10 [15] AR26 XDP_TCLK
[7] FDI_TXN7 FDI1_TX#[3] PEG_RX[10] TCK TP20

PWR MANAGEMENT
F32 AR27 PCH_JTAG_TMS

JTAG & BPM


PEG_RX[11] PEG_RX11 [15] TMS TP19
D34 PM_SYNC AM34 AP30 XDP_TRST#
PEG_RX[12] PEG_RX12 [15] [7] PM_SYNC PM_SYNC TRST# TP12
[7] FDI_TXP0 A22 FDI0_TX[0] PEG_RX[13] E31 PEG_RX13 [15]
G19 C33 apply C5205 for nosie C165 0.1u/10V_4 AR28 PCH_JTAG_TDI
[7] FDI_TXP1 FDI0_TX[1] PEG_RX[14] PEG_RX14 [15] TDI TP56
E20 B32 PEG_RX15 [15] AP26 PCH_JTAG_TDO
[7] FDI_TXP2 FDI0_TX[2] PEG_RX[15] H_PWRGOOD TDO
[7] FDI_TXP3 G18 [10] H_PWRGOOD AP33
FDI0_TX[3] R_PEG_TX#0 C395 EV@0.22u/6.3V_4 UNCOREPWRGOOD
[7] FDI_TXP4 B20 FDI1_TX[0] PEG_TX#[0] M29 PEG_TX#0 [15]
C19 M32 R_PEG_TX#1 C400 EV@0.22u/6.3V_4 PEG_TX#1 [15] R116 10K_4
[7] FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
D19 M31 R_PEG_TX#2 C402 EV@0.22u/6.3V_4 AL35
C [7] FDI_TXP6 FDI1_TX[2] PEG_TX#[2] PEG_TX#2 [15] DBR# XDP_DBRST# [7] C
F17 L32 R_PEG_TX#3 C405 EV@0.22u/6.3V_4 PEG_TX#3 [15] PM_DRAM_PWRGD_R V8
[7] FDI_TXP7 FDI1_TX[3] PEG_TX#[3] R_PEG_TX#4 SM_DRAMPWROK
L29 C407 EV@0.22u/6.3V_4 PEG_TX#4 [15]
PEG_TX#[4] R_PEG_TX#5 C413 EV@0.22u/6.3V_4 XDP_BPM0
[7] FDI_FSYNC0 J18 K31 PEG_TX#5 [15] AT28 TP54
FDI0_FSYNC PEG_TX#[5] R_PEG_TX#6 C414 EV@0.22u/6.3V_4 +1.05V BPM#[0] XDP_BPM1
[7] FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#[6] K28 PEG_TX#6 [15] BPM#[1] AR29 TP55
J30 R_PEG_TX#7 C418 EV@0.22u/6.3V_4 AR30 XDP_BPM2
PEG_TX#[7] PEG_TX#7 [15] BPM#[2] TP51
H20 J28 R_PEG_TX#8 C421 EV@0.22u/6.3V_4 R107 75_4 R113 43_4 CPU_PLTRST#_R AR33 AT30 XDP_BPM3
[7] FDI_INT FDI_INT PEG_TX#[8]
PEG_TX#[9] H29 R_PEG_TX#9 C424 EV@0.22u/6.3V_4
PEG_TX#8 [15]
PEG_TX#9 [15]
RESET# BPM#[3]
BPM#[4] AP32 XDP_BPM4 TP52
TP49
For XDP
J19 G27 R_PEG_TX#10 C425 EV@0.22u/6.3V_4 AR31 XDP_BPM5
[7] FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10] PEG_TX#10 [15] BPM#[5] TP47
H17 E29 R_PEG_TX#11 C430 EV@0.22u/6.3V_4 PEG_TX#11 [15] AT31 XDP_BPM6
[7] FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] BPM#[6] TP50
F27 R_PEG_TX#12 C431 EV@0.22u/6.3V_4 CPU_PLTRST# AR32 XDP_BPM7
PEG_TX#[12] PEG_TX#12 [15] BPM#[7] TP46
D28 R_PEG_TX#13 C434 EV@0.22u/6.3V_4 PEG_TX#13 [15] R115
PEG_TX#[13] R_PEG_TX#14 C439 EV@0.22u/6.3V_4
PEG_TX#[14] F26 PEG_TX#14 [15]
E25 R_PEG_TX#15 C440 EV@0.22u/6.3V_4 *750/F_4
PEG_TX#[15] PEG_TX#15 [15]
A18
eDP_COMP eDP_COMPIO R_PEG_TX0 C398 EV@0.22u/6.3V_4 Ivy Bridge_rPGA_2DPC_Rev0p61
A17 eDP_ICOMPO PEG_TX[0] M28 PEG_TX0 [15]
B16 M33 R_PEG_TX1 C401 EV@0.22u/6.3V_4 PEG_TX1 [15]
[22] INT_eDP_HPD_Q eDP_HPD PEG_TX[1] R_PEG_TX2
M30 C404 EV@0.22u/6.3V_4 PEG_TX2 [15]
PEG_TX[2] R_PEG_TX3 C406 EV@0.22u/6.3V_4
PEG_TX[3] L31 PEG_TX3 [15]
C15 L28 R_PEG_TX4 C408 EV@0.22u/6.3V_4 PEG_TX4 [15]
[22] EDP-AUX+ eDP_AUX PEG_TX[4]
D15 K30 R_PEG_TX5 C409 EV@0.22u/6.3V_4
[22] EDP-AUX- eDP_AUX# PEG_TX[5] PEG_TX5 [15]
eDP

K27 R_PEG_TX6 C417 EV@0.22u/6.3V_4 PEG_TX6 [15]


PEG_TX[6] R_PEG_TX7 C419 EV@0.22u/6.3V_4 R114 *1.5K/F_4
J29 PEG_TX7 [15] [9] PCI_PLTRST#
PEG_TX[7] R_PEG_TX8 C420 EV@0.22u/6.3V_4
[22] EDP-ML0+ C17 J27 PEG_TX8 [15]
eDP_TX[0] PEG_TX[8] R_PEG_TX9 C422 EV@0.22u/6.3V_4
F16 H28 PEG_TX9 [15] +3V
eDP_TX[1] PEG_TX[9] R_PEG_TX10 C427 EV@0.22u/6.3V_4
TP59 C16 G28 PEG_TX10 [15]
eDP_TX[2] PEG_TX[10] R_PEG_TX11 C428 EV@0.22u/6.3V_4
G15 E28 PEG_TX11 [15]
eDP_TX[3] PEG_TX[11] R_PEG_TX12 C433 EV@0.22u/6.3V_4 C167
PEG_TX[12] F28 PEG_TX12 [15] CRB 1.0 : change to +3V(S0)
C18 D27 R_PEG_TX13 C436 EV@0.22u/6.3V_4 U3 0.1u/10V_4
[22] EDP-ML0- eDP_TX#[0] PEG_TX[13] PEG_TX13 [15]
E16 E26 R_PEG_TX14 C437 EV@0.22u/6.3V_4 PEG_TX14 [15] 1 5
eDP_TX#[1] PEG_TX[14] R_PEG_TX15 C444 EV@0.22u/6.3V_4 NC VCC
TP58 D16 eDP_TX#[2] PEG_TX[15] D25 PEG_TX15 [15]
F15 2 +3V_S5
eDP_TX#[3] IN
3 4 CPU_PLTRST#
Ivy Bridge_rPGA_2DPC_Rev0p61 GND OUT
74LVC1G07GW +1.5V_CPU
HPD disable DG 1.0 : C516
The recommended AC cap value is changed to 220nF for compatibility with 0.1u/10V_4
B This signal can be left as no PCIe Gen3 on future platforms. B

connect if entire eDP interface For Gen2 only designs, it is acceptable to continue to use the 100nF capacitor. R461

5
is disabled. U18 200/F_4
[7] SYS_PWROK 2
4 PM_DRAM_PWRGD_Q R459 130/F_4 PM_DRAM_PWRGD_R
[7] PM_DRAM_PWRGD 1

74AHC1G09

3
R462 *39_4 3 1

Q30 *2N7002K

2
MAINON_ON_G
MAINON_ON_G [5,41]

FDI Disabling (Discrete Only) DP & PEG Compensation


+1.05V

3
+1.05V Processor pull-up(CPU)
9/26 add [7,35] IMVP_PWRGD 2 Q4 [5,7,8,9,11,22,32,35,36,40,41] +1.05V
[7,8,9,10,11,13,14,19,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41] +3V
FDV301N
+1.05V Routed within 500 mils +1.05V

1
FDI_INT

R444
R446
DO@0_4
DO@0_4
FDI_FSYNC0
FDI_FSYNC1
Routed within 25 mils R439 24.9/F_4 PEG_COMP H_PROCHOT#
PCH_JTAG_TDO
R122
R134
62_4
51_4
R86
1K_4
R443 DO@0_4 FDI_LSYNC0 PEG_ICOMPI and RCOMPO signals should PCH_JTAG_TMS R135 51_4
A FDI_LSYNC1 R433 24.9/F_4 eDP_COMP be routed within 500 mils PCH_JTAG_TDI R430 51_4 9/27 modify A
XDP_PREQ# R132 *51_4
typical impedance = 43 mohms

2
FDI_FSYNC can gang eDP_COMPIO and ICOMPO signals should XDP_TCLK R137 51_4
R441 all these 4 be shorted near balls and routed with XDP_TRST# R128 51_4 Q5
R447 PEG_ICOMPO signals should PM_THRMTRIP# 1 3 MMBT3904 SYS_SHDN# [34,41]
DO@1K/F_4 DO@1K/F_4 signals together typical impedance <25 mohms
and tie them with be routed within 500 mils
only one 1K typical impedance = 14.5 mohms
resistor to GND
(DG V0.5 Ch2.2.9).
Quanta Computer Inc.
PROJECT : ZQTA/ZQSA
Size Document Number Rev
IVY Bridge 1/4 1A

Date: Friday, November 11, 2011 Sheet 3 of 44


5 4 3 2 1
5 4 3 2 1

IVY Bridge Processor (DDR3)

U16C U16D

[13] M_A_DQ[63:0] SA_CLK[0] AB6 M_A_CLK0 [13] [14] M_B_DQ[63:0] SB_CLK[0] AE2 M_B_CLK0 [14]
AA6 M_A_CLK0# [13] AD2 M_B_CLK0# [14]
D M_A_DQ0 SA_CLK#[0] M_B_DQ0 SB_CLK#[0] D
C5 V9 M_A_CKE0 [13] C9 R9 M_B_CKE0 [14]
M_A_DQ1 SA_DQ[0] SA_CKE[0] M_B_DQ1 SB_DQ[0] SB_CKE[0]
D5 A7
M_A_DQ2 SA_DQ[1] M_B_DQ2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
M_A_DQ3 D2 M_B_DQ3 C8
M_A_DQ4 SA_DQ[3] M_B_DQ4 SB_DQ[3]
D6 AA5 M_A_CLK1 [13] A9 AE1 M_B_CLK1 [14]
M_A_DQ5 SA_DQ[4] SA_CLK[1] M_B_DQ5 SB_DQ[4] SB_CLK[1]
C6 SA_DQ[5] SA_CLK#[1] AB5 M_A_CLK1# [13] A8 SB_DQ[5] SB_CLK#[1] AD1 M_B_CLK1# [14]
M_A_DQ6 C2 V10 M_B_DQ6 D9 R10
SA_DQ[6] SA_CKE[1] M_A_CKE1 [13] SB_DQ[6] SB_CKE[1] M_B_CKE1 [14]
M_A_DQ7 C3 M_B_DQ7 D8
M_A_DQ8 SA_DQ[7] M_B_DQ8 SB_DQ[7]
F10 G4
M_A_DQ9 SA_DQ[8] M_B_DQ9 SB_DQ[8]
F8 F4
M_A_DQ10 SA_DQ[9] M_B_DQ10 SB_DQ[9]
G10 AB4 F1 AB2
M_A_DQ11 SA_DQ[10] SA_CLK[2] M_B_DQ11 SB_DQ[10] SB_CLK[2]
G9 SA_DQ[11] SA_CLK#[2] AA4 G1 SB_DQ[11] SB_CLK#[2] AA2
M_A_DQ12 F9 W9 M_B_DQ12 G5 T9
M_A_DQ13 SA_DQ[12] SA_CKE[2] M_B_DQ13 SB_DQ[12] SB_CKE[2]
F7 SA_DQ[13] F5 SB_DQ[13]
M_A_DQ14 G8 M_B_DQ14 F2
M_A_DQ15 SA_DQ[14] M_B_DQ15 SB_DQ[14]
G7 SA_DQ[15] G2 SB_DQ[15]
M_A_DQ16 K4 AB3 M_B_DQ16 J7 AA1
M_A_DQ17 SA_DQ[16] SA_CLK[3] M_B_DQ17 SB_DQ[16] SB_CLK[3]
K5 SA_DQ[17] SA_CLK#[3] AA3 J8 SB_DQ[17] SB_CLK#[3] AB1
M_A_DQ18 K1 W10 M_B_DQ18 K10 T10
M_A_DQ19 SA_DQ[18] SA_CKE[3] M_B_DQ19 SB_DQ[18] SB_CKE[3]
J1 SA_DQ[19] K9 SB_DQ[19]
M_A_DQ20 J5 M_B_DQ20 J9
M_A_DQ21 SA_DQ[20] M_B_DQ21 SB_DQ[20]
J4 SA_DQ[21] J10 SB_DQ[21]
M_A_DQ22 J2 AK3 M_B_DQ22 K8 AD3
SA_DQ[22] SA_CS#[0] M_A_CS#0 [13] SB_DQ[22] SB_CS#[0] M_B_CS#0 [14]
M_A_DQ23 K2 AL3 M_B_DQ23 K7 AE3
SA_DQ[23] SA_CS#[1] M_A_CS#1 [13] SB_DQ[23] SB_CS#[1] M_B_CS#1 [14]
M_A_DQ24 M8 AG1 M_B_DQ24 M5 AD6
M_A_DQ25 SA_DQ[24] SA_CS#[2] M_B_DQ25 SB_DQ[24] SB_CS#[2]
N10 SA_DQ[25] SA_CS#[3] AH1 N4 SB_DQ[25] SB_CS#[3] AE6
M_A_DQ26 N8 M_B_DQ26 N2
M_A_DQ27 SA_DQ[26] M_B_DQ27 SB_DQ[26]
N7 N1
M_A_DQ28 SA_DQ[27] M_B_DQ28 SB_DQ[27]
M10 M4
M_A_DQ29 SA_DQ[28] M_B_DQ29 SB_DQ[28]
M9 SA_DQ[29] SA_ODT[0] AH3 M_A_ODT0 [13] N5 SB_DQ[29] SB_ODT[0] AE4 M_B_ODT0 [14]

DDR SYSTEM MEMORY B


M_A_DQ30 N9 AG3 M_B_DQ30 M2 AD4
DDR SYSTEM MEMORY A

SA_DQ[30] SA_ODT[1] M_A_ODT1 [13] SB_DQ[30] SB_ODT[1] M_B_ODT1 [14]


M_A_DQ31 M7 AG2 M_B_DQ31 M1 AD5
C M_A_DQ32 SA_DQ[31] SA_ODT[2] M_B_DQ32 SB_DQ[31] SB_ODT[2] C
AG6 SA_DQ[32] SA_ODT[3] AH2 AM5 SB_DQ[32] SB_ODT[3] AE5
M_A_DQ33 AG5 M_B_DQ33 AM6
M_A_DQ34 SA_DQ[33] M_B_DQ34 SB_DQ[33]
AK6 SA_DQ[34] AR3 SB_DQ[34]
M_A_DQ35 AK5 M_B_DQ35 AP3
M_A_DQ36 SA_DQ[35] M_B_DQ36 SB_DQ[35]
AH5 SA_DQ[36] AN3 SB_DQ[36]
M_A_DQ37 AH6 C4 M_A_DQS#0 M_B_DQ37 AN2 D7 M_B_DQS#0
M_A_DQ38 SA_DQ[37] SA_DQS#[0] M_A_DQS#1 M_B_DQ38 SB_DQ[37] SB_DQS#[0] M_B_DQS#1
AJ5 SA_DQ[38] SA_DQS#[1] G6 AN1 SB_DQ[38] SB_DQS#[1] F3
M_A_DQ39 AJ6 J3 M_A_DQS#2 M_B_DQ39 AP2 K6 M_B_DQS#2
M_A_DQ40 SA_DQ[39] SA_DQS#[2] M_A_DQS#3 M_B_DQ40 SB_DQ[39] SB_DQS#[2] M_B_DQS#3
AJ8 M6 AP5 N3
M_A_DQ41 SA_DQ[40] SA_DQS#[3] M_A_DQS#4 M_B_DQ41 SB_DQ[40] SB_DQS#[3] M_B_DQS#4
AK8 AL6 AN9 AN5
M_A_DQ42 SA_DQ[41] SA_DQS#[4] M_A_DQS#5 M_B_DQ42 SB_DQ[41] SB_DQS#[4] M_B_DQS#5
AJ9 AM8 AT5 AP9
M_A_DQ43 SA_DQ[42] SA_DQS#[5] M_A_DQS#6 M_B_DQ43 SB_DQ[42] SB_DQS#[5] M_B_DQS#6
AK9 AR12 AT6 AK12
M_A_DQ44 SA_DQ[43] SA_DQS#[6] M_A_DQS#7 M_B_DQ44 SB_DQ[43] SB_DQS#[6] M_B_DQS#7
AH8 SA_DQ[44] SA_DQS#[7] AM15 M_A_DQS#[7:0] [13] AP6 SB_DQ[44] SB_DQS#[7] AP15 M_B_DQS#[7:0] [14]
M_A_DQ45 AH9 M_B_DQ45 AN8
M_A_DQ46 SA_DQ[45] M_B_DQ46 SB_DQ[45]
AL9 SA_DQ[46] AR6 SB_DQ[46]
M_A_DQ47 AL8 M_B_DQ47 AR5
M_A_DQ48 SA_DQ[47] M_B_DQ48 SB_DQ[47]
AP11 AR9
M_A_DQ49 SA_DQ[48] M_A_DQS0 M_B_DQ49 SB_DQ[48] M_B_DQS0
AN11 D4 AJ11 C7
M_A_DQ50 SA_DQ[49] SA_DQS[0] M_A_DQS1 M_B_DQ50 SB_DQ[49] SB_DQS[0] M_B_DQS1
AL12 F6 AT8 G3
M_A_DQ51 SA_DQ[50] SA_DQS[1] M_A_DQS2 M_B_DQ51 SB_DQ[50] SB_DQS[1] M_B_DQS2
AM12 K3 AT9 J6
M_A_DQ52 SA_DQ[51] SA_DQS[2] M_A_DQS3 M_B_DQ52 SB_DQ[51] SB_DQS[2] M_B_DQS3
AM11 N6 AH11 M3
M_A_DQ53 SA_DQ[52] SA_DQS[3] M_A_DQS4 M_B_DQ53 SB_DQ[52] SB_DQS[3] M_B_DQS4
AL11 AL5 AR8 AN6
M_A_DQ54 SA_DQ[53] SA_DQS[4] M_A_DQS5 M_B_DQ54 SB_DQ[53] SB_DQS[4] M_B_DQS5
AP12 SA_DQ[54] SA_DQS[5] AM9 AJ12 SB_DQ[54] SB_DQS[5] AP8
M_A_DQ55 AN12 AR11 M_A_DQS6 M_B_DQ55 AH12 AK11 M_B_DQS6
M_A_DQ56 SA_DQ[55] SA_DQS[6] M_A_DQS7 M_B_DQ56 SB_DQ[55] SB_DQS[6] M_B_DQS7
AJ14 AM14 M_A_DQS[7:0] [13] AT11 AP14 M_B_DQS[7:0] [14]
M_A_DQ57 SA_DQ[56] SA_DQS[7] M_B_DQ57 SB_DQ[56] SB_DQS[7]
AH14 SA_DQ[57] AN14 SB_DQ[57]
M_A_DQ58 AL15 M_B_DQ58 AR14
M_A_DQ59 SA_DQ[58] M_B_DQ59 SB_DQ[58]
AK15 AT14
M_A_DQ60 SA_DQ[59] M_B_DQ60 SB_DQ[59]
AL14 AT12
M_A_DQ61 SA_DQ[60] M_A_A0 M_B_DQ61 SB_DQ[60] M_B_A0
AK14 AD10 AN15 AA8
M_A_DQ62 SA_DQ[61] SA_MA[0] M_A_A1 M_B_DQ62 SB_DQ[61] SB_MA[0] M_B_A1
AJ15 W1 AR15 T7
M_A_DQ63 SA_DQ[62] SA_MA[1] M_A_A2 M_B_DQ63 SB_DQ[62] SB_MA[1] M_B_A2
AH15 SA_DQ[63] SA_MA[2] W2 AT15 SB_DQ[63] SB_MA[2] R7
B M_A_A3 M_B_A3 B
W7 T6
SA_MA[3] M_A_A4 SB_MA[3] M_B_A4
V3 T2
SA_MA[4] M_A_A5 SB_MA[4] M_B_A5
V2 T4
SA_MA[5] M_A_A6 SB_MA[5] M_B_A6
SA_MA[6] W3 SB_MA[6] T3
[13] M_A_BS#0 AE10 W6 M_A_A7 [14] M_B_BS#0 AA9 R2 M_B_A7
SA_BS[0] SA_MA[7] M_A_A8 SB_BS[0] SB_MA[7] M_B_A8
[13] M_A_BS#1 AF10 SA_BS[1] SA_MA[8] V1 [14] M_B_BS#1 AA7 SB_BS[1] SB_MA[8] T5
[13] M_A_BS#2 V6 W5 M_A_A9 [14] M_B_BS#2 R6 R3 M_B_A9
SA_BS[2] SA_MA[9] M_A_A10 SB_BS[2] SB_MA[9] M_B_A10
AD8 AB7
SA_MA[10] M_A_A11 SB_MA[10] M_B_A11
SA_MA[11] V4 SB_MA[11] R1
W4 M_A_A12 T1 M_B_A12
SA_MA[12] M_A_A13 SB_MA[12] M_B_A13
[13] M_A_CAS# AE8 AF8 [14] M_B_CAS# AA10 AB10
SA_CAS# SA_MA[13] M_A_A14 SB_CAS# SB_MA[13] M_B_A14
[13] M_A_RAS# AD9 V5 [14] M_B_RAS# AB8 R5
SA_RAS# SA_MA[14] M_A_A15 SB_RAS# SB_MA[14] M_B_A15
[13] M_A_WE# AF9 V7 M_A_A[15:0] [13] [14] M_B_WE# AB9 R4 M_B_A[15:0] [14]
SA_WE# SA_MA[15] SB_WE# SB_MA[15]

Ivy Bridge_rPGA_2DPC_Rev0p61 Ivy Bridge_rPGA_2DPC_Rev0p61

+1.5VSUS

R503
1K/F_4
A Q36 2N7002K A
R502 1K/F_4 CD_DRAMRST# 3 1
[13,14] DDR3_DRAMRST# CPU_DRAMRST# [3]
2

[9,13,14] DRAMRST_CNTRL_PCH
R500
C547 4.99K/F_4 Quanta Computer Inc.
0.047u/16V_4
PROJECT : ZQTA/ZQSA
Size Document Number Rev
IVY Bridge 2/4 1A

Date: Friday, November 11, 2011 Sheet 4 of 44


5 4 3 2 1
5 4 3 2 1

[3,7,8,9,11,22,32,35,36,40,41] +1.05V
[35] +VCC_CORE
[8,10,11,41] +1.8V CPU VTT
[35] +VCC_GFX
IVY 45W:8.5A
CPU VGT IVY SPEC IVY Bridge Processor (GRAPHIC POWER)
[3] +1.5V_CPU IVY Processor (POWER) Cose down IVY 45W:TDC 38A Cose down 22uF_8 x2 Socket TOP cavity
+VDDR_REF_CPU SNB : Spec 330uF x1 330uF x1 22uF_8 x2 Socket BOT cavity
330uF/6mohm x 2
Spec 22uF_8 x4 Socket TOP edge
[38] +VCCSA

22uF x 12
10uF x 10
22uF x 2 470uF/4mohm x 2 22uF x 4
22uF x 12 10uF x 10
22uF_8 x4 Socket BOT edge
470uF_7343 x2 U16G
POWER 0929 change value by CRB
+1.05V
CPU Core Power 22uF x 7 (Non-stuff) reserved x 4
POWER R81 IV@10/F_4 +VCC_GFX

SENSE
LINES
IVY 45W:TDC 52A U16F +VCC_GFX AT24 AK35 VCC_AXG_SENSE [35]
VAXG1 VAXG_SENSE
AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE [35]
IVY SPEC +VCC_CORE AT21 R98 IV@10/F_4
+ C502 + C233 + C514 VAXG3
D AT20 D
22uF_8 x8 Socket TOP cavity + C511 + C213 AT18
VAXG4
330u/2V_7343 330u/2V_7343 IV@330u/2V_7343 *IV@330u/2V_7343 VAXG5
22uF_8 x10 Socket BOT cavity AG35
VCC1
AT17
VAXG6
AG34 AH13 IV@330u/2V_7343 AR24
22uF_8 x8 Socket TOP edge AG33
VCC2 VCCIO1
AH10 AR23
VAXG7
VCC3 VCCIO2 VAXG8
470uF_7343 x4 AG32 VCC4 VCCIO3 AG10 AR21 VAXG9 10 mil For M3 solution
AG31 AC10 AR20
total : 10uF x 10 , RSVD x 1 AG30
VCC5 VCCIO4
Y10 AR18
VAXG10
AL1 +VDDR_REF_CPU +VDDR_REF_CPU
need Rb4, Rd1
VCC6 VCCIO5 VAXG11 SM_VREF
total : 22uF x 16 , RSVD x 3 AG29
VCC7 VCCIO6
U10 AR17
VAXG12 W/O M3 then NC

VREF
AG28 P10 AP24
tatal : 470u x 4, RSVD x2 VCC8 VCCIO7 C506 C198 C209 C509 C212 C510 C477 C471 C493 C470 VAXG13 ball B4 and D1
AG27 VCC9 VCCIO8 L10 AP23 VAXG14
AG26 J14 IV@22u/6.3V_8 IV@22u/6.3V_8 AP21 Rb4 R234 *1K_4
VCC10 VCCIO9 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 IV@22u/6.3V_8 IV@22u/6.3V_8 VAXG15
AF35 VCC11 VCCIO10 J13 AP20 VAXG16 SA_DIMM_VREFDQ B4 SMDDR_VREF_DQ0_M3 [13]
AF34 J12 AP18 D1 SMDDR_VREF_DQ1_M3 [14]
VCC12 VCCIO11 VAXG17 SB_DIMM_VREFDQ R239 *1K_4
SNB : Spec Cose down AF33 VCC13 VCCIO12 J11 AP17 VAXG18 Rd1
AF32 H14 AN24
VCC14 VCCIO13 VAXG19
470uF/4mohm x 4 330uF x2 AF31
VCC15 VCCIO14
H12 AN23
VAXG20
AF30 VCC16 VCCIO15 H11 AN21 VAXG21 IVY SPEC
22uF x 16 22uF x 4 AF29 VCC17 VCCIO16 G14 AN20 VAXG22 330uF x1, 10uF_8 x6 Socket BOT edge. +1.5V_CPU

DDR3 -1.5V RAILS


AF28 G13 C508 C507 C215 C501 C503 C505 AN18
VCC18 VCCIO17 VAXG23

PEG AND DDR


10uF x 10 10uF x 20 AF27 VCC19 VCCIO18 G12 AN17 VAXG24

GRAPHICS
AF26 F14 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 C484 C472 C190 C180 AM24 AF7
reserved x 5 AD35
VCC20 VCCIO19
F13 *IV@22u/6.3V_8 IV@22u/6.3V_8 AM23
VAXG25 VDDQ1
AF4
VCC21 VCCIO20 *IV@22u/6.3V_8 IV@22u/6.3V_8 VAXG26 VDDQ2
AD34 VCC22 VCCIO21 F12 AM21 VAXG27 VDDQ3 AF1
AD33 F11 AM20 AC7
VCC23 VCCIO22 VAXG28 VDDQ4 C526 C524 C534 C531 C232
AD32 E14 AM18 AC4
C185 C489 C498 C497 C176 C187 C186 VCC24 VCCIO23 VAXG29 VDDQ5 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8
AD31 VCC25 VCCIO24 E12 AM17 VAXG30 VDDQ6 AC1
AD30 VCC26 AL24 VAXG31 VDDQ7 Y7
22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 AD29 E11 C202 C495 C500 C494 C512 C515 AL23 Y4
*22u/6.3V_8
VCC27 VCCIO25 VAXG32 VDDQ8
AD28 VCC28 VCCIO26 D14 AL21 VAXG33 VDDQ9 Y1
AD27 D13 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 AL20 U7
VCC29 VCCIO27 C183 C473 C179 C178 VAXG34 VDDQ10
AD26 VCC30 VCCIO28 D12 AL18 VAXG35 VDDQ11 U4
AC35 D11 *IV@22u/6.3V_8 IV@22u/6.3V_8 AL17 U1
VCC31 VCCIO29 *IV@22u/6.3V_8 IV@22u/6.3V_8 VAXG36 VDDQ12 C533
AC34 VCC32 VCCIO30 C14 AK24 VAXG37 VDDQ13 P7
C211 C201 C487 C170 C485 C181 C486 AC33 C13 IVY SPEC AK23 P4 C236 C234 C229 +
VCC33 VCCIO31 VAXG38 VDDQ14 10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8
AC32 C12 22uF_8 x7 Socket TOP cavity AK21 P1
22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 VCC34 VCCIO32 VAXG39 VDDQ15 330u/2V_7343
AC31 VCC35 VCCIO33 C11 AK20 VAXG40
*22u/6.3V_8 *22u/6.3V_8 AC30 B14 22uF_8 x5 Socket BOT cavity AK18
C VCC36 VCCIO34 VAXG41 C
AC29 B12 22uF_8 x2 Socket TOP cavity (no stuff) AK17
VCC37 VCCIO35 VAXG42
AC28 A14 22uF_8 x5 Socket BOT cavity (no stuff) AJ24
VCC38 VCCIO36 C488 C499 C482 C492 VAXG43
AC27 VCC39 VCCIO37 A13 330uF_7343 x2 AJ23 VAXG44
AC26 A12 IV@22u/6.3V_8 IV@22u/6.3V_8 AJ21
VCC40 VCCIO38 IV@22u/6.3V_8 IV@22u/6.3V_8 VAXG45
AA35 VCC41 VCCIO39 A11 AJ20 VAXG46
AA34 VCC42 AJ18 VAXG47
AA33 J23 +1.05V_VTT_40 R436 *SHORT_4 AJ17 M27

SA RAIL
VCC43 VCCIO40 +1.05V VAXG48 VCCSA1 +VCCSA
C490 C184 C197 C491 C496 AA32 AH24 M26
VCC44 VAXG49 VCCSA2
AA31 AH23 L26
10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 VCC45 VAXG50 VCCSA3 C196 C188 C192 + C415
AA30 AH21 J26
VCC46 VAXG51 VCCSA4 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 330u/2V_7343
AA29 AH20 J25
AA28
VCC47 R157 Z DO@0/J_4 AH18
VAXG52 VCCSA5
J24
VCC48 VAXG53 VCCSA6
AA27 VCC49 AH17 VAXG54 VCCSA7 H26
AA26 H25
VCC50 VCCSA8
CORE SUPPLY

Y35
C199 C479 C480 C481 C194 Y34
VCC51 /^s' hDK
VCC52
10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8
Y33
Y32
VCC53 Z  E
VCC54

1.8V RAIL
*10u/6.3V_8 Y31 VCC55
Y30 H23 VCCSA_SENSE [38]
VCC56 R476 0_8 VCCSA_SENSE
Y29 VCC57 +1.8V
Y28
VCC58 R470 0_8 CPU_VCCPLL
Y27 B6
VCC59 VCCPLL1

MISC
10uF (Reserved) Y26
VCC60
A6
VCCPLL2 VCCSA_VID[0]
C22 VCCSA_VID0 [38]
V35 A2 C24
VCC61 CPU VCCPL VCCPLL3 VCCSA_VID[1] VCCSA_VID1 [38]
SVID

V34 AJ29 H_CPU_SVIDALRT#


C191 C189 C182 C205 C195 VCC62 VIDALERT# H_CPU_SVIDCLK C537 C528 C529 + C535
V33 AJ30
VCC63 VIDSCLK H_CPU_SVIDDAT 10u/6.3V_8 1u/6.3V_4 1u/6.3V_4 *330u/2V_7343
V32 VCC64 VIDSOUT AJ28 IVY 45W:1.5A VCCIO_SEL_NC
22u/6.3V_8 22u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 V31 A19
VCC65 VCCIO_SEL TP57
V30
V29
VCC66 Spec Real
VCC67 Ivy Bridge_rPGA_2DPC_Rev0p61
V28
VCC68 330uF/7mohm x 1 10uF x 1
V27
VCC69
Voltage selection for VCCIO:
V26 VCC70 10uF x 1 1uF x 2 this pin must be pulled high
U35 on the motherboard
C193 C200 C169 C168 VCC71
+ + + +
U34
VCC72 1uF x 2
B U33 VCC73 B
U32
VCC74
On CRB
330u/2V_7343 330u/2V_7343 *470u/2V_7343 *470u/2V_7343 U31 IVY SPEC H_SNB_IVB#_PWRCTRL = low, 1.0V
VCC75
U30 330uF x1, 10uF_8 x1, 1uF_4 x2 H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
VCC76
U29
VCC77 Socket BOT edge.
U28 VCC78
U27
VCC79
U26 VCC80 IVY SPEC
R35
R34
VCC81 Layout note: need routing 330uF x1, 10uF_8 x1 Socket BOT edge, CPU MCH
VCC82 SVID CLK 10uF_8 x2 Socket BOT cavity.
R33
R32
VCC83 together and ALERT need IVY 45W: 5A
VCC84
R31
R30
VCC85 between CLK and DATA Remove PU resistor 54.9/F, CPU SA Spec
VCC86 stuff at IMVP7 page
R29
VCC87 IVY 45W: 6A 330uF/6mohm x 1
SENSE LINES

R28 R83 100/F_4 +VCC_CORE


VCC88 R100 0_4
R27
VCC89 VCC_SENSE
AJ35
R99 0_4
VCC_SENSE [35] Spec Real 10uF x 6
R26 AJ34 VSS_SENSE [35]
VCC90 VSS_SENSE R82 100/F_4
P35 VCC91 330uF/7mohm x 1 10uF x 3 Real
P34
VCC92 H_CPU_SVIDCLK R78 *SHORT_4
P33 VCC93 VTT_VCCP_SENSE
VR_SVID_CLK [35] 10uF x 3 10uF x 8
P32 B10 VTT_VCCP_SENSE [36]
VCC94 VCCIO_SENSE VTT_VSSP_SENSE
P31 VCC95 VSS_SENSE_VCCIO A10 VTT_VSSP_SENSE [36]
P30 VCC96
JP12 P29
4.5A +1.5VSUS *SHORT_PAD +1.5V_CPU P28
VCC97 Place PU resistor close to CPU
P27
VCC98 R456 10/F_4 SVID DATA
VCC99 +1.05V +1.05V +SMDDR_VREF +VDDR_REF_CPU +1.5VSUS
2 1 +1.5V_CPU P26
VCC100 R457 10/F_4 Remove PU resistor 130/F,
Q34 AO4496
stuff at IMVP7 page
Trace Route to Power IC area.
8 1 R492 *0_8 R497
7 2 Ivy Bridge_rPGA_2DPC_Rev0p61 R97 *1K/F_4
6 3 130/F_4
5
H_CPU_SVIDDAT R80 *SHORT_4 VR_SVID_DATA [35] 3 1
4

A Q32 A
MAIND 2N7002K R498

2
R466 MAIND R499
220_8 Place PU resistor close to CPU SVID ALERT [34,37,41] MAIND
100K_4
*1K/F_4

C543
*470p/50V_4 +1.05V
3

[3,41] MAINON_ON_G MAINON_ON_G 2


R96
Q29 75_4 Quanta Computer Inc.
DMN601K-7 [35] +VCC_GFX
H_CPU_SVIDALRT# R95 43_4 R79 *SHORT_4
[35] +VCC_CORE VR_SVID_ALERT# [35] PROJECT : ZQTA/ZQSA
1

Size Document Number Rev


IVY Bridge 3/4 1A

Date: Friday, November 11, 2011 Sheet 5 of 44


5 4 3 2 1
5 4 3 2 1

IVY Bridge Processor (GND)


U16H U16I IVY Bridge Processor (RESERVED, CFG)
AT35 AJ22 U16E
VSS1 VSS81
AT32 VSS2 VSS82 AJ19
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19
AT25 AJ10 T33 E30 AH27 VCC_DIE_SENSE
VSS5 VSS85 VSS163 VSS236 XDP_CFG0 VCC_DIE_SENSE VSS_DIE_SENSE TP14
AT22 VSS6 VSS86 AJ7 T32 VSS164 VSS237 E27 TP16 AK28 CFG[0] VSS_DIE_SENSE AH26 TP21
AT19 AJ4 T31 E24 CFG1 AK29
VSS7 VSS87 VSS165 VSS238 TP13 CFG2 CFG[1]
AT16 VSS8 VSS88 AJ3 T30 VSS166 VSS239 E21 AL26 CFG[2]
AT13 AJ2 T29 E18 CFG3 AL27 Rs R136
VSS9 VSS89 VSS167 VSS240 TP17 CFG[3]
D AT10 AJ1 T28 E15 CFG4 AK26 L7 *SP@0_4 For Sandy For IVY D
VSS10 VSS90 VSS168 VSS241 CFG5 CFG[4] RSVD28
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13 AL29 CFG[5] RSVD29 AG7
AT4 AH34 T26 E10 CFG6 AL30 AE7 Rs Stuff NC
VSS12 VSS92 VSS170 VSS243 CFG7 CFG[6] RSVD30
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9 AM31 CFG[7] RSVD31 AK2
AR25 AH30 P8 E8 AM32

CFG
VSS14 VSS94 VSS172 VSS245 CFG[8]
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7 AM30 CFG[9] RSVD32 W8
AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6 AM28 CFG[10]
AR16 VSS17 VSS98 AH25 P3 VSS175 VSS248 E5 AM26 CFG[11]
AR13 VSS18 VSS99 AH22 P2 VSS176 VSS249 E4 AN28 CFG[12] RSVD33 AT26
AR10 VSS19 VSS100 AH19 N35 VSS177 VSS250 E3 AN31 CFG[13] RSVD34 AM33
AR7 VSS20 VSS101 AH16 N34 VSS178 VSS251 E2 AN26 CFG[14] RSVD35 AJ27
AR4 VSS21 VSS102 AH7 N33 VSS179 VSS252 E1 AM27 CFG[15]
AR2 VSS22 VSS103 AH4 N32 VSS180 VSS253 D35 AK31 CFG[16]
AP34 VSS23 VSS104 AG9 N31 VSS181 VSS254 D32 AN29 CFG[17]
AP31 VSS24 VSS105 AG8 N30 VSS182 VSS255 D29
AP28 VSS25 VSS106 AG4 N29 VSS183 VSS256 D26
AP25 VSS26 VSS107 AF6 N28 VSS184 VSS257 D20 RSVD37 T8
AP22 VSS27 VSS108 AF5 N27 VSS185 VSS258 D17 RSVD38 J16
AP19 VSS28 VSS109 AF3 N26 VSS186 VSS259 C34 TP10 AJ31 VAXG_VAL_SENSE RSVD39 H16
AP16 VSS29 VSS110 AF2 M34 VSS187 VSS260 C31 TP15 AH31 VSSAXG_VAL_SENSE RSVD40 G16
AP13 VSS30 VSS111 AE35 L33 VSS188 VSS261 C28 AJ33 VCC_VAL_SENSE
AP10 VSS31 VSS112 AE34 L30 VSS189 VSS262 C27 AH33 VSS_VAL_SENSE
AP7 VSS32 VSS113 AE33 L27 VSS190 VSS263 C25
AP4 VSS33 VSS114 AE32 L9 VSS191 VSS264 C23
AP1 VSS34 VSS115 AE31 L8 VSS192 VSS265 C10 AJ26 RSVD5 RSVD41 AR35

RESERVED
AN30 VSS35 VSS116 AE30 L6 VSS193 VSS266 C1 RSVD42 AT34
AN27 VSS36 VSS117 AE29 L5 VSS194 VSS267 B22 RSVD43 AT33
AN25 AE28 L4 B19 AP35
C AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
RSVD44
RSVD45 AR34 C

AN16 VSS40 VSS121 AE9 L1 VSS198 VSS271 B13


AN13 VSS41 VSS122 AD7 K35 VSS199 VSS272 B11 F25 RSVD8
AN10 VSS42 VSS123 AC9 K32 VSS200 VSS273 B9 F24 RSVD9
AN7 VSS43 VSS124 AC8 K29 VSS201 VSS274 B8 F23 RSVD10
AN4 VSS44 VSS125 AC6 K26 VSS202 VSS275 B7 D24 RSVD11 RSVD46 B34
AM29 VSS45 VSS126 AC5 J34 VSS203 VSS276 B5 G25 RSVD12 RSVD47 A33
AM25 VSS46 VSS127 AC3 J31 VSS204 VSS277 B3 G24 RSVD13 RSVD48 A34
AM22 VSS47 VSS128 AC2 H33 VSS205 VSS278 B2 E23 RSVD14 RSVD49 B35
AM19 VSS48 VSS129 AB35 H30 VSS206 VSS279 A35 D23 RSVD15 RSVD50 C35
AM16 VSS49 VSS130 AB34 H27 VSS207 VSS280 A32 C30 RSVD16
AM13 VSS50 VSS131 AB33 H24 VSS208 VSS281 A29 A31 RSVD17
AM10 VSS51 VSS132 AB32 H21 VSS209 VSS282 A26 B30 RSVD18
AM7 VSS52 VSS133 AB31 H18 VSS210 VSS283 A23 B29 RSVD19
AM4 VSS53 VSS134 AB30 H15 VSS211 VSS284 A20 D30 RSVD20 RSVD51 AJ32 TP8
AM3 VSS54 VSS135 AB29 H13 VSS212 VSS285 A3 B31 RSVD21 RSVD52 AK32 TP9
AM2 VSS55 VSS136 AB28 H10 VSS213 A30 RSVD22
AM1 VSS56 VSS137 AB27 H9 VSS214 C29 RSVD23
AL34 VSS57 VSS138 AB26 H8 VSS215
AL31 VSS58 VSS139 Y9 H7 VSS216 BCLK_ITP AN35 TP43
AL28 VSS59 VSS140 Y8 H6 VSS217 J20 RSVD24 BCLK_ITP# AM35 TP44
AL25 VSS60 VSS141 Y6 H5 VSS218 B18 RSVD25
AL22 VSS61 VSS142 Y5 H4 VSS219
AL19 VSS62 VSS143 Y3 H3 VSS220
AL16 VSS63 VSS144 Y2 H2 VSS221
AL13 VSS64 VSS145 W 35 H1 VSS222 J15 RSVD27 RSVD56 AT2
AL10 VSS65 VSS146 W 34 G35 VSS223 RSVD57 AT1
B AL7 VSS66 VSS147 W 33 G32 VSS224 RSVD58 AR1 B
AL4 VSS67 VSS148 W 32 G29 VSS225
AL2 VSS68 VSS149 W 31 G26 VSS226
AK33 VSS69 VSS150 W 30 G23 VSS227
AK30 VSS70 VSS151 W 29 G20 VSS228 KEY B1
AK27 VSS71 VSS152 W 28 G17 VSS229
AK25 VSS72 VSS153 W 27 G11 VSS230
AK22 VSS73 VSS154 W 26 F34 VSS231
AK19 VSS74 VSS155 U9 F31 VSS232
AK16 VSS75 VSS156 U8 F29 VSS233
AK13 U6 Ivy Bridge_rPGA_2DPC_Rev0p61
VSS76 VSS157
AK10 VSS77 VSS158 U5
AK7 VSS78 VSS159 U3
AK4 VSS79 VSS160 U2
AJ25 VSS80

Ivy Bridge_rPGA_2DPC_Rev0p61 Ivy Bridge_rPGA_2DPC_Rev0p61

The CFG signals have a default value of '1' if not terminated on the board. 9/26 modify
Processor Strapping CFG[6:5] (PCIE Port Bifurcation Straps)
CFG2 R133 1K/F_4
1 0 CFG5 R130 *1K/F_4 11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG6 R127 *1K/F_4 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
CFG2 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
A (PEG Static Lane Reversal) Normal Operation Lane Reversed CFG4 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled A
R129 IV@1K/F_4 eDP_EN# [22]

CFG4
(DP Presence Strap) Disable; No physical DP attached to eDP Enable; An ext DP device is connected to eDP
CFG7 R123 *1K/F_4
Quanta Computer Inc.
CFG7 PEG train immediately following PEG wait for BIOS training
(PEG Defer Training) xxRESETB de assertion PROJECT : ZQTA/ZQSA
Size Document Number Rev
IVY Bridge 4/4 1A

Date: Friday, November 11, 2011 Sheet 6 of 44


5 4 3 2 1
5 4 3 2 1

[3,5,8,9,11,22,32,35,36,40,41] +1.05V
9,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41]
[3,8,9,10,11,15,28,30,31,34,35,36,41,42]
+3V
+3V_S5 CPT/PPT (LVDS,DDI)
U20D

CPT/PPT (DMI,FDI,PM) [22] INT_LVDS_BLON J47


M45
L_BKLTEN SDVO_TVCLKINN
AP43
AP45
[22] INT_LVDS_DIGON L_VDD_EN SDVO_TVCLKINP
U20C
[22] INT_LVDS_BRIGHT P45 AM42
L_BKLTCTL SDVO_STALLN
AM40
D SDVO_STALLP D
[3] DMI_RXN0 BC24 BJ14 FDI_TXN0 [3] [22] INT_LVDS_EDIDCLK T40
DMI0RXN FDI_RXN0 L_DDC_CLK
[3] DMI_RXN1 BE20 AY14 FDI_TXN1 [3] [22] INT_LVDS_EDIDDATA K47 AP39
DMI1RXN FDI_RXN1 L_DDC_DATA SDVO_INTN
[3] DMI_RXN2 BG18 DMI2RXN FDI_RXN2 BE14 FDI_TXN2 [3] SDVO_INTP AP40
[3] DMI_RXN3 BG20 BH13 +3V R164 2.2K_4 T45
DMI3RXN FDI_RXN3 FDI_TXN3 [3] L_CTRL_CLK
BC12 R188 2.2K_4 P39
FDI_RXN4 FDI_TXN4 [3] L_CTRL_DATA
[3] DMI_RXP0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_TXN5 [3]
[3] DMI_RXP1 BC20 BG10 R186 2.37K/F_4 AF37 P38
DMI1RXP FDI_RXN6 FDI_TXN6 [3] LVD_IBG SDVO_CTRLCLK HDMI_DDCCLK_SW [23]
[3] DMI_RXP2 BJ18 BG9 FDI_TXN7 [3] T7 AF36 M39 HDMI_DDCDATA_SW [23]
DMI2RXP FDI_RXN7 LVD_VBG SDVO_CTRLDATA
[3] DMI_RXP3 BJ20
DMI3RXP
BG14 FDI_TXP0 [3] AE48
FDI_RXP0 LVD_VREFH

INT. HDMI
[3] DMI_TXN0 AW24 BB14 FDI_TXP1 [3] AE47 AT49
DMI0TXN FDI_RXP1 LVD_VREFL DDPB_AUXN
[3] DMI_TXN1 AW20 DMI1TXN FDI_RXP2 BF14 FDI_TXP2 [3] DDPB_AUXP AT47
[3] DMI_TXN2 BB18 BG13 FDI_TXP3 [3] AT40 HDMI_HP [23]
DMI2TXN FDI_RXP3 DDPB_HPD
[3] DMI_TXN3 AV18 BE12 [22] INT_TXLCLKOUT- AK39

DMI
FDI

LVDS
DMI3TXN FDI_RXP4 FDI_TXP4 [3] LVDSA_CLK#
BG12 [22] INT_TXLCLKOUT+ AK40 AV42 INT_HDMITX2N_R RP184 3 IV@0_4P2R
FDI_RXP5 FDI_TXP5 [3] LVDSA_CLK DDPB_0N INT_HDMITX2N [23]
[3] DMI_TXP0 AY24 BJ10 AV40 INT_HDMITX2P_R 2 1
DMI0TXP FDI_RXP6 FDI_TXP6 [3] DDPB_0P INT_HDMITX2P [23]
[3] DMI_TXP1 AY20 BH9 [22] INT_TXLOUT0- AN48 AV45 INT_HDMITX1N_R RP194 3 IV@0_4P2R
DMI1TXP FDI_RXP7 FDI_TXP7 [3] LVDSA_DATA#0 DDPB_1N INT_HDMITX1N [23]
[3] DMI_TXP2 AY18 [22] INT_TXLOUT1- AM47 AV46 INT_HDMITX1P_R 2 1 INT_HDMITX1P [23]

Digital Display Interface


DMI2TXP LVDSA_DATA#1 DDPB_1P INT_HDMITX0N_R RP204 IV@0_4P2R
[3] DMI_TXP3 AU18 DMI3TXP [22] INT_TXLOUT2- AK47 LVDSA_DATA#2 DDPB_2N AU48 3 INT_HDMITX0N [23]
AW16 AJ48 AU47 INT_HDMITX0P_R 2 1
FDI_INT FDI_INT [3] LVDSA_DATA#3 DDPB_2P INT_HDMITX0P [23]
AV47 INT_HDMICLK-_R RP214 3 IV@0_4P2R
DDPB_3N INT_HDMICLK- [23]
BJ24 AV12 [22] INT_TXLOUT0+ AN47 AV49 INT_HDMICLK+_R 2 1
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 [3] LVDSA_DATA0 DDPB_3P INT_HDMICLK+ [23]
[22] INT_TXLOUT1+ AM49
R521 49.9/F_4 DMI_COMP LVDSA_DATA1
+1.05V BG25 BC10 FDI_FSYNC1 [3] [22] INT_TXLOUT2+ AK49
DMI_IRCOMP FDI_FSYNC1 LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
R527 750/F_4 BH21 AV14 P42 DDPC_HPD_PU
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 [3] DDPC_CTRLDATA

FDI_LSYNC1 BB10 FDI_LSYNC1 [3] AF40 LVDSB_CLK#


AF39 AP47
LVDSB_CLK DDPC_AUXN
C AP49 C
DDPC_AUXP
AH45 AT38
LVDSB_DATA#0 DDPC_HPD
A18 DSWVREN [8] AH47
DSWVRMEN LVDSB_DATA#1
AF49 AY47
LVDSB_DATA#2 DDPC_0N DDPC_HPD_PU R169 *2.2K_4

System Power Management


AF45 AY49
SUS_PWR_ACK R539 *0_4 SUSACK#_R PCH_RSMRST# LVDSB_DATA#3 DDPC_0P
C12 E22 AY43
SUSACK# DPWROK DDPC_1N DDPD_HPD_PU R197 *2.2K_4
AH43 AY45
XDP_DBRST# LVDSB_DATA0 DDPC_1P
[3] XDP_DBRST# AH49 BA47
PCIE_WAKE# LVDSB_DATA1 DDPC_2N
K3 SYS_RESET# WAKE# B9 PCIE_WAKE# [28] AF47 LVDSB_DATA2 DDPC_2P BA48 0 : Port not detected
C607 *1u/10V_4 AF43 BB47
LVDSB_DATA3 DDPC_3N
DDPC_3P BB49
SYS_PWROK P12 +3V N3 CLKRUN# CLKRUN# [32]
SYS_PWROK CLKRUN# / GPIO32
INT_CRT_BLU N48 M43
[22] INT_CRT_BLU CRT_BLUE DDPD_CTRLCLK
R583 *0_4 L22 +3V_S5 G8 SUS_STAT# T15 INT_CRT_GRN P49 M36 DDPD_HPD_PU
PWROK SUS_STAT# / GPIO61 [22] INT_CRT_GRN CRT_GREEN DDPD_CTRLDATA
INT_CRT_RED T49
[22] INT_CRT_RED CRT_RED
PWROK_EC L10 +3V_S5 N14 PCH_SUSCLK T12 AT45

CRT
APWROK SUSCLK / GPIO62 DDPD_AUXN
[22] INT_CRT_DDCCLK T39 AT43
CRT_DDC_CLK DDPD_AUXP
[22] INT_CRT_DDCDAT M40 CRT_DDC_DATA DDPD_HPD BH41
[3] PM_DRAM_PWRGD PM_DRAM_PWRGD B13 +3V_S5 D10 PCH_SLP_S5# T14
DRAMPWROK SLP_S5# / GPIO63
DDPD_0N BB43
R126 IV@33_4 INT_CRT_HSYNC_R M47 BB45
[22] INT_HSYNC CRT_HSYNC DDPD_0P
[32] PCH_RSMRST# PCH_RSMRST# C21 H4 SUSC# [32] R125 IV@33_4 INT_CRT_VSYNC_R M49 BF44
RSMRST# SLP_S4# [22] INT_VSYNC CRT_VSYNC DDPD_1N
DDPD_1P BE44
+3V_S5 The required series-resistors are: DDPD_2N BF42
SUS_PWR_ACK K16 F4 SUSB# [32] Direct Connect - 33 DAC_IREF T43 BE42
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# DAC_IREF DDPD_2P
Docking Topology - 20 T42 BJ42
CRT_IRTN DDPD_3N
DDPD_3P BG42
[32] DNBSWON# E20 G10 SLP_A# SLP_A# [32] R187
B PWRBTN# SLP_A# 1K/F_4 PANTHER POINT
B

10/31 modify R place close to PCH


AC_PRESENT H20 DSW G16 SLP_SUS# T10
ACPRESENT / GPIO31 SLP_SUS# R483 IV@150/F_4 INT_CRT_BLU

PM_BATLOW# R482 IV@150/F_4 INT_CRT_GRN


BATLOW# / GPIO72 +3V_S5
E10 AP14 PM_SYNC [3]
PMSYNCH
R484 IV@150/F_4 INT_CRT_RED
PM_RI# A10 +3V_S5 K14 SLP_LAN#
RI# SLP_LAN# / GPIO29

PANTHER POINT

System PWR_OK(CLG) IMVP_PWRGD PU +3V


PCH Pull-high/low(CLG) +3V_S5 +3V_S5
PWROK_EC PD
CRB 1.0 change R8315 to 1K so AND gate output dont need PD again
+3V
PM_RI# R545 10K_4

CLKRUN# R584 8.2K_4 PM_BATLOW# R282 8.2K_4 C629


*0.1u/10V_4
XDP_DBRST# R567 4.99K/F_4 PCIE_WAKE# R261 10K_4
5

R554 *1K_4 SLP_LAN# R230 *10K_4 to PCH Pin12, XDP and EE debug U24
2 IMVP_PWRGD [3,35]
A PCH_RSMRST# R219 10K_4 SUS_PWR_ACK R538 10K_4 [3] SYS_PWROK SYS_PWROK 4 A
1 PWROK_EC
PWROK_EC [32]
AC_PRESENT R220 10K_4
TC7SH08FU
3

SYS_PWROK R601 *10K_4


R594
PM_DRAM_PWRGD R232 200/F_4 100K_4
Quanta Computer Inc.
wo S3 leakage, remove R
PROJECT : ZQTA/ZQSA
Size Document Number Rev
1A
Panther Point 1/6
Date: Friday, November 11, 2011 Sheet 7 of 44
5 4 3 2 1
5 4 3 2 1

RTC Circuitry(RTC) PCH2(CLG)


20mils D11 +3V_RTC CPT/PPT (HDA,JTAG,SATA)
R445 0_6
+3VPCU
R596 20K_4 RTC_RST# C564 18p/50V_4
+3V_RTC_1

2
1
20MIL J1
BAT54C C614 Y3 U20A
1u/6.3V_4 32.768KHZ R524
R448 30mils *SHORT_PAD 10M_4 RTC_X1 A20 C38

2
RTCX1 FWH0 / LAD0 LPC_LAD0 [24,32]
1K_4 A38

LPC
LPC_LAD1 [24,32]

3
4
C563 18p/50V_4 RTC_X2 FWH1 / LAD1
C20 RTCX2 FWH2 / LAD2 B37 LPC_LAD2 [24,32]
20MIL CN11 FWH3 / LAD3 C37 LPC_LAD3 [24,32]
R593 20K_4 SRTC_RST# RTC_RST# D20 RTCRST#
D 1 FWH4 / LFRAME# D36 LPC_LFRAME# [24,32] D

1
J2 SRTC_RST# G22
2 SRTCRST#
C620 C612 E36 PCH_DRQ#0 TP24

RTC
SM_INTRUDER# LDRQ0#
RTC_CON. 1u/6.3V_4 1u/6.3V_4 +3V_RTC R216 1M_4 K22 INTRUDER# +3V LDRQ1# / GPIO23 K36 PCH_DRQ#1 TP23
*SHORT_PAD

2
PCH_INVRMEN
10/5 chnage footprint & PN Add MOSFET to separate CODEC SYNC signal C17 INTVRMEN SERIRQ V5
R287 8.2K_4
IRQ_SERIRQ [32]
+3V
CN13 battery +5V R201 10K_4
SATA0RXN AM3 SATA_RXN0_C [25]
DFWF02MS118 AHL03003022

2
ACZ_BITCLK_R N34 AM1 SATA_RXP0_C [25]
HDA_BCLK SATA0RXP

SATA 6G
AHL03003024 SATA0TXN AP7 SATA_TXN0 [25] SATA HDD
ACZ_SYNC_CODEC 1 3 ACZ_SYNC_R L34 AP5 SATA_TXP0 [25]
HDA_SYNC SATA0TXP
Q13 SPKR T10 AM10
HDA Bus(CLG) [26] PCH_AZ_CODEC_BITCLK R202 33_4 ACZ_BITCLK_R CRB 1.0
R175
2N7002K
[26] SPKR
ACZ_RST#_R
SPKR SATA1RXN
SATA1RXP AM8
SATA_RXN_SSD
SATA_RXP_SSD
[24]
[24]
R176 33_4 ACZ_SYNC_CODEC 1M_4
K34 HDA_RST# SATA1TXN AP11
AP10
SATA_TXN_SSD [24] SSD
[26] PCH_AZ_CODEC_SYNC SATA1TXP SATA_TXP_SSD [24]

[26] PCH_AZ_CODEC_RST# R198 33_4 ACZ_RST#_R [26] PCH_AZ_CODEC_SDIN0 E34 AD7


HDA_SDIN0 SATA2RXN
SATA2RXP AD5
[26] PCH_AZ_CODEC_SDOUT R506 33_4 ACZ_SDOUT_R G34 AH5 DG recommended that AC coupling capacitors should be
TP25 HDA_SDIN1 SATA2TXN
SATA2TXP AH4 TP64 close to the connector (<100 mils) for optimal signal quality.
C34

IHDA
HDA_SDIN2
SATA3RXN AB8
A34 AB10
PCH JTAG Debug (CLG) +3V_S5 HDA_SDIN3 SATA3RXP
SATA3TXN AF3
SATA3TXP AF1 TP65
ACZ_SDOUT_R A36

SATA
HDA_SDO
9/27 add SATA4RXN Y7
SATA4RXP Y5
PCH_GPIO33 C36 +3V AD3
TP60 HDA_DOCK_EN# / GPIO33 SATA4TXN
R564 R292 R293 AD1 TP37
210/F_4 210/F_4 210/F_4 PCH_GPIO13 SATA4TXP
TP28 N32 HDA_DOCK_RST# / GPIO13 +3V_S5
SATA5RXN Y3 SATA_RXN5_C [25]
PCH_JTAG_TMS_R Y1 SATA ODD
SATA5RXP SATA_RXP5_C [25]
PCH_JTAG_TDI_R AB3 SATA_TXN5 [25]
C
PCH_JTAG_TCK PCH_JTAG_TCK SATA5TXN C
J3 JTAG_TCK SATA5TXP AB1 SATA_TXP5 [25]
PCH_JTAG_TDO_R
PCH_JTAG_TMS_R H7 Y11

JTAG
JTAG_TMS SATAICOMPO
R553 R552 PCH_JTAG_TDI_R K5 Y10 SATA_COMP R236 37.4/F_4 +1.05V
51_4 *100/F_4 R279 R280 JTAG_TDI SATAICOMPI
100/F_4 100/F_4 PCH_JTAG_TDO_R H1 JTAG_TDO SATA3_COMP R231 49.9/F_4
SATA3RCOMPO AB12

SATA3COMPI AB13

PCH_SPI_CLK T3 AH1 SATA3_RBIAS R561 750/F_4


PCH Dual SPI (CLG) (Default for WIN8) [32] PCH_SPI_CLK
PCH_SPI_CS0#
SPI_CLK SATA3RBIAS
Y14 SPI_CS0# R570 10K_4 +3V
W25Q32BVSSIG / AKE391P0N00----->4MB R336 10K_4 PCH_SPI_CS1# T1

SPI
+3VPCU SPI_CS1#
P3 SATA_ACT#
SATALED# SATA_ACT# [31]
W25Q16BVSSIG / AKE38FP0N01----->2MB
[32] PCH_SPI_SI PCH_SPI_SI V4 +3V V14 SATA0GP R274 10K_4 +3V
SPI_MOSI SATA0GP / GPIO21
for BA W25Q64BVSSIG / AKE3EFP0N00----->8MB
[32] PCH_SPI_SO PCH_SPI_SO U3 +3V P1 BBS_BIT0 SATA0GP/GPIO21
R319 VA@0_6 SPI_MISO SATA1GP / GPIO19
+3V_S5 +3V_PCH_ME SATA4GP/GPIO16

+3V_M R551 BA@0_6 PCH Strap Table PANTHER POINT


SATA5GP/GPIO49
If these pins are unused use 8.2k
10/31 add 10/11 add +3V_PCH_ME to 10k pull-up to +Vcc3_3 or 8.2k
U6 to 10k pull-down to ground
PCH_SPI_CS0# Pin Name Strap description Sampled Configuration
1 CE# VDD 8
PCH_SPI_CLK R324 33_4 6 0 = Default (weak pull-down 20K)
PCH_SPI_SI R334 33_4 5 SCK R301 *1K_4 SPKR
PCH_SPI_SO R322 33_4 2 SI SPKR No reboot mode setting PWROK +3V
SO HOLD# 7 R320 3.3K_4 1 = Setting to No-Reboot mode

C344
3 WP# VSS 4
C338
0 = "top-block swap" mode R171 *1K_4
GNT3# / GPIO55 Top-Block Swap Override PWROK PCI_GNT3# [9] Used as GPIO only. at chklist 1.2
B *22p/50V_4 ROM-2M 0.1u/10V_4 1 = Default (weak pull-up 20K) B

INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up R526 330K_4 PCH_INVRMEN
+3V_RTC
+3V_PCH_ME R328 3.3K_4

+3V_PCH_ME GNT1# / GPIO51 Boot BIOS Selection 1 [bit-1] PWROK GNT1# GNT0# Boot Location
10/11 add
U8 Default weak pull-up on GNT0/1#
PCH_SPI_CS1# 1 1 SPI R473 *1K_4
PCH_SPI_CLK R325
1
33_4 6 CE# VDD 8 * BBS_BIT1 [9]
[Need external pull-down for LPC BIOS]
PCH_SPI_SI R333 33_4 5 SCK R558 *1K_4 BBS_BIT0
SI GPIO19 Boot BIOS Selection 0 [bit-0] PWROK 0 0 LPC
PCH_SPI_SO R326 33_4 2 7 R335 3.3K_4
SO HOLD#
3 WP# VSS 4 0 = effect (default)(weak pull-down 20K)
C343 C351 HDA_SDO Flash Descriptor Security RSMRST R505 *SHORT_4 ACZ_SDOUT_R
*22p/50V_4 ROM-4M 0.1u/10V_4
[32] ME_WR ME_WR default EC setting folating
1 = overridden
0 = Set to Vss (weak pull-down 20K) R548 2.2K_4 for future CPU, Sandy Bridge NC
+1.8V 0930
R339 3.3K_4
DF_TVS DMI/FDI Termination voltage PWROK R546 1K_4
H_SNB_IVB# [3] DF_TVS needs to be pulled up to VccDFTERM power rail
+3V_PCH_ME 1 = Set to Vcc DF_TVS [10] through 2.2 kOhm 5% - R8361 change to 0 or not??
0 = Disable R277 *1K_4
PCH_SPI_CS0#
GPIO28 On-die PLL Voltage Regulator RSMRST# PLL_ODVR_EN [10]
R321 *0_4 1 = Enable (weak pull-up 20K)
0 = Support by 1.8V (weak pull-down) ACZ_SYNC_R
HDA_SYNC On-Die PLL VR Voltage Select RSMRST +3V_S5 R177 1K_4 Needs to be pulled High for Huron River platform.
PCH_SPI_CS1#
1 = Support by 1.5V chklist 1.2
[32] SPI_CS0#_UR_ME R331 0_4
Intel ME Crypto Transport Layer 0 = Disable (Default)
GPIO15 Security (TLS) cipher suite RSMRST
1 = Enable +3V_S5 R563 1K_4 PCH_GPIO15 [10]
internal PD
A A

DEEP S4/S5 well High = Enable (Default) +3V_RTC R530 330K_4 DSWVREN [7]
DSWVREN On Die DSW VR Enable DSW
Low = Disable R528 *330K_4
[22,25,30,31,32,33,34,41,42] +3VPCU
[11,22,23,25,26,31,34,41] +5V
[3,7,9,10,11,15,28,30,31,34,35,36,41,42] +3V_S5

Intel Anti-Theft HDD protection Quanta Computer Inc.


[3,5,7,9,11,22,32,35,36,40,41] +1.05V NV_ALE PWROK 0 = Disable (Internal pull-down 20kohm) +1.8V R308 *1K_4
NV_ALE [9]
23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41] +3V Only for Interposer
[5,10,11,41] +1.8V PROJECT :ZQTA/ZQSA
Size Document Number Rev
1A
Panther Point 2/6
Date: Friday, November 11, 2011 Sheet 8 of 44
5 4 3 2 1
5 4 3 2 1

13,14,19,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41] +3V
[3,7,8,10,11,15,28,30,31,34,35,36,41,42]
[3,5,7,8,11,22,32,35,36,40,41]
+3V_S5
+1.05V CPT/PPT (PCI-E,SMBUS,CLK)
U20B
CPT/PPT (PCI,USB,NVRAM)
BG34
U20E PERN1 SMBALERT#
BJ34
PERP1 +3V_S5 SMBALERT# / GPIO11
E12
AY7 AV32
RSVD1 PETN1 SMB_PCH_CLK
AV7 AU32 H14
RSVD2 PETP1 SMBCLK
BG26 AU3
TP1 RSVD3 SMB_PCH_DAT
BJ26 BG4 BE34 C9
TP2 RSVD4 PERN2 SMBDATA
BH25 BF34
TP3 PERP2
BJ16 AT10 BB32
TP4 RSVD5 PETN2
BG16 BC8 AY32

SMBUS
TP5 RSVD6 PETP2 DRAMRST_CNTRL_PCH
AH38
TP6 +3V_S5 SML0ALERT# / GPIO60
A12 DRAMRST_CNTRL_PCH [4,13,14]
AH37 AU2 [28] PCIE_RX3- BG36
D TP7 RSVD7 PERN3 SMB_ME0_CLK D
AK43 AT4 [28] PCIE_RX3+ BJ36 C8
TP8 RSVD8 C252 0.1u/10V_4 PCIE_TXN3_C PERP3 SML0CLK
AK45
C18
TP9 RSVD9
AT3
AT1
LAN [28] PCIE_TX3-
C249 0.1u/10V_4 PCIE_TXP3_C
AV34
AU34
PETN3
G12 SMB_ME0_DAT For LAN
TP10 RSVD10 [28] PCIE_TX3+ PETP3 SML0DATA
N30 AY3
TP11 RSVD11
H3 AT5 BF36
TP12 RSVD12 PERN4
AH12 AV3 BE36
TP13 RSVD13 PERP4 SML1ALERT#_R R536 *0_4
AM4
TP14 RSVD14
AV1 AY34
PETN4 +3V_S5 SML1ALERT# / PCHHOT# / GPIO74
C13 SML1ALERT# [10,31]
AM5 BB1 BB34
TP15 RSVD15 PETP4 SMB_ME1_CLK
Y13 BA3 +3V_S5 E14

PCI-E*
TP16 RSVD16 SML1CLK / GPIO58
K24
L24
TP17 RSVD17
BB5
BB3
BG37
BH37
PERN5
+3V_S5 M16 SMB_ME1_DAT For EC
TP18 RSVD18 PERP5 SML1DATA / GPIO75
AB46 BB7 AY36
TP19 RSVD19 PETN5
AB45 BE8 BB36

RSVD
TP20 RSVD20 PETP5
BD4
RSVD21
BF6 BJ38
RSVD22 PERN6
BG38

Controller
PERP6 CL_CLK1
B21 AV5 NV_ALE [8] AU36 M7 TP33
TP21 RSVD23 PETN6 CL_CLK1
M20 AV10 AV36
TP22 RSVD24 PETP6
AY16

Link
TX AC cap place at connector side, AC cap to TP23 CL_DATA1
BG46 AT8 BG40 T11 TP36
TP24 RSVD25 PERN7 CL_DATA1
connector < 400mils BJ40
PERP7
AY5 AY40
RSVD26 PETN7 CL_RST1#
BA2 BB40 P10 TP35
RSVD27 PETP7 CL_RST1#
BE28 USB30_RX1N
TP25
h^ [30] USB30_RX3-
USB30_RX3-
BC30
BE32
TP26 USB30_RX2N
USB30_RX3N
RSVD28
AT12
BF3
[24] PCIE_RX8-
[24] PCIE_RX8+
BE38
BC38
PERN8
TP62 USB30_RX4- TP27 RSVD29 C250 0.1u/10V_4 PCIE_TXN8_C PERP8
BJ32 USB30_RX4N Wireless [24] PCIE_TX8- AW38
TP28 C253 0.1u/10V_4 PCIE_TXP8_C PETN8
BC28
TP29 USB30_RX1P Port1 and port9 can be used on debug mode [24] PCIE_TX8+ AY38
PETP8
BE30 USB30_RX2P
USB30_RX3+ TP30 CLK_PEGA_REQ#
[30] USB30_RX3+ BF32
TP31 USB30_RX3P +3V_S5 PEG_A_CLKRQ# / GPIO47
M10 CLK_PEGA_REQ# [15]
TP61 USB30_RX4+ BG32 C24 USBP0- T41 Y40
TP32 USB30_RX4P USBP0N CLKOUT_PCIE0N
TP30 USB30_TX1- AV26 USB30_TX1N A24 USBP0+ T40 Reserve for USB I/O function Y39
TP33 USBP0P CLKOUT_PCIE0P
BB26 USB30_TX2N C25 XHCI for USBP0-3 AB37 CLK_PCIE_VGA# [15]

CLOCKS
TP34 USBP1N USBP1- [30] CLKOUT_PEG_A_N
USB30_TX3- AU28 B25 USB/B-USB1-1/USB debug PCIE_CLK_USB30_REQ# J2 +3V_S5 AB38 CLK_PCIE_VGA [15]
[30] USB30_TX3- TP35 USB30_TX3N USBP1P USBP1+ [30] PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P
TP26 USB30_TX4- AY30 C26
TP36 USB30_TX4N USBP2N USBP2- [30]
TP29 USB30_TX1+ AU26 A26 MB USB
TP37 USB30_TX1P USBP2P USBP2+ [30]
AY26 K28 USBP3- AB49 AV22 CLK_CPU_BCLKN [3]
TP38 USB30_TX2P USBP3N USBP3- [24] CLKOUT_PCIE1N CLKOUT_DMI_N
USB30_TX3+ AV28 H28 USBP3+ Mini-SSD AB47 AU22 CLK_CPU_BCLKP [3]
[30] USB30_TX3+ TP39 USB30_TX3P USBP3P USBP3+ [24] CLKOUT_PCIE1P CLKOUT_DMI_P
TP27 USB30_TX4+ AW30 E28 EHCI1
TP40 USB30_TX4P USBP4N USBP4- [30]
C D28 BLUETOOTH PCIE_CLKREQ1# M1 +3V C
USBP4P USBP4+ [30] PCIECLKRQ1# / GPIO18
C28 USBP5- T39 AM12 CLK_DPLL_SSCLKN [3]
USBP5N USBP5+ T38 CLKOUT_DP_N
USBP5P
A28 Reserve for SIM card CLKOUT_DP_P
AM13 CLK_DPLL_SSCLKP [3]
C29 AA48
USBP6N USB port6/7 may not be available on all PCH sku CLKOUT_PCIE2N
B29 AA47
PCI_PIRQA# USBP6P (HM55 support 12port only) CLKOUT_PCIE2P CLK_BUF_PCIE_3GPLLN
K40 N28 BF18
PCI_PIRQB# PIRQA# USBP7N PCIE_CLK_REQ2# CLKIN_DMI_N CLK_BUF_PCIE_3GPLLP
K38 M28 V10 +3V BE18
PCI

PCI_PIRQC# PIRQB# USBP7P PCIECLKRQ2# / GPIO20 CLKIN_DMI_P


H38 L30 USBP8- [22]
PCI_PIRQD# PIRQC# USBP8N
G38
PIRQD# USBP8P
K30 USBP8+ [22] Camera
G30 Y37 BJ30 CLK_BUF_BCLKN
USBP9N USBP9- [30] CLKOUT_PCIE3N CLKIN_GND1_N
dGPU_EDIDSEL# CLK_BUF_BCLKP
REQ1# / GPIO50 +3V USB/B-USB1-2
C46 E30 Y36 BG30
USB

USBP9P USBP9+ [30] CLKOUT_PCIE3P CLKIN_GND1_P


dGPU_SELECT#
REQ2# / GPIO52 +3V
C44 C30 USBP10- [24]
REQ#3 USBP10N PCIE_CLKREQ3#
REQ3# / GPIO54 +3V Mini Card (WLAN) +3V_S5
E40 A30 USBP10+ [24] A8
USBP10P PCIECLKRQ3# / GPIO25 CLK_BUF_DREFCLKN
USBP11N
L32 EHCI2 CLKIN_DOT_96N
G24
CLK_BUF_DREFCLKP
GNT1# / GPIO51 +3V Reserve for card reader
[8] BBS_BIT1 D47 K32 E24
USBP11P CLKIN_DOT_96P
GNT2# / GPIO53 +3V
[10] BOARD_ID2 E42 G32 Y43
USBP12N CLKOUT_PCIE4N
GNT3# / GPIO55 +3V Reserve for Touch pad
[8] PCI_GNT3# F46 E32 Y45
USBP12P CLKOUT_PCIE4P CLK_BUF_DREFSSCLKN
C32 AK7
11/2 modify USBP13N PCIE_CLKREQ4# CLKIN_SATA_N CLK_BUF_DREFSSCLKP
USBP13P
A32 Reserve for FP L12
PCIECLKRQ4# / GPIO26 +3V_S5 CLKIN_SATA_P
AK5
G_SENSOR_INT#_PCH
PIRQE# / GPIO2 +3V
[25] G_SENSOR_INT#_PCH G42
dGPU_PWR_EN
PIRQF# / GPIO3 +3V
[40] dGPU_PWR_EN G40
DGPU_HOLD_RST# USB_BIAS R507 22.6/F_4 CLK_PCH_SRC5# CLK_PCH_14M
PIRQG# / GPIO4 +3V
[15] DGPU_HOLD_RST# C42 C33 [24] CLK_PCH_SRC5# V45 K45
EXTTS_SNI_DRV1_PCH USBRBIAS# CLK_PCH_SRC5 CLKOUT_PCIE5N REFCLK14IN
PIRQH# / GPIO5 +3V
D44 [24] CLK_PCH_SRC5 V46
CLKOUT_PCIE5P
B33
Wireless PCIE_CLKREQ5# L14 +3V_S5 H45 CLK_PCI_FB C538 27p/50V_4
USBRBIAS [24] PCIE_CLK_REQ5# PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK
TP32 PCI_PME# K10
PME#

2
[3] PCI_PLTRST# PCI_PLTRST# C6 +3V_S5 A14 USB_OC0# USB_OC0# [30] CLK_PCIE_LOM# AB42 V47 XTAL25_IN Y2
PLTRST# OC0# / GPIO59 [28] CLK_PCIE_LOM# CLKOUT_PEG_B_N XTAL25_IN
+3V_S5 K20 USB_OC1# CLK_PCIE_LOM AB40 V49 XTAL25_OUT R486 25MHz
OC1# / GPIO40 USB_OC1# [30] [28] CLK_PCIE_LOM CLKOUT_PEG_B_P XTAL25_OUT
+3V_S5 USB_OC2# 1M_4
B17 LAN

1
OC2# / GPIO41 USB_OC3# CLK_PCIE_LAN_REQ#
H49
CLKOUT_PCI0 +3V_S5 OC3# / GPIO42
C16 [28] CLK_PCIE_LAN_REQ# E6
PEG_B_CLKRQ# / GPIO56+3V_S5
TP22 H43 +3V_S5 L16 USB_OC4# C539 27p/50V_4
CLK_PCI_FB R485 22_4 CLK_PCI_FB_C CLKOUT_PCI1 OC4# / GPIO43 USB_OC5# XCLK_RCOMP R478 90.9/F_4
J48
CLKOUT_PCI2 +3V_S5 OC5# / GPIO9
A16
XCLK_RCOMP
Y47 +1.05V
R183 22_4 CLK_LPC_DEBUG_C K42 +3V_S5 D14 USB_OC6# V40
[24] CLK_LPC_DEBUG CLKOUT_PCI3 OC6# / GPIO10 CLKOUT_PCIE6N
R184 22_4 CLK_PCI_775_C H40 +3V_S5 C14 USB_OC7# T6 CLK_PCH_SRC6P V42
[32] CLK_PCI_775 CLKOUT_PCI4 OC7# / GPIO14 CLKOUT_PCIE6P
CLK_PCIE_REQ6# T13 +3V_S5
PANTHER POINT PCIECLKRQ6# / GPIO45
V38 +3V K43 SKU_ID1

FLEX CLOCKS
T8 CLK_PCH_SRC7P CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
V37
B CLKOUT_PCIE7P CLK_FLEX1 T5 B
+3V CLKOUTFLEX1 / GPIO65
F47
CLK_PCIE_REQ7# K12 +3V_S5
PCIECLKRQ7# / GPIO46
+3V CLKOUTFLEX2 / GPIO66
H47 BOARD_ID4 [10,31]
T11 CLK_ITPN AK14
For XDP T13 CLK_ITPP AK13
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P +3V CLKOUTFLEX3 / GPIO67
K49 48M_CLK_CR T37

PANTHER POINT

PLTRST#(CLG) PCI/USBOC# Pull-up(CLG) +3V CLK_REQ/Strap Pin(CLG) SMBus(EC) SMBus(PCH)


+3V_S5 PCI_PIRQA# R161 8.2K_4 +3V_S5 +3V
R534 PCI_PIRQB# R191 8.2K_4 +3V_S5
+3V 10/11 modify 10 1 USB_OC6# PCI_PIRQC# R469 8.2K_4
USB_OC1# 9 2 USB_OC0# PCI_PIRQD# R170 8.2K_4 R565 10K_4 PCIE_CLK_USB30_REQ#
USB_OC4# 8 3 USB_OC7# R549 10K_4 PCIE_CLKREQ3#
USB_OC2# 7 4 USB_OC5# R294 10K_4 PCIE_CLKREQ4# R149 R603
USB_OC3# 6 5 11/2 modify R225 10K_4 PCIE_CLKREQ5# 2.2K_4 S5 4.7K_4 S0

2
C605 +3V R306 10K_4 CLK_PCIE_LAN_REQ#
0.1u/10V_4 10K_10P8R R479 R278 10K_4 CLK_PCIE_REQ6#
10 1 DGPU_HOLD_RST# R281 10K_4 CLK_PCIE_REQ7# [32] 2ND_MBCLK 3 1 SMB_ME1_CLK SMB_PCH_DAT 3 1
5

11/2 modify G_SENSOR_INT#_PCH 9 2 EXTTS_SNI_DRV1_PCH CLK_SDATA [13,14,24,25,31]


PCI_PLTRST# 2 8 3 dGPU_EDIDSEL# +3V Q7 Q41
4 PLTRST# [15,24,28,32] REQ#3 7 4 dGPU_SELECT# 2N7002K 2N7002K
1 dGPU_PWR_EN 6 5 R556 10K_4 PCIE_CLKREQ1#
R273 10K_4 PCIE_CLK_REQ2# +3V_S5 +3V
U22 10K_10P8R
3

TC7SH08FU R582
100K_4 9/26 modify
R586 *10K_4 CLK_PEGA_REQ# R150 R602
dGPU_PW_CTRL# SKU_ID1 SKU_ID0 VGA H/W Setup 2.2K_4 4.7K_4

2
+3V (GPIO68) (GPIO64) (GPIO16) Signal Menu
CTL : dGPU_VRON
R495 *SP@1K_4 3 1 SMB_ME1_DAT SMB_PCH_CLK 3 1
dGPU_PW_CTRL# [10] [32] 2ND_MBDATA CLK_SCLK [13,14,24,25,31]A
A R496 SP@100K_4
UMA Only 1 0 0 UMA Hidden UMA boot CLK_BUF_BCLKN R514 10K_4 Q8 Q40
CLK_BUF_BCLKP R513 10K_4 2N7002K 2N7002K

+3V dGPU Only 0 0 1 GPU Hidden GPU boot


CLK_BUF_PCIE_3GPLLN R532 10K_4
R166 OP@10K_4 SKU_ID1 Switchable CLK_BUF_PCIE_3GPLLP R531 10K_4
R162 SP@10K_4 (Mux) UMA+GPU dGPU/SG UMA boot CLK_BUF_DREFCLKN R211 10K_4 +3V_S5
CLK_BUF_DREFCLKP R205 10K_4
Optimize CLK_BUF_DREFSSCLKN R240 10K_4
(Muxless) 0 1 1 UMA UMA/SG UMA boot CLK_BUF_DREFSSCLKP R244 10K_4 R246 1K_4 DRAMRST_CNTRL_PCH
+3V CLK_PCH_14M R163 10K_4

R571 EV@10K_4
R295
R590
10K_4
2.2K_4
SMBALERT#
SMB_PCH_CLK
Quanta Computer Inc.
SKU_ID0 [10] dGPU_PW_CTRL# CLOCK TERMINATION for FCIM
R559 SP@10K_4 1 = GPU power is control by H/W (pure Discrete SKU) R591 2.2K_4 SMB_PCH_DAT
0 = GPU power is control by PCH GPIO (Discrete, SG or Optimize) R296 2.2K_4 SMB_ME0_CLK PROJECT : ZQTA/ZQSA
--->(Default) R283 2.2K_4 SMB_ME0_DAT Size Document Number Rev
R537 10K_4 SML1ALERT#_R 1A
Panther Point 3/6
Date: Friday, November 11, 2011 Sheet 9 of 44
5 4 3 2 1
5 4 3 2 1

9,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41]
[3,7,8,9,11,15,28,30,31,34,35,36,41,42]
+3V
+3V_S5 CPT/PPT (GPIO,VSS_NCTF,RSVD)
U20F

S_GPIO R276 100_4 T7 +3V +3V C40 dGPU_PW _CTRL# [9]


BMBUSY# / GPIO0 TACH4 / GPIO68
SIO_EXT_SMI# A42 +3V +3V B41
[32] SIO_EXT_SMI# TACH1 / GPIO1 TACH5 / GPIO69 CABLE_ID [22] GPIO Pull-up/Pull-down(CLG)
BOARD_ID1 H36 +3V +3V C41 BOARD_ID3
D TACH2 / GPIO6 TACH6 / GPIO70 D

[32] SIO_EXT_SCI# SIO_EXT_SCI# E38 +3V +3V A40 R491 10K_4 +3V +3V_S5
TACH3 / GPIO7 TACH7 / GPIO71
TP63 C10 +3V_S5 PCH_GPIO24 R307 *10K_4
GPIO8
TP66 GPIO12 C4 +3V_S5 PLL_ODVR_EN R303 10K_4
LAN_PHY_PWR_CTRL / GPIO12
SIO_A20GATE
[8] PCH_GPIO15 G2 GPIO15 +3V_S5 A20GATE P4 SIO_A20GATE [32] +3V
10/31 modify
AU16 PCH_PECI TP31
PECI SIO_EXT_SMI# R148 10K_4
[9] SKU_ID0 U2 SATA4GP / GPIO16 +3V SIO_RCIN# SIO_EXT_SCI# R145 10K_4
RCIN# P5 SIO_RCIN# [32]

GPIO
[15,19] DGPU_PW ROK D40 +3V AY11 H_PW RGOOD [3] STP_PCI# R566 *10K_4

CPU/MISC
TACH0 / GPIO17 PROCPWRGD SIO_A20GATE R290 10K_4
G_SENSOR_ID T5 +3V AY10 PCH_THRMTRIP# R249 390_4 PM_THRMTRIP# [3] SIO_RCIN# R304 10K_4
SCLOCK / GPIO22 THRMTRIP# CRIT_TEMP_REP# R560 10K_4
11/2 modify PCH_GPIO24 E8 GPIO24 / MEM_LED +3V_S5 INIT3_3V# T14
+1.8V
PCH_GPIO27 E16 DSW AY1 DF_TVS DF_TVS [8] DF_TVS R550 *1K_4
GPIO27 DF_TVS

[8] PLL_ODVR_EN PLL_ODVR_EN P8 +3V_S5 Follow the Emerald Lake 2 CRB


GPIO28
TS_VSS1 AH8
STP_PCI# K1 +3V
STP_PCI# / GPIO34 PCH_GPIO27 R223 10K_4
TS_VSS2 AK11
[39,40] dGPU_VRON K4 GPIO35 +3V
TS_VSS3 AH10
C DMI_OVRVLTG V8 +3V C
SATA2GP / GPIO36
TS_VSS4 AK10
FDI_OVRVLTG M5 +3V GPIO27 : If not used then use 8.2-k to 10-k pull-down to GND.
SATA3GP / GPIO37
MFG_MODE N2 +3V P37
SLOAD / GPIO38 NC_1
BOARD_ID0 M3 +3V
SDATAOUT0 / GPIO39
TEST_SET_UP V13 +3V BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
[9,31] SML1ALERT# R572 *SHORT_4 CRIT_TEMP_REP# V3 +3V BG48
SATA5GP / GPIO49 VSS_NCTF_16
TP34 SV_DET_NC D6 GPIO57 +3V_S5 VSS_NCTF_17 BH3

R266 100K_4 BH47


VSS_NCTF_18
A4 VSS_NCTF_1 VSS_NCTF_19 BJ4

10/11 modify A44 VSS_NCTF_2 VSS_NCTF_20 BJ44

A45 VSS_NCTF_3 VSS_NCTF_21 BJ45

NCTF
A46 VSS_NCTF_4 VSS_NCTF_22 BJ46

A5 VSS_NCTF_5 VSS_NCTF_23 BJ5

A6 VSS_NCTF_6 VSS_NCTF_24 BJ6


B B
B3 VSS_NCTF_7 VSS_NCTF_25 C2

B47 VSS_NCTF_8 VSS_NCTF_26 C48

BD1 D1 SV_SET_UP Reserve for future +3V


VSS_NCTF_9 VSS_NCTF_27
BD49 D49 R555 10K_4 BOARD_ID0 R568 *10K_4
VSS_NCTF_10 VSS_NCTF_28
High = Strong (Default) R471 10K_4 BOARD_ID1 R467 *10K_4
BE1 E1 +3V
VSS_NCTF_11 VSS_NCTF_29 R490 *10K_4 BOARD_ID3 R487 10K_4
BE49 E49 TEST_SET_UP R272 10K_4 R472 *10K_4 BOARD_ID4 R468 10K_4
VSS_NCTF_12 VSS_NCTF_30 R285 *1K_4
BF1 VSS_NCTF_13 VSS_NCTF_31 F1 BOARD_ID3 [31]
BOARD_ID4 [9,31]
BF49 VSS_NCTF_14 VSS_NCTF_32 F49

SGPIO BOARD_ID2
PANTHER POINT

8 Layer ------->High *
SATA2GP : strap for reserved at chklist 1.2 +3V 6 Layer ------->Low
+3V
SATA3GP : strap for reserved at chklist 1.2 S_GPIO R302 1K_4
NOTE: The internal pull-down is disabled after PLTRST# deasserts. R289 *1K_4 R167 *10K_4
BOARD_ID2 [9]
NOTE: This signal should not be pulled high when strap is sampled. R172 10K_4
A A

+3V +3V +3V


R288
R305 100K_4 FDI_OVRVLTG R291 *1K_4 DMI_OVRVLTG R286 *200K/F_4 G_SENSOR_ID SP@10K_4
R275 SP@1K_4
MFG-TEST Quanta Computer Inc.
+3V
Low = Tx, Rx terminated to
FDI TERMINATION LOW - Tx, Rx terminated DMI TERMINATION same voltage (DC Coupling Mode) High = W/O G_SENSOR MFG_MODE R569 10K_4 PROJECT : ZQTA/ZQSA
VOLTAGE OVERRIDE to same voltage VOLTAGE OVERRIDE (DEFAULT) BIOS RECOVERY R557 *1K_4 Size Document Number Rev
Low = W G_SENSOR Panther Point 4/6 1A

Date: Friday, November 11, 2011 Sheet 10 of 44


5 4 3 2 1
5 4 3 2 1

PCH5(CLG)
CPT/PPT (POWER)
+VCCA_DAC_1_2 +3V
VccADAC =1mA(8mils)
U20G POWER L30
BKP1608HS181-T/180ohm/1.5A_6
CPT/PPT (POWER)
+1.05V +1.05V_PCH_VCC R480 *0_8 +1.05V_VCCUSBCORE +1.05V
+1.05V
VccCORE =1.3 A(60mils) C525 C541 C540 C527
R284 0.002/F_1206 AA23
VCCCORE[1] VCCADAC
U48 22u/6.3V_8 0.01u/25V_4 0.1u/10V_4 10u/6.3V_6 U20J POWER R203 *SHORT_8
AC23 VCCCORE[2]

CRT
AD21 +VCCACLK AD49 N26
C266 C272 C262 C289 VCCCORE[3] +VCCALVDS +3V VCCACLK VCCIO[29] C269
AD23 VCCCORE[4] VSSADAC U47

VCC CORE
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 10u/6.3V_6 AF21 VccALVDS=1mA(8mils) VCCDSW3_3= 3mA P26 1u/6.3V_4 VCCSUS3_3 = 119mA(15mils)
VCCCORE[5] R195 IV@0_4 R250 *SHORT_4 +VCCPDSW VCCIO[30]
AF23 +3V_S5 T16
VCCCORE[6] VCCDSW3_3 +3V_S5
AG21 VCCCORE[7] VCCIO[31] P28
D D
R5285 near PCH ball for VCCP GND sense AG23 R190 DO@0_4
VCCCORE[8] C319 PCH_VCCDSW R243 *SHORT_6
AG24 AK36 V12 T27
+1.05V +1.05V_PCH_VCCDPLL_EXP VCCCORE[9] VCCALVDS 0.1u/10V_4 DCPSUSBYP VCCIO[32]
AG26 VCCCORE[10]
When Dis sku, LVDS power can short to GND
AG27 VCCCORE[11] VSSALVDS AK37 VCCIO[33] T29
R224 *SHORT_6 AG29 +VCC_TX_LVDS +1.8V C309 +3V_SUS_CLKF33 T38 C316
VCCCORE[12] +1.05V +VCCAPLL_CPY_PCH *0.1u/10V_4 VCC3_3[5] 0.1u/10V_4
AJ23 VccTX_LVDS=60mA(10mils)

LVDS
VCCCORE[13] L34 +3V_VCCPUSB
AJ26 AM37 T23
+1.05V +1.05V_VCCAPLL_EXP VCCCORE[14] VCCTX_LVDS[1] IV@0.1uH/250mA_8 L35 *10uH/100mA_8 VCCSUS3_3[7]
AJ27 VCCCORE[15] BH23 VCCAPLLDMI2
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38 VCCSUS3_3[8] T24
L36 *1uH/25mA_6 AJ31 C554 C553 C552 R511 DO@0_4 +1.05V R199 *SHORT_6 +VCCDPLL_CPY AL29 R235 *SHORT_6
VCCCORE[17] IV@0.01u/25V_4 IV@22u/6.3V_8 C565 VCCIO[14]
AP36 V23

USB
VCCTX_LVDS[3] *10u/6.3V_6 VCCSUS3_3[9]
C569 AP37 IV@0.01u/25V_4 +VCCSUS1 AL24 V24 C308
*10u/6.3V_6 VCCTX_LVDS[4] DCPSUS[3] VCCSUS3_3[10] 0.1u/10V_4
AN19
VCCIO[28] +3V_VCCAUBG
P24
C271 VCCSUS3_3[6]
VCCME(+1.05V) = ??A(??mils)
BJ22 +3V_VCC_GIO +3V *1u/6.3V_4 AA19
+1.05V +1.05V_VCCIO VCCAPLLEXP VCCASW[1] +VCCAUPLL R209 *SHORT_6
T26 +1.05V
R196 *SHORT_6 +1.05V +1.05V_VCCEPW VCCIO[34]
VccIO =2.925 A(140mils) V33 AA21 VCC5REFSUS=1mA

HVCMOS
R533 0.002/F_1206 VCC3_3[6] VCCASW[2]
AN16 VCCIO[15] VccASW =1.01 A(60mils)
VCCDMI = 42mA(10mils) R587 VA@0.002/F_1206 AA24 M26 +5V_PCH_VCC5REFSUS R229 10/F_4 +5V_S5
C260 +1.05V VCCASW[3] V5REF_SUS
AN17 VCCIO[16]

Clock and Miscellaneous


C290 C259 C263 V34 0.1u/10V_4 +1.1V_VCC_DMI R648 AA26 D6 RB500V-40
VCC3_3[7] +1.05V_M VCCASW[4] +3V_S5
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 BA@0.002/F_1206 C267 C286 C273 AN23 +VCCA_USBSUS C302
R258 *SHORT_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 DCPSUS[4] 0.1u/10V_4
AN21 AA27
VCCIO[17] VCCASW[5] +3V_VCCPSUS
VCCSUS3_3[1] AN24
AN26 10/31 add AA29 C285
VCCIO[18] VCCASW[6] *1u/6.3V_4
AN27 AT16 +VCCAFDI_VRM +VCCAFDI_VRM C318 AA31 V5REF= 1mA
VCCIO[19] VCCVRM[3] VCCASW[7]
1u/6.3V_4
C265 C291 AP21 AC26 P34 +5V_PCH_VCC5REF R168 10/F_4 +5V
1u/6.3V_4 10u/6.3V_6 VCCIO[20] C603 C257 VCCASW[8] V5REF
AP23 AT20 VCCCLKDMI = 20mA(8mils) 22u/6.3V_8 22u/6.3V_8 AC27 D5 RB500V-40 +3V
VCCIO[21] VCCDMI[1] VCCASW[9] C240
N20

DMI

PCI/GPIO/LPC
+1.1V_VCC_DMI_CCI +VCC_DMI_CCI +1.05V VCCSUS3_3[2] 1u/6.3V_4
AP24 AC29

VCCIO
VCCIO[22] VCCASW[10]
N22
L31 R477 *1/F_4 VCCSUS3_3[3]
AP26 VCCIO[23] VCCCLKDMI AB36 AC31 VCCASW[11]
*10uH/100mA_8 P20 +3V_VCCPSUS R238 *SHORT_6 +3V_S5
R474 0_4 VCCSUS3_3[4]
AT24 VCCIO[24] AD29 VCCASW[12]
C +3V +3V_VCC_EXP C532 C530 P22 VCCSUS3_3 = 119mA(15mils) C
1u/6.3V_4 *10u/6.3V_6 VCCSUS3_3[5] C311
AD31 VCCASW[13]
R519 *SHORT_8 AN33 1u/10V_4
VCCIO[25]
W21 VCCASW[14] VCC3_3[1] AA16
AN34 VCCIO[26] VCCDFTERM[1] AG16
C558 +VCCP_NAND +1.8V VCCPNAND = 190 mA(15mils) W23 W16 +3V_VCCPCORE R247 *SHORT_6
VCCASW[15] VCC3_3[8] +3V
0.1u/10V_4
BH29 AG17 R300 *SHORT_8 W24 T34 VCCPCORE = 28mA(10mils)

DFT / SPI
VCC3_3[3] VCCDFTERM[2] VCCASW[16] VCC3_3[4] +3V
C315
W26 0.1u/10V_4
C332 VCCASW[17] C255
VCCDFTERM[3] AJ16
0.1u/10V_4 W29 0.1u/10V_4
+VCCAFDI_VRM VCCASW[18]
+VCCAFDI_VRM AP16 VCCVRM[2]
AJ17 +1.05V W31 AJ2
VCCDFTERM[4] VCCASW[19] VCC3_3[2] +3V

+1.05V R542 *0_8 +1.05V_VCCAPLL_FDI BG6 VCCSPI = 20mA(8mils) R562 *SHORT_6 W33
VccAFDIPLL VCCASW[20] C317
VCCIO[5] AF13
+3V_VCCME_SPI +3V_S5 0.1u/10V_4
R267 *SHORT_8 +1.05V_VCCDPLL_FDI AP17 C599 C299 0.1u/10V_4 +VCCRTCEXT N16
VCCIO[27] DCPRTC
FDI

V1 R575 VA@0_6 10/31 add 1u/6.3V_4 AH13 +V1.05S_SATA3 R299 *SHORT_8 +1.05V
VCCSPI VCCIO[12]

+1.1V_VCC_DMI AU20 R647 BA@0_6 +VCCAFDI_VRM +VCCAFDI_VRM Y49 AH14


VCCDMI[2] +3V_M VCCVRM[4] VCCIO[13]
R192 *SHORT_6 C331
1u/10V_4
PANTHER POINT C593 Reserve +3V_S5 to VCCSPI for EC 795 AF14
1u/6.3V_4 C256 +1.05V_VCCA_A_DPL VCCIO[6]
65mA(10mils) BD47 ??mA(??mils)

SATA
1u/6.3V_4 VCCADPLLA +V1.1LAN_VCCAPLL L37
VCCAPLLSATA AK1 +1.05V
8mA(8mils) +1.05V_VCCA_B_DPL BF47 VCCVRM= 114mA(15mils) *10uH/100mA_8
VCCADPLLB C594
R481 *SHORT_6 AF11 +VCCAFDI_VRM *10u/6.3V_6
+VCCDIFFCLK VCCVRM[1]
AF17 VCCIO[7]
+VCCDIFFCLKN AF33
C544 VCCDIFFCLKN[1] R228 *SHORT_6
VCCDIFFCLKN= 55mA(10mils) AF34
VCCDIFFCLKN[2] VCCIO[2]
AC16 +1.05V
1u/6.3V_4 AG34
+1.05V VCCDIFFCLKN[3]
VCCIO[3] AC17
VCCSSC= 95mA(10mils) C294
R226 *0_6 +V1.05V_SSCVCC AG33 AD17 1u/6.3V_4
+VCCAFDI_VRM VCCSSC VCCIO[4]

C295 C298 0.1u/10V_4 +VCCSST V16 +1.05V_VCCEPW VCCME = 1.01A(60mils)


B
*1u/6.3V_4 DCPSST B
VCCVRM: 1.8V (Destop)
+1.5V R263 0_6 1.5V (Mobile)
+1.05V T17 DCPSUS[1] VCCASW[22] T21
+1.05V R264 *0_6 +V1.05M_VCCSUS V19

MISC
DCPSUS[2]
1mA(8mils)
R535 *SHORT_4 +VTT_VCCPCPU V21
VCCASW[23]

CPU
BJ8 V_PROC_IO
C583 C586 T19
C580 0.1u/10V_4 0.1u/10V_4 VCCASW[21]
VCCRTC<1mA(8mils) 4.7u/6.3V_6 R159 *0_4 +1.5VSUS

RTC
A22 P32 +V3.3A_1.5A_HDA_IO R160 0_4 VCCSUSHDA= 10mA(8mils)

HDA
+3V_RTC VCCRTC VCCSUSHDA +3V_S5

C288 C296 C287 PANTHER POINT C239 C238


1u/6.3V_4 0.1u/10V_4 0.1u/10V_4 *1u/6.3V_4 0.1u/10V_4

[3,7,8,9,10,15,28,30,31,34,35,36,41,42] +3V_S5
[26,30,34,35,36,37,38,39] +5V_S5

[4,5,13,14,37,40] +1.5VSUS

[8,22,23,25,26,31,34,41] +5V
10,13,14,19,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41] +3V
[24,37,41] +1.5V +1.05V L32 10uH/100mA_8 +1.05V_VCCA_A_DPL
[3,5,7,8,9,22,32,35,36,40,41] +1.05V
[5,8,10,41] +1.8V
+ C546 C542
[8] +3V_RTC 220u/2.5V_3528 1u/6.3V_4

+3V

L33 10uH/100mA_8 +1.05V_VCCA_B_DPL


R165 1/F_4 L15 10uH/100mA_8 +3V_SUS_CLKF33

+ C548 C551
C235 C237 220u/2.5V_3528 1u/6.3V_4
10u/6.3V_6 1u/10V_4
A A

Quanta Computer Inc.


PROJECT :ZQTA/ZQSA
Size Document Number Rev
1A
Panther Point 5/6
Date: Friday, November 11, 2011 Sheet 11 of 44
5 4 3 2 1
5 4 3 2 1

PCH6(CLG)

U20I

AY4 H46
IBEX PEAK-M (GND) AY42
AY46
VSS[159]
VSS[160]
VSS[259]
VSS[260] K18
K26
VSS[161] VSS[261]
D AY8 VSS[162] VSS[262] K39 D
B11 VSS[163] VSS[263] K46
B15 VSS[164] VSS[264] K7
B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
B27 VSS[167] VSS[267] L20
B31 VSS[168] VSS[268] L26
B35 VSS[169] VSS[269] L28
B39 VSS[170] VSS[270] L36
B7 VSS[171] VSS[271] L48
U20H F45 M12
VSS[172] VSS[272]
H5 VSS[0] BB12 VSS[173] VSS[273] P16
BB16 VSS[174] VSS[274] M18
AA17 VSS[1] VSS[80] AK38 BB20 VSS[175] VSS[275] M22
AA2 VSS[2] VSS[81] AK4 BB22 VSS[176] VSS[276] M24
AA3 VSS[3] VSS[82] AK42 BB24 VSS[177] VSS[277] M30
AA33 VSS[4] VSS[83] AK46 BB28 VSS[178] VSS[278] M32
AA34 VSS[5] VSS[84] AK8 BB30 VSS[179] VSS[279] M34
AB11 VSS[6] VSS[85] AL16 BB38 VSS[180] VSS[280] M38
AB14 VSS[7] VSS[86] AL17 BB4 VSS[181] VSS[281] M4
AB39 VSS[8] VSS[87] AL19 BB46 VSS[182] VSS[282] M42
AB4 VSS[9] VSS[88] AL2 BC14 VSS[183] VSS[283] M46
AB43 VSS[10] VSS[89] AL21 BC18 VSS[184] VSS[284] M8
AB5 VSS[11] VSS[90] AL23 BC2 VSS[185] VSS[285] N18
AB7 VSS[12] VSS[91] AL26 BC22 VSS[186] VSS[286] P30
AC19 VSS[13] VSS[92] AL27 BC26 VSS[187] VSS[287] N47
AC2 VSS[14] VSS[93] AL31 BC32 VSS[188] VSS[288] P11
AC21 VSS[15] VSS[94] AL33 BC34 VSS[189] VSS[289] P18
AC24 VSS[16] VSS[95] AL34 BC36 VSS[190] VSS[290] T33
AC33 VSS[17] VSS[96] AL48 BC40 VSS[191] VSS[291] P40
AC34 VSS[18] VSS[97] AM11 BC42 VSS[192] VSS[292] P43
AC48 VSS[19] VSS[98] AM14 BC48 VSS[193] VSS[293] P47
C C
AD10 VSS[20] VSS[99] AM36 BD46 VSS[194] VSS[294] P7
AD11 VSS[21] VSS[100] AM39 BD5 VSS[195] VSS[295] R2
AD12 VSS[22] VSS[101] AM43 BE22 VSS[196] VSS[296] R48
AD13 VSS[23] VSS[102] AM45 BE26 VSS[197] VSS[297] T12
AD19 VSS[24] VSS[103] AM46 BE40 VSS[198] VSS[298] T31
AD24 VSS[25] VSS[104] AM7 BF10 VSS[199] VSS[299] T37
AD26 VSS[26] VSS[105] AN2 BF12 VSS[200] VSS[300] T4
AD27 VSS[27] VSS[106] AN29 BF16 VSS[201] VSS[301] W34
AD33 VSS[28] VSS[107] AN3 BF20 VSS[202] VSS[302] T46
AD34 VSS[29] VSS[108] AN31 BF22 VSS[203] VSS[303] T47
AD36 VSS[30] VSS[109] AP12 BF24 VSS[204] VSS[304] T8
AD37 VSS[31] VSS[110] AP19 BF26 VSS[205] VSS[305] V11
AD38 VSS[32] VSS[111] AP28 BF28 VSS[206] VSS[306] V17
AD39 VSS[33] VSS[112] AP30 BD3 VSS[207] VSS[307] V26
AD4 VSS[34] VSS[113] AP32 BF30 VSS[208] VSS[308] V27
AD40 VSS[35] VSS[114] AP38 BF38 VSS[209] VSS[309] V29
AD42 VSS[36] VSS[115] AP4 BF40 VSS[210] VSS[310] V31
AD43 VSS[37] VSS[116] AP42 BF8 VSS[211] VSS[311] V36
AD45 VSS[38] VSS[117] AP46 BG17 VSS[212] VSS[312] V39
AD46 VSS[39] VSS[118] AP8 BG21 VSS[213] VSS[313] V43
AD8 VSS[40] VSS[119] AR2 BG33 VSS[214] VSS[314] V7
AE2 VSS[41] VSS[120] AR48 BG44 VSS[215] VSS[315] W17
AE3 VSS[42] VSS[121] AT11 BG8 VSS[216] VSS[316] W19
AF10 VSS[43] VSS[122] AT13 BH11 VSS[217] VSS[317] W2
AF12 VSS[44] VSS[123] AT18 BH15 VSS[218] VSS[318] W27
AD14 VSS[45] VSS[124] AT22 BH17 VSS[219] VSS[319] W48
AD16 VSS[46] VSS[125] AT26 BH19 VSS[220] VSS[320] Y12
AF16 VSS[47] VSS[126] AT28 H10 VSS[221] VSS[321] Y38
AF19 VSS[48] VSS[127] AT30 BH27 VSS[222] VSS[322] Y4
AF24 VSS[49] VSS[128] AT32 BH31 VSS[223] VSS[323] Y42
AF26 VSS[50] VSS[129] AT34 BH33 VSS[224] VSS[324] Y46
B AF27 AT39 BH35 Y8 B
VSS[51] VSS[130] VSS[225] VSS[325]
AF29 VSS[52] VSS[131] AT42 BH39 VSS[226] VSS[328] BG29
AF31 VSS[53] VSS[132] AT46 BH43 VSS[227] VSS[329] N24
AF38 VSS[54] VSS[133] AT7 BH7 VSS[228] VSS[330] AJ3
AF4 VSS[55] VSS[134] AU24 D3 VSS[229] VSS[331] AD47
AF42 VSS[56] VSS[135] AU30 D12 VSS[230] VSS[333] B43
AF46 VSS[57] VSS[136] AV16 D16 VSS[231] VSS[334] BE10
AF5 VSS[58] VSS[137] AV20 D18 VSS[232] VSS[335] BG41
AF7 VSS[59] VSS[138] AV24 D22 VSS[233] VSS[337] G14
AF8 VSS[60] VSS[139] AV30 D24 VSS[234] VSS[338] H16
AG19 VSS[61] VSS[140] AV38 D26 VSS[235] VSS[340] T36
AG2 VSS[62] VSS[141] AV4 D30 VSS[236] VSS[342] BG22
AG31 VSS[63] VSS[142] AV43 D32 VSS[237] VSS[343] BG24
AG48 VSS[64] VSS[143] AV8 D34 VSS[238] VSS[344] C22
AH11 VSS[65] VSS[144] AW14 D38 VSS[239] VSS[345] AP13
AH3 VSS[66] VSS[145] AW18 D42 VSS[240] VSS[346] M14
AH36 VSS[67] VSS[146] AW2 D8 VSS[241] VSS[347] AP3
AH39 VSS[68] VSS[147] AW22 E18 VSS[242] VSS[348] AP1
AH40 VSS[69] VSS[148] AW26 E26 VSS[243] VSS[349] BE16
AH42 VSS[70] VSS[149] AW28 G18 VSS[244] VSS[350] BC16
AH46 VSS[71] VSS[150] AW32 G20 VSS[245] VSS[351] BG28
AH7 VSS[72] VSS[151] AW34 G26 VSS[246] VSS[352] BJ28
AJ19 VSS[73] VSS[152] AW36 G28 VSS[247]
AJ21 VSS[74] VSS[153] AW40 G36 VSS[248]
AJ24 VSS[75] VSS[154] AW48 G48 VSS[249]
AJ33 VSS[76] VSS[155] AV11 H12 VSS[250]
AJ34 VSS[77] VSS[156] AY12 H18 VSS[251]
AK12 VSS[78] VSS[157] AY22 H22 VSS[252]
AK3 VSS[79] VSS[158] AY28 H24 VSS[253]
H26 VSS[254]
PANTHER POINT H30 VSS[255]
A H32 VSS[256] A
H34 VSS[257]
F3 VSS[258]

PANTHER POINT

Quanta Computer Inc.


PROJECT :ZQTA/ZQSA
Size Document Number Rev
Panther Point 6/6 1A

Date: Friday, November 11, 2011 Sheet 12 of 44


5 4 3 2 1
5 4 3 2 1

+1.5VSUS
JDIM1B
[4] M_A_A[15:0] JDIM1A M_A_DQ[63:0] [4]
75 VDD1 VSS16 44
M_A_A0 98 5 M_A_DQ4 76 48
M_A_A1 A0 DQ0 M_A_DQ0 VDD2 VSS17
97 A1 DQ1 7 81 VDD3 VSS18 49
M_A_A2 96 15 M_A_DQ2 82 54
M_A_A3 A2 DQ2 M_A_DQ3 VDD4 VSS19
95 A3 DQ3 17 87 VDD5 VSS20 55
M_A_A4 92 4 M_A_DQ1 88 60
M_A_A5 A4 DQ4 M_A_DQ5 VDD6 VSS21
91 A5 DQ5 6 93 VDD7 VSS22 61
M_A_A6 90 16 M_A_DQ6 94 65
M_A_A7 86
A6 DQ6
18 M_A_DQ7
2.48A 99
VDD8 VSS23
66
M_A_A8 A7 DQ7 M_A_DQ12 VDD9 VSS24
D 89 A8 DQ8 21 100 VDD10 VSS25 71 D
M_A_A9 85 23 M_A_DQ13 105 72
M_A_A10 A9 DQ9 M_A_DQ11 VDD11 VSS26

PC2100 DDR3 SDRAM SO-DIMM


107 A10/AP DQ10 33 106 VDD12 VSS27 127
M_A_A11 84 35 M_A_DQ10 111 128
M_A_A12 A11 DQ11 M_A_DQ8 VDD13 VSS28
83 A12/BC# DQ12 22 112 VDD14 VSS29 133
M_A_A13 119 24 M_A_DQ9 117 134
M_A_A14 A13 DQ13 M_A_DQ14 VDD15 VSS30
80 A14 DQ14 34 118 VDD16 VSS31 138
M_A_A15 78 36 M_A_DQ15 123 139
A15 DQ15 M_A_DQ17 VDD17 VSS32

PC2100 DDR3 SDRAM SO-DIMM


DQ16 39 124 VDD18 VSS33 144
109 41 M_A_DQ20 145
[4] M_A_BS#0 BA0 DQ17 VSS34
108 51 M_A_DQ18 199 150
[4] M_A_BS#1 BA1 DQ18 +3V VDDSPD VSS35
79 53 M_A_DQ19 151
[4] M_A_BS#2 BA2 DQ19 VSS36
114 40 M_A_DQ16 77 155
[4] M_A_CS#0 S0# DQ20 NC1 VSS37
121 42 M_A_DQ21 122 156
[4] M_A_CS#1 S1# DQ21 NC2 VSS38
101 50 M_A_DQ22 R206 *10K_4 125 161
[4] M_A_CLK0 CK0 DQ22 +3V NCTEST VSS39
103 52 M_A_DQ23 162
[4] M_A_CLK0# CK0# DQ23 VSS40
102 57 M_A_DQ24 PM_EXTTS#0 198 167
[4] M_A_CLK1 CK1 DQ24 EVENT# VSS41
104 59 M_A_DQ28 30 168
[4] M_A_CLK1# CK1# DQ25 [4,14] DDR3_DRAMRST# RESET# VSS42
M_A_DQ25
[4] M_A_CKE0 73
74
CKE0 DQ26 67
69 M_A_DQ26
M3 solution VSS43 172
173
[4] M_A_CKE1 CKE1 DQ27 VSS44
115 56 M_A_DQ27 R222 *M3@0_6 +SMDDR_VREF_DQ0 1 178
[4] M_A_CAS# CAS# DQ28 [5] SMDDR_VREF_DQ0_M3 VREF_DQ VSS45
110 58 M_A_DQ29 126 179
[4] M_A_RAS# RAS# DQ29 +SMDDR_VREF_DIMM VREF_CA VSS46
113 68 M_A_DQ31 184
[4] M_A_WE# WE# DQ30 VSS47
R208 10K_4 DIMM0_SA0 197 70 M_A_DQ30 185
R207 10K_4 DIMM0_SA1 SA0 DQ31 M_A_DQ36 VSS48
201 SA1 DQ32 129 2 VSS1 VSS49 189
CLK_SCLK 202 131 M_A_DQ33 3 190
[9,14,24,25,31] CLK_SCLK CLK_SDATA SCL DQ33 M_A_DQ34 VSS2 VSS50
200 141 8 195

(204P)
[9,14,24,25,31] CLK_SDATA SDA DQ34 M_A_DQ39 VSS3 VSS51
C DQ35 143 9 VSS4 VSS52 196 C
116 130 M_A_DQ32 13
[4] M_A_ODT0 ODT0 DQ36 VSS5
120 132 M_A_DQ37 14
[4] M_A_ODT1 ODT1 DQ37 VSS6
140 M_A_DQ38 19
DQ38 M_A_DQ35 VSS7
11 DM0 DQ39 142 20 VSS8
28 147 M_A_DQ45 25
DM1 DQ40 M_A_DQ44 VSS9
46 149 26 203 +0.75V_DDR_VTT
63
DM2
DM3
(204P) DQ41
DQ42 157 M_A_DQ40 31
VSS10
VSS11
VTT1
VTT2 204
136 159 M_A_DQ42 32
DM4 DQ43 M_A_DQ47 VSS12
153 DM5 DQ44 146 37 VSS13 GND 205
170 148 M_A_DQ41 38 206
DM6 DQ45 M_A_DQ46 VSS14 GND
187 DM7 DQ46 158 43 VSS15
160 M_A_DQ43
M_A_DQS0 DQ47 M_A_DQ53
12 DQS0 DQ48 163
M_A_DQS1 29 165 M_A_DQ52 DDR3-DIMM1_H=9.2_Reverse
M_A_DQS2 DQS1 DQ49 M_A_DQ50 +1.5VSUS
47 DQS2 DQ50 175
M_A_DQS3 64 177 M_A_DQ55
M_A_DQS4 DQS3 DQ51 M_A_DQ49
137 DQS4 DQ52 164
M_A_DQS5 154 166 M_A_DQ48
M_A_DQS6 DQS5 DQ53 M_A_DQ54 R194 +SMDDR_VREF_DIMM
171 DQS6 DQ54 174
M_A_DQS7 188 176 M_A_DQ51 change to 1K/F_4 1K/F_4
[4] M_A_DQS[7:0] DQS7 DQ55
M_A_DQS#0 10 181 M_A_DQ56
M_A_DQS#1 DQS#0 DQ56 M_A_DQ57
27 DQS#1 DQ57 183
M_A_DQS#2 45 191 M_A_DQ62 +SMDDR_VREF R182 *0_6 +SMDDR_VREF_DIMM [14]
M_A_DQS#3 DQS#2 DQ58 M_A_DQ59
62 DQS#3 DQ59 193
M_A_DQS#4 135 180 M_A_DQ60
M_A_DQS#5 DQS#4 DQ60 M_A_DQ61 R218 C300
152 DQS#5 DQ61 182
B M_A_DQS#6 169 192 M_A_DQ63 1K/F_4 470p/50V_4 B
M_A_DQS#7 DQS#6 DQ62 M_A_DQ58 +1.5VSUS +SMDDR_VREF_DQ0
[4] M_A_DQS#[7:0] 186 DQS#7 DQ63 194

DDR3-DIMM1_H=9.2_Reverse R213
1K/F_4
change to 1K/F_4
M1 solution
Place these Caps near So-Dimm0. +SMDDR_VREF R221 *0_6 +SMDDR_VREF_DQ0

SMDDR_VREF_DQ0_M3 1 3 C281
+1.5VSUS 470p/50V_4
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0 REV:B Add
C244 C279 C274 C247 C278 Q14 R214

2
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 0.1u/16V_4 0.1u/16V_4 [4,9,14] DRAMRST_CNTRL_PCH BA@AP2302GN 1K/F_4

C246 + C241 C293 C283 C280 C275


*330u/2V_7343
10u/6.3V_6 0.1u/16V_4 0.1u/16V_4

C242 C277 C245 C243 C276 2.2u/6.3V_6 2.2u/6.3V_6


10u/6.3V_6 10u/6.3V_6 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4

A
+3V [4,5,11,14,37,40] +1.5VSUS A
+0.75V_DDR_VTT [3,7,8,9,10,11,14,19,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41] +3V
[14,37,41] +0.75V_DDR_VTT

C555 C557 C561 C572 C560 C562 C567


C576
2.2u/6.3V_6
C575
0.1u/16V_4
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6
[5,14,37] +SMDDR_VREF
Quanta Computer Inc.
PROJECT : ZQTA/ZQSA
Size Document Number Rev
1A
DDRIII SO-DIMM-0
Date: Friday, November 11, 2011 Sheet 13 of 44
5 4 3 2 1
5 4 3 2 1

+1.5VSUS
[4] M_B_A[15:0] JDIM2A M_B_DQ[63:0] [4] JDIM2B
M_B_A0 98 5 M_B_DQ5 75 44
M_B_A1 A0 DQ0 M_B_DQ1 VDD1 VSS16
97 A1 DQ1 7 76 VDD2 VSS17 48
M_B_A2 96 15 M_B_DQ2 81 49
M_B_A3 A2 DQ2 M_B_DQ3 VDD3 VSS18
95 A3 DQ3 17 82 VDD4 VSS19 54
M_B_A4 92 4 M_B_DQ0 87 55
M_B_A5 A4 DQ4 M_B_DQ4 VDD5 VSS20
91 A5 DQ5 6 88 VDD6 VSS21 60
M_B_A6 90 16 M_B_DQ6 93 61
M_B_A7 A6 DQ6 M_B_DQ7 VDD7 VSS22
86 A7 DQ7 18 94 VDD8 VSS23 65
M_B_A8 89 21 M_B_DQ13 99 66
D
M_B_A9 85
A8 DQ8
23 M_B_DQ9
2.48A 100
VDD9 VSS24
71
D

M_B_A10 A9 DQ9 M_B_DQ10 VDD10 VSS25


107 A10/AP DQ10 33 105 VDD11 VSS26 72
M_B_A11 M_B_DQ11

PC2100 DDR3 SDRAM SO-DIMM


84 A11 DQ11 35 106 VDD12 VSS27 127
M_B_A12 83 22 M_B_DQ12 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ8 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_B_A14 80 34 M_B_DQ14 117 134
M_B_A15 A14 DQ14 M_B_DQ15 VDD15 VSS30
78 A15 DQ15 36 118 VDD16 VSS31 138
M_B_DQ20

PC2100 DDR3 SDRAM SO-DIMM


DQ16 39 123 VDD17 VSS32 139
109 41 M_B_DQ17 124 144
[4] M_B_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_B_DQ23 145
[4] M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ18 199 150
[4] M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ16 151
[4] M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ21 77 155
[4] M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ19 122 156
[4] M_B_CLK0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ22 R529 *10K_4 125 161
[4] M_B_CLK0# CK0# DQ23 +3V NCTEST VSS39
102 57 M_B_DQ28 162
[4] M_B_CLK1 CK1 DQ24 VSS40
104 59 M_B_DQ24 PM_EXTTS#1 198 167
[4] M_B_CLK1# CK1# DQ25 EVENT# VSS41
M_B_DQ31
[4] M_B_CKE0 73
74
CKE0 DQ26 67
69 M_B_DQ27
M3 solution [4,13] DDR3_DRAMRST# 30 RESET# VSS42 168
172
[4] M_B_CKE1 CKE1 DQ27 VSS43
115 56 M_B_DQ29 173
[4] M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ25 R270 *M3@0_6 +SMDDR_VREF_DQ1 1 178
[4] M_B_RAS# RAS# DQ29 [5] SMDDR_VREF_DQ1_M3 VREF_DQ VSS45
113 68 M_B_DQ30 126 179
[4] M_B_WE# WE# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R573 10K_4 DIMM1_SA0 197 70 M_B_DQ26 184
R574 10K_4 DIMM1_SA1 SA0 DQ31 M_B_DQ32 VSS47
+3V 201 SA1 DQ32 129 VSS48 185
202 131 M_B_DQ33 2 189
[9,13,24,25,31] CLK_SCLK SCL DQ33 M_B_DQ34 VSS1 VSS49
200 SDA DQ34 141 3 VSS2 VSS50 190
[9,13,24,25,31] CLK_SDATA 143 M_B_DQ35 8 195

(204P)
C DQ35 VSS3 VSS51 C
116 130 M_B_DQ36 9 196
[4] M_B_ODT0 ODT0 DQ36 VSS4 VSS52
120 132 M_B_DQ37 13
[4] M_B_ODT1 ODT1 DQ37 VSS5
140 M_B_DQ38 14
DQ38 M_B_DQ39 VSS6
11 DM0 DQ39 142 19 VSS7
28 147 M_B_DQ40 20
DM1 DQ40 M_B_DQ41 VSS8
46 149 25
63
DM2
DM3
(204P) DQ41
DQ42 157 M_B_DQ46 26
VSS9
VSS10 VTT1 203 +0.75V_DDR_VTT
136 159 M_B_DQ43 31 204
DM4 DQ43 M_B_DQ44 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
170 148 M_B_DQ45 37 205
DM6 DQ45 M_B_DQ47 VSS13 GND
187 DM7 DQ46 158 38 VSS14 GND 206
160 M_B_DQ42 43
M_B_DQS0 DQ47 M_B_DQ49 VSS15
12 DQS0 DQ48 163
M_B_DQS1 29 165 M_B_DQ53
M_B_DQS2 DQS1 DQ49 M_B_DQ55
47 DQS2 DQ50 175 DDR3-DIMM1_H=5.2_Reverse
M_B_DQS3 64 177 M_B_DQ54
M_B_DQS4 DQS3 DQ51 M_B_DQ52
137 DQS4 DQ52 164
M_B_DQS5 154 166 M_B_DQ48
M_B_DQS6 DQS5 DQ53 M_B_DQ51
171 DQS6 DQ54 174
M_B_DQS7 188 176 M_B_DQ50
[4] M_B_DQS[7:0] DQS7 DQ55
M_B_DQS#0 10 181 M_B_DQ60
M_B_DQS#1 DQS#0 DQ56 M_B_DQ56
27 DQS#1 DQ57 183
M_B_DQS#2 45 191 M_B_DQ59
M_B_DQS#3 DQS#2 DQ58 M_B_DQ58
62 DQS#3 DQ59 193
M_B_DQS#4 135 180 M_B_DQ61
M_B_DQS#5 DQS#4 DQ60 M_B_DQ57 +1.5VSUS +SMDDR_VREF_DQ1
152 DQS#5 DQ61 182
B M_B_DQS#6 169 192 M_B_DQ62 B
M_B_DQS#7 DQS#6 DQ62 M_B_DQ63
[4] M_B_DQS#[7:0] 186 DQS#7 DQ63 194
M1 solution R271
DDR3-DIMM1_H=5.2_Reverse 1K/F_4

+SMDDR_VREF R233 *0_6 +SMDDR_VREF_DQ1

change to 1K/F_4
+1.5VSUS Place these Caps near So-Dimm1. C327
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1 SMDDR_VREF_DQ1_M3 1 3 470p/50V_4
C325 C304 C303 C305 C322
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 0.1u/16V_4 0.1u/16V_4 REV:B Add
Q15 R269

2
C324 + C301 C248 C282 C328 C329 BA@AP2302GN 1K/F_4
[4,9,13] DRAMRST_CNTRL_PCH
330u/2V_7343
10u/6.3V_6 0.1u/16V_4 0.1u/16V_4

C326 C306 C307 C321 C323 2.2u/6.3V_6 2.2u/6.3V_6


10u/6.3V_6 10u/6.3V_6 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4

+3V +0.75V_DDR_VTT

[4,5,11,13,37,40] +1.5VSUS
A C588 C589 C568 C570 C581 C584 C587[3,7,8,9,10,11,13,19,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41] +3V A
C601 C600 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 [13,37,41] +0.75V_DDR_VTT
2.2u/6.3V_6 0.1u/16V_4 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6
[13] +SMDDR_VREF_DIMM
[5,13,37] +SMDDR_VREF
Quanta Computer Inc.
PROJECT : ZQTA/ZQSA
Size Document Number Rev
1A
DDRIII SO-DIMM-1
Date: Friday, November 11, 2011 Sheet 14 of 44
5 4 3 2 1
1 2 3 4 5 6 7 8

+1.05V_GFX
 EW'> :EWd

To be placed no further from the GPU C435 EV@22u/6.3V_8 U15A


EW'^ :EWd
than bewteen the PS and GPU C441 EV@22u/6.3V_8 AG19 PEX_IOVDD_1 PEX_RX0 AN12 PEG_TX15 PEG_TX15 [3]
IV@:iGPU
C388 EV@10u/6.3V_6 AG21 PEG_TX#15 ED'^ :EDd
C392 EV@10u/6.3V_6 AG22
PEX_IOVDD_2 W'/ PEX_RX0_N AM12
AN14 PEG_TX14
PEG_TX#15 [3]
PEG_TX14 [3]
EV@:dGPU
PLACE UNDER BGA C74 EV@4.7u/6.3V_6 PEX_IOVDD_3 PEX_RX1 PEG_TX#14
AG24 AM14 PEG_TX#14 [3]
C91 EV@1u/6.3V_4 AH21
PEX_IOVDD_4
PEX_IOVDD_5
PEX_RX1_N
PEX_RX2 AP14 PEG_TX13 PEG_TX13 [3] OP@:Optimus
PLACE NEAR BALLS C98 EV@1u/6.3V_4 AH25 AP15 PEG_TX#13 PEG_TX#13 [3]
PEX_IOVDD_6 PEX_RX2_N
PEX_RX3 AN15 PEG_TX12
PEG_TX#12
PEG_TX12 [3] DO@:Discrete only +3V_GFX
+3V_S5
A +1.05V_GFX AG13 PEX_IOVDDQ_1 PEX_RX3_N AM15 PEG_TX#12 [3] A

To be placed no further from the GPU


C443
C432
EV@22u/6.3V_8
EV@22u/6.3V_8
AG15 PEX_IOVDDQ_2 PEX_RX4 AN17 PEG_TX11
PEG_TX#11
PEG_TX11 [3] SP@:Special R589 10K/F_4
AG16 PEX_IOVDDQ_3 PEX_RX4_N AM17 PEG_TX#11 [3]
than bewteen the PS and GPU C114 EV@10u/6.3V_6 AG18 AP17 PEG_TX10
PEX_IOVDDQ_4 PEX_RX5 PEG_TX10 [3]
C109 EV@10u/6.3V_6 AG25 AP18 PEG_TX#10 PEG_TX#10 [3] R384
PLACE UNDER BGA PEX_IOVDDQ_5 PEX_RX5_N CLK_PEGA_REQ# [9]
C52 EV@4.7u/6.3V_6 AH15 AN18 PEG_TX9 PEG_TX9 [3] 10/31 modify EV@10K/F_4
PEX_IOVDDQ_6 PEX_RX6

3
C86 EV@1u/6.3V_4 AH18 AM18 PEG_TX#9 PEG_TX#9 [3]
PLACE NEAR BALLS C78 EV@1u/6.3V_4 PEX_IOVDDQ_7 PEX_RX6_N PEG_TX8
AH26 PEX_IOVDDQ_8 PEX_RX7 AN20 PEG_TX8 [3]
AH27 AM20 PEG_TX#8 PEG_TX#8 [3] [10,19] DGPU_PW ROK R649 *EV@10K/F_4 2 Q39
PEX_IOVDDQ_9 PEX_RX7_N PEG_TX7 EV@DTC144EUA
AJ27 PEX_IOVDDQ_10 PEX_RX8 AP20 PEG_TX7 [3]

3
PEG_TX#7
 AK27
AL27
PEX_IOVDDQ_11 PEX_RX8_N AP21
AN21 PEG_TX6
PEG_TX#7 [3]
PEG_TX6 [3]

1
PEX_IOVDDQ_12 PEX_RX9 PEG_TX#6 PEX_CLKREQ# Q22
AM28 PEX_IOVDDQ_13 PEX_RX9_N AM21 PEG_TX#6 [3] 2
AN28 AN23 PEG_TX5 PEG_TX5 [3]
PEX_IOVDDQ_14 PEX_RX10 PEG_TX#5
PEX_RX10_N AM23 PEG_TX#5 [3]
AP23 PEG_TX4 PEG_TX4 [3] EV@PDTC143TT

1
PEX_RX11 PEG_TX#4 +3V_GFX
PEX_RX11_N AP24 PEG_TX#4 [3]
AN24 PEG_TX3 PEG_TX3 [3] 10/11 chnage type 10/5 modify
PEX_RX12 PEG_TX#3
PEX_RX12_N AM24 PEG_TX#3 [3]
AN26 PEG_TX2 PEG_TX2 [3]
PEX_RX13 PEG_TX#2
PEX_RX13_N AM26 PEG_TX#2 [3]
AP26 PEG_TX1 PEG_TX1 [3]
PEX_RX14 PEG_TX#1 C390
PEX_RX14_N AP27 PEG_TX#1 [3]
AN27 PEG_TX0 PEG_TX0 [3] EV@0.1u/10V_4
PEX_RX15 PEG_TX#0
PEX_RX15_N AM27 PEG_TX#0 [3]

5
[9,24,28,32] PLTRST# 2
AK14 R_PEG_RX15 C133 EV@0.22u/6.3V_4 PEG_RX15 [3] 4 PEGX_RST#
PEX_TX0 R_PEG_RX#15 C138 EV@0.22u/6.3V_4
PEX_TX0_N AJ14 PEG_RX#15 [3] [9] DGPU_HOLD_RST# 1
B AH14 R_PEG_RX14 C140 EV@0.22u/6.3V_4 PEG_RX14 [3]
B
PEX_TX1 R_PEG_RX#14 C145 EV@0.22u/6.3V_4 R374
AG14 PEG_RX#14 [3]

3
PEX_TX1_N R_PEG_RX13 C128 EV@0.22u/6.3V_4 U14
PEX_TX2 AK15 PEG_RX13 [3]
AJ15 R_PEG_RX#13 C130 EV@0.22u/6.3V_4 PEG_RX#13 [3] EV@100K_4
PEX_TX2_N R_PEG_RX12 C120 EV@0.22u/6.3V_4 EV@MC74VHC1G08DFT2G
PEX_TX3 AL16 PEG_RX12 [3]
AK16 R_PEG_RX#12 C123 EV@0.22u/6.3V_4 PEG_RX#12 [3]
PEX_TX3_N R_PEG_RX11 C112 EV@0.22u/6.3V_4
PEX_TX4 AK17 PEG_RX11 [3]
AJ17 R_PEG_RX#11 C119 EV@0.22u/6.3V_4 PEG_RX#11 [3]
PEX_TX4_N R_PEG_RX10 C106 EV@0.22u/6.3V_4
PEX_TX5 AH17 PEG_RX10 [3]
AC6 AG17 R_PEG_RX#10 C111 EV@0.22u/6.3V_4 PEG_RX#10 [3]
NC_1 PEX_TX5_N R_PEG_RX9 C100 EV@0.22u/6.3V_4
AJ28 NC_2 PEX_TX6 AK18 PEG_RX9 [3]
AJ4 AJ18 R_PEG_RX#9 C105 EV@0.22u/6.3V_4 PEG_RX#9 [3]
NC_3 PEX_TX6_N R_PEG_RX8 C99 EV@0.22u/6.3V_4
AJ5 NC_4 PEX_TX7 AL19 PEG_RX8 [3]
AL11 AK19 R_PEG_RX#8 C95 EV@0.22u/6.3V_4 PEG_RX#8 [3]
NC_5 PEX_TX7_N R_PEG_RX7 C93 EV@0.22u/6.3V_4
C15 NC_6 PEX_TX8 AK20 PEG_RX7 [3]
D19 AJ20 R_PEG_RX#7 C89 EV@0.22u/6.3V_4 PEG_RX#7 [3]
NC_7 PEX_TX8_N R_PEG_RX6 C87 EV@0.22u/6.3V_4
D20 NC_8 PEX_TX9 AH20 PEG_RX6 [3]
D23 AG20 R_PEG_RX#6 C84 EV@0.22u/6.3V_4 PEG_RX#6 [3]
NC_9 PEX_TX9_N R_PEG_RX5 C81 EV@0.22u/6.3V_4
D26 NC_10 PEX_TX10 AK21 PEG_RX5 [3]
H31 AJ21 R_PEG_RX#5 C77 EV@0.22u/6.3V_4 PEG_RX#5 [3]
NC_11 PEX_TX10_N R_PEG_RX4 C76 EV@0.22u/6.3V_4
T8 NC_12 PEX_TX11 AL22 PEG_RX4 [3]
V32 AK22 R_PEG_RX#4 C71 EV@0.22u/6.3V_4 PEG_RX#4 [3]
NC_13 PEX_TX11_N R_PEG_RX3 C64 EV@0.22u/6.3V_4
PEX_TX12 AK23 PEG_RX3 [3]
AJ23 R_PEG_RX#3 C62 EV@0.22u/6.3V_4 PEG_RX#3 [3]
PEX_TX12_N R_PEG_RX2 C55 EV@0.22u/6.3V_4
PEX_TX13 AH23 PEG_RX2 [3]
AG23 R_PEG_RX#2 C54 EV@0.22u/6.3V_4 PEG_RX#2 [3]
PEX_TX13_N R_PEG_RX1 C61 EV@0.22u/6.3V_4
PEX_TX14 AK24 PEG_RX1 [3]
AJ24 R_PEG_RX#1 C59 EV@0.22u/6.3V_4 PEG_RX#1 [3]
PEX_TX14_N R_PEG_RX0 C57 EV@0.22u/6.3V_4
PEX_TX15 AL25 PEG_RX0 [3]
C R_PEG_RX#0 C56 EV@0.22u/6.3V_4 C
PEX_TX15_N AK25 PEG_RX#0 [3]

AL13 CLK_PCIE_VGA CLK_PCIE_VGA [9]


PEX_REFCLK CLK_PCIE_VGA#
PEX_REFCLK_N AK13 CLK_PCIE_VGA# [9]

AJ26 PEX_TSTCLK R53 *EV@200_4


PEX_TSTCLK_OUT PEX_TSTCLK#
+3V_GFX J8 VDD33_1 PEX_TSTCLK_OUT_N AK26
K8 VDD33_2
L8 VDD33_3 PEX_WAKE AJ11 TP5
M8 AJ12 PEGX_RST#
VDD33_4 PEX_RST_N
10/11 change to 1k
AK12 PEX_CLKREQ# R390 EV@1K_4 +3V_GFX
PEX_CLKREQ_N

PEX_TERMP AP29 PEX_TERMP R372 EV@2.49K/F_4


EWD'^ EW'>
3(;B567WLPLQJ
TESTMODE R393 EV@10K/F_4
AK11 R46 GSS@0_6 +1.05V_GFX
+3V_GFX TESTMODE L3 GL@160808-120
PLACE CLOSE TO BGA ^Z ZZ
C154 EV@4.7u/6.3V_6 AG26 PEX_PLLVDD C47 EV@4.7u/6.3V_6 PLACE NEAR BGA I/O 3.3V
PEX_PLLVDD CLOSE TO CAPS
C159 EV@1u/10V_6 C48 EV@1u/6.3V_4
Z> ^>
PEX_PLL_HVDD AH12
AG12 PLACE UNDER BGA PEX_RST
C143 EV@0.1u/10V_4 PEX_SVDD_3V3 C63 EV@0.1u/10V_4
D C142 EV@0.1u/10V_4 PLACE NEAR BALLS
D
C144 EV@0.1u/10V_4 P8
C141 EV@0.1u/10V_4 3.3V_AUX_NC
+3V_GFX
C124 EV@0.1u/10V_4 Trise >= 1uS Tfail <=500nS
L4 C459 EV@4.7u/6.3V_6
PLACE CLOSE TO GPU BALLS VDD_SENSE C447 EV@4.7u/6.3V_6

GND_SENSE L5  PLACE NEAR BGA Quanta Computer Inc.


EV@N13x
GPUVCC_SENSE [39] PROJECT : ZQTA/ZQSA
N13P GPUVSS_SENSE [39] [16,17,19,40] +1.05V_GFX
Size Document Number Rev
[17,18,19,39,40] +3V_GFX
1A
[3,7,8,9,10,11,28,30,31,34,35,36,41,42] +3V_S5 DGPU 1/5 (PEG)
[3,7,8,9,10,11,13,14,19,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41] +3V
Date: Friday, November 11, 2011 Sheet 15 of 44
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

U15B U15C
FBC_CMD0 D13 G9 VMC_DQ0
[21] FBC_CMD[30:0] FBB_CMD0 (FBC_CMD25) FBC_D00
FBC_CMD1 E14 E9 VMC_DQ1
FBA_CMD0 VMA_DQ0 FBC_CMD2 FBB_CMD1 (FBC_CMD23) FBC_D01 VMC_DQ2 FBA_CMD2 R37 EV@10K/F_4
[20] FBA_CMD[30:0]
FBA_CMD1
U30 FBA_CMD0 (FBA_CMD25) FBA_D00 L28
VMA_DQ1 FBC_CMD3
F14 FBC_CMD2 DDKZz/& FBC_D02 G8
VMC_DQ3
FBA_CMD2
T31 FBA_CMD1 (FBA_CMD23) DDKZz/& FBA_D01 M29
VMA_DQ2 FBC_CMD4
A12 FBB_CMD3 (FBC_CMD0) FBC_D03 F9
VMC_DQ4 FBA_CMD3 R363 EV@10K/F_4
U29 FBA_CMD2 FBA_D02 L29 B12 FBB_CMD4 (FBC_CMD10) FBC_D04 F11
FBA_CMD3 R34 M28 VMA_DQ3 FBC_CMD5 C14 G11 VMC_DQ5
FBA_CMD4 FBA_CMD3 (FBA_CMD0) FBA_D03 VMA_DQ4 FBC_CMD6 FBB_CMD5 (FBC_CMD26) FBC_D05 VMC_DQ6 FBA_CMD5 R367 EV@10K/F_4
R33 FBA_CMD4 (FBA_CMD10) FBA_D04 N31 B14 FBB_CMD6 (FBC_CMD14) FBC_D06 F12
FBA_CMD5 U32 P29 VMA_DQ5 FBC_CMD7 G15 G12 VMC_DQ7
FBA_CMD6 FBA_CMD5 (FBA_CMD26) FBA_D05 VMA_DQ6 FBC_CMD8 FBC_CMD7 FBC_D07 VMC_DQ8 FBA_CMD18 R368 EV@10K/F_4
U33 R29 F15 G6
FBA_CMD7 FBA_CMD6 (FBA_CMD14) FBA_D06 VMA_DQ7 FBC_CMD9 FBB_CMD8 (FBC_CMD1) FBC_D08 VMC_DQ9
U28 P28 E15 F5
FBA_CMD8 FBA_CMD7 FBA_D07 VMA_DQ8 FBC_CMD10 FBB_CMD9 (FBC_CMD22) FBC_D09 VMC_DQ10 FBA_CMD19 R33 EV@10K/F_4
V28 J28 D15 E6
A FBA_CMD9 FBA_CMD8 (FBA_CMD1) FBA_D08 VMA_DQ9 FBC_CMD11 FBB_CMD10 (FBC_CMD20) FBC_D10 VMC_DQ11 A
V29 H29 A14 F6
FBA_CMD10 FBA_CMD9 (FBA_CMD22) FBA_D09 VMA_DQ10 FBC_CMD12 FBB_CMD11 (FBC_CMD24) FBC_D11 VMC_DQ12 FBC_CMD2 R66 EV@10K/F_4
V30 J29 D14 F4
FBA_CMD11 FBA_CMD10 (FBA_CMD20) FBA_D10 VMA_DQ11 FBC_CMD13 FBB_CMD12 (FBC_CMD18) FBC_D12 VMC_DQ13
U34 H28 A15 G4
FBA_CMD12 FBA_CMD11 (FBA_CMD24) FBA_D11 VMA_DQ12 FBC_CMD14 FBB_CMD13 (FBC_CMD9) FBC_D13 VMC_DQ14 FBC_CMD3 R386 EV@10K/F_4
U31 G29 B15 E2
FBA_CMD13 FBA_CMD12 (FBA_CMD18) FBA_D12 VMA_DQ13 FBC_CMD15 FBB_CMD14 (FBC_CMD29) FBC_D14 VMC_DQ15
V34 E31 C17 F3
FBA_CMD14 FBA_CMD13 (FBA_CMD9) FBA_D13 VMA_DQ14 FBC_CMD16 FBB_CMD15 (FBC_CMD8) FBC_D15 VMC_DQ16 FBC_CMD5 R61 EV@10K/F_4
V33 E32 D18 C2
FBA_CMD15 FBA_CMD14 (FBA_CMD29) FBA_D14 VMA_DQ15 FBC_CMD17 FBB_CMD16 (FBC_CMD27) FBC_D16 VMC_DQ17
Y32 FBA_CMD15 (FBA_CMD8) FBA_D15 F30 E18 FBB_CMD17 (FBC_CMD15) FBC_D17 D4
FBA_CMD16 AA31 C34 VMA_DQ16 FBC_CMD18 F18 D3 VMC_DQ18 FBC_CMD18 R378 EV@10K/F_4
FBA_CMD17 FBA_CMD16 (FBA_CMD27) FBA_D16 VMA_DQ17 FBC_CMD19 FBB_CMD18 (FBC_CMD11) FBC_D18 VMC_DQ19
AA29 D32 A20 C1
FBA_CMD18 FBA_CMD17 (FBA_CMD15) FBA_D17 VMA_DQ18 FBC_CMD20 FBB_CMD19 (FBC_CMD16) FBC_D19 VMC_DQ20 FBC_CMD19 R47 EV@10K/F_4
AA28 B33 B20 B3
FBA_CMD19 FBA_CMD18 (FBA_CMD11) FBA_D18 VMA_DQ19 FBC_CMD21 FBB_CMD20 (FBC_CMD28) FBC_D20 VMC_DQ21
AC34 C33 C18 C4
FBA_CMD20 FBA_CMD19 (FBA_CMD16) FBA_D19 VMA_DQ20 FBC_CMD22 FBB_CMD21 (FBC_CMD3) FBC_D21 VMC_DQ22
FBA_CMD21
AC33 FBA_CMD20 (FBA_CMD28) FBA_D20 F33
VMA_DQ21 FBC_CMD23
B18 FBB_CMD22 (FBC_CMD17) FBC_D22 B5
VMC_DQ23
&&
AA32 F32 G18 C5
FBA_CMD22 FBA_CMD21 (FBA_CMD3) FBA_D21 VMA_DQ22 FBC_CMD24 FBB_CMD23 (FBC_CMD5) FBC_D23 VMC_DQ24
AA33 FBA_CMD22 (FBA_CMD17) FBA_D22 H33 G17 FBB_CMD24(FBC_CMD4) FBC_D24 A11
FBA_CMD23 Y28 H32 VMA_DQ23 FBC_CMD25 F17 C11 VMC_DQ25
FBA_CMD24 FBA_CMD23 (FBA_CMD5) FBA_D23 VMA_DQ24 FBC_CMD26 FBB_CMD25 (FBC_CMD21) FBC_D25 VMC_DQ26 VMA_DQ[63:0]
Y29 FBA_CMD24 (FBA_CMD4) FBA_D24 P34 D16 FBB_CMD26 (FBC_CMD6) FBC_D26 D11 VMA_DQ[63:0] [20]
FBA_CMD25 W31 P32 VMA_DQ25 FBC_CMD27 A18 B11 VMC_DQ27
FBA_CMD26 FBA_CMD25 (FBA_CMD21) FBA_D25 VMA_DQ26 FBC_CMD28 FBB_CMD27 (FBC_CMD13) FBC_D27 VMC_DQ28 VMC_DQ[63:0]
Y30 P31 D17 D8 VMC_DQ[63:0] [21]
FBA_CMD27 FBA_CMD26 (FBA_CMD6) FBA_D26 VMA_DQ27 FBC_CMD29 FBB_CMD28 (FBC_CMD19) FBC_D28 VMC_DQ29
AA34 P33 A17 A8
FBA_CMD28 FBA_CMD27 (FBA_CMD13) FBA_D27 VMA_DQ28 FBC_CMD30 FBB_CMD29 (FBC_CMD12) FBC_D29 VMC_DQ30
Y31 L31 B17 C8
FBA_CMD29 FBA_CMD28 (FBA_CMD19) FBA_D28 VMA_DQ29 FBC_CMD30 FBC_D30 VMC_DQ31
Y34 L34 E17 B8
FBA_CMD30 FBA_CMD29 (FBA_CMD12) FBA_D29 VMA_DQ30 T3 FBC_CMD31 (NC) FBC_D31 VMC_DQ32
Y33 L32 F24
FBA_CMD30 FBA_D30 VMA_DQ31 FBC_D32 VMC_DQ33
V31 L33 G23
T1 FBA_CMD31 (NC) FBA_D31 VMA_DQ32 VMC_DM0 FBC_D33 VMC_DQ34
FBA_D32 AG28 [21] VMC_DM[7:0] E11 FBC_DQM0 FBC_D34 E24
AF29 VMA_DQ33 VMC_DM1 E3 G24 VMC_DQ35
VMA_DM0 FBA_D33 VMA_DQ34 VMC_DM2 FBC_DQM1 FBC_D35 VMC_DQ36
[20] VMA_DM[7:0] P30 AG29 A3 D21
VMA_DM1 FBA_DQM0 FBA_D34 VMA_DQ35 VMC_DM3 FBC_DQM2 FBC_D36 VMC_DQ37
F31 AF28 C9 E21
VMA_DM2 FBA_DQM1 FBA_D35 VMA_DQ36 VMC_DM4 FBC_DQM3 FBC_D37 VMC_DQ38
F34 FBA_DQM2 FBA_D36 AD30 F23 FBC_DQM4 FBC_D38 G21
VMA_DM3 M32 AD29 VMA_DQ37 VMC_DM5 F27 F21 VMC_DQ39
VMA_DM4 FBA_DQM3 FBA_D37 VMA_DQ38 VMC_DM6 FBC_DQM5 FBC_D39 VMC_DQ40
AD31 AC29 C30 G27
VMA_DM5 FBA_DQM4 FBA_D38 VMA_DQ39 VMC_DM7 FBC_DQM6 FBC_D40 VMC_DQ41
AL29 FBA_DQM5 FBA_D39 AD28 A24 FBC_DQM7 FBC_D41 D27
VMA_DM6 AM32 AJ29 VMA_DQ40 G26 VMC_DQ42
VMA_DM7 FBA_DQM6 FBA_D40 VMA_DQ41 FBC_D42 VMC_DQ43
AF34 FBA_DQM7 FBA_D41 AK29 FBC_D43 E27
AJ30 VMA_DQ42 VMC_WDQS0 D10 E29 VMC_DQ44
B FBA_D42 [21] VMC_WDQS[7:0] FBC_DQS_WP0 FBC_D44 B
AK28 VMA_DQ43 VMC_WDQS1 D5 F29 VMC_DQ45
VMA_WDQS0 FBA_D43 VMA_DQ44 VMC_WDQS2 FBC_DQS_WP1 FBC_D45 VMC_DQ46
[20] VMA_WDQS[7:0] M31 FBA_DQS_WP0 FBA_D44 AM29 C3 FBC_DQS_WP2 FBC_D46 E30
VMA_WDQS1 G31 AM31 VMA_DQ45 VMC_WDQS3 B9 D30 VMC_DQ47
VMA_WDQS2 FBA_DQS_WP1 FBA_D45 VMA_DQ46 VMC_WDQS4 FBC_DQS_WP3 FBC_D47 VMC_DQ48
E33 FBA_DQS_WP2 FBA_D46 AN29 E23 FBC_DQS_WP4 FBC_D48 A32
VMA_WDQS3 M33 AM30 VMA_DQ47 VMC_WDQS5 E28 C31 VMC_DQ49
VMA_WDQS4 FBA_DQS_WP3 FBA_D47 VMA_DQ48 VMC_WDQS6 FBC_DQS_WP5 FBC_D49 VMC_DQ50
AE31 FBA_DQS_WP4 FBA_D48 AN31 B30 FBC_DQS_WP6 FBC_D50 C32
VMA_WDQS5 AK30 AN32 VMA_DQ49 VMC_WDQS7 A23 B32 VMC_DQ51
VMA_WDQS6 FBA_DQS_WP5 FBA_D49 VMA_DQ50 FBC_DQS_WP7 FBC_D51 VMC_DQ52
AN33 AP30 D29
VMA_WDQS7 FBA_DQS_WP6 FBA_D50 VMA_DQ51 FBC_D52 VMC_DQ53
AF33 AP32 A29
FBA_DQS_WP7 FBA_D51 VMA_DQ52 VMC_RDQS0 FBC_D53 VMC_DQ54
AM33 [21] VMC_RDQS[7:0] D9 C29
FBA_D52 VMA_DQ53 VMC_RDQS1 FBC_DQS_RN0 FBC_D54 VMC_DQ55
AL31 E4 B29
VMA_RDQS0 FBA_D53 VMA_DQ54 VMC_RDQS2 FBC_DQS_RN1 FBC_D55 VMC_DQ56
[20] VMA_RDQS[7:0] M30 AK33 B2 B21
VMA_RDQS1 FBA_DQS_RN0 FBA_D54 VMA_DQ55 VMC_RDQS3 FBC_DQS_RN2 FBC_D56 VMC_DQ57
H30 AK32 A9 C23
VMA_RDQS2 FBA_DQS_RN1 FBA_D55 VMA_DQ56 VMC_RDQS4 FBC_DQS_RN3 FBC_D57 VMC_DQ58
E34 AD34 D22 A21
VMA_RDQS3 FBA_DQS_RN2 FBA_D56 VMA_DQ57 VMC_RDQS5 FBC_DQS_RN4 FBC_D58 VMC_DQ59
M34 AD32 D28 C21
VMA_RDQS4 FBA_DQS_RN3 FBA_D57 VMA_DQ58 VMC_RDQS6 FBC_DQS_RN5 FBC_D59 VMC_DQ60
AF30 FBA_DQS_RN4 FBA_D58 AC30 A30 FBC_DQS_RN6 FBC_D60 B24
VMA_RDQS5 AK31 AD33 VMA_DQ59 VMC_RDQS7 B23 C24 VMC_DQ61
VMA_RDQS6 FBA_DQS_RN5 FBA_D59 VMA_DQ60 FBC_DQS_RN7 FBC_D61 VMC_DQ62
AM34 FBA_DQS_RN6 FBA_D60 AF31 FBC_D62 B26
VMA_RDQS7 AF32 AG34 VMA_DQ61 C26 VMC_DQ63
FBA_DQS_RN7 FBA_D61 VMA_DQ62 FBC_D63
AG32
FBA_D62 VMA_DQ63
AG33
FBA_D63 VMC_CLK0
+1.5V_GFX AA27 D12 VMC_CLK0 [21]
FBVDDQ_1 FBC_CLK0 VMC_CLK0#
AA30 E12 VMC_CLK0# [21]
FBVDDQ_2 VMA_CLK0 FBC_CLK0_N VMC_CLK1
AB27 R30 VMA_CLK0 [20] E20 VMC_CLK1 [21]
FBVDDQ_3 FBA_CLK0 VMA_CLK0# FBC_CLK1 VMC_CLK1#
AB33 R31 VMA_CLK0# [20] F20 VMC_CLK1# [21]
FBVDDQ_4 FBA_CLK0_N VMA_CLK1 FBC_CLK1_N
AC27 FBVDDQ_5 FBA_CLK1 AB31 VMA_CLK1 [20]
AD27 AC31 VMA_CLK1# VMA_CLK1# [20]
FBVDDQ_6 FBA_CLK1_N FBC_DEBUG R65 EV@60.4/F_4
AE27
FBVDDQ_7 15mils width (FBC_DEBUG) FBB_DEBUG0
G14 +1.5V_GFX
AF27 G20 FBC_DEBUG1 R60 EV@60.4/F_4
FBVDDQ_8 FBA_DEBUG R50 EV@60.4/F_4 (NC) FBB_DEBUG1
AG27 R28 +1.5V_GFX
FBVDDQ_9 (FBA_DEBUG) FBA_DEBUG0 FBA_DEBUG1 R54 EV@60.4/F_4
B13 AC28 C12
FBVDDQ_10 (NC) FBA_DEBUG1 FBB_CMD_RFU0
B16 H26 C20
FBVDDQ_11 FB_VREF_NC T2 FBB_CMD_RFU1
B19
FBVDDQ_12
C E13 R32 F8 C
FBVDDQ_13 FBA_CMD_RFU0 FBB_WCK01
E16 FBVDDQ_14 FBA_CMD_RFU1 AC32 FBB_WCK01_N E8
E19 A5
FBVDDQ_15 FBB_WCK23
H10 K31 A6
FBVDDQ_16 FBA_WCK01 FBB_WCK23_N
H11 L30 D24
FBVDDQ_17 FBA_WCK01_N FBB_WCK45
H12 FBVDDQ_18 FBA_WCK23 H34 FBB_WCK45_N D25
H13 J34 B27
FBVDDQ_19 FBA_WCK23_N FBB_WCK67
H14 AG30 C27
FBVDDQ_20 FBA_WCK45 FBB_WCK67_N
H15 AG31
FBVDDQ_21 FBA_WCK45_N
H16 AJ34
FBVDDQ_22 FBA_WCK67
H18 AK34 D6
FBVDDQ_23 FBA_WCK67_N FBB_WCKB01
+1.5V_GFX H19 D7
FBVDDQ_24 FBB_WCKB01_N
H20 FBVDDQ_25 FBA_WCKB01 J30 FBB_WCKB23 C6
H21 J31 B6
FBVDDQ_26 FBA_WCKB01_N FBB_WCKB23_N
H22
FBVDDQ_27 FBA_WCKB23
J32 EWD'^ EW'> FBB_WCKB45
F26
H23 J33 E26
FBVDDQ_28 FBA_WCKB23_N FBB_WCKB45_N
PLACE CLOSE TO GPU BALLS H24 AH31 A26
FBVDDQ_29 FBA_WCKB45 FBB_WCKB67
C366 EV@4.7u/6.3V_6
H8
FBVDDQ_30 FBA_WCKB45_N
AJ31 ^Z ZZ FBB_WCKB67_N
A27
H9 AJ32
C387 EV@4.7u/6.3V_6 FBVDDQ_31 FBA_WCKB67
L27 FBVDDQ_32 FBA_WCKB67_N AJ33
C12 1 2 EV@1u/10V_6 M27 Ra H17 +FB_PLLAVDD C107 EV@0.1u/10V_4
C46 1 FBVDDQ_33 FBB_PLL_AVDD
2 EV@1u/10V_6 N27
FBVDDQ_34 RSVD
E1 PS_FB_CLAMP R415 GSS@10K_4
C85 EV@0.1u/10V_4 P27 PLACE CLOSE TO BALL
C127 EV@0.1u/10V_4 FBVDDQ_35 +FB_PLLAVDD C70 EV@0.1u/10V_4
R27 K27
C82 EV@0.1u/10V_4 FBVDDQ_36 FB_DLL_AVDD PLACE CLOSE TO BALL EV@N13x
T27
C129 EV@0.1u/10V_4 FBVDDQ_37 +FB_PLLAVDD L2 EV@PBY160808T-30Y-N_6
T30 U27 +1.05V_GFX
C69 EV@0.1u/10V_4 FBVDDQ_38 FBA_PLL_AVDD C45 EV@22u/6.3V_8
T33
C373 EV@0.1u/10V_4 FBVDDQ_39 FBVDDQ_SENSE_NC PLACE CLOSE TO BGA
V27 F1
C36 EV@0.1u/10V_4 FBVDDQ_40 FBVDDQ_PROBE T18 C66 EV@0.1u/10V_4
W27
C65 EV@0.1u/10V_4 FBVDDQ_41 FB_GND_SENSE_NC C67 EV@0.1u/10V_4
W30 FBVDDQ_42 GND_PROBE F2
W33 T19
FBVDDQ_43 FB_CAL_PD_VDDQ R55 EV@40.2/F_4
Y27 J27 +1.5V_GFX
C18 EV@10u/6.3V_8 FBVDDQ_44 FB_CAL_PD_VDDQ
C19 EV@10u/6.3V_8 FB_CAL_PU_GND R57 EV@42.2/F_4
EW'> :EWd
FB_CAL_PU_GND H27
D C17 EV@10u/6.3V_8 D
C367 EV@10u/6.3V_8 H25 FB_CAL_TERM_GND R59 EV@51.1/F_4 EW'^ :EWd
FB_CALTERM_GND
PLACE CLOSE TO BGA PLACE CLOSE TO GPU BALLS
EV@N13x ED'^ :EDd

C43 *EV@330u/2.5V_3528 [19,20,21,40] +1.5V_GFX


Quanta Computer Inc.
+

+1.5V_GFX [15,17,19,40] +1.05V_GFX


C39 EV@330u/2.5V_3528
PROJECT : ZQTA/ZQSA
+

10/7 add Size Document Number Rev


1A
DGPU 2/5 (Memory)
Date: Friday, November 11, 2011 Sheet 16 of 44
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

IV@:iGPU
C157 *DO@0.1u/10V_4 10/7 add
C158 DO@1u/6.3V_4
0929 Exchange + & - ; because symbol error EV@:dGPU
R77 OP@10K/F_4 C136 DO@0.1u/10V_4
C161 DO@4.7u/6.3V_6 OP@:Optimus
U15D
+1.05V_GFX L4 DO@160808-120 IFPAB_PLLVDD 50 mA AH8 AN6 EV_TXLCLK- [22] DO@:Discrete only
IFPAB_PLLVDD IFPA_TXC
/&W>s^ IFPA_TXC_N AM6 EV_TXLCLK+ [22]
L5 DO@160808-0180P IFPAB_IOVDD 320 mA IFPA_TXD0 AN3 EV_TXLOUT0- [22] SP@:Special
+3V_GFX AG8 IFPA_IOVDD IFPA_TXD0_N AP3 EV_TXLOUT0+ [22]
10/6 modify IFPA_TXD1 AM5 EV_TXLOUT1- [22]
C153 *DO@0.1u/10V_4 AG9 AN5 EV_TXLOUT1+ [22]
R75 OP@10K/F_4 C150 DO@1u/6.3V_4 IFPB_IOVDD IFPA_TXD1_N
A
C156 DO@4.7u/6.3V_6 IFPA_TXD2 AK6 EV_TXLOUT2- [22] EW'> :EWd A
10/7 add IFPA_TXD2_N AL6 EV_TXLOUT2+ [22]
IFPA_TXD3 AH6
R396 *EV@1K/F_4 IFPAB_RSET AJ8 AJ6 EW'^ :EWd
IFPAB_RSET IFPA_TXD3_N

IFPB_TXC AH9
IFPB_TXC_N AJ9 ED'^ :EDd
IFPB_TXD4 AP5
IFPB_TXD4_N AP6
IFPB_TXD5 AL7
IFPB_TXD5_N AM7
IFPB_TXD6 AM8
IFPB_TXD6_N AN8
IFPB_TXD7 AL8
IFPB_TXD7_N AK8

DO@SBK160808T-301Y-N_6
+3V_GFX L26 +IFPCD_PLLVDD 220 mA AF7 AG3 EV_HDMI_DDCCK_C EV_HDMI_DDCCK_C [23]
IFPC_PLLVDD IFPC_AUX_I2CW_SCL EV_HDMI_DDCDAT_C
C149 *DO@0.1u/10V_4
/&WdD^IFPC_AUX_I2CW_SDA_N AG2 EV_HDMI_DDCDAT_C [23]
AG7 IFPD_PLLVDD IFPC_L0 AK1 EV_HDMITX2P [23]
C463 *DO@0.1u/10V_4 AJ1
IFPC_L0_N EV_HDMITX2N [23]
C457 DO@1u/6.3V_4 10/7 add AJ3
IFPC_L1 EV_HDMITX1P [23]
R426 OP@10K/F_4 C146 DO@0.1u/10V_4 AJ2
IFPC_L1_N EV_HDMITX1N [23]
C462 DO@4.7u/6.3V_6 AH3
IFPC_L2 EV_HDMITX0P [23]
IFPC_L2_N AH4 EV_HDMITX0N [23]
DO@BLM18PG221SN1D AG5
L28 +IFPCD_IOVDD 285 mA AF6
IFPC_L3
AG4
EV_HDMICLK+ [23]
(1.05V +/- 3% ) +1.05V_GFX IFPC_IOVDD IFPC_L3_N EV_HDMICLK- [23]
C155 DO@0.1u/10V_4 AG6 AK3 EV_EDP-AUX+ [22]
B R425 OP@10K/F_4 C460 DO@1u/6.3V_4 IFPD_IOVDD IFPD_AUX_I2CX_SCL B
IFPD_AUX_I2CX_SDA_N AK2 EV_EDP-AUX- [22]
C461 DO@4.7u/6.3V_6 AM1 EV_EDP-ML0+ [22]
C151 *DO@0.1u/10V_4 IFPD_L0
10/7 add IFPD_L0_N AM2 EV_EDP-ML0- [22]
IFPD_L1 AM3
R397 DO@1K/F_4 IFPC_RSET AF8 AM4
IFPC_RSET IFPD_L1_N
IFPD_L2 AL3
R399 DO@1K/F_4 IFPD_RSET AN2 AL4
IFPD_RSET IFPD_L2_N
IFPD_L3 AK4
IFPD_L3_N AK5

R413 EV@10K/F_4 IFPEF_PLLVDD AB8 AB3


IFPEF_PLLVDD IFPE_AUX_I2CY_SCL
/&W&W IFPE_AUX_I2CY_SDA_N AB4
IFPE_L0 AD2
IFPEF_IOVDD AC7 AD3
R398 EV@10K/F_4 IFPE_IOVDD IFPE_L0_N
AC8 IFPF_IOVDD IFPE_L1 AD1
IFPE_L1_N AC1
IFPE_L2 AC2
AD6 IFPEF_RSET IFPE_L2_N AC3
IFPE_L3 AC4
IFPE_L3_N AC5

IFPF_AUX_I2CZ_SCL AF3
IFPF_AUX_I2CZ_SDA_N AF2
IFPF_L0 AE3
IFPF_L0_N AE4
IFPF_L1 AF4
DO@BLM18PG221SN1D AF5
L27 C455 DO@0.1u/10V_4 IFPF_L1_N
+3V_GFX IFPF_L2 AD4
C C452 DO@1u/6.3V_4 C
IFPF_L2_N AD5
C458 DO@4.7u/6.3V_6 AG1
C134 DO@0.1u/10V_4 IFPF_L3
IFPF_L3_N AF1

EV_CRT_RED R72 DO@150/F_4


R400 OP@10K/F_4 +DACA_VDD 120 mA AG10 AK9 EV_CRT_RED EV_CRT_RED [22]
DACA_VDD DACA_RED EV_CRT_GRN EV_CRT_GRN R67 DO@150/F_4
Zd DACA_GREEN AL10
EV_CRT_BLU
EV_CRT_GRN [22]
DACA_BLUE AL9 EV_CRT_BLU [22]
C449 DO@0.1u/10V_4 DACA_VREF AP9 EV_CRT_BLU R71 DO@150/F_4
DACA_VREF
AM9 EV_HSYNC_R R103 DO@33_4 HSYNC_COM [22]
R395 DO@124/F_4 DACA_RSET DACA_HSYNC EV_VSYNC_R R102 DO@33_4
AP8 DACA_RSET DACA_VSYNC AN9 VSYNC_COM [22]

R4 EV_CRTDCLK EV_CRTDCLK [22]


I2CA_SCL EV_CRTDDAT
I2CA_SDA R5 EV_CRTDDAT [22]

+1.05V_GFX L29 EV@160808-30Y NV_PLLVDD AD8 PLLVDD


C454 C135
R414 EV@0.1u/10V_4
*EV@0_4 EV@22u/6.3V_8

SP_PLLVDD AE8 [15,16,19,40] +1.05V_GFX


SP_PLLVDD
D [15,18,19,39,40] +3V_GFX D

PLACE CLOSE TO GPU


H3 CLK_27M_VGA_2
L25 EV@160808-0180P VID_PLLVDD XTAL_IN XTALOUT Y1
+1.05V_GFX AD7 VID_PLLVDD XTAL_OUT H2
yd>/E J4 R91 EV@10K/F_4 2 1
C456 C451 C147 C450 XTAL_OUTBUFF R401 EV@10K/F_4
H1

EV@N13x
XTAL_SSIN EV@27MHZ
C163
Quanta Computer Inc.
EV@22u/6.3V_8 EV@4.7u/6.3V_6 EV@0.1u/10V_4 C162 EV@18P/50V_4
EV@18P/50V_4 PROJECT : ZQTA/ZQSA
EV@0.1u/10V_4 Size Document Number Rev
PLACE CLOSE TO BALLS 1A
DGPU 3/5 (Display)
Date: Friday, November 11, 2011 Sheet 17 of 44
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

/RJLFDO6WUDS%LW0DSSLQJ
389'' 3' /RJLFDO /RJLFDO /RJLFDO /RJLFDO
6WUDSSLQJ%LW 6WUDSSLQJ%LW 6WUDSSLQJ%LW 6WUDSSLQJ%LW

[15,17,19,39,40] +3V_GFX
.   520B62 FB_1 FB_0 SMB_ALT_ADDR VGA_DEVICE 

U15E .   520B6&/. PCI_DEVIDE[4] SUB_VENDOR PCI_DEVID[5] PEX_PLL_EN_TERM 

D/K .   520B6, RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0] ;;;;
STRAP2 .   675$3 USER[3] USER[2] USER[1] USER[0] 
N13P-GL (1001) ---> 10k PU
A N13P-GS (1011) ---> 20K PU
.   675$3 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0] 
A

.   675$3 PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] 

.   675$3 SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED 

STRAP1 .   675$3 RESERVED PCI SPEED CHANGE GEN3 PCI_MAX SPEED DP_PLL_VDD33 

N13P-GL (0111) ---> 45.3k PD


+3V_GFX
N13P-GS (0110) ---> 34.8K PD EW'> :EWd +3V_GFX

EW'^ :d
R420 R85 R89 R109 R110
STRAP3 ED'^ :d SNP@45.3K/F_4 SP@34.8K/F_4 *EV@10K/F_4
R111 R87 R112
Optimus ---> 4.99k PD *SP@4.99K/F_4 GS@10K/F_4 GS@4.99K/F_4 STRAP0 SP@4.99K/F_4 *SP@34.8K/F_4
STRAP1
Discrete only ---> 15K PD ROM_SI STRAP2
ROM_SO STRAP3
ROM_SCLK STRAP4

Resistor P/N
D/K R93 R88 R94 R421 R76 R84 R90 R92
4.99K---> CS24992FB26 SP@34.8K/F_4 SP@10K/F_4 SP@15K/F_4 SP@34.8K/F_4 SP@15K/F_4 EV@10K/F_4
10K ---> CS31002FB26 10/3 add SNM@10K/F_4 *SP@34.8K/F_4
15K ---> CS31502FB24 +3V_GFX
B 20K ---> CS32002FB29 dGPU_AC_DC# R404 EV@10K/F_4
B

34.8K---> CS33482FB22
JTAG_TMS R392 *EV@10K/F_4
45.3K ---> CS34532FB18 N13P-GS/-GL Straping table
JTAG_TDI R394 *EV@10K/F_4

VGA_OVT# R403 EV@10K/F_4


ROM_SI
1G Hynix 64Mx16 -->15K PD ROM_SO ROM_SCLK
ALERT R423 EV@10K/F_4
1G Micron 64Mx16 -->20K PD N13P-GL --> 10K PD N13P-GL (0010) ---> 15k PD
JTAG_TCK R68 *EV@10K/F_4 2G Hynix 128Mx16 -->35K PD (Default) N13P-GS --> 10K PU N13P-GS (1000) ---> 4.99K PU
JTAG_TRST# R391 EV@10K/F_4 2G Micron 128Mx16 -->45K PD
DGPU_DPST_PW M R73 *EV@2K/F_4

N13M-GS Straping table


TP6 JTAG_TCK AM10 P6
JTAG_TCK GPIO0 GPU_VID4 [39]
TP41 JTAG_TMS
TP42 JTAG_TDI
AP11 JTAG_TMS D/^'W/K/:d'd,Z GPIO1 M3
DGPU_DPST_PW M
GPU_VID3 [39] WE ^D s
AM11 JTAG_TDI GPIO2 L6 DGPU_DPST_PW M [22]
TP39 JTAG_TDO AP12 P5 DGPU_DISP_ON [22]
TP40 JTAG_TRST# JTAG_TDO GPIO3
AN11 JTAG_TRST_N GPIO4 P7 DGPU_LVDS_BLON [22]
GPIO5 L7 GPU_VID1 [39]  
GPIO6 M7 GPU_VID2 [39]
C +3V_GFX R410 EV@2.2K_4 N13P_SCL R7 N8 C
I2CB_SCL GPIO7
R409 EV@2.2K_4 N13P_SDA R6 I2CB_SDA GPIO8 M1 VGA_OVT#
ALERT
 
GPIO9 M2
GPIO10 L1
+3V_GFX R411
R412
OP@2.2K_4
OP@2.2K_4
DGPU_EDIDCLK R2
DGPU_EDIDDATA R3 I2CC_SCL GPIO11 M5
dGPU_AC_DC#
GPU_VID0 [39]  
 
I2CC_SDA GPIO12 N3 10/3 modify
GPIO13 M4 GPU_VID5 [39]
GPIO14 N4 
GFx_SCL T4 I2CS_SCL GPIO15 P2 EV_HDMI_HPD [23]  

GFx_SDA T3 I2CS_SDA GPIO16 R8 GPU_DPRSLPVR [39] 


GPIO17 M6 EV_eDP_HPD [22]
GPIO18 R1
TP48
TP7
THERM+
THERM-
K4 THERMDP GPIO19 P3   
K3 THERMDN GPIO20 P4
GPIO21 P1


[22] DGPU_EDIDCLK
[22] DGPU_EDIDDATA
DGPU_EDIDCLK
DGPU_EDIDDATA

H4 ROM_SCLK
'&^D/
GFx_SCL 1 3
**
GPUT_CLK [32]

STRAP0 ROM_SCLK R69 EV@10K_4
STRAP1
J2 STRAP0 D/^ZKD ROM_CS_N H6
ROM_SI
+3V_GFX
R406 Q26
J7 STRAP1 ROM_SI H5
STRAP2 J6 H7 ROM_SO EV@4.7K_4 EV@2N7002
2
STRAP3 STRAP2 ROM_SO
J5 STRAP3

STRAP4 J3 +3V_GFX
STRAP4
R405
2

EV@4.7K_4 Q25
D 

  R422 SNP@40.2K/F_4 J1
MULTISTRAP_REF_GND BUFRST_N L2 R402 *EV@10K_4
GFx_SDA
EV@2N7002 D
1 3 GPUT_DATA [32]


  CEC L3 R108 GL@10K_4 +3V_GFX
11/8 change for GPU temp detect
EV@N13x

VGA_OVT# 1 dGPU_AC_DC# 1
EWD'^ EW'> ALERT
Quanta Computer Inc.
3 TP71 3 TP72 1 3 GPU_THERMAL_ALERT# [32]
Q9 Q23 ZZ ^Z Q10 PROJECT : ZQTA/ZQSA
*EV@2N7002 *EV@2N7002 EV@2N7002 Size Document Number Rev
2

10/5 add 1A
DGPU 4/5 (MIO/GPIO)
+3V_GFX +3V_GFX +3V_GFX Date: Friday, November 11, 2011 Sheet 18 of 44
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

EW'> :EWd
U15G
A2 GND_1 GND_101 D2 EW'^ :EWd
AA17 GND_2 'Wh'E GND_102 D31
+VGACORE
AA18 GND_3 GND_103 D33
+VGACORE AA20 GND_4 GND_104 E10 ED'^ :EDd
AA22 GND_5 GND_105 E22
U15F AB12 E25 C92 EV@1u/6.3V_4
GND_6 GND_106 C75 EV@0.1u/10V_4
AA12 VDD_001 XVDD_001 U1 AB14 GND_7 GND_107 E5
AA14 'Whs U2 AB16 E7 C110 EV@0.1u/10V_4
VDD_002 XVDD_002 GND_8 GND_108 C116 EV@0.1u/10V_4
AA16 U3 AB19 F28
VDD_003 XVDD_003 GND_9 GND_109 C115 EV@0.1u/10V_4
AA19 U4 AB2 F7
VDD_004 XVDD_004 GND_10 GND_110 C104 EV@0.1u/10V_4
AA21 U5 AB21 G10
VDD_005 XVDD_005 GND_11 GND_111 C113 EV@0.1u/10V_4
AA23 U6 A33 G13
A
AB13
VDD_006
VDD_007
XVDD_006
XVDD_007
U7 AB23
GND_12
GND_13
GND_112
GND_113
G16 PLACE UNDER GPU C83 EV@0.1u/10V_4 A

AB15 U8 AB28 G19 C94 EV@0.1u/10V_4


VDD_008 XVDD_008 GND_14 GND_114
AB17 V1 AB30 G2
VDD_009 XVDD_009 GND_15 GND_115
AB18 V2 AB32 G22
VDD_010 XVDD_010 GND_16 GND_116
AB20 V3 AB5 G25
VDD_011 XVDD_011 GND_17 GND_117
AB22 V4 AB7 G28
VDD_012 XVDD_012 GND_18 GND_118 +VGACORE
AC12 VDD_013 XVDD_013 V5 AC13 GND_19 GND_119 G3
AC14 V6 AC15 G30
VDD_014 XVDD_014 GND_20 GND_120
AC16 V7 AC17 G32
VDD_015 XVDD_015 GND_21 GND_121
AC19 V8 AC18 G33
VDD_016 XVDD_016 GND_22 GND_122
AC21 W2 AA13 G5
VDD_017 XVDD_017 GND_23 GND_123 C103 C131 C102 C122 C126 C139 C80 C117
AC23 VDD_018 XVDD_018 W3 AC20 GND_24 GND_124 G7
M12 W4 AC22 K2
VDD_019 XVDD_019 GND_25 GND_125
M14 VDD_020 XVDD_020 W5 AE2 GND_26 GND_126 K28
M16 W7 AE28 K30 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6
VDD_021 XVDD_021 GND_27 GND_127 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6
M19 VDD_022 XVDD_022 W8 AE30 GND_28 GND_128 K32
M21 Y1 AE32 K33
VDD_023 XVDD_023 GND_29 GND_129
M23 Y2 AE33 K5
VDD_024 XVDD_024 GND_30 GND_130
N13 Y3 AE5 K7
VDD_025 XVDD_025 GND_31 GND_131
N15 Y4 AE7 M13
VDD_026 XVDD_026 GND_32 GND_132
N17 Y5 AH10 M15
VDD_027 XVDD_027 GND_33 GND_133
N18 Y6 AA15 M17
VDD_028 XVDD_028 GND_34 GND_134
N20 Y7 AH13 M18
VDD_029 XVDD_029 GND_35 GND_135
N22 VDD_030 XVDD_030 Y8 AH16 GND_36 GND_136 M20
P12 AA1 AH19 M22 +VGACORE
VDD_031 XVDD_031 GND_37 GND_137
P14 AA2 AH2 N12
VDD_032 XVDD_032 GND_38 GND_138
P16 AA3 AH22 N14
VDD_033 XVDD_033 GND_39 GND_139
P19 VDD_034 XVDD_034 AA4 AH24 GND_40 GND_140 N16
P21 VDD_035 XVDD_035 AA5 AH28 GND_41 GND_141 N19
P23 AA6 AH29 N2 C118 C72 C125 C101 C108 C90 C73
VDD_036 XVDD_036 GND_42 GND_142
R13 VDD_037 XVDD_037 AA7 AH30 GND_43 GND_143 N21
R15 VDD_038 XVDD_038 AA8 AH32 GND_44 GND_144 N23
R17 AH33 N28 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6
VDD_039 GND_45 GND_145 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6
B R18 VDD_040 AH5 GND_46 GND_146 N30 B
R20 VDD_041 AH7 GND_47 GND_147 N32
R22 VDD_042 AJ7 GND_48 GND_148 N33
T12 VDD_043 AK10 GND_49 GND_149 N5
T14 VDD_044 AK7 GND_50 GND_150 N7
T16 AL12 P13
VDD_045 GND_51 GND_151
T19 VDD_046 AL14 GND_52 GND_152 P15
T21 VDD_047 AL15 GND_53 GND_153 P17
T23 AL17 P18
VDD_048 GND_54 GND_154
U13 AL18 P20
VDD_049 GND_55 GND_155
U15 AL2 P22
VDD_050 GND_56 GND_156
U17 AL20 R12
VDD_051 GND_57 GND_157
U18 AL21 R14
VDD_052 GND_58 GND_158
U20 AL23 R16
VDD_053 GND_59 GND_159
U22 AL24 R19
VDD_054 GND_60 GND_160
V13 AL26 R21
VDD_055 GND_61 GND_161
V15 AL28 R23
V17
VDD_056
VDD_057 AL30
GND_62
GND_63
GND_162
GND_163 T13 PLACE NEAR GPU +VGACORE
V18 VDD_058 AL32 GND_64 GND_164 T15
V20 VDD_059 AL33 GND_65 GND_165 T17
V22 AL5 T18
VDD_060 GND_66 GND_166
W12 AM13 T2
VDD_061 GND_67 GND_167 C96
W14 AM16 T20
VDD_062 GND_68 GND_168 + C467 C164 C166 C464 C465 C160 C466
W16 AM19 T22
VDD_063 GND_69 GND_169
W19 AM22 AG11
VDD_064 GND_70 GND_170 EV@4.7u/25V_8 EV@4.7u/25V_8 EV@4.7u/25V_8 EV@47u/6.3V_8
W21 AM25 T28
VDD_065 GND_71 GND_171 EV@330u/2.5V_3528 EV@4.7u/25V_8 EV@4.7u/25V_8 EV@22u/6.3V_8
W23 VDD_066 AN1 GND_72 GND_172 T32
Y13 AN10 T5
VDD_067 GND_73 GND_173
Y15 AN13 T7
VDD_068 GND_74 GND_174
Y18 AN16 U12
VDD_069 GND_75 GND_175
Y17 AN19 U14
VDD_070 GND_76 GND_176
Y20 AN22 U16
VDD_071 GND_77 GND_177
Y22 AN25 U19
VDD_072 GND_78 GND_178 +3V_GFX
AN30 U21
EV@N13x GND_79 GND_179
C AN34 U23 C
GND_80 GND_180
AN4 GND_81 GND_181 V12
AN7 V14
GND_82 GND_182 R383
AP2 V16
GND_83 GND_183 +3V EV@4.7K_4
AP33 V19
GND_84 GND_184
B1 GND_85 GND_185 V21
B10 V23
GND_86 GND_186 R380
B22 W13 DGPU_PWROK [10,15]
GND_87 GND_187 EV@4.7K_4
B25 W15
GND_88 GND_188
B28 W17
GND_89 GND_189

3
B31 W18 R382
GND_90 GND_190
B34 W20 EV@100K/F_4
GND_91 GND_191 DGPU_PGOK-1
B4 W22 2
GND_92 GND_192
B7 W28
GND_93 GND_193
C10 Y12
GND_94 GND_194

3
C13 Y14 Q21

1
GND_95 GND_195 R381 DGPU_POK4 C411 EV@DTC144EUA
Ws'&y C19
C22
GND_96 GND_196
Y16
Y19
+1.5V_GFX
EV@4.7K_4
2
Q20 EV@1000P/50V_4
GND_97 GND_197 EV@MMBT3904-7-F
C25 Y21

1
GND_98 GND_198 C412
C28 GND_99 GND_199 Y23
+VGACORE D4 EV@RB500V-40 C7 AH11 10/31 modify *EV@1000P/50V_4
GND_100 GND_200<