IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO.
2, FEBRUARY 2015
Modeling of Wide Bandgap Power
Semiconductor DevicesPart I
Homer Alan Mantooth, Fellow, IEEE, Kang Peng, Student Member, IEEE,
Enrico Santi, Senior Member, IEEE, and Jerry L. Hudgins, Fellow, IEEE
(Invited Paper)
Abstract Wide bandgap power devices have emerged as an
often superior alternative power switch technology for many
power electronic applications. These devices theoretically have
excellent material properties enabling power device operation at
higher switching frequencies and higher temperatures compared
with conventional silicon devices. However, material defects
can dominate device behavior, particularly over time, and this
should be strongly considered when trying to model actual
characteristics of currently available devices. Compact models
of wide bandgap power devices are necessary to analyze and
evaluate their impact on circuit and system performance.
Available compact models, i.e., models compatible with circuit-
level simulators, are reviewed. In particular, this paper presents
a review of compact models for silicon carbide power diodes and
MOSFETs.
Index Terms Gallium-nitride (GaN), modeling, power device
modeling, power semiconductor devices, silicon-carbide (SiC),
wide bandgap.
I. I NTRODUCTION
P OWER electronics can be defined as the application of
solid-state electronics to condition, control, and convert
electric power. With increasing concern for energy delivery
and environmental protection, power electronics is playing an
increasingly important role in human society. Power semi-
conductor devices are the core solid-state components in
the overall power conversion system, and they most often
consume the largest portion of power losses in that system.
Therefore, the development of power semiconductor devices
has been the driving force in the progress of power elec-
tronics systems. Recently, silicon (Si)-based devices have
dominated the power device market due to mature and well-
established fabrication technology for Si. However, there
have been applications where Si power electronics have not
made the inroads necessary for widespread deployment due
to insufficient thermal capabilities, voltage breakdown, or
Manuscript received August 12, 2014; revised October 20, 2014; accepted
October 23, 2014. Date of publication November 26, 2014; date of current
version January 20, 2015. This work was supported by the Office of Naval
Research, Arlington, VA, USA, under Grant N00014-08-1-0080. The review
of this paper was arranged by Editor N. Ohtani.
H. A. Mantooth is with the University of Arkansas, Fayetteville, AR 72701
USA (e-mail: mantooth@uark.edu).
K. Peng and E. Santi are with the Department of Electrical Engineer-
ing, University of South Carolina, Columbia, SC 29208 USA (e-mail:
pengk@email.sc.edu; santi@engr.sc.edu).
J. L. Hudgins is with the Department of Electrical Engineering, University
of NebraskaLincoln, Lincoln, NE 68588 USA (e-mail: jhudgins2@unl.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2014.2368274
0018-9383 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
423
frequency of operation. This has created a growing need for
power device technologies that can deliver high temperature,
high-power density, and high-frequency operation. For
example, a variety of applications in the aircraft, automotive,
and energy exploration industries require power conversion
systems to operate at an ambient temperature significantly
> 200 C, far beyond Si material limits. Consequently, a new
generation of so-called wide bandgap semiconductor devices
has emerged as viable replacements for the current Si-based
power devices.
A substantial amount of research and development activity
has occurred over the past 20 years in the silicon carbide (SiC)
and gallium nitride (GaN) fields. These efforts have deliv-
ered several classes of power semiconductor devices, with
voltage ratings from 30 V to 15 kV and growing, for a wide
variety of applications. Circuit and system researchers have
collaborated in parallel to demonstrate the efficacy of these
device technologies in demonstration designs ranging from
laptop chargers (200 V) to plug-in hybrid electric vehicle
battery chargers (1200 V) to fault current limiters for the
electric power grid (10 kV). The ability of these devices to
switch at higher frequencies than their Si counterparts has
led to system-level benefits in volume or efficiency even at
operational temperatures where Si is suitable.
At present, SiC and GaN are the most promising among
all wide bandgap semiconductor materials [1]. Table I [2]
compares the material properties of Si, SiC, and GaN. The SiC
and GaN have almost a three times larger bandgap (3 eV)
compared with Si (1 eV). The breakdown electric field of
SiC and GaN is one order of magnitude higher than that
of Si. The higher breakdown electric field enables the design
of wide bandgap power devices with thinner and higher doped
voltage-blocking layers. For unipolar power devices, this can
yield a lower ON-state voltage drop and conduction loss. For
bipolar power devices, this can lead to a shorter switching
time and lower switching loss. The high thermal conductivity
of SiC, together with the large bandgap, allows SiC-based
devices to operate at temperatures easily exceeding 200 C.
All of these properties make wide bandgap semiconductor
devices a promising alternative to Si-based devices.
Substantial improvements in GaN and SiC material quality
over the past several years have led to the availability of
commercial SiC and GaN power devices. In particular, SiC
Schottky diodes, MOSFETs, and junction gate FETs (JFETs)
have reached the market. Although GaN-based devices can
theoretically offer better performance than SiC, the lack
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TABLE I
M ATERIAL P ROPERTIES
of good-quality substrates hinders the development of high
voltage vertical GaN power devices. However, the interest in
GaN power devices by industry is increasing.
Nevertheless, material defects are a root cause of device
failures. These defects and corresponding secondary effects
are exacerbated by additional energy from high electric fields,
large current densities, increasing temperature, and interface
stress of material layers. For example, nonmicropipe defects in
the bulk and epitaxial layers of SiC have been reported to limit
the current and voltage ratings in devices and have contributed
to degraded performance and failure [3]. The bottom line
question is whether SiC and GaN can meet or exceed Si
Failure In Time (FIT) (109 failures per device operation hour)
levels to take advantage of a projected significant increase
in power density in wide bandgap devices. This improved
power density typically means higher operating temperatures,
greater thermal cycling, higher impressed electric fields -
all in opposition to device reliability. Yet presently, some
second-generation SiC Schottky diodes are reported to have
a failure rate of < 0.15 ppm. In addition, some SiC junction-
barrier Schottky (JBS) diodes have achieved a failure rate
of <0.5 failures per billion of operational hours (0.5 FIT) [4].
Meanwhile, looking at comparison with silicon devices,
Si insulated gate bipolar transistor (IGBT) modules are around
tens to a few FIT. Gate drivers now have a higher FIT
(and, therefore, worse reliability) than Si IGBT devices, and
Si Integrated Gate Commutated Thyristor (IGCT) operation in
rail inverter applications has indicated > 45 years mean time
between failures and an associated low FIT [5]. Therefore,
SiC diodes have been shown to meet the reliability levels of
Si; but because material defects can dominate device behavior,
particularly over time, this should be strongly considered when
trying to model actual characteristics of wide bandgap devices,
particularly devices other than diodes.
The commercially available wide bandgap semiconductor
power devices indicate that a significant breakthrough in power
electronics has been achieved over the past decades. As power
devices have progressed, power device simulation is becoming
an increasingly significant method for studying device perfor-
mance. Significant work has been devoted to the creation and
validation of compact device models for the purpose of power
electronic circuit simulations. As many of the SiC devices
were created, researchers developed SiC models, starting with
diodes and static induction transistors and then proceeded
to MOSFETs and JFETs. Others, such as thyristors, gate
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015
turn-OFF thyristors, and IGBTs, were modeled in addi-
tion to bipolar junction transistors (BJTs) and SiC junction
transistors [6].
This paper presents a survey of recent progress on
SiC- and GaN-based power semiconductor devices along with
their device models. In Section II, an overview of device mod-
eling requirements is given, and five different device model
levels are described. An SiC power devices are described
in Section III, while GaN power devices are presented
in Section IV. Throughout this paper, a description of reli-
ability issues associated with these wide bandgap devices is
provided. Some assertions regarding outstanding issues and
future trends of power device modeling are provided in the
concluding section.
II. C OMPACT D EVICE M ODEL R EQUIREMENTS
The basic objective in compact device modeling is to
achieve a predictive description of the current flow through
the device as a function of the applied voltages and currents,
environmental conditions, such as temperature and radiation,
and physical characteristics, such as geometry, doping levels,
and so on. Understanding this objective and the mathematical
formulation that is consistent with the numerical algorithms
used by circuit simulators to analyze circuits and systems,
is the first step in understanding how to create compact
models that are predictive of device behavior and also run at
computationally attractive speeds. For device models, at least
a good approximation to the actual relationship of the elec-
trical variables needs to be obtained. A compromise between
computational speed and model accuracy is usually made. The
required accuracy and simulation time are crucial factors con-
sidered by device model designers when making this tradeoff.
A very simple device model generally provides fast simulation
speed but loses physics insight into power device behavior and
simulation accuracy. In contrast, a very complicated physics-
based model is usually preferred for accurate simulation of
device behavior, but is very time-consuming and not very
suitable for circuit simulation.
The predictive nature of a good compact model varies
depending on the intended use of the model. In the case
of power semiconductor device models, the intended use is
typically as a power switch in power electronics applications.
Therefore, it is not necessary to model first derivative
characteristics, such as device transconductance and output
conductance, to the degree of accuracy expected in a Berkeley
short-channel insulated gate FET model for analog integrated
circuit design. The primary considerations are predicting the
dc I V characteristics of the device along with switching
characteristics resulting from attributes, such as device capaci-
tances, carrier lifetimes, and conductivity modulation of lightly
doped, voltage-blocking regions.
A basic device model selection procedure is shown in Fig. 1.
As a first step, the device model requirements are determined
based on the balance between model accuracy and simulation
time. According to the device modeling requirements, an
appropriate device model is chosen for characterization. Static
I V and CV measurements are performed to extract model
MANTOOTH et al.: MODELING OF WIDE BANDGAP POWER SEMICONDUCTOR DEVICESPART I
Fig. 1. Device model selection procedure: measurements, parameter extrac-
tion, and model validation.
parameters that determine the accuracy of the device model.
Pulsed I V measurements are used to avoid self-heating
issues. Based on these measurements, model parameters are
extracted to achieve a best fit to the measured data. Model val-
idation is performed to check the effectiveness of the resulting
device model. For power devices, a double-pulse test circuit is
often used to validate the dynamic behavior of device models
and is sometimes used for device characterization. Based on
the validation against experimental results, the selected model
may be either accepted or rejected. If the device model is
rejected, a new device model needs to be chosen; and the
same process described above must be repeated.
High computational speed and accuracy are required for
compact models of power semiconductor devices. For the
development of power device models, it is critical that certain
prominent device features be captured in the model if they
dominate the static or switching device performance. For
example, MOS capacitances have significant impact on the
dynamic behavior of devices with isolated gates (MOSFET,
IGBT, and MOS-controlled thyristor). These inherent capaci-
tances vary strongly with device terminal voltages. In addition,
for bipolar power devices (p-i-n diodes, IGBT, BJT, and
thyristor), conductivity modulation is a key effect that reduces
the resistance of the thick, lightly doped semiconductor layer.
During its conduction period, the large injected carrier con-
centration exceeds the background doping concentration; and
the resistance of the region is reduced dramatically. Therefore,
the conductivity modulation effect should be considered for
bipolar device modeling. Due to high power loss, power
devices heat up during operation. The device characteristics are
typically a strong function of junction temperature, so that an
accurate model must capture this relationship. For this reason,
electrothermal device models are sometimes used, while static
thermal models (i.e., device characteristics are temperature
dependent, but temperature is constant during simulation)
are sufficient for most instances. Moreover, breakdown in
power devices might occur, typically under extreme tran-
sient conditions. The most common breakdown mechanism
is avalanche breakdown, due to impact ionization; but punch-
through breakdown and Zener breakdown are also possible in
some cases [7].
Depending on the modeling method used, available mod-
els of power semiconductor devices can be categorized into
five different levels, starting with the simplest behavioral
models and then moving to more complex physics-based
models [8], [9]. Assuming such models exist, then the model
selection procedure of Fig. 1 can be exercised to obtain the
appropriate model for the task.
425
1) Behavioral Models: These models simulate power
devices without considering their physical mechanism
of operation, and usually they are implemented using
mathematical fitting methods. Their relevant model para-
meters have no direct physical meaning. The advantage
of these behavioral models is that they are simple and
less time-consuming, although their accuracy is low,
especially when the device operates under conditions
different from those used for parameter curve fitting.
2) Semiphysics Models: Such models are partly based on
device physics. For simplicity, in many cases, the stan-
dard low voltage device models, which are available in
circuit simulation tools, such as SPICE and SABER, are
adapted to address high-voltage power device modeling.
Therefore, the physical meaning of some device model
parameters and equations might be lost. Some behavioral
equations may also be included in these semiphysics
models.
3) Physics-Based Models: These models are based on
semiconductor physics. The description of electrical
and thermal behavior is obtained by solving physics
equations with some simplifications.
4) Seminumerical Models: These models are in between
physics-based and numerical models. For example, for
some power devices, especially bipolar power devices,
carrier distribution in different regions of the devices is
determined by the ambipolar diffusion equation (ADE)
under high-level injection. The solution to the ADE is
obtained using a numerical method, such as Fourier
series, Laplace transformation, or other methods, so
that the spatial carrier distribution is calculated by the
model.
5) Numerical Models: Numerical simulation tools
(SILVACO, Sentaurus TCAD, MEDICI, etc) are
available for power devices and circuit simulation [10].
The 2-D numerical simulation greatly contributes to
the development of power devices. These numerical
models can provide very accurate results, but they are
complicated, computationally intensive, and require
detailed information on material properties and device
geometry.
The most commonly used levels are behavioral and
physics-based models. Ideal switch models are often used
to simulate overall circuit behavior when perhaps comparing
circuit topologies. Once the topology is selected and detailed
converter design begins, a physics-based model is soon desir-
able when component interactions, switching waveforms, and
thermal management considerations need to be addressed. Any
model-based design flow will employ different device models
at different stages in the design process [11].
The process of developing a physics-based model is shown
in Fig. 2. The initial phase involves device characterization
through experimental evaluation of samples along with numer-
ical device simulations of a representative device structure.
Through the analysis of these results, model equations are
formulated from physics principles of charge transport and
storage, field effects, junctions, depleted regions, interface
traps, and so on. These relationships are simplified to a
426
Fig. 2. Model development methodology for physics-based models (Level 3).
lumped version or to a 1-D version for computational speed.
Sometimes 2-D effects are captured in a simplified manner,
giving rise to so-called 1.5-D models. A large-signal model is
constructed and the equations parameterized based on observ-
ability from experimental measurements. The model is then
implemented in the appropriate format for the target simulator.
Modeling tools such as ModLyng are very useful at this stage
because they allow for graphical construction of the model
and subsequent code generation into a variety of formats for
various simulators, such as Saber, HSpice, and Spectre [12].
Then, the model is parameterized by fitting it to the measured
data through model parameter extraction and then simulating
it under test configurations, such as clamped-inductive load,
to compare the measured with the simulated results. If the
requisite effects are captured, then the model is complete.
If they are not, then the model must be enhanced and part
of the process repeats.
III. SiC P OWER D EVICES AND T HEIR M ODELS
Due to the significant improvements in SiC material
growth technology, SiC-based power devices are available for
high power, high temperature, and high frequency applica-
tions. Micropipes in SiC have been nearly eliminated (now
< 2.5 per cm2 ). Other defects are likely to be resolved within
several years. These include threading screw dislocation (TSD)
(TSD density is currently 1000 cm2 ) [13], basal plane
dislocation (BPD) (BPD density is currently a few to tens
of cm2 ) [14], and threading edge dislocation (TED) (TED
density is presently 1001000 s of cm2 ) [15]. Comparatively,
GaN can have bulk defect densities exceeding 106 cm2 .
Currently, several manufacturers have produced SiC diodes
that have a FIT of < 0.5 [16]. However, all non-Si devices are
conduction-current limited in their ratings because of material
quality.
Substrate screw dislocations can propagate into an adjoining
epilayer depending on the epitaxial growth method. One dislo-
cation has been shown to reduce the breakdown voltage rating
by 5%35% and soften the breakdown characteristic. Highly
localized current may concentrate in the dislocation resulting
in microplasmas. The defects may also cause a reduction
in the charge carrier lifetime. The density of these types of
dislocation defects is currently 10003000 cm2 [17], [18].
Basal plane defects (BPD) are one of the troublesome
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015
imperfections in SiC material. Stacking faults originate from
the BPD and have been shown to cause an increase in
the forward voltage, under constant current, in bipolar SiC
devices and an increase in reverse-biased leakage current, and
a decrease in forward-biased conduction current in unipo-
lar devices. The main source of BPDs in the epitaxial
layer is from propagation of BPDs present in the substrate.
At present, the density is < 10 cm2 due to improvements
in bulk and epitaxial growth [19]. The TED are usually
1-D defects on the wafer surface that occur by insertion or
removal of an extra half plane of atoms between two lattice
atomic planes. Typically, the density of these defects is several
thousands per cm2 . Diodes with higher TED densities have
higher leakage current and slightly lower breakdown voltage
compared with devices without dislocations [20].
Overcurrent during the ON-state causes an increase in the
recombination energy being absorbed that then creates and fur-
ther extends existing material defects. These increased defects
lead to more charge carrier recombination, thus delivering
more energy to the crystal and increasing the effective forward
voltage drop (increasing the power dissipated in the device).
In particular, BPDs expand into triangular-shaped stacking
faults [21]. The 48 off-orientation of the crystallographic
c-axis for the epitaxial layer can cause BPD growth that is
inclined to the surface, originating from the epilayer, and sub-
strate interface with a growing stacking fault. For a SiC BJT,
interface states near the emitter act as recombination sites and
affect the current gain. Stacking faults grow from the surface
and degrade the current gain by up to 50% after a few hours
of operation. This can be mitigated by proper processing of
surface passivation layers [21]. Failure of Schottky diodes has
been reported from dv/dt stress that causes breakdown due
to excess charge generation in the space charge region, under
reverse bias, in an area with dislocation defects [22]. The JBS
diode structures have been shown to handle surge current den-
sities at least twice as high as for Schottky diodes [23], [24].
However, operation of JBS diodes has shown an increased
forward voltage over time due to stacking faults increasing
charge carrier recombination and impeding charge flow, just
as in other SiC bipolar devices [21].
Problems exist with aluminum (Al) at operating tempera-
tures > 200 C [4]. There is a phenomenon termed interlayer
dielectric erosion (IDE) where Al electrodes erode and pene-
trate the underlying interlayer dielectric and finally reach the
poly-Si gate contact, resulting in a gatesource short-circuit.
The erosion progression depends on the temperature and the
quality of the silicate glass. To prevent IDE, Si doped (1 wt%)
Al can be used to effectively reduce dissolution and movement;
or use of a barrier metal can prevent the movement of Al into
the underlying material. An example of this is to deposit 50 nm
of tantalum (Ta) and 150 nm of tantalum nitride as a barrier
dielectric over the silicate glass interlayer.
Another problem is Al spearing in poly-Si. The Al spears
(or spikes) are observed in the gate located between the
Al-interconnect and the gate after storage at an elevated
temperature. This is caused by massive movement of Al of
the gate interconnecting with the poly-Si gate. The Al spears
extend to the channel region along the poly-Si gate and
MANTOOTH et al.: MODELING OF WIDE BANDGAP POWER SEMICONDUCTOR DEVICESPART I 427

TABLE II
P UBLISHED SiC P OWER D IODE M ODELS

Fig. 3. Cross-sectional views of (a) SiC Schottky diode, (b) SiC p-i-n diode,
and (c) SiC hybrid diode.

compromise the gate oxide, causing a dielectric breakdown

failure and finally a gate-to-source short circuit.
Nickel silicide (Ni2 Si) contacts have low resistance and
are used as ohmic contacts on n-type 4H-SiC. A com-
mon technique for fabricating these contacts is to deposit
a thin nickel (Ni) film followed by rapid thermal annealing
at 950 C1050 C. Surface segregation of carbon due to
this annealing causes the upper metallization layer to sep-
arate from the semiconductor, thus delaminating the entire
contact. To avoid this reaction, the surface segregated carbon
is removed before the metallization process can be performed.
However, delamination can still occur probably due to move-
ment of carbon back to the surface over time. Ni2 Si contact
degradation also occurs when the NiSi-based ohmic contacts
interact with the Al interconnects due to Al reacting with
Ni2 Si, decomposing it and forming NiAl and Si.

A. SiC Power Diodes

The power diode is a key component in power electronics
applications. Basically, SiC power diodes can be classified into
three types: 1) SiC Schottky diode; 2) SiC p-i-n diode; and
3) SiC merged p-n-Schottky diode (MPS), also called JBS.
1) SiC Schottky Diodes: The Schottky diode is a very
attractive unipolar device formed by an electrically
nonlinear contact between a metal and a semiconductor
bulk region, as shown in Fig. 3(a). It has low ON-state
voltage drop, almost zero reverse recovery charge and
extremely high switching speed, but its reverse leakage
current is large, especially at high temperature, due to
its lower built-in potential barrier. In addition, the max-
imum breakdown voltage of practical Schottky diodes
is limited by the increase in drift region resistance with
breakdown voltage in the absence of conductivity mod-
ulation effects. The commercially available Si Schottky
diodes are usually rated at maximum breakdown
voltages < 100 V. Beyond this limit, Si Schottky diodes
cannot compete with Si p-i-n diodes due to the unac-
ceptably large ON-state resistance of Schottky diodes.
In comparison with their Si counterparts, novel SiC
Schottky diodes can block thousands of volts because
SiC material has a much larger breakdown electric field. carrier injection in the epitaxial drift region result-
2) SiC p-i-n Diodes: SiC p-i-n diodes consist of a highly ing in conductivity modulation. However, conductivity
doped n-type substrate, a lightly doped n-type epitax- modulation causes significant reverse recovery current
ial layer with specified thickness, and a highly doped during switching, which is undesirable because it causes
p-type region for the anode, which is shown in Fig. 3(b). additional turn-ON loss in the active switch.
The advantage of the SiC p-i-n diode is low ON-state 3) SiC JBS/MPS Diodes: Hybrid diodes (JBS or MPS)
voltage drop in high current conduction, due to minority combine the attractive benefits of the low ON-state
428
TABLE II
(CONTINUED.) P UBLISHED SiC P OWER D IODE M ODELS
voltage drop of a Schottky contact and the high blocking
voltage of p-i-n diodes and have become common-
place starting with the second generation of SiC diode
structures. Hybrid diodes have Schottky-like ON-state
and switching behavior and p-i-n-like OFF-state char-
acteristics at the same time. An MPS or JBS
diode consists of interleaved Schottky and p+ doped
regions [Fig. 3(c)]. For very small ON-state voltage
drop, only Schottky contact areas are active. On the
other hand, when the diodes are reverse-biased, Schottky
contact conduction areas are electrically shielded by
p-i-n junction depletion regions. An additional advantage
of hybrid diodes is increased surge current capability,
due to the conduction of the p-i-n areas at higher forward
voltages.
To evaluate the behavior of power electronics systems,
accurate power diode device models are required for power
converter designers. Consequently, accurate and reliable power
diode models are necessary. Most of the SiC power diode
models published have been reviewed, and they are listed
chronologically in Table II.
B. Behavioral Models
In [43], the linear model of a SiC Schottky diode, including
a dc voltage drop and a series resistor, has been reported.
Linear equations have been used to approximate the tem-
perature effects on the dc voltage drop and on series resis-
tance. In [34], the exact same method has been applied to
estimate power loss characteristics of a SiC Schottky diode.
A behavioral model of SiC merged p-i-n Schottky diodes was
presented in [32] and [33]. The forward and reverse current
versus voltage relationships were described using exponential
equations, and model parameters were approximated using
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015
curve fitting equations as a function of temperature. However,
no dynamic characteristics were validated with this model.
Another electrothermal behavioral model for SiC MPS diodes
has been reported in [48]. Mathematical equations with no
direct physical meaning and several curve-fitting parameters
were used to describe the static behavior of the diode under
forward and reverse bias voltages, and thermal network mod-
eling is based on the analysis of the thermal constant spectrum
of the temperature response of the diode.
C. Semiphysics-Based Models
In [44], the conventional p-n junction Shockley equation
was used to model forward conduction and reverse leakage
currents for SiC JBS. The temperature dependence of series
resistance was modeled as a second-order relationship with the
difference between the device junction temperature and ambi-
ent temperature. However, the reverse recovery characteristic
was not included in this model. The charge-controlled model
was used in [35] to accurately model the dynamic effects of
parasitic device capacitance. In [47], the Shockley equation
was also applied to model a SiC Schottky diode; and the effects
of image force barrier lowering and tunneling on reverse
leakage current were considered. In [36], the forward current
voltage characteristic of a SiC Schottky diode was modeled
using standard Schottky diode equations based on thermionic
emission theory. Note that the parameters used, such as
Schottky barrier height and effective Richardson constant,
have a clear physical meaning. The reverse leakage current
was modeled using a parallel conductance. Zhang et al. [41]
presented a SiC Schottky diode model using the standard
Schottky diode equation, including the temperature effect on
carrier mobility. The parameter extraction procedure of this
approach to model a SiC Schottky diode was presented in [49].
However, this model was not complete, because the tempera-
ture and reverse bias voltage effects on reverse leakage current
were not included. In [38][40], modified Schottky diode
models were proposed, considering the dependence of the
reverse leakage current on the electric field and temperature.
D. Physics-Based Models
The Mantooth unified diode model is capable of describing
SiC p-i-n, Schottky, and MPS diodes under different
simulation conditions, including forward bias, emitter
recombination, conductivity modulation, breakdown behav-
ior, reverse recovery, and temperature effects [26][30]. The
temperature dependence of the forward series resistance,
semiconductor material bandgap, and carrier mobility was
considered in this model. In [31], the lumped charge method
was used to model SiC p-i-n diodes. The main idea of this
approach is that the n-drift region is divided into a number
of small subregions, and charge control equations are applied
to each subregion. For a high voltage JBS diode, a novel
physics-based model was developed in [42]. The forward
ON -resistance was more accurately approximated, consider-
ing the current spreading from anode to cathode due to
the presence of nonconducting p+ regions on the anode
side [Fig. 3(c)]. The electric field at Schottky contact and
MANTOOTH et al.: MODELING OF WIDE BANDGAP POWER SEMICONDUCTOR DEVICESPART I
the FowlerNordheim tunneling currents were considered to
model the reverse leakage current.
E. Seminumerical-Based Models
The forward I V characteristics of 4H-SiC p-i-n diodes
were investigated using an analytic model describing the
minority carrier distributions in different diode regions
(high-doped regions and low-doped drift region) [46]. In this
model, the solution to the ADE in a lightly doped drift
region was derived under high injection conditions. The
doping dependence of bandgap narrowing, incomplete dop-
ing ionization, carrier lifetime, and mobility have been
considered. The accuracy of this model has been verified
by comparisons with numerical simulations and experimen-
tal results under different temperature and conduction cur-
rent conditions. However, this model is inconvenient for
implementation into circuit simulators, due to its com-
plicated carrier distribution solution. In [45] and [50],
a Fourier-based solution to the ADE was used to develop
p-i-n diode models. The second-order partial differential car-
rier diffusion equation was turned into an infinite number of
first-order linear differential equations with series coefficients
implemented by equivalent RC components. The Fourier
series of first-order equations is truncated to implement this
model.
F. Numerical Models
The finite-element simulation tool SILVACO was used to
simulate a 10 kV SiC p-i-n diode in [37], and simulation
results have been compared with test results from the actual
device. A good agreement between the SILVACO model and
the experimental results was demonstrated.
G. SiC Power MOSFET
A SiC vertical power MOSFET is a next-generation
switching device expected to replace conventional Si power
switching devices in many applications because it can operate
with lower power loss, at a higher switching frequency and at
higher operating temperatures. In the past ten years, a lot of
effort has been devoted to developing SiC power MOSFETs;
and great progress has been achieved. The first SiC power
MOSFET was demonstrated in 1994 in the form of a vertical
trench gate structure (UMOSFET) [51]. The reported device
had 150 V blocking voltage and 3.3 mcm2 specific
ON -resistance. It suffered from a high electric field in the gate
oxide at the trench corner and low inversion carrier mobility.
To avoid these drawbacks in a UMOSFET, a SiC planar gate
MOSFET was fabricated using a double implantation MOS
process to form p-base (DMOSFET) [52]. A diagram of a typi-
cal UMOSFET and DMOSFET are shown in Fig. 4. A 6H-SiC
DMOSFET was based on a 10-m thick and 6.5 1015 cm3
doped n-type drift layer, which can support a reverse blocking
voltage of 760 V. Later on, DMOSFETs with higher reverse
blocking voltages have been reported. A 10-kV 4H-SiC power
DMOSFET was demonstrated [53]. This was the highest
reported blocking voltage for SiC power MOSFETs [53].
429
This high blocking voltage was achieved using an 85-m thick
and 8 1014 cm3 doped n-type drift epilayer. A specific
ON -resistance of 123 mcm2 was obtained with a gate
voltage bias of 18 V, and an effective channel carrier mobility
of 22 cm2 /Vs was measured. However, 10-kV SiC MOSFETs
are not mature enough to be commercially available now.
For oxides in SiC, the electric field stress is determined by
the oxide thickness and gate voltage. Choices are limited due
to targets for threshold voltage and transconductance. Due to
permittivity differences between SiO2 and SiC, the electric
field strength in the oxide is typically three times higher than
in the SiC. Control of the pitch in p-body modifies this field
distribution. Various intrinsic defects not related to dopants or
impurities are observed at the SiC/SiO2 interface. An SiC has a
higher surface density of atoms per unit area compared with Si,
resulting in a higher density of dangling Si- and C-bonds, and
carbon cluster at the interface. Defects located in the near-
interfacial oxide layer may appear in the energy gap of SiC
and act as traps for electrons. Low channel mobility in 4H-SiC
is directly linked to very high interface state densities at the
SiO2 /SiC boundary. Interface state density reduction plays a
critical role in increasing channel mobility and improving high
temperature performance, as well as the reliability of power
SiC MOSFETs and IGBTs.
Reduction of the interface state density and improvement in
device reliability can be achieved by the use of nitric oxide
postoxidation annealing. This reduces carbon clusters at the
interface, thus increasing the channel mobility and the dielec-
tric quality. One promising solution is to create a carefully
formed oxide-nitride-oxide dielectric on 4H-SiC [4], [21].
An accurate model of a SiC MOSFET is necessary for
device evaluation, system design, and power converter behav-
ior prediction. Therefore, much effort is needed to model
SiC MOSFETs. A few SiC MOSFET models have been
published and are listed chronologically in Table III.
H. Behavioral Models
To model the turn-ON dynamic characteristics of a
SiC MOSFET, a behavioral MOSFET model has been
proposed in [71]. The SiC MOSFET model consists of a
drainsource resistance and three constant interelectrode
capacitances. The drainsource resistance can be switched
from infinity to a finite small value and vice versa, according
to the transistors gate voltage. The parasitic inductances from
device packages have been considered to accurately simulate
the transient ringing. A behavioral SiC MOSFET model is
built in [72] using polynomial functions to create a model
that estimates device loss.
I. Semiphysics-Based Models
The conventional Shockley lateral MOSFET equations,
which can describe the static I V characteristic curve, have
been used to model a SiC vertical power MOSFET. These
equations are implemented, for example, in the level 1
MOSFET model in PSpice. Since the Shockley MOSFET
model was originally developed for lateral structure devices in
Si and germanium (Ge), many researchers have proposed some
430
TABLE III
P UBLISHED SiC P OWER MOSFET M ODELS
modification to these equations for their proposed SiC vertical
power MOSFET models. In [60], a simple SPICE model
for SiC power DMOSFETs was proposed with some specific
modifications in the conventional Si lateral MOS channel mod-
eling approach. Temperature-dependent voltage and current
sources were added to describe the temperature-dependent gate
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015
TABLE III
(CONTINUED.) P UBLISHED SiC P OWER MOSFET M ODELS
threshold voltage and device transconductance. The reduced
carrier mobility in the drift layer and JFET region was
considered in modeling ON-state resistance. This proposed
model was validated from 25 C to 200 C. On the basis
of the same model, Sun et al. [69] and Lu et al. [70]
investigated a modified SiC MOSFET model that can simulate
device behavior at low temperature (25 C). The effect of
negative gate drive voltage on gatesource capacitance was
also included in this proposed model. In [67], to account
for the device self-heating effect, a Foster RC network was
used for thermal modeling and coupled with the electri-
cal model that used Shockley lateral MOSFET equations.
Moreover, another large-signal model for 6H-SiC MOSFET
with temperature compensation has been proposed [58]. The
temperature-dependent compensating currents were considered
to be in parallel with the MOS channel current between the
drain and source. These three temperature-dependent currents
were the body leakage current, channel current change due to
the gate threshold voltage variation and the channel current
change due to drain, and source contact resistance variation.
In [74], a temperature-dependent voltage source is added in
series with the gate of the standard MOSFET model, to sim-
ulate the gate threshold voltage variation with operating tem-
perature. To include temperature-dependent carrier mobility
MANTOOTH et al.: MODELING OF WIDE BANDGAP POWER SEMICONDUCTOR DEVICESPART I
Fig. 4. (a) Cross-sectional views of SiC UMOSFET. (b) SiC DMOSFET [40].
behavior and avalanche effect, two parallel current sources
are added in parallel with the standard MOSFET model.
Sakurai and Newton [73] introduced a simple nth power law
MOSFET model. This model had the excellent feature of
fast parameter extraction, and was originally proposed for
short-channel CMOS. In [62] and [66], this nth power law
MOSFET model was used to simulate high-voltage SiC power
MOSFETs, improving the accuracy of forward I V curves.
J. Physics-Based Models
An analytical model for a DMOSFET was developed
in [56] and [57]. This model was proposed based on regional
analysis of carrier transport in the channel and drift regions.
The drift region was divided into three parts, as shown
in Fig. 5: 1) an accumulation Region A; 2) a drift Region B
with a varying cross section area; and 3) a drift Region C
with a constant cross-region area. The voltage drops across
these regions were calculated as a function of the electric
field in these regions. Another physics-based model for a
SiC DMOSFET was proposed in [63], where the nonuniform
current distribution in the JFET region was modeled using
a nonlinear voltage source and a resistance network. One
advantage of this novel DMOSFET model was that only a
single set of equations was used to describe device operation
in both the linear and saturation regions.
McNutt et al. [54], [55] presented a compact model for
SiC power MOSFET. The expression for the channel current
in this model was the sum of two distinct components with
different gate threshold voltages, providing additional flexi-
bility for device modeling. Due to the unique feature of the
channel current description, this model could reproduce the
gradual transition from linear to saturation region observed
in SiC power MOSFETs. The parameter extraction was done
using a software package called IMPACT. In [64] and [65],
a new parameter extraction strategy for the McNutt model was
introduced, which relied on the device datasheet data only,
eliminating the need for experimental characterization.
K. Seminumerical-Based Models
Low channel mobility of electrons in the surface inversion
layer is a severe limitation for a SiC MOSFET operating at
431
Fig. 5. Cross-sectional views of SiC DMOSFET for modeling.
high power and temperature conditions. This poor inversion
surface mobility is due to the large number of interface
defects during the MOS thermal oxidation process. A com-
prehensive physical model was given, incorporating interface
trap densities, Coulombic interface trap scattering, surface
roughness scattering, phonon scattering, velocity saturation,
and so forth [61]. Coulomb scattering and surface roughness
scattering reduce surface mobility in the subthreshold and
linear region, whereas the saturation current is limited by
carrier saturation velocity.
L. Numerical Models
A 2-D device model was created using the SILVACO
ATLAS simulator to investigate a 4H-SiC 1200 V power
MOSFET [68]. This model included recombination effects,
bandgap narrowing, impact ionization, and lattice heating.
A comprehensive numerical model considering carrier mobil-
ity and interface states was established in [59]. The channel
current distribution versus bias voltage was solved numerically
in two dimensions.
IV. C ONCLUSION
This paper begins a comprehensive review of available
devices and models in the power semiconductor space. The
most prominent devices, the SiC diode and MOSFET, were
included here. Part II of this paper will complete the lesser
used SiC power devices and describe what is available in
GaN devices and models as well.
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H. Alan Mantooth (S83M90SM97F09)
received the Ph.D. degree from the Georgia Institute
of Technology, Atlanta, GA, USA, in 1990.
He joined the faculty of the Department of Elec-
trical Engineering, University of Arkansas, Fayet-
teville, AR, USA, in 1998, where he is currently a
Distinguished Professor.
Kang Peng received the B.S. degree in electri-
cal engineering from Hunan University, Changsha,
China, and the M.S. degree in electrical engineering
from the Huazhong University of Science and Tech-
nology, Wuhan, China, in 2008 and 2011, respec-
tively. He is currently pursuing the Ph.D. degree
with the University of South Carolina, Columbia,
SC, USA.
His current research interests include power semi-
conductor devices modeling and application.
Enrico Santi (S90M94SM02) received the
Ph.D. degree from the California Institute of Tech-
nology, Pasadena, CA, USA, in 1994.
He has been with the University of South Carolina,
Columbia, SC, USA, since 1998, where he is cur-
rently an Associate Professor. His current research
interests include modeling and simulation of semi-
conductor power devices, control of power elec-
tronics systems, and advanced modeling of power
systems.
Jerry L. Hudgins received the Ph.D. degree from
Texas Tech University, Lubbock, TX, USA, in 1985.
He is currently the Chair of the Department
of Electrical Engineering with the University of
Nebraska, Lincoln, NE, USA. His current research
interests include power electronic device characteri-
zation and modeling, power electronics design, and
renewable energy systems.